Storage device based on flash memory and reading operation method thereof

Abstract

A memory device includes: a memory cell array including a plurality of memory cells; a page buffer circuit connected to the plurality of memory cells through bit lines and configured to read data stored in the plurality of memory cells in page units; and a column decoding circuit configured to output, as valid data, discontinuous sub-pages among the page data stored in the page buffer circuit based on the sub-page bitmap information included in the read command during a read operation.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2024 - 0006736, filed with the Korean Intellectual Property Office on January 16, 2024, the disclosure of which is incorporated herein by reference in its entirety.

[0003] Example embodiments of the inventive concept described herein relate to a semiconductor memory device, and more particularly, to a flash - based storage device and a method of reading the same. Background Art

[0004] Semiconductor memories can be mainly classified into volatile memories or non - volatile memories. Read and write speeds of volatile memories (e.g., DRAM or SRAM) are fast, but when the power is turned off, data stored in the volatile memories disappears (e.g., is lost). In contrast, non - volatile memories can retain data even when the power is turned off. Thus, non - volatile memories can be used to store content that must be preserved regardless of whether power is supplied.

[0005] A representative example embodiment of non - volatile memory is flash memory. Flash memory is widely used as a storage medium for audio and video data in information devices such as computers and smart phones. Recently, active research has been conducted on high - capacity, high - speed input / output, and low - power technologies for flash memory for use in mobile devices such as smart phones.

[0006] Non - volatile memory can perform a read operation on a page - by - page basis. Non - volatile memory can divide a page into multiple sub - pages during a read operation and output valid sub - pages among the multiple sub - pages. Summary of the Invention

[0007] Example embodiments of the inventive concept provide a memory device that performs a read operation by using a read command transmitted once, the read command including bitmap information indicating positions of sub - pages and offset information indicating sizes of sub - pages, and a storage device including the memory device.

[0008] According to some example embodiments, a memory device includes: a memory cell array including a plurality of memory cells; a page buffer circuit connected to the plurality of memory cells through bit lines and configured to read data stored in the plurality of memory cells in units of pages; and a column decoding circuit configured to output non - consecutive sub - pages among page data stored in the page buffer circuit as valid data based on sub - page bitmap information included in a read command during a read operation.

[0009] According to some example embodiments, a memory device includes: a memory cell array including a plurality of memory cells; an address decoder connected to the plurality of memory cells via word lines and configured to select one word line based on a read command; a page buffer circuit connected to the plurality of memory cells via bit lines and configured to temporarily store page data stored in the memory cells connected to the selected word line; and a column decoding circuit configured to output at least one sub-page selected from the page data based on sub-page offset information and sub-page bitmap information included in the read command as valid data.

[0010] According to some example embodiments, a storage device includes: a memory device including a plurality of memory cells; and a memory controller configured to send a read command including sub-page bitmap information to the memory device to read data stored in the plurality of memory cells. The memory device is configured to select a word line based on the read command and output non-consecutive sub-pages among the page data stored in the memory cells connected to the selected word line as valid data based on the sub-page bitmap information. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other objects and features of the inventive concept will become apparent by describing in detail some example embodiments of the inventive concept with reference to the accompanying drawings.

[0012] Figure 1 is a block diagram showing a user device according to some example embodiments.

[0013] Figure 2 is a block diagram showing an example of the memory device shown in Figure 1 according to some example embodiments.

[0014] Figure 3 is a circuit diagram showing an example of a memory block BLK1 of a memory cell array shown in Figure 2 according to some example embodiments.

[0015] Figure 4 is a circuit diagram showing a cell string selected by a first string selection line SSL1 among cell strings of a memory block BLK1 shown in Figure 3 shown in according to some example embodiments.

[0016] Figure 5 is a block diagram showing a memory controller of Figure 1 according to some example embodiments.

[0017] Figure 6 is a schematic diagram showing a first read mode of a memory device of Figure 2 according to some example embodiments.

[0018] Figure 7 is a schematic diagram showing the configuration of a read command according to a first read mode according to some example embodiments Figure 6 thereof.

[0019] Figure 8 is a schematic diagram showing a second read mode of a memory device according to some example embodiments Figure 2 thereof.

[0020] Figure 9 is a schematic diagram showing the configuration of a read command according to a second read mode according to some example embodiments Figure 8 thereof.

[0021] Figure 10 is a schematic diagram showing bitmap information corresponding to valid data including non - consecutive sub - pages in a second read mode of a memory device according to some example embodiments Figure 2 thereof.

[0022] Figure 11 is a schematic diagram showing an example embodiment of a column decoding circuit according to some example embodiments Figure 2 thereof.

[0023] Figure 12 is a schematic diagram showing an example of a read method of a memory device according to some example embodiments Figure 2 thereof.

[0024] Figure 13 is a schematic diagram showing an example of a column decoding circuit according to some example embodiments Figure 2 thereof.

[0025] Figure 14 is a schematic diagram showing a look - up table of an example of a read method of a memory device according to some example embodiments Figure 2 thereof. DETAILED DESCRIPTION

[0026] Hereinafter, some example embodiments of the inventive concept will be described in detail and clearly so that those of ordinary skill in the art can easily implement the inventive concept.

[0027] Figure 1 is a block diagram showing a user device according to some example embodiments. Referring Figure 1 , the user device 100 may include a storage device 1000 and a host 1500. The storage device 1000 and the host 1500 may be connected through a host interface 1201. The host interface 1201 may be a standard interface such as ATA, SATA, PATA, USB, SCSI, ESDI, IEEE 1394, IDE, and / or card interface, etc.

[0028] According to some example embodiments, the storage device 1000 may be a non-volatile memory-based storage device. For example, the storage device 1000 may include a memory device 1100, a memory controller 1200, and a buffer memory 1300. The memory device 1100 may be a non-volatile memory, such as a flash memory or a phase change memory (PRAM). In some example embodiments, when the memory device 1100 is a flash memory, the storage device 1000 may be a flash-based flash storage device. For example, the storage device 1000 may be an SSD (Solid State Drive), a UFS (Universal Flash Storage), and / or a memory card, etc. The buffer memory 1300 may include a volatile memory (e.g., DRAM).

[0029] According to some example embodiments, the memory device 1100 may be connected to the memory controller 1200 through a memory interface 1202. The memory device 1100 may include a memory cell array 1110 and peripheral circuits. The peripheral circuits may include all analog or digital circuits required to store or read data in the memory cell array 1110.

[0030] According to some example embodiments, the peripheral circuits may receive external power from the memory controller 1200 and generate internal power of various levels. The peripheral circuits may receive commands, addresses, and data from the storage controller 1200, and store the data in the memory cell array 1110 according to control signals. In some example embodiments, the peripheral circuits may read the data stored in the memory cell array 1110 and provide the data to the memory controller 1200.

[0031] According to some example embodiments, the memory cell array 1110 may include a plurality of memory blocks. Each memory block may have a vertical three-dimensional structure. Each memory block may include a plurality of memory cells. Multi-bit data may be stored in each memory cell. For example, the memory device 1100 may be a TLC flash memory capable of storing 3-bit data in one memory cell.

[0032] According to some example embodiments, due to the design layout structure, the memory cell array 1110 may be located beside or above the peripheral circuits. The structure in which the memory cell array 1110 is located above the peripheral circuits is called a COP (Cell On Peripheral) structure. The memory cell array 1110 may be manufactured as a chip separate from the peripheral circuits. The upper chip including the memory cell array 1110 and the lower chip including the peripheral circuits may be connected to each other using a bonding method. This structure is called a C2C (Chip to Chip) structure.

[0033] According to some example embodiments, the memory controller 1200 may be connected between the memory device 1100 and the host 1500. In some example embodiments, the memory controller 1200 may be connected between the buffer memory 1300 and the host 1500. The memory controller 1200 may control read or write operations of the memory device 1100 and / or the buffer memory 1300 in response to requests from the host 1500. The memory controller 1200 may receive host data from the host 1500 and provide, transmit, or send the host data to the memory device 1100 and / or the buffer memory 1300.

[0034] According to some example embodiments, the memory controller 1200 may include a control unit and a working memory (not shown). The control unit may control the overall operation of the memory controller 1200. For example, the control unit may control the flash translation layer (FTL) to perform an address mapping operation. The control unit may be a commercially available or customized microprocessor.

[0035] According to some example embodiments, the working memory may be a cache memory (e.g., SRAM). The working memory may be used as a buffer memory that can temporarily store data. In some example embodiments, the working memory may be the driving memory of the memory controller 1200. The working memory may drive the FTL.

[0036] According to some example embodiments, the FTL may be firmware or a program for efficiently managing the memory device 1100. Different from a hard disk drive, the memory device 1100 may not support a rewrite function. Therefore, the memory device 1100 may perform the following process while updating data written to a page. First, the memory device 1100 may copy all valid data in the first memory block to which the write page belongs to an empty second memory block. Second, the memory device 1100 may erase the first memory block and make it an empty memory block. The memory device 1100 may perform a large number of page copy operations (e.g., page read operations and / or page write operations) and erase operations while undergoing this process.

[0037] According to some example embodiments, an FTL may be used between a host 1500 and a memory device 1100 to reduce the number of page copy and erase operations. The FTL may perform functions such as an address mapping function, a garbage collection function, and a wear-level function. When a rewrite request is received from the host 1500, the address mapping function may write the corresponding data to another empty page instead of rewriting the original page, thereby reducing additional page copy and block erase operations. To this end, an address mapping table having a specified, specific, or alternatively desired size must be maintained in the working memory and the buffer memory 1300. Through this, the FTL may manage the operation of mapping a logical address received from the host 1500 to a physical address in the memory device 1100.

[0038] According to some example embodiments, the buffer memory 1300 may be connected to the memory controller 1200 through a buffer interface 1203. For example, the buffer memory 1300 may be used to temporarily store data to be stored in or read from the memory device 1100. In some example embodiments, a cache area capable of storing cache data may be allocated to the buffer memory 1300. The buffer memory 1300 may be implemented using DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory), etc. The buffer memory 1300 may be included in the memory device 1100 or the memory controller 1200.

[0039] According to some example embodiments, the host 1500 may include a processor and a host memory (not shown). The processor and the host memory may be connected via an address / data bus. The host 1500 may be a personal digital assistant (PDA), a computer, a digital audio player, a digital camera, and / or a mobile phone, etc., but the example embodiments are not limited thereto. The host memory may be a non-volatile or volatile memory in the form of a cache, ROM (Read Only Memory), PROM (Programmable Read Only Memory), EPROM (Erasable Programmable Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory), flash memory, SRAM, DRAM, etc.

[0040] According to some example embodiments, the host memory may drive multiple software or firmware. For example, the host memory may drive an operating system (OS), applications, a file system, a memory manager, and I / O drivers, etc.

[0041] According to some example embodiments, the memory controller 1200 may include a command generation module 1230. For example, the memory controller 1200 may receive various requests from the host 1500. The command generation module 1230 may generate commands for controlling memory operations of the memory device 1100 based on the requests received from the host 1500. As an example, the command generation module 1230 may set the format of the command CMD.

[0042] According to some example embodiments, the memory device 1100 may include a column decoding circuit 100. For example, the memory device 1100 may receive various commands from the memory controller 1200. During a read operation, the column decoding circuit 100 may decode the read command received from the memory controller 1200 to determine valid data read from the memory cell array 1110.

[0043] Figure 2 is a block diagram showing an example of a memory device according to some example embodiments Figure 1 as shown in. Figure 1 The storage device 1000 may be a flash-based flash storage device. For example, the storage device 1000 may be implemented as an SSD, UFS, and / or a memory card, etc.

[0044] Referring to Figure 1 and Figure 2 , the memory device 1100 may include a memory cell array 1110 and peripheral circuits. The peripheral circuits may include an address decoder 1120, a page buffer circuit 1130, an input / output circuit 1140, a word line voltage generator 1150, and a control logic 1160. The page buffer circuit 1130 may include the column decoding circuit 100. Alternatively, in some example embodiments, the column decoding circuit 100 may be arranged separately from the page buffer circuit 1130 or located between the page buffer circuit 1130 and the input / output circuit 1140.

[0045] According to some example embodiments, the memory cell array 1110 may include a plurality of memory blocks BLK1 to BLKn. Each memory block may be configured as a plurality of pages. Each page may include a plurality of memory cells. Each memory cell may store multi-bit data (e.g., two or more bits). Each memory block may correspond to an erase unit, and each page may correspond to a read and / or write unit.

[0046] According to some example embodiments, the memory cell array 1110 may be formed in a direction perpendicular to the substrate. It should be understood that an element and / or its property (such as structure, surface, direction, etc.) that may be referred to as "vertical", "parallel", "coplanar", etc. relative to other elements and / or their properties may be "vertical", "parallel", "coplanar", etc., or may be "substantially vertical", "substantially parallel", "substantially coplanar" respectively relative to other elements and / or their properties. The gate electrode layer and the insulating layer may be alternately deposited or located on the substrate. It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it may be directly on the other element, or there may also be an intermediate element. In contrast, when an element is referred to as being "directly on" another element, there is no intermediate element. It should also be understood that when an element is referred to as being "on" another element, it may be above, below, or adjacent to (e.g., horizontally adjacent to) the other element. Each memory block (e.g., BLK1) may be connected to one or more string selection lines SSL, a plurality of word lines WL1 to WLm, and one or more ground selection lines GSL. WLk is the selected word line, and the remaining word lines (WL1 to WLk - 1, WLk + 1 to WLm) are unselected word lines.

[0047] According to some example embodiments, the address decoder 1120 may be connected to the memory cell array 1110 through the string selection lines SSL, the ground selection lines GSL, and the word lines WL1 to WLm. The address decoder 1120 may select a word line during a programming operation or a read operation. The address decoder 1120 may receive the word line voltage VWL from the word line voltage generator 1150 and provide, transfer, transmit, or send a programming voltage or a read voltage to the selected word line.

[0048] According to some example embodiments, the page buffer circuit 1130 may be connected to the memory cell array 1110 through the bit lines BL1 to BLz. The page buffer circuit 1130 may temporarily store data to be stored in the memory cell array 1110 or data read from the memory cell array 1110. The page buffer circuit 1130 may include page buffers PB1 to PBz connected to the respective bit lines BL1 to BLz. Each page buffer may include a plurality of latches to store or read multi-bit data.

[0049] According to some example embodiments, the input / output circuit 1140 may be internally connected to the page buffer circuit 1130 through a data line and externally connected to a memory controller through input / output lines IO1 to IOn (e.g., refer to Figure 1, 1200). The input / output circuit 1140 may receive programming data from the memory controller 1200 during a programming operation. In some example embodiments, the input / output circuit 1140 may provide, transfer, or send data read from the memory cell array 1110 to the memory controller 1200 during a read operation.

[0050] According to some example embodiments, the word line voltage generator 1150 may receive internal power from the control logic 1160 and generate the word line voltage VWL required for reading or writing data. The word line voltage VWL may be provided, transferred, or sent to the selected word line sWL or the unselected word line uWL through the address decoder 1120.

[0051] According to some example embodiments, the word line voltage generator 1150 may include a programming voltage generator and a pass voltage generator. The programming voltage generator may generate the programming voltage Vpgm that is provided, transferred, or sent to the selected word line sWL during a programming operation. The pass voltage generator may generate the pass voltage Vpass that is provided, transferred, or sent to the selected word line sWL and the unselected word line uWL.

[0052] According to some example embodiments, the word line voltage generator 1150 may include a read voltage generator and a read pass voltage generator. The read voltage generator may generate the selected read voltage Vrd that is provided, transferred, or sent to the selected word line sWL during a read operation. The read pass voltage generator may generate the read pass voltage Vrdps that is provided, transferred, or sent to the unselected word line uWL. The read pass voltage Vrdps may be a voltage sufficient to turn on the memory cells connected to the unselected word line uWL during a read operation.

[0053] According to some example embodiments, the control logic 1160 may use the command CMD, address ADDR, and control signal CTRL provided, transferred, or sent from the Figure 1 memory controller 1200 shown in to control the operations of the memory device 1100, such as reading, writing, and erasing. The address ADDR may include a block selection address for selecting one memory block, a row address for selecting one page, and a column address for selecting one memory cell.

[0054] Figure 3 is a circuit diagram showing an example of the memory block BLK1 of the memory cell array shown in according to some example embodiments. Refer to Figure 2 shown in the memory cell array of Figure 3, in the storage block BLK1, a plurality of cell strings STR11 to STR8z can be formed between bit lines BL1 to BLz and a common source line CSL. Each cell string includes a string selection transistor SST, a plurality of memory cells MC1 to MCm, and a ground selection transistor GST.

[0055] According to some example embodiments, the string selection transistors SST can be connected to string selection lines SSL1 to SSL8. The ground selection transistors GST can be connected to ground selection lines GSL1 to GSL8. The string selection transistors SST can be connected to bit lines BL1 to BLz, and the ground selection transistors GST can be connected to the common source line CSL.

[0056] According to some example embodiments, the first to m-th word lines WL1 to WLm can be connected to the plurality of memory cells MC1 to MCm in the row direction. The first bit line BL1 to the z-th bit line BLz can be connected to the plurality of memory cells MC1 to MCm in the column direction.

[0057] According to some example embodiments, the first word line WL1 can be placed above the first ground selection line GSL1 to the eighth ground selection line GSL8. The first memory cell MC1 placed at the same height from the substrate can be connected to the first word line WL1. The m-th word line WLm can be placed below the first string selection line SSL1 to the eighth string selection line SSL8. The m-th memory cell MCm placed at the same height from the substrate can be connected to the m-th word line WLm. In a similar manner, the second to the (m - 1)-th memory cells MC2 to MCm - 1 placed at the same height from the substrate can be respectively connected to the second to the (m - 1)-th word lines WL2 to WLm - 1.

[0058] Figure 4 is a circuit diagram showing a cell string selected by the first string selection line SSL1 among the cell strings of the memory block BLK1 shown according to some example embodiments. The 11th to the 1z-th cell strings STR11 to STR1z can be selected by the first string selection line SSL1. The 11th to the 1z-th cell strings STR11 to STR1z can be respectively connected to the first to the z-th bit lines BL1 to BLz. The first to the z-th page buffers PB1 to PBz can be respectively connected to the first to the z-th bit lines BL1 to BLz. Figure 3

[0059] ​According to some example embodiments, the 11th unit string STR11 may be connected to the first bit line BL1 and the common source line CSL. The 11th unit string STR11 may include a string select transistor SST selected by the first string select line SSL1, first to mth memory cells MC1 to MCm connected to the first to mth word lines WL1 to WLm, and a ground select transistor GST selected by the first ground select line GSL1. The 12th unit string STR12 may be connected to the second bit line BL2 and the common source line CSL. The 1zth unit string STR1z may be connected to the zth bit line BLz and the common source line CSL.

[0060] According to some example embodiments, the first word line WL1 and the mth word line WLm may be edge word lines. The second word line WL2 and the m-1th word line WLm-1 may be edge adjacent word lines. The kth word line WLk may be the selected word line sWL. The k-1th word line WLk-1 and the k+1th word line WLk+1 may be adjacent word lines adjacent to the selected word line sWL. When the kth word line WLk is the selected word line sWL, the remaining word lines WL1 to WLk-1 and WLk+1 to WLm may be unselected word lines uWL.

[0061] According to some example embodiments, the first memory cell MC1 and the mth memory cell MCm may be edge memory cells. The second memory cell MC2 and the m-1th memory cell MCm-1 may be edge adjacent memory cells. The kth memory cell MCk may be the selected memory cell sMC. The k-1th memory cell MCk-1 and the k+1th memory cell MCk+1 may be memory cells adjacent to the selected memory cell (hereinafter referred to as adjacent memory cells). When the kth memory cell MCk is the selected memory cell sMC, the remaining memory cells MC1 to MCk-1 and MCk+1 to MCm may be unselected memory cells uMC.

[0062] According to some example embodiments, a set of memory cells selected by one string select line and connected to one word line may be a page. For example, the memory cells selected by the first string select line SSL1 and connected to the kth word line WLk may be a page. For example, eight pages may be configured on the kth word line WLk. Among the eight pages, the page connected to the first string select line SSL1 is the selected page, and the pages connected to the second to eighth string select lines SSL2 to SSL8 are unselected pages.

[0063] Figure 5 is a block diagram showing a Figure 1 memory controller according to some example embodiments. Refer to Figure 5, the memory controller 1200 includes a host interface 1201, a memory interface 1202, a buffer interface 1203, a control unit 1210, a working memory 1220, and / or a command generation module 1230.

[0064] Although not shown in Figure 5 , in some example embodiments, the memory controller 1200 may further include various other components. For example, the memory controller 1200 may further include an ECC circuit or the like. The ECC circuit may generate an error correction code (ECC) to correct failed bits or error bits of the data received from the memory device 1100. According to some example embodiments, each of the memory controller 1200 and the control unit 1210 and / or the command generation module 1230 may include one or more processing circuits or be implemented in one or more processing circuits, such as hardware including logic circuits; a hardware / software combination, such as a processor executing software; or a combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0065] According to some example embodiments, the host interface 1201 may provide an interface between the host 1500 and the memory controller 1200. Standard interfaces include various interface methods, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) card, Multimedia Card (MMC), Embedded Multimedia Card (eMMC), Universal Flash Storage (UFS), Compact Flash (CF) card interface, etc.

[0066] According to some example embodiments, the memory interface 1202 may provide an interface between the memory device 1100 and the memory controller 1200. For example, write data or read data may be transferred / sent to and received from the memory device 1100 through the memory interface 1202. The memory interface 1202 may provide, transfer, or send commands and addresses to the memory device 1100. In some example embodiments, the memory interface 1202 may provide, transfer, or send the data read from the memory device 1100 to the memory controller 1200.

[0067] According to some example embodiments, buffer interface 1203 may provide an interface between buffer memory 1300 and memory controller 1200. For example, data temporarily stored in buffer memory 1300 may be transferred or sent to buffer memory 1300 and received from buffer memory 1300 via buffer interface 1203.

[0068] According to some example embodiments, control unit 1210 may include a central processing unit, a microprocessor, etc., and may control the overall operation of memory controller 1200. Control unit 1210 may drive the firmware loaded in working memory 1220 to control memory controller 1200.

[0069] According to some example embodiments, working memory 1220 may be implemented with various memories (e.g., at least one of a cache memory, DRAM, SRAM, PRAM, and flash memory), but the example embodiments are not limited thereto. Working memory 1220 may drive a flash translation layer (FTL) under the control of control unit 1210.

[0070] According to some example embodiments, FTL may be firmware or a program for efficiently managing memory device 1100. Different from a hard disk, memory device 1100 does not support an overwrite function. Therefore, in order to modify data on a written page, it is necessary to copy all valid data (or valid pages) in the previous block to which the page belongs to another empty block and delete the previous block. This process may perform multiple page copies (reading and writing pages) and erase operations.

[0071] According to some example embodiments, FTL is used between host 1500 and memory device 1100 to reduce the number of page copies and erase operations. FTL may include an address mapping module, a garbage collection module, and / or a wear-leveling module, etc. In some example embodiments, FTL and each of the address mapping module, the garbage collection module, and / or the wear-leveling module may include one or more processing circuits or be implemented in one or more processing circuits, such as hardware including logic circuits; a hardware / software combination, such as a processor executing software; or a combination thereof.

[0072] According to some example embodiments, the address mapping module may perform an address mapping operation on a page-by-page or block-by-block basis. The page address mapping operation is an operation of converting a logical page address received from a file system into a physical page address within memory device 1100. To this end, a page-level address mapping table must be maintained in working memory 1220. The page address mapping operation may provide excellent or improved garbage collection performance, but may require a large address mapping table.

[0073] According to some examples, the garbage collection module may perform garbage collection operations by referring to an address mapping table. For example, to ensure one or more free blocks, the garbage collection module may use the address mapping table to record one or more valid data stored in the source block to a random block, and ensure free blocks by erasing the source block in which all the valid data has been moved.

[0074] According to some example embodiments, the wear module may manage the wear of the memory cells of the memory device 1100. The memory cells may deteriorate due to write and erase operations, etc. The deteriorated memory cells may cause defects. The wear module may manage the programming and erase cycles of the memory cell array 1110 to prevent or reduce the wear of a specific cell region faster than other cell regions. The wear module may control the address mapping module such that the programming and erase times can be equally allocated to the cell regions of the memory cell array 1110.

[0075] According to some example embodiments, the command generation module 1230 may generate commands for controlling the memory operations of the memory device 1100 based on requests received from the host 1500. As an example, the command generation module 1230 may set the format of the commands.

[0076] Figure 6 is a schematic diagram showing a first read mode of a Figure 2 memory device according to some example embodiments. Figure 7 is a schematic diagram showing the configuration of a read command of a first read mode according to Figure 6 according to some example embodiments. Referring to Figure 6 and Figure 7 , the memory device 1100 may perform a read operation RDMA based on the read command RCMD. The memory device 1100 may perform a read operation RDMA based on a page.

[0077] According to some example embodiments, the memory controller 1200 may transmit, provide, or send a read command RCMD to the memory device 1100 based on a read request from the host 1500. For example, Figure 5 the command generation module 1230 of

[0078] may generate a read command RCMD based on the first read mode. As an example, the read command RCMD may include row selection information RS and column selection information CS. Figure 2to page buffers PB1 to PBz. The column decoding circuit 100 may transfer valid data VDATA from the page data PDATA stored in the page buffers PB1 to PBz to the input / output circuit 1140 based on the column selection information CS of the read command RCMD.

[0079] According to some example embodiments, during a read operation RDMA, the memory device 1100 may divide a page into a plurality of sub-pages. The memory device 1100 may output a valid sub-page (or valid data VDATA) corresponding to the read command RCMD among the plurality of sub-pages.

[0080] For example, when a page has a capacity of 16 KB, a page may be divided into four sub-pages SP1, SP2, SP3, and SP4, each having 4 KB. The first sub-page SP1 may start at a first column start position C1. The second sub-page SP2 may start at a second column start position C2. The third sub-page SP3 may start at a third column start position C3. The fourth sub-page SP4 may start at a fourth column start position C4.

[0081] According to some example embodiments, the memory device 1100 may output valid data VDATA including consecutive sub-pages. For example, in Figure 6 during a first read operation RDMA1, the memory device 1100 may output first valid data VDATA1 based on a first read command RD1.

[0082] For example, in Figure 7 the first read command RD1 may include first column selection information CS1. The first column selection information CS1 may include a first column start position C1 as a read start position. Accordingly, the first valid data VDATA1 may include the first sub-page SP1 to the fourth sub-page SP4 after the first column start position C1.

[0083] According to some example embodiments, the memory device 1100 may output valid data VDATA including non-consecutive sub-pages. For example, in Figure 6 during a second read operation RDMA2, the memory device 1100 may output second valid data VDATA2 based on a second read command RD2 and a third read command RD3.

[0084] For example, in Figure 7In this case, the second read command RD2 may include second column selection information CS2. The second column selection information CS2 may include a first column start position C1 as a read start position. The third read command RD3 may include third column selection information CS3. The third column selection information CS3 may include a third column start position C3 as a read start position. Accordingly, the second valid data VDATA2 is the first sub-page SP1 after the first column start position C1, and the third sub-page SP3 and the fourth sub-page SP4 after the third column start position C3. During the second read operation RDMA2, the second sub-page SP2 may be excluded from the second valid data VDATA2.

[0085] According to some example embodiments, the read command RCMD may include a sub-page bitmap SPBM. In the first read mode, the sub-page bitmap SPBM may be disabled. For example, in the first read mode, the sub-page bitmap SPBM may be set to "0". For example, in Figure 7 this case, the first sub-page bitmap SPBM1, the second sub-page bitmap SPBM2, and the third sub-page bitmap SPBM3 may be set to "0".

[0086] As described above, in some example embodiments, the memory device 1100 may perform a read operation according to the first read mode. When performing a read operation in the first read mode, the read command RCMD may include row selection information RS and column selection information CS. However, in some example embodiments, when performing a read operation on valid data VDATA including non-consecutive sub-pages in the first read mode, the memory device 1100 may receive two read commands (e.g., the second read command RD2 and the third read command RD3).

[0087] Figure 8 is a schematic diagram showing a second read mode of a Figure 2 memory device according to some example embodiments. Figure 9 is a schematic diagram showing a configuration of a read command of a second read mode according to some example embodiments according to Figure 8 Reference Figure 8 and Figure 9 , the memory device 1100 may perform a read operation RDMA based on the read command RCMD. The memory device 1100 may perform a read operation RDMA based on a page.

[0088] According to some example embodiments, the memory controller 1200 may transmit, provide, or send the read command RCMD to the memory device 1100 based on a read request from the host 1500. For example, when performing a read operation RDMA corresponding to valid data VDATA including non-consecutive sub-pages, Figure 5The command generation module 1230 can generate a read command RCMD based on the second read mode. For example, the read command RCMD can include row selection information RS, sub-data offset size S_OFS, and sub-page bitmap information SPBM.

[0089] According to some example embodiments, the memory device 1100 can perform a read operation RDMA by decoding the read command RCMD. For example, the address decoder 1120 can select a word line based on the row selection information RS of the read command RCMD. Page data PDATA corresponding to the selected word line can be temporarily stored in Figure 2 the page buffers PB1 to PBz. The column decoding circuit 100 can transfer, provide, or send valid data VDATA among the page data PDATA stored in the page buffers PB1 to PBz to the input / output circuit 1140 based on the sub-data offset size S_OFS and the sub-page bitmap information SPBM of the read command RCMD.

[0090] According to some example embodiments, during the read operation RDMA, the memory device 1100 can divide a page into multiple sub-pages. The memory device 1100 can output valid sub-pages (or valid data VDATA) corresponding to the read command RCMD among the multiple sub-pages.

[0091] For example, when a page has a capacity of 16KB, a page can be divided into four sub-pages SP1, SP2, SP3, and SP4, each with 4KB. The first sub-page SP1 can correspond to the first bitmap M1. The second sub-page SP2 can correspond to the second bitmap M2. The third sub-page SP3 can correspond to the third bitmap M3. The fourth sub-page SP4 can correspond to the fourth bitmap M4.

[0092] According to some example embodiments, when outputting valid data VDATA including consecutive sub-pages, the memory device 1100 can perform the read operation RDMA in the first read mode. For example, in Figure 8 , during the third read operation RDMA3, the memory device 1100 can output the third valid data VDATA3 based on the read command RD.

[0093] According to some example embodiments, when outputting valid data VDATA including non-consecutive sub-pages, the memory device 1100 can perform the read operation RDMA in the second read mode. For example, in Figure 8 and Figure 9 , during the fourth read operation RDMA4, the memory device 1100 can read the fourth valid data VDATA4 based on the sub-data offset size S_OFS and the sub-page bitmap information SPBM.

[0094] For example, inFigure 9 In this case, the bitmap read command MRD may include a sub-data offset size S_OFS and fifth sub-page bitmap information SPBM5. The sub-data offset size S_OFS may be set to 4 KB. The fifth sub-page bitmap information SPBM5 may be indicated as 4-bit information (e.g., 1101) according to the positions of valid sub-pages SP1, SP2, SP3, and SP4.

[0095] Figure 10 is a schematic diagram showing bitmap information corresponding to valid data including non-consecutive sub-pages in a second read mode of a memory device according to some example embodiments. Refer to Figure 2 In, the sub-page bitmap information SPBM may indicate valid sub-pages among sub-pages SP1, SP2, SP3, and SP4 of a page data PDATA. Figure 10 According to some example embodiments, in the second read mode RMODE2, the bitmap read command MRD may include a sub-data offset size S_OFS and sub-page bitmap information SPBM. For example, when a page is divided into four sub-pages SP1, SP2, SP3, and SP4, the first to fourth sub-pages SP1, SP2, SP3, and SP4 may correspond to the first to fourth bitmaps M1, M2, M3, and M4. The sub-page bitmap information SPBM may indicate the positions of valid sub-pages within a page.

[0096]

[0097] Figure 11 Figure 2 is a schematic diagram showing an example of a column decoding circuit according to some example embodiments. Refer to Figure 2 and Figure 11 and

[0098]

[0099] According to some example embodiments, the read mode detector 110 may detect a read mode corresponding to a read command RCMD. For example, when the sub-page bitmap information SPBM is inactive or deactivated (e.g., 0000), the read mode detector 110 may determine the first read mode RMODE1. When the first read mode is detected, the read mode detector 110 may transmit, provide, or send a first-mode column address CA_M1 to the column decoder 130.

[0099] When the sub-page bitmap information SPBM is included in Figure 10When one of the values in the bit map table is detected, the read mode detector 110 may determine the second read mode RMODE2. When the second read mode RMODE2 is detected (e.g., activated), the read mode detector 110 may transmit, provide, or send the sub-data offset size S_OFS and the sub-page bit map information SPBM included in the read command RCMD to the column address calculator 120.

[0100] According to some example embodiments, when receiving the sub-data offset size S_OFS and the sub-page bit map information SPBM from the read mode detector 110, the column address calculator 120 may transmit, provide, or send the second mode column address CA_M2 to the decoder 130. When no signal is received from the read mode detector 110, the column address calculator 120 may not operate.

[0101] According to some example embodiments, when receiving the first mode column address CA_M1, the column decoder 130 may output valid data VDATA including consecutive sub-pages among the page data PDATA stored in the page buffers PB1 to PBz as in Figure 6 the first read operation RDMA1. When receiving the second mode column address CA_M2, the column decoder 130 may output valid data VDATA including non-consecutive sub-pages among the page data PDATA, as shown in Figure 10 the bit map table. For example, as shown in Figure 10 the bit map table, when the sub-page bit map information SPBM is 0101, the first sub-page SP1 and the third sub-page SP3 are output as valid data VDATA. When the sub-page bit map information SPBM is 1001, the first sub-page SP1 and the fourth sub-page SP4 are output as valid data VDATA. When the sub-page bit map information is 1010, the second sub-page SP2 and the fourth sub-page SP4 are output as valid data VDATA. When the sub-page bit map information SPBM is 1011, the first, second, and fourth sub-pages SP1, SP2, SP4 are output as valid data VDATA. When the sub-page bit map information SPBM is 1101, the first, third, and fourth sub-pages SP1, SP3, SP4 are output as valid data VDATA.

[0102] Figure 12 is a schematic diagram showing an example of a read method of a memory device according to some example embodiments. Referring to Figure 2 and Figure 2 as well as Figure 12 the memory device 1100 may perform a read operation RDMA based on the read command RCMD. The read command RCMD may include row selection information RS, a sub-data offset size S_OFS, and / or sub-page bit map information SPBM.

[0103] According to some example embodiments,Figure 5 The command generation module 1230 can generate a read command RCMD including a sub-data offset size S_OFS and sub-page bitmap information SPBM based on a read request from the host 1500. For example, the sub-page bitmap information SPBM can indicate the positions of valid sub-pages within a page. The sub-data offset size S_OFS can indicate the size of a sub-page.

[0104] According to some example embodiments, Figure 2 the column decoding circuit 100 can output valid data VDATA based on the read command RCMD. For example, the column decoding circuit 100 can output sub-pages corresponding to the sub-page bitmap information SPBM as the valid data VDATA, as Figure 12 shown in the bit map table. In Figure 12 this case, the column decoding circuit 100 can output the valid data VDATA through one read command RCMD regardless of whether the sub-pages included in the valid data VDATA are consecutive.

[0105] Figure 13 FIG. is a diagram showing an example embodiment of a column decoding circuit according to some example embodiments of Figure 2 this. Referring to Figure 2 FIG., Figure 12 FIG., Figure 13 and

[0106] According to some example embodiments, the read command decoder 140 can output the sub-data offset size S_OFS and the sub-page bitmap information SPBM based on the read command RCMD. The column address calculator 120 can output the column address CA of the valid sub-page based on the sub-data offset size S_OFS and the sub-page bitmap information SPBM. The column decoder 130 can output the valid data VDATA as shown in the bit map table among the page data PDATA stored in the page buffers PB1 to PBz based on the column address CA. Figure 12 FIG.

[0107] Figure 14 FIG. is a schematic diagram of a look-up table showing an example of a read method of a memory device according to some example embodiments of Figure 2 this. Referring to Figure 2 FIG. Figure 14 and Figure 13 FIG., Figure 14 the column decoding circuit 100 of

[0108] According to some example embodiments, the sub-page bitmap information SPBM included in the read command RCMD can be based on Figure 14The lookup table is converted into a valid data bitmap (VDATA bitmap). For example, the sub-page bitmap information SPBM may be matched with the information about valid sub-pages. The information about valid sub-pages may include a first address, a second address, a valid data size (VDATA size), a valid data bitmap (VDATA bitmap), and / or valid data VDATA. The first address and the second address may indicate the starting position of the valid sub-page. The valid data size (VDATA size) may represent the total data size included in the valid data VDATA.

[0109] According to the inventive concept, the read operation time can be shortened by performing a read operation on non-consecutive sub-pages within a page by transmitting, providing, or sending a single read command.

[0110] Although the inventive concept has been described with reference to some exemplary embodiments of the inventive concept, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the inventive concept as set forth in the appended claims.

Claims

1. A memory device, comprising: A memory cell array including a plurality of memory cells; A page buffer circuit connected to the plurality of memory cells via bit lines and configured to read data stored in the plurality of memory cells in units of pages; And A column decoding circuit configured to output non - consecutive sub - pages among the page data stored in the page buffer circuit as valid data during a read operation based on sub - page bitmap information included in a read command.

2. The memory device according to claim 1, wherein The read command is configured to include sub - page offset information, and The column decoding circuit is configured to determine each of the non - consecutive sub - pages based on the sub - page bitmap information and the sub - page offset information.

3. The memory device according to claim 1, wherein, In a first read mode, the column decoding circuit is configured to: when the sub - page bitmap information is deactivated, output at least one consecutive sub - page from a column address included in the read command as valid data.

4. The memory device according to claim 1, wherein, In a second read mode, the column decoding circuit is configured to: when the sub - page bitmap information is activated, output the non - consecutive sub - pages at positions corresponding to the sub - page bitmap information as valid data.

5. The memory device according to claim 1, wherein, The column decoding circuit is configured to: When the sub - page bitmap information is deactivated, output a first - mode column address based on the column address included in the read command in the first read mode, or When the sub - page bitmap information is activated, output the sub - page bitmap information and sub - page offset information included in the read command in the second read mode.

6. The memory device according to claim 5, wherein, In the first read mode, the column decoding circuit is configured to output at least one consecutive sub - page of the page data based on the first - mode column address.

7. The memory device according to claim 5, wherein, In the second read mode, the column decoding circuit is configured to output a second - mode column address based on the sub - page bitmap information and the sub - page offset information.

8. The memory device according to claim 7, wherein, In the second read mode, the column decoding circuit is configured to output the non - consecutive sub - pages of the page data based on the second - mode column address.

9. A memory device, comprising: A memory cell array including a plurality of memory cells; An address decoder connected to the plurality of memory cells via word lines and configured to select one word line based on a read command; A page buffer circuit connected to the plurality of memory cells via bit lines and configured to temporarily store page data stored in the memory cells connected to the selected word line; And A column decoding circuit configured to output at least one sub - page selected among the page data based on sub - page offset information and sub - page bitmap information included in the read command as valid data.

10. The memory device according to claim 9, wherein The page data is configured to be divided into a plurality of sub - pages, and The sub - page bitmap information is configured as a plurality of bits.

11. The memory device according to claim 10, wherein, Each of the bits of the sub - page bitmap information is configured to indicate the position of each of the sub - pages.

12. The memory device according to claim 9, wherein, The sub - page offset information is configured to indicate the size of the at least one sub - page.

13. The memory device according to claim 9, wherein, The column decoding circuit is configured to output the sub - page offset information and the sub - page bitmap information based on the read command.

14. The memory device according to claim 13, wherein, The column decoding circuit is configured to generate column addresses corresponding to the at least one sub - page based on the sub - page offset information and the sub - page bitmap information.

15. The memory device according to claim 14, wherein, The column decoding circuit is configured to output the at least one sub - page of the page data based on the column addresses.

16. The memory device according to claim 9, wherein, The column decoding circuit is configured to store a look - up table in response to the sub - page bitmap information, the look - up table including a valid data bitmap indicating the positions of the at least one sub - page.

17. The memory device according to claim 16, wherein, The look - up table further includes a first start address, a second start address, and a valid data size corresponding to the at least one sub - page.

18. A storage device, comprising: A memory device including a plurality of memory cells; And A memory controller configured to send a read command including sub - page bitmap information to the memory device to read data stored in the plurality of memory cells, The memory device is configured to select word lines based on the read command and output non - consecutive sub - pages among the page data stored in the memory cells connected to the selected word lines as valid data based on the sub - page bitmap information.

19. The storage device according to claim 18, wherein, In a first read mode, the memory device is configured to output at least one consecutive sub - page as valid data from a column address included in the read command when the sub - page bitmap information is deactivated.

20. The storage device according to claim 18, wherein, In a second read mode, the memory device is configured to output non - consecutive sub - pages at positions corresponding to the sub - page bitmap information as valid data when the sub - page bitmap information is activated.

Images