Manufacturing method of semiconductor structure and semiconductor structure
By forming a protective layer covering only the first region in the trench, the problem of complex doping and etching in specific regions in semiconductor manufacturing is solved, the performance of the semiconductor structure is improved and the processing difficulty is reduced.
Patent Information
- Application Number
- CN202510525612.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-24
- Publication Date
- 2025-07-18
AI Technical Summary
In semiconductor manufacturing, as device size shrinks and structural complexity increases, doping and etching processes in specific regions become complicated and the results are not ideal.
A protective layer covering only the first region is formed in the trench, and by precisely adjusting the diffusion path of the target element, the portion of the stacked structure corresponding to the first region is avoided to be doped, forming a completely separate transistor.
It improves the performance of the semiconductor structure, reduces the difficulty of subsequent processing processes, and realizes directional doping and precise formation of transistors.
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Figure CN120341114A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and more particularly to a method for fabricating a semiconductor structure and a semiconductor structure. Background Art
[0002] In the process of the rapid advancement of semiconductor manufacturing technology towards three-dimensional structures (such as FinFET, GAA transistors, and 3D NAND), doping or etching of a specific region is often involved.
[0003] However, with the continuous miniaturization of device dimensions and the increase in structural complexity, the processes of doping and etching a specific region are becoming increasingly complex, and the effects are not ideal. Summary of the Invention
[0004] The following is an overview of the subject matter described in detail in the present disclosure. This overview is not intended to limit the scope of protection of the claims.
[0005] In a first aspect of the present disclosure, there is provided a method for fabricating a semiconductor structure, including:
[0006] Providing a substrate on which a stacked structure is formed;
[0007] Forming a plurality of trenches arranged in an array in the stacked structure, and the inner wall surface of each trench includes a first region and a second region;
[0008] Forming a protective layer that only covers the first region;
[0009] Performing a doping process on the second region;
[0010] Removing a part of the stacked structure corresponding to the first region, and retaining a part of the stacked structure corresponding to the second region as a channel region.
[0011] In some embodiments, the forming of the protective layer includes:
[0012] Forming an initial protective layer to cover the entire inner wall surface of the trench;
[0013] Performing at least one etching process on the initial protective layer until the second region is exposed, and the first region is covered with the etched residue of the initial protective layer to form the protective layer, wherein during the etching process, the etching rate of the part of the initial protective layer covering the second region is greater than the etching rate of the part of the initial protective layer covering the first region.
[0014] In some embodiments, the method for fabricating the semiconductor structure includes:
[0015] The first region includes a first sub-region and a second sub-region that are oppositely arranged in a first direction, the second region includes a third sub-region and a fourth sub-region that are oppositely arranged in a second direction, there is a first distance between the first sub-region and the second sub-region in the first direction, there is a second distance between the third sub-region and the fourth sub-region in the second direction, the first distance is greater than the second distance, and there is a preset included angle between the first direction and the second direction;
[0016] The etching rate of the etching agent during the etching process in the second direction is greater than that in the first direction, so that the etching rate of the part of the initial protective layer covering the second region is greater than the etching rate of the part of the initial protective layer covering the first region.
[0017] In some embodiments, the at least one etching treatment of the initial protective layer includes:
[0018] In each etching treatment, the initial protective layer is etched with an etching agent under a preset pressure, and the by-products generated by the etching are removed;
[0019] Wherein, the etching agent includes at least one of elemental fluorine, fluorine-containing mixture, and organic fluoride.
[0020] In some embodiments, the etching agent includes hydrogen fluoride gas and ammonia gas;
[0021] The range of the preset pressure is 60 to 110 microns of mercury; and / or, the pressure range of the hydrogen fluoride gas is 20 to 30 microns of mercury; and / or, the pressure range of the ammonia gas is 20 to 30 microns of mercury.
[0022] In some embodiments, the forming of the initial protective layer covering all inner wall surfaces of the trench includes:
[0023] The initial protective layer is formed, and the initial protective layer covers the top surface of the stacked structure and the inner wall surfaces of the trench, and the inner wall surfaces include the side wall surfaces and the bottom surface of the trench.
[0024] In some embodiments, the at least one etching treatment of the initial protective layer further includes:
[0025] Removing the initial protective layer covering the bottom surface of the trench and the top surface of the stacked structure to expose the top surface of the stacked structure and the bottom surface of the trench.
[0026] In some embodiments, the doping treatment of the second region includes:
[0027] A doped layer is formed, and the doped layer covers at least the target region and the protective layer, where the target region includes the bottom surface of the trench and the second region;
[0028] An annealing process is performed to diffuse the target element contained in the doped layer into the target region for doping treatment.
[0029] In some embodiments, the method for manufacturing the semiconductor structure is characterized in that after performing the annealing process, it further includes:
[0030] The doped layer is removed to expose the second region and the bottom surface of the sidewall of the trench after doping treatment, and the protective layer.
[0031] In some embodiments, the doped layer includes at least one of a boron-containing compound layer and a boron elemental layer, and the target element includes a boron element.
[0032] In some embodiments, it further includes:
[0033] A word line is formed, and the word line is located on opposite sides of the channel region in the second direction, where the second direction is the arrangement direction of the plurality of trenches;
[0034] A first source / drain region and a second source / drain region are formed, and the first source / drain region and the second source / drain region are respectively located on opposite sides of the channel region in the first direction. The first direction has a preset included angle with the second direction and is perpendicular to the thickness direction of the substrate;
[0035] A storage capacitor and a bit line are formed, and the storage capacitor and the bit line are respectively connected to the first source / drain region and the second source / drain region.
[0036] In some embodiments, the stacked structure includes a plurality of active layers and a plurality of sacrificial layers alternately arranged along the thickness direction of the substrate;
[0037] The forming of the plurality of trenches arranged in an array includes: etching from the top surface of the stacked structure towards the substrate direction to form a plurality of trenches in the stacked structure, and the trenches expose a part of the top surface of the substrate.
[0038] According to a second aspect of the present disclosure, there is provided a semiconductor structure formed by using the method for manufacturing the semiconductor structure as described in the first aspect. The semiconductor structure includes:
[0039] A substrate, on which a stacked structure is provided. The stacked structure includes a plurality of active regions, and the plurality of active regions are spaced apart along the second direction and the thickness direction of the substrate; the active region includes a channel region and a first source / drain region and a second source / drain region respectively disposed on both sides of the channel region in the first direction;
[0040] Word lines, extending along the thickness direction of the substrate, and a plurality of the word lines are arranged at intervals along the second direction and are located on opposite sides of the channel region in the second direction;
[0041] Bit lines, extending along the second direction, and a plurality of the bit lines are arranged at intervals along the thickness direction of the substrate and are connected to the second source / drain regions of the plurality of active regions;
[0042] Storage capacitors, and a plurality of the storage capacitors are respectively connected to the first source / drain regions of the plurality of active regions in one-to-one correspondence;
[0043] Wherein, a preset included angle exists between the first direction and the second direction, and both are perpendicular to the thickness direction of the substrate.
[0044] In the manufacturing method of the semiconductor structure provided by the present disclosure, by forming a protective layer covering only the first region in the trench, the protective layer can block target elements to prevent the part of the stacked structure corresponding to the first region from being doped, resulting in the first region being easily removed in subsequent steps, thereby forming completely separated transistors. By precisely controlling the diffusion path of the target elements, directional doping is achieved, which is beneficial to improving the performance of the semiconductor structure and reducing the difficulty of subsequent processing technology.
[0045] Other aspects can be understood after reading and understanding the drawings and the detailed description. BRIEF DESCRIPTION OF THE DRAWINGS
[0046] The drawings incorporated into the specification and constituting a part of the specification illustrate embodiments of the present disclosure and, together with the description, are used to explain the principles of the embodiments of the present disclosure. In these drawings, like reference numerals are used to represent like elements. The drawings in the following description are some embodiments of the present disclosure, not all embodiments. For those skilled in the art, other drawings can be obtained based on these drawings without creative efforts.
[0047] Figure 1 is a flowchart of a manufacturing method of a semiconductor structure shown according to an exemplary embodiment;
[0048] Figure 2 is a flowchart of a manufacturing method of a semiconductor structure shown according to an exemplary embodiment;
[0049] Figure 3 is a flowchart of a manufacturing method of a semiconductor structure shown according to an exemplary embodiment;
[0050] Figure 4 is a flowchart of a manufacturing method of a semiconductor structure shown according to an exemplary embodiment;
[0051] Figure 5Schematic diagram of forming a substrate and a stacked structure of a semiconductor structure shown according to an exemplary embodiment;
[0052] Figure 6 Top view of the semiconductor structure after forming trenches shown according to an exemplary embodiment;
[0053] Figure 7 Is Figure 6 Cross-sectional view in the a1-a1 direction in;
[0054] Figure 8 Is Figure 6 Cross-sectional view in the b1-b1 direction in;
[0055] Figure 9 Top view of the semiconductor structure after forming an initial protective layer shown according to an exemplary embodiment;
[0056] Figure 10 Is Figure 9 Cross-sectional view in the a2-a2 direction in;
[0057] Figure 11 Is Figure 9 Cross-sectional view in the b2-b2 direction in;
[0058] Figure 12 Top view of the semiconductor structure after forming a protective layer shown according to an exemplary embodiment;
[0059] Figure 13 Is Figure 12 Cross-sectional view in the a3-a3 direction in;
[0060] Figure 14 Is Figure 12 Cross-sectional view in the b3-b3 direction in;
[0061] Figure 15 Top view of the semiconductor structure after doping treatment shown according to an exemplary embodiment;
[0062] Figure 16 Is Figure 15 Cross-sectional view in the a4-a4 direction in;
[0063] Figure 17 Is Figure 15 Cross-sectional view in the b4-b4 direction in;
[0064] Figure 18 Top view of the semiconductor structure after removing the doped layer shown according to an exemplary embodiment;
[0065] Figure 19 Top view of the semiconductor structure after removing a part of the stacked structure shown according to an exemplary embodiment;
[0066] Figure 20 is a top view after forming an initial word line structure of a semiconductor structure shown according to an exemplary embodiment;
[0067] Figure 21 is a top view after forming a word line structure of a semiconductor structure shown according to an exemplary embodiment;
[0068] Figure 22 is a schematic diagram of a semiconductor structure shown according to an exemplary embodiment.
[0069] Reference numerals:
[0070] 10, Substrate;
[0071] 20, Stacked structure; 20a, Active layer; 20b, Sacrificial layer; 21, Trench; 22, First region; 221, First sub-region; 222, Second sub-region; 23, Second region; 231, Third sub-region; 232, Fourth sub-region; 24, Channel region; 25, First source / drain region; 26, Second source / drain region; 27, Lightly doped region;
[0072] 30, Protective layer; 30’, Initial protective layer;
[0073] 40, Doped layer;
[0074] 50, Word line; 50’, Initial word line structure; 51, Gate dielectric layer; 51’, Gate dielectric material layer; 52, Gate conductive layer; 52’, Gate conductive material layer; 53, Gate isolation layer; 53’, Gate isolation material layer; 54, Sidewall;
[0075] 60, Bit line;
[0076] 70, Storage capacitor. Detailed implementation manners
[0077] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Apparently, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present disclosure without creative efforts shall fall within the protection scope of the present disclosure. It should be noted that, without conflict, the embodiments in the present disclosure and the features in the embodiments may be combined with each other arbitrarily.
[0078] To improve the problems existing in the related art, embodiments of the present disclosure provide a method for manufacturing a semiconductor structure and a semiconductor structure. The manufacturing method includes: providing a substrate on which a stacked structure is formed; forming a plurality of trenches arranged in an array in the stacked structure, and the inner wall surface of each trench includes a first region and a second region; forming a protective layer that only covers the first region; doping the second region; removing the part of the stacked structure corresponding to the first region, and retaining the part of the stacked structure corresponding to the second region as the channel region. In the present disclosure, by forming a protective layer that only covers the first region in the trench, the protective layer can block target elements to prevent the part of the stacked structure corresponding to the first region from being doped, resulting in the first region being easily removed in subsequent steps, thereby forming completely separated transistors. While maintaining the advantages of anisotropic etching, directional doping is achieved by precisely controlling the diffusion path of the target elements, which is beneficial to improving the performance of the semiconductor structure and reducing the difficulty of subsequent processing technology.
[0079] In an exemplary embodiment of the present disclosure, embodiments of the present disclosure provide a method for manufacturing a semiconductor structure. The semiconductor structure manufactured by the manufacturing method provided in this embodiment includes, but is not limited to, a dynamic random access memory (DRAM), a static random access memory (SRAM), a non-volatile memory, etc.
[0080] As Figure 1 shown, the method for manufacturing the semiconductor structure includes the following steps:
[0081] Step S110: Provide a substrate on which a stacked structure is formed.
[0082] In this step, as Figure 5 shown, the substrate 10 serves as a support platform for the semiconductor structure to support other structures and functional layers of the semiconductor structure. In this embodiment, the substrate 10 is taken as a silicon (Si) substrate as an example for illustration. It can be understood that the material of the substrate 10 includes, but is not limited to, silicon (Si), such as it can also be any one of gallium nitride (GaN), gallium arsenide (GaAs), silicon carbide (SiC), and silicon on insulator (SOI). The appropriate substrate 10 material can be selected according to performance requirements, cost, and process compatibility to achieve a balance between semiconductor performance and economic benefits.
[0083] As Figure 5 shown, a stacked structure 20 is formed on the substrate 10, and the stacked structure 20 is composed of at least two material layers along the thickness direction of the substrate 10 ( Figure 5Alternately stacked in the z - direction (as shown), in this embodiment, various material layers can be alternately formed on the top surface of the substrate 10 by processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), epitaxial growth, etc., to form the stacked structure 20.
[0084] Different material layers in the stacked structure 20 can have different functions. For example, some material layers can be used to form semiconductor structures, and some material layers, as temporary supports during the manufacturing process, will ultimately be removed. In one example, referring to Figure 5 , the stacked structure 20 includes a plurality of active layers 20a and a plurality of sacrificial layers 20b alternately arranged along the thickness direction of the substrate 10. Among them, the active layer 20a can be used to form the channel region 24, source - drain regions, etc. The material of the active layer 20a can be the same as that of the substrate 10, which will not be elaborated here. The sacrificial layer 20b, as a temporary support structure, will ultimately be removed or replaced by other structures in the subsequent process. The material of the sacrificial layer 20b only needs to have a high etching selectivity ratio, thermal stability, and low stress with respect to the material of the active layer 20a. The material of the sacrificial layer 20b includes, but is not limited to, silicon germanide (SiGe), silicon dioxide (SiO2), silicon nitride (Si3N4), polysilicon (Poly - Si), etc.
[0085] By forming the stacked structure 20 on the substrate 10, a three - dimensional (3D) semiconductor structure can be fabricated in the subsequent process to meet the requirements of high - density integration.
[0086] Step S120: Form a plurality of trenches arranged in an array in the stacked structure. The inner wall surface of each trench includes a first region and a second region.
[0087] In this step, referring to Figures 5 to 8 , a part of the material of the stacked structure 20 can be removed along the thickness direction of the substrate 10 ( Figure 5 the z - direction as shown) to form a plurality of trenches 21 arranged in an array in the stacked structure 20. In this embodiment, processes such as photolithography and etching can be used to remove a part of the structure of the stacked structure 20 from the top surface of the stacked structure 20 towards the substrate 10. The region where the material of the stacked structure 20 is removed forms the trench 21, and the trench 21 can expose a part of the top surface of the substrate 10. In this embodiment, the cross - sectional shape of the trench 21 is not overly limited. For example, it can be a racetrack shape, a rectangle, an ellipse, a rhombus, etc.
[0088] Referring to Figure 6 , a partial region of the substrate 10 and the stacked structure 20 is shown. In this region, the plurality of trenches 21 arranged in an array are along the second direction ( Figure 5The inner wall surfaces of each trench 21 are provided at intervals in the y direction (as shown), and the inner wall surface of each trench 21 includes a first region 22 and a second region 23. The part of the stacked structure 20 facing the second region 23 can be used to form a channel region 24, and the part of the stacked structure 20 facing the first region 22 needs to be removed in a subsequent process to separate the multiple channel regions 24.
[0089] Step S130: Form a protective layer that only covers the first region.
[0090] In this step, refer to Figures 12 to 14 , the protective layer 30 is formed in the trench 21 and only covers the first region 22 of the trench 21. The protective layer 30 can provide protection for the part of the stacked structure 20 corresponding to the first region 22. In one example, the material of the protective layer 30 can be an oxide such as silicon dioxide.
[0091] The protective layer 30 that only covers the first region 22 can be formed in any of the following ways. For example, an initial protective layer 30' (detailed later) is formed on the entire side wall surface of the trench 21, and the initial protective layer 30' covering the second region 23 is directionally removed, and the remaining initial protective layer 30' covering the first region 22 forms the protective layer 30. Another example is to fill the trench 21 with photoresist, perform local exposure and development on the photoresist, and then remove part of the photoresist (for example, remove the structures at both ends of the photoresist in the first direction) so that the first region 22 of the trench 21 is exposed, and then a protective material is filled in the area where the photoresist is removed to form the protective layer 30.
[0092] Step S140: Perform doping treatment on the second region.
[0093] In this step, a target element (i.e., a doping element) can be introduced into the trench 21, and the target element can diffuse into the stacked structure 20 to achieve doping. Among them, refer to Figures 9 to 11 , since the first region 22 is covered with the protective layer 30, and the protective layer 30 blocks the incorporation and diffusion of the target element, the target element in the trench 21 can only be incorporated into the stacked structure 20 through the second region 23, so as to perform doping treatment on the second region 23 directionally. In this embodiment, the target element includes but is not limited to phosphorus (P), arsenic (As), boron (B), etc.
[0094] Step S150: Remove the part of the stacked structure corresponding to the first region, and retain the part of the stacked structure corresponding to the second region as the channel region.
[0095] In this step, refer to Figure 12 , Figure 18 and Figure 19, processes such as photolithography and etching can be used to directionally remove the part of the stacked structure 20 corresponding to the first region 22, and at least the stacked structure 20 corresponding to the second region 23 is retained. The part of the stacked structure 20 corresponding to the second region 23 can form the channel region 24 because of the doping process.
[0096] Refer to Figure 12 and Figure 19 , based on the fact that the stacked structure 20 not affected by doping is easily removed by specific means. In this embodiment, a protective layer 30 covering only the first region 22 is formed in the trench 21. The protective layer 30 can block the target elements to prevent the part of the stacked structure 20 corresponding to the first region 22 from being affected by doping and becoming difficult to remove, so as to facilitate the effective removal of the part of the stacked structure 20 corresponding to the first region 22 to form multiple separated transistors. Exemplarily, refer to Figure 19 , in the semiconductor structure fabricated by the manufacturing method provided in this embodiment, the projected pattern of the region between adjacent channel regions 24 on the substrate 10 can be a rounded rectangle or a rectangle.
[0097] In the embodiments of the present disclosure, by forming a protective layer covering only the first region in the trench, the protective layer can block the target elements to prevent the part of the stacked structure corresponding to the first region from being doped, resulting in the first region being easily removed in subsequent steps, thus forming completely separated transistors. While maintaining the advantages of anisotropic etching, directional doping is achieved by precisely controlling the diffusion path of the target elements, which is beneficial to improving the performance of the semiconductor structure and reducing the difficulty of subsequent processing technology.
[0098] In an exemplary embodiment, this embodiment further illustrates step S130 in the foregoing embodiment. As Figure 2 shown, forming the protective layer 30 may include the following steps:
[0099] Step S210: Form an initial protective layer covering all inner wall surfaces of the trench.
[0100] In this step, refer to Figures 9 to 11 , and in combination with Figures 6 to 8 , processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD) can be used to form an initial protective layer 30' covering all inner wall surfaces of the trench 21.
[0101] Step S220: Perform at least one etching process on the initial protective layer until the second region is exposed, and the initial protective layer with etching residues covers the first region to form a protective layer.
[0102] In this step, referring to Figures 9 to 14 , during the etching process of the initial protective layer 30', the etching rates of different regions of the initial protective layer 30' are different. Among them, the etching rate of the part of the initial protective layer 30' covering the second region 23 is greater than that covering the first part. It can be understood that by adjusting parameters such as the etching duration and the number of etching times, it is possible to remove the initial protective layer 30' covering the second region 23 to expose the second region 23, while the initial protective layer 30' covering the first region 22 is not completely removed, and the remaining initial protective layer 30' covering the first region 22 forms the protective layer 30.
[0103] In some embodiments, the shape of the trench 21 affects the etching rates of the etchant in different directions, so that the initial protective layer 30' covering the first region 22 can be retained after the etching process.
[0104] Exemplarily, referring to Figure 6 , the first region 22 of the trench 21 includes a first sub-region 221 and a second sub-region 222 oppositely arranged in the first direction ( Figure 5 the x direction shown in Figure 5 ), the second region 23 includes a third sub-region 231 and a fourth sub-region 232 oppositely arranged in the second direction (
[0105] the y direction shown in
[0106] Figure 5 ). There is a first distance between the first sub-region 221 and the second sub-region 222, and a second distance between the third sub-region 231 and the fourth sub-region 232. The first distance is greater than the second distance, and there is a preset angle between the first direction and the second direction. The preset angle can be, for example, 90°.
[0105] It can be understood that when the etchant is introduced into the trench 21 and diffuses in the first direction and the second direction, affected by the aspect ratio of the trench 21, the movement rate of the etchant in the second direction is greater than that in the first direction, and the distance that the etchant moves in the second direction to contact the initial protective layer 30' is less than that in the first direction. This makes the contact frequency of the etchant with the initial protective layer 30' in the second direction greater than that in the first direction. As a result, the etching rate of the etchant on the initial protective layer 30' covering the second region 23 is greater than that on the initial protective layer 30' covering the first region 22, so that only the initial protective layer 30' covering the second region 23 is removed, and the remaining initial protective layer 30' covering the first region 22 forms the protective layer 30.
[0106] Exemplarily, the etching rate ratio of the etchant in the second direction to the first direction is 1.1:1 to 3:1. Performing 1-5 etching processes can remove the initial protective layer 30' covering the second region 23 and retain the initial protective layer 30' of the first region 22. In one example, the etching rate ratio is 2:1 and the number of etching processes is 3 times.
[0107] In this embodiment, by setting the shape of the trench 21, for example, by adjusting the aspect ratio of the trench 21, the movement speed of the etchant in different directions in the trench 21 is controlled, so as to change the etching rate of the etchant at different positions of the initial protective layer 30', thereby achieving the removal of only the initial protective layer 30' covering the second region 23.
[0108] Among them, in the previous embodiment, in step S220, when performing at least one etching process on the initial protective layer 30', each etching process may include the following steps:
[0109] Step S221: In each etching process, the initial protective layer is etched with an etchant under a preset pressure, and the by-products generated by the etching are removed.
[0110] When using an etchant to etch the initial protective layer 30', the etchant will react with the initial protective layer 30' to generate by-products. The by-products may deposit on the etching surface to form a physical barrier, thereby hindering the contact between the etchant and the initial protective layer 30' and resulting in a decrease in the etching rate. In addition, the by-products attached to the inner wall surface of the trench 21 may also damage the perpendicularity of the trench 21, affecting the shape and structural reliability of the final product. Therefore, it is necessary to remove the by-products in time after each etching.
[0111] In this embodiment, the by-products formed can be determined according to the materials of the etchant and the protective layer 30, and then corresponding physical and chemical methods can be selected for removal according to the characteristics of the by-products.
[0112] In some embodiments, the etchant includes at least one of elemental fluorine, fluorine-containing mixtures, and organic fluorides. For example, any one of elemental fluorine, fluorine-containing mixtures, or organic fluorides can be used alone. For another example, any two can be mixed, and for another example, all three can be mixed. Elemental fluorine includes but is not limited to fluorine gas (F2), fluorine-containing mixtures include but are not limited to hydrogen fluoride (HF), a mixture of hydrogen fluoride and water, ammonium bifluoride (NH4F), nitrogen trifluoride (NF3), and sulfur hexafluoride (SF6), and organic fluorides include but are not limited to trifluoroacetic acid (C2HF3O2).
[0113] In one example, the protective layer 30 is made of an oxide (such as silicon dioxide), and a mixture formed by hydrogen fluoride gas and ammonia gas can be selected as the etchant. The preset pressure in the reaction chamber is 60-110 microns of mercury, wherein the pressure of the hydrogen fluoride gas is 20-30 microns of mercury, and the pressure of the ammonia gas is 20-30 microns of mercury. In some alternative embodiments, while using the etchant to remove the protective layer 30, a protective gas (such as an inert gas like argon) can also be introduced into the trench 21. The protective gas can purge the unreacted residual gas and carry away the by-products (such as silicon tetrafluoride, ammonium hexafluorosilicate, etc.) that may be generated during the reaction. Additionally, the etching reaction rate can be controlled by controlling the partial pressure of the etchant and the partial pressure of the protective gas. For example, increasing the partial pressure of the protective gas can reduce the etching reaction rate. In one example, the pressure of argon can be 25-30 microns of mercury. The advantage of using gas etching is that the etching selectivity is relatively high and the damage to the sidewalls after etching is relatively small.
[0114] During the etching process, excessive hydrogen fluoride gas reacts with silicon dioxide to form hexafluorosilicic acid:
[0115] SiO2 + 5HF → H2SiF6 + 2H2O
[0116] Hexafluorosilicic acid reacts with ammonia gas to form ammonium hexafluorosilicate:
[0117] H2SiF6 + 2NH3 → (NH4)2SiF6
[0118] The methods for removing ammonium hexafluorosilicate include, but are not limited to, heating, dissolving with an alkaline solution, etc.
[0119] Among them, in the foregoing embodiment, step S210, forming the initial protective layer 30' to cover all the inner wall surfaces of the trench 21, may include the following steps:
[0120] Step S211, forming the initial protective layer. The initial protective layer covers the top surface of the stacked structure and the inner wall surfaces of the trench. The inner wall surfaces include the side wall surfaces and the bottom surface of the trench.
[0121] In this step, referring to Figures 9 to 11 , for example, a deposition process can be used to form the initial protective layer 30' on the stacked structure 20. The initial protective layer 30' covers the top surface of the stacked structure 20 and the inner wall surfaces of the trench 21. The inner wall surfaces of the trench 21 include the side wall surfaces (the first region 22 and the second region 23) and the bottom surface of the trench 21.
[0122] Among them, in the foregoing embodiment, when performing at least one etching treatment on the initial protective layer 30' in step S220, the following steps can also be included:
[0123] Step S222: Remove the initial protective layer covering the bottom surface of the trench and the top surface of the stacked structure, exposing the top surface of the stacked structure and the bottom surface of the trench.
[0124] In this step, referring to Figures 12 to 14 , processes such as etching and grinding can be used to remove the portions of the initial protective layer 30' covering the bottom surface of the trench 21 and the top surface of the stacked structure 20. By removing the above structures of the initial protective layer 30', it is convenient to form a uniformly filled doping layer 40 (detailed later) during subsequent doping processing, reducing or avoiding voids in the doping layer 40 to improve the doping effect.
[0125] In some embodiments, when the initial protective layer 30' is etched at least once using an etchant, the aforementioned structures of the initial protective layer 30' can be removed, thereby only retaining the initial protective layer 30' covering the first region 22 to form the protective layer 30.
[0126] In an exemplary embodiment, this embodiment further illustrates step S140 in the foregoing embodiment. As Figure 3 shown, doping the second region 23 may include the following steps:
[0127] Step S310: Form a doping layer that covers at least the target region and the protective layer.
[0128] In this step, processes such as deposition and epitaxial growth can be used to form a doping layer 40 covering the target region and the protective layer 30. In one embodiment, the doping layer 40 includes, but is not limited to, a boron-containing compound layer, such as borosilicate glass (BSG) and borophosphosilicate glass (BPSG).
[0129] It should be noted that when the topmost structure of the stacked structure 20 is the active layer 20a, after forming the doping layer 40, processes such as etching and grinding can be used to remove a portion of the doping layer 40 to expose the top surface of the portion of the stacked structure 20 corresponding to the first region 22, thereby preventing the target element in the doping layer 40 from entering the portion of the stacked structure 20 corresponding to the first region 22. In some alternative embodiments, a mask layer can be pre-formed on the top surface of the stacked structure 20 before forming the doping layer 40. The material of the mask layer can be the same as or different from that of the sacrificial layer 20b. When the material of the mask layer is the same as that of the sacrificial layer, that is, the topmost structure of the stacked structure 20 is the sacrificial layer 20b.
[0130] In another embodiment, an inclined ion implantation method can also be used to replace the formation of the doping layer, thereby doping the portion of the stacked structure corresponding to the first region 22, and the doping element includes boron.
[0131] Step S320: Perform annealing treatment to cause the target elements contained in the doping layer to diffuse into the target region for doping treatment.
[0132] In this step, the target elements (i.e., doping elements) contained in the doping layer 40 include boron elements. By performing annealing treatment on the doping layer 40, boron atoms can migrate to lattice substitution sites to form electroactive doping, and repair the lattice structure damaged by doping or ion implantation in the stacked structure 20 to reduce the degree of defects. Moreover, by adjusting the annealing parameters, the diffusion depth and concentration gradient of boron elements can also be adjusted to improve the electrical performance and reliability of the channel region 24.
[0133] Among them, after performing the annealing treatment, the manufacturing method of the semiconductor structure may further include:
[0134] Step S330: Remove the doping layer to expose the second region and the bottom surface of the sidewall of the trench after doping treatment, and the protective layer.
[0135] In this step, referring to Figures 15 to 18 , processes such as wet etching, dry etching, and selective atomic layer etching can be used to remove the doping layer 40 to expose the second region 23 and the bottom surface of the sidewall of the trench 21 after doping treatment.
[0136] In some embodiments, in combination with Figure 15 and Figure 18 , if the doping layer 40 is no longer needed in subsequent steps, the doping layer 40 can be completely removed.
[0137] In some alternative implementation manners, the second region 23 can also be doped by the following method: providing a target element, and there is a preset included angle between the movement direction of the target element and the depth direction of the trench, such as ion implantation with an inclined angle.
[0138] In an exemplary embodiment, as Figure 4 shown, the manufacturing method of the semiconductor structure may further include:
[0139] Step S410: Provide a substrate, and a stacked structure is formed on the substrate.
[0140] The implementation manner and principle of this step are the same as those of step S110 in the foregoing embodiments, and will not be elaborated here.
[0141] Step S420: Form a plurality of trenches arranged in an array in the stacked structure, and the inner wall surface of each trench includes a first region and a second region.
[0142] The implementation manner and principle of this step are the same as those of step S120 in the foregoing embodiments, and will not be elaborated here.
[0143] Step S430: Form a protective layer that only covers the first region.
[0144] The implementation method and principle of this step are the same as those of step S130 in the foregoing embodiment, and will not be elaborated here.
[0145] Step S440: Perform doping treatment on the second region.
[0146] The implementation method and principle of this step are the same as those of step S140 in the foregoing embodiment, and will not be elaborated here.
[0147] Step S450: Remove the part corresponding to the first region in the stacked structure, and retain the part corresponding to the second region in the stacked structure as the channel region.
[0148] The implementation method and principle of this step are the same as those of step S150 in the foregoing embodiment, and will not be elaborated here.
[0149] Step S460: Form word lines.
[0150] In this step, the steps of forming word lines include:
[0151] Referring to Figure 20 , form a gate dielectric material layer 51', the gate dielectric material layer 51' covers the sidewalls of the protective layer 30 and the sidewalls of the second region 23; form a gate conductive material layer 52', the gate conductive material layer 52' covers the sidewalls of the gate dielectric material layer 51'; form a gate isolation material layer 53', the gate isolation material layer 53' covers the sidewalls of the gate conductive material layer 52', and the gate dielectric material layer 51', the gate conductive material layer 52' and the gate isolation material layer 53' form an initial word line structure 50'. Referring to Figure 21 , remove the partial structures at both ends of the initial word line structure 50' along the first direction, so as to divide the integral gate dielectric material layer 51' in the initial word line structure 50' into two gate dielectric layers 51, and divide the integral gate conductive material layer 52' into two gate conductive layers 52. The gate isolation material layer 53' forms a gate isolation structure 53. Each initial word line structure 50' can form two word lines 50, and the extending direction of each word line 50 is parallel to the thickness direction of the substrate 10 ( Figure 5 the z direction shown in
[0152] The method of removing part of the initial word line structure 50', for example, form a mask layer to cover the middle part of the initial word line structure 50', and use photolithography and etching processes to remove the part of the initial word line structure 50' that is not covered by the mask layer. The remaining initial word line structure 50' can form two word lines 50.
[0153] In some alternative embodiments, after forming the word line 50, sidewalls 54 can be formed on both sides of the word line 50 along the first direction, and the sidewalls 54 are used as a mask to dope opposite ends of the channel region 24 in the first direction by means of inclined ion implantation, so as to form lightly doped drain regions 27 (LDD) at both ends of the channel region 24, and the lightly doped drain regions 27 can effectively prevent the short channel effect.
[0154] Step S470: Form a first source / drain region and a second source / drain region, which are respectively located on opposite sides of the channel region in the first direction.
[0155] In this step, referring to Figure 19 , the active layer 20a can be selectively etched to form a bit line recess (not shown in the drawings) and a capacitor recess (not shown in the drawings) on opposite sides of the active layer 20a in the first direction. The bit line recess and the capacitor recess are formed between adjacent sacrificial layers 20b along the thickness direction of the substrate 10 ( Figure 5 the z direction shown in Figure 19 ). The projection of the bit line recess on the top surface of the substrate 10 falls within the
[0156] BL (Bit Line) region shown in Figure 22 , and the projection of the capacitor recess on the top surface of the substrate 10 falls within the SC (Storage Capacitor) region.
[0157] Each bit line recess and capacitor recess exposes both ends of the active region in the first direction. Ion implantation can be performed through the bit line recess and the capacitor recess to the two ends of the active region, so as to form a first source / drain region 25 and a second source / drain region 26 at both ends of the active region in the first direction (that is, on opposite sides of the channel region 24 in the first direction). One of the first source / drain region 25 and the second source / drain region 26 is a source region, and the other is a drain region. In one example, referring to
[0158]
[0159] Figure 22 In this step, referring to Figure 5 , a plurality of bit lines 60 can be formed in the bit line recesses by using a deposition or epitaxial growth process. Each bit line 60 extends along the second direction ( Figure 5 the y direction shown in
[0160] Referring to Figure 22, a storage capacitor 70 can be formed in the capacitive recess by deposition or epitaxial growth, and a plurality of storage capacitors 70 are connected to the source regions of a plurality of active regions in a one-to-one correspondence. The storage capacitor 70 includes an upper electrode, a lower electrode, and a dielectric layer located between the upper and lower electrodes. The upper and lower electrodes are usually made of a conductive material (such as doped polysilicon, metal, or metal nitride), and the dielectric layer is usually made of a high dielectric constant (high-k) material (such as silicon nitride). The method of fabricating the storage capacitor 70 and the bit line 60 is a mature technology in the related art and will not be elaborated in this embodiment.
[0161] In some alternative embodiments, after step S490, the method of fabricating the semiconductor structure further includes:
[0162] Step S490: Removing the sacrificial layer using an etchant that has a high selectivity to the sacrificial layer and a low selectivity to the active layer.
[0163] According to an exemplary embodiment of the present disclosure, as Figure 22 shown, this embodiment provides a semiconductor structure, and the semiconductor structure can be fabricated by using the fabrication method provided in any of the foregoing embodiments of the present disclosure.
[0164] As Figure 22 shown, the semiconductor structure includes a substrate 10. The substrate 10 serves as a support platform for the semiconductor structure to support other structures and functional layers of the semiconductor structure. The material of the substrate 10 includes, but is not limited to, any one of silicon (Si), gallium nitride (GaN), gallium arsenide (GaAs), silicon carbide (SiC), and silicon on insulator (SOI). A suitable substrate 10 material can be selected according to performance requirements, cost, and process compatibility to achieve a balance between semiconductor performance and economic benefits.
[0165] Referring to Figure 22 , a stacked structure 20 is formed on the substrate 10. The stacked structure 20 includes a plurality of active regions (refer to the AA regions shown in Figure 19 ). The plurality of active regions are spaced apart along a second direction (the y direction shown in Figure 22 ) and the thickness direction of the substrate 10 (the z direction shown in Figure 22 ). Among them, the pitch between adjacent active regions in the second direction can be formed by step S450 in the foregoing embodiment, and the pitch between adjacent active regions in the thickness direction can be formed by step S490.
[0166] Referring to Figure 22 , the active region includes a channel region 24, and a first source / drain region 25 and a second source / drain region 26 that are disposed on both sides of the channel region 24 along a first direction (the x direction shown in Figure 22 ). A preset angle (such as 90°) is provided between the first direction and the second direction, and both are perpendicular to the thickness direction of the substrate 10.
[0167] As shown Figure 22 in the figure, the semiconductor structure further includes a plurality of word lines 50, which are arranged at intervals along the second direction and are located on opposite sides of the channel region 24 in the second direction. Each word line 50 extends along the thickness direction of the substrate 10 to connect and control the channel regions 24 of a plurality of active regions simultaneously.
[0168] As shown Figure 22 in the figure, the semiconductor structure further includes a plurality of bit lines 60, which are arranged at intervals along the thickness direction of the substrate 10. Each bit line 60 extends along the second direction and is connected to the second source / drain regions 26 of a plurality of active regions in the stacked structure 20. Refer to Figure 22 , such an arrangement enables the plurality of word lines 50 and the plurality of bit lines 60 to form a cross matrix architecture, so that any one of the active regions in the stacked structure 20 can be selected by the intersection of a word line 50 and a bit line 60.
[0169] As shown Figure 22 in the figure, the semiconductor structure further includes a plurality of storage capacitors 70, which are connected to the first source / drain regions 25 of the plurality of active regions in the stacked structure 20 in a one-to-one correspondence. The intersection points of the bit lines 60 and the word lines 50 correspond to an independent active region and a storage capacitor 70. By using the plurality of bit lines 60 and word lines 50 arranged in a cross matrix layout, the target storage capacitor 70 can be accurately selected, so as to read and write data in the storage capacitor 70.
[0170] The semiconductor structure provided in this embodiment is fabricated by using the fabrication method provided in the foregoing embodiment, so that while maintaining the advantages of anisotropic etching, directional doping can be achieved by precisely controlling the diffusion path of the target element, thereby having stronger performance, lower processing difficulty and higher yield.
[0171] In this specification, the embodiments or implementation manners are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.
[0172] In the description of this specification, the description with reference to terms such as "embodiment", "exemplary embodiment", "some implementation manners", "schematic implementation manners", "example", etc. means that the specific features, structures, materials or characteristics described in connection with the implementation manner or example are included in at least one implementation manner or example of the present disclosure.
[0173] In this specification, the schematic expressions of the above terms do not necessarily refer to the same implementation manner or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more implementation manners or examples.
[0174] In the description of the present disclosure, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present disclosure.
[0175] It can be understood that the terms "first", "second", etc. used in the present disclosure can be used in the present disclosure to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.
[0176] In one or more of the drawings, the same elements are represented by like reference numerals. For clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of brevity, the structure obtained after several steps can be described in one figure. Many specific details of the present disclosure, such as the structure, materials, dimensions, processing techniques and technologies of the device, are described hereinafter in order to understand the present disclosure more clearly. However, as those skilled in the art can understand, the present disclosure can be implemented without these specific details.
[0177] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present disclosure.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that, Comprising: Providing a substrate, on which a stacked structure is formed; Forming a plurality of trenches arranged in an array in the stacked structure, and the inner wall surface of each trench includes a first region and a second region; Forming a protective layer, which only covers the first region; Performing doping treatment on the second region; Removing the part of the stacked structure corresponding to the first region, and retaining the part of the stacked structure corresponding to the second region as a channel region.
2. The manufacturing method of the semiconductor structure according to claim 1, wherein, The forming of the protective layer includes: Forming an initial protective layer to cover the entire inner wall surface of the trench; Performing at least one etching treatment on the initial protective layer until the second region is exposed, and the first region is covered with the etched residue of the initial protective layer to form the protective layer, wherein, during the etching treatment process, the etching rate of the part of the initial protective layer covering the second region is greater than the etching rate of the part of the initial protective layer covering the first region.
3. The manufacturing method of the semiconductor structure according to claim 2, characterized in that, The manufacturing method of the semiconductor structure includes: The first region includes a first sub-region and a second sub-region oppositely arranged in a first direction, the second region includes a third sub-region and a fourth sub-region oppositely arranged in a second direction, there is a first distance between the first sub-region and the second sub-region in the first direction, there is a second distance between the third sub-region and the fourth sub-region in the second direction, the first distance is greater than the second distance, and there is a preset included angle between the first direction and the second direction; The movement rate of the etchant during the etching treatment process in the second direction is greater than the movement rate in the first direction, so that the etching rate of the part of the initial protective layer covering the second region is greater than the etching rate of the part of the initial protective layer covering the first region.
4. The method for manufacturing a semiconductor structure according to claim 2, wherein, The performing at least one etching treatment on the initial protective layer includes: In each etching treatment, etching the initial protective layer with an etchant under a preset pressure, and removing the by-products generated by the etching; Wherein, the etchant includes at least one of elemental fluorine, fluorine-containing mixture, and organic fluoride.
5. The manufacturing method of the semiconductor structure according to claim 4, characterized in that, The etchant includes hydrogen fluoride gas and ammonia gas; The range of the preset pressure is 60 to 110 microns of mercury; and / or, the pressure range of the hydrogen fluoride gas is 20 to 30 microns of mercury; and / or, the pressure range of the ammonia gas is 20 to 30 microns of mercury.
6. The manufacturing method of the semiconductor structure according to claim 2, characterized in that, The forming of the initial protective layer to cover the entire inner wall surface of the trench includes: Forming the initial protective layer, and the initial protective layer covers the top surface of the stacked structure and the inner wall surface of the trench, and the inner wall surface includes the side wall surface and the bottom surface of the trench.
7. The method for manufacturing a semiconductor structure according to claim 6, wherein, The performing at least one etching treatment on the initial protective layer further includes: Removing the initial protective layer covering the bottom surface of the trench and the top surface of the stacked structure, and exposing the top surface of the stacked structure and the bottom surface of the trench.
8. The method for manufacturing a semiconductor structure according to claim 1, wherein, The performing doping treatment on the second region includes: Forming a doping layer, and the doping layer at least covers a target region and the protective layer, and the target region includes the bottom surface of the trench and the second region; Perform an annealing process to cause the target element contained in the doped layer to diffuse into the target region for doping treatment.
9. The method for fabricating a semiconductor structure according to claim 8, wherein The method for manufacturing the semiconductor structure is characterized in that after performing the annealing process, it further includes: Remove the doped layer to expose the second region of the sidewall surface and the bottom surface of the trench after doping treatment, and the protective layer.
10. The method for manufacturing a semiconductor structure according to claim 8, wherein, The doped layer includes at least one of a boron-containing compound layer and a boron elemental layer, and the target element includes a boron element.
11. The method for manufacturing a semiconductor structure according to claim 1, wherein, It further includes: Form word lines, the word lines are located on opposite sides of the channel region in the second direction, and the second direction is the arrangement direction of the plurality of trenches; Form a first source / drain region and a second source / drain region, the first source / drain region and the second source / drain region are respectively located on opposite sides of the channel region in the first direction, a preset included angle exists between the first direction and the second direction, and both are perpendicular to the thickness direction of the substrate; Form a storage capacitor and a bit line, the storage capacitor and the bit line are respectively connected to the first source / drain region and the second source / drain region.
12. The manufacturing method of the semiconductor structure according to claim 1, wherein, The stacked structure includes a plurality of active layers and a plurality of sacrificial layers alternately arranged along the thickness direction of the substrate; The formation of the plurality of trenches arranged in an array includes: etching from the top surface of the stacked structure towards the substrate direction to form a plurality of trenches in the stacked structure, and the trenches expose a part of the top surface of the substrate.
13. A semiconductor structure, characterized in that, Formed by using the method for manufacturing the semiconductor structure according to any one of claims 1 to 12, the semiconductor structure includes: A substrate, on which a stacked structure is provided, the stacked structure includes a plurality of active regions, and the plurality of active regions are spaced along the second direction and the thickness direction of the substrate; the active region includes a channel region and a first source / drain region and a second source / drain region respectively disposed on both sides of the channel region in the first direction; Word lines, extending along the thickness direction of the substrate, a plurality of the word lines are spaced along the second direction, and are located on opposite sides of the channel region in the second direction; Bit lines, extending along the second direction, a plurality of the bit lines are spaced along the thickness direction of the substrate, and are connected to the second source / drain regions of the plurality of active regions; Storage capacitors, a plurality of the storage capacitors are respectively connected to the first source / drain regions of the plurality of active regions in one-to-one correspondence; Wherein, a preset included angle exists between the first direction and the second direction, and both are perpendicular to the thickness direction of the substrate.