Semiconductor element with pad contact and preparation method thereof

Abstract

The invention provides a unit contact structure, a semiconductor element and a preparation method thereof. The cell contact structure includes: a contact layer on a substrate and surrounded by a plurality of bit line structures and a plurality of spacer layers; and a liner layer between the contact layer and the substrate, between the contact layer and the bit line structures, and between the contact layer and the spacer layers. A top surface of the contact layer and a top surface of the liner layer are substantially coplanar. The liner layer includes doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon germanium. The contact layer includes tungsten, titanium, or titanium nitride.

Description

[0001] This application is a divisional of Chinese Patent Application No. 202410689608.3, titled "Semiconductor Element with Pad Contact and Method of Manufacturing the Same", filed on May 30, 2024. Application No. 202410689608.3 claims the priority and benefits of U.S. Provisional Application No. 18 / 413,510, filed on January 16, 2024, the content of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a semiconductor element and a method of manufacturing the same. In particular, it relates to a semiconductor element with pad contact and a method of manufacturing the same. Background Art

[0003] Semiconductor elements have been used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor elements has been continuously miniaturized to meet the growing demand for computing power. However, various problems occur during the miniaturization process, and such problems are continuously increasing. Therefore, there are still challenges in improving quality, yield, performance, and reliability, as well as reducing complexity.

[0004] The above description of "prior art" is provided only as background art and does not admit that the above description of "prior art" discloses the subject matter of the present disclosure, does not form the prior art of the present disclosure, and any description of the above "prior art" should not be taken as any part of the present disclosure. Summary of the Invention

[0005] One aspect of the present disclosure provides a cell contact structure, which includes: a contact layer located on a substrate and surrounded by a plurality of bit line structures and a plurality of spacer layers; and a liner layer located between the contact layer and the substrate, between the contact layer and the bit line structures, and between the contact layer and the spacer layers. A top surface of the contact layer and a top surface of the liner layer are substantially coplanar. The liner layer includes doped polysilicon, doped polycrystalline germanium, or doped polysilicon germanium. The contact layer includes tungsten, titanium, or titanium nitride.

[0006] Another aspect of the present disclosure provides a semiconductor device, which includes: a substrate; two bit line structures formed on the substrate, extending along a first direction and separated from each other; two spacer layers located on the substrate, extending along a second direction perpendicular to the first direction and separated from each other, and simultaneously contacting the two bit line structures; and a unit contact structure. The unit contact structure includes: a contact layer located on the substrate and surrounded by the two bit line structures and the two spacer layers; and a liner layer located between the substrate and the contact layer, between the two bit line structures and the contact layer, and between the two spacer layers and the contact layer. A top surface of the liner layer and a top surface of the contact layer are substantially coplanar. The liner layer includes doped polysilicon, doped polygermanium, or doped polysilicon germanium. The contact layer includes tungsten, titanium, or titanium nitride.

[0007] Another aspect of the present disclosure provides a method for manufacturing a semiconductor device, which includes: providing a substrate; forming two bit line structures on the substrate, extending along a first direction and separated from each other; forming a plurality of spacer structures on side surfaces of the two bit line structures; forming two spacer layers on the substrate, extending along a second direction perpendicular to the first direction and separated from each other, thereby creating a contact opening combined with the spacer structures; conformally forming a liner layer in the contact opening; and forming a contact layer on the liner layer and within the contact opening. The liner layer includes doped polysilicon, doped polygermanium, or doped polysilicon germanium. The contact layer includes tungsten, titanium, or titanium nitride. The liner layer and the contact layer together constitute a unit contact structure.

[0008] Due to the design of the semiconductor device of the present disclosure, junction leakage of the unit contact structure can be reduced by adopting a liner layer including doped polysilicon, doped polygermanium, or doped polysilicon germanium. In addition, sheet resistance of the unit contact structure can be reduced by adopting a contact layer including titanium nitride, tungsten, or titanium. As a result, the performance of the semiconductor device can be improved.

[0009] The technical features and advantages of the present disclosure have been outlined rather extensively above, so that a better understanding of the detailed description of the present disclosure below can be obtained. Other technical features and advantages forming the subject matter of the claims of the present disclosure will be described below. Those skilled in the art to which the present disclosure pertains should understand that the concepts and specific embodiments disclosed below can be quite easily utilized as a basis for modifying or designing other structures or processes to achieve the same purpose as the present disclosure. Those skilled in the art to which the present disclosure pertains should also understand that such equivalent constructs cannot depart from the spirit and scope of the present disclosure defined by the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] A more complete understanding of the present disclosure can be obtained by referring to the detailed description and the claims when considered in conjunction with the accompanying drawings, in which like reference numerals represent like elements throughout the drawings, and:

[0011] Figure 1 A method for fabricating a semiconductor device is shown in the form of a flowchart according to an embodiment of the present disclosure.

[0012] Figure 2 A top view schematic diagram of an intermediate semiconductor device is shown according to an embodiment of the present disclosure.

[0013] Figure 3 Showing a cross-sectional schematic diagram taken along line A-A' and B-B' in Figure 2 .

[0014] Figure 4 A top view schematic diagram of an intermediate semiconductor device is shown according to an embodiment of the present disclosure.

[0015] Figure 5 Showing a cross-sectional schematic diagram taken along line A-A' and B-B' in Figure 4 .

[0016] Figure 6 A top view schematic diagram of an intermediate semiconductor device is shown according to an embodiment of the present disclosure.

[0017] Figure 7 Showing a cross-sectional schematic diagram taken along line A-A' and B-B' in Figure 6 .

[0018] Figure 8 A top view schematic diagram of an intermediate semiconductor device is shown according to an embodiment of the present disclosure.

[0019] Figure 9 Showing a cross-sectional schematic diagram taken along line A-A' and B-B' in Figure 8 .

[0020] Figure 10 A top view schematic diagram of an intermediate semiconductor device is shown according to an embodiment of the present disclosure.

[0021] Figure 11 Showing a cross-sectional schematic diagram taken along line A-A' and B-B' in Figure 10 .

[0022] Figure 12 A top view schematic diagram of an intermediate semiconductor device is shown according to an embodiment of the present disclosure.

[0023] Figure 13 Showing a cross-sectional schematic diagram taken along line A-A' and B-B' in Figure 12 .

[0024] Figure 14 A top view schematic diagram showing an intermediate semiconductor element according to an embodiment of the present disclosure.

[0025] Figure 15 and Figure 16 A cross-sectional schematic diagram shown according to an embodiment of the present disclosure along lines A-A' and B-B' in Figure 14 showing a partial process of fabricating a semiconductor element.

[0026] Figure 17 A top view schematic diagram showing an intermediate semiconductor element according to an embodiment of the present disclosure.

[0027] Figure 18 Showing a cross-sectional schematic diagram along lines A-A' and B-B' in Figure 17

[0028] Figure 19 A top view schematic diagram showing an intermediate semiconductor element according to an embodiment of the present disclosure.

[0029] Figures 20 to 23 A cross-sectional schematic diagram shown according to an embodiment of the present disclosure along lines A-A' and B-B' in Figure 19 showing a partial process of fabricating a semiconductor element.

[0030] Figure 24 A top view schematic diagram showing an intermediate semiconductor element according to an embodiment of the present disclosure.

[0031] Figure 25 and Figure 26 A cross-sectional schematic diagram shown according to an embodiment of the present disclosure along lines A-A' and B-B' in Figure 24 showing a partial process of fabricating a semiconductor element.

[0032] Figures 27 to 29 A cross-sectional schematic diagram of a semiconductor element shown according to some embodiments of the present disclosure.

[0033] Description of reference numerals:

[0034] 1A: Semiconductor element

[0035] 1B: Semiconductor element

[0036] 1C: Semiconductor element

[0037] 1D: Semiconductor element

[0038] 10: Method

[0039] 101: Substrate

[0040] 103: Isolation layer ​

[0041] 105: Impurity region

[0042] 105-1: Source region

[0043] 105-3: Drain region

[0044] 107: Bottom dielectric layer

[0045] 109: Top insulating layer

[0046] 200: Character line structure

[0047] 201: Character line dielectric layer

[0048] 203: Character line barrier layer

[0049] 205: Character line conductive layer

[0050] 207: Character line covering layer

[0051] 300: Bit line structure

[0052] 300S: Side surface

[0053] 301: Bit line top conductive layer

[0054] 303: Bit line intermediate conductive layer

[0055] 305: Bit line bottom conductive layer

[0056] 307: Bit line covering layer

[0057] 307TS: Top surface

[0058] 309: Bit line contact

[0059] 400: Spacer structure

[0060] 401: In-bit line spacer

[0061] 401TS: Top surface

[0062] 403: Intermediate bit line spacer

[0063] 403TS: Top surface

[0064] 405: Outer bit line spacer

[0065] 405TS: Top surface

[0066] 407: Air gap

[0067] 500: Cell contact structure

[0068] 501: Liner

[0069] 501TS: Top surface

[0070] 503: Contact layer

[0071] 503TS: Top surface

[0072] 601: Spacer layer

[0073] 601TS: Top surface

[0074] 701: First mask layer

[0075] 801: Sacrificial layer

[0076] 803: Spacer material

[0077] 805: Liner material

[0078] 807: First conductive material

[0079] AA: Active area

[0080] A - A’: Line

[0081] B - B’: Line

[0082] OP1: Spacer opening

[0083] OP2: Contact opening

[0084] P1: Linear pattern

[0085] S11: Step

[0086] S13: Step

[0087] S15: Step

[0088] S17: Step

[0089] TR: Character line trench

[0090] X: Direction

[0091] Y: Direction

[0092] Z: Direction Detailed implementation manner

[0093] The following discloses providing many different embodiments or examples to implement different components of the embodiments of the present disclosure. The following describes examples of specific elements and their arrangements to simplify the embodiments of the present disclosure. Of course, these are only examples and should not limit the scope of the embodiments of the present disclosure. For example, when it is described in the description that the first component is formed "on" or "above" the second component, it may include embodiments where the first component is in direct contact with the second component, and may also include embodiments where there are other components formed between the two without direct contact. Additionally, the present disclosure may repeat reference symbols and / or markings in different embodiments. These repetitions are for the purpose of simplicity and clarity and are not used to define the relationship between the different embodiments and / or structures being discussed.

[0094] In addition, where spatial-related terms are used, such as: "below", "beneath", "lower", "above", "higher", and their like, are for facilitating the description of the relationship between one element or component and another element or component shown in the drawings. These spatial relationship terms are used to cover different orientations of the elements in use or operation other than the orientation depicted in the drawings. The element may be turned to different orientations (rotated 90 degrees or other orientations), and the spatial-related adjectives used therein can be interpreted in the same way accordingly.

[0095] It should be understood that when an element or layer is referred to as "connected to" or "coupled to" another element or layer, it can be directly connected or coupled to the other element or layer, or there may be intermediate elements or layers.

[0096] It should be understood that although terms such as first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. Unless otherwise specified, these terms are only used to distinguish one element from another. Thus, for example, without departing from the teachings of the present disclosure, the first element, the first component, or the first part discussed below can be referred to as the second element, the second component, or the second part.

[0097] Unless the context otherwise indicates, terms such as "same", "equal", "flat", or "coplanar" used herein when referring to orientation, layout, position, shape, size, quantity, or other measurements do not necessarily mean exactly the same orientation, layout, position, shape, size, quantity, or other measurements, but are intended to cover orientations, layouts, positions, shapes, sizes, quantities, or other measurements that are almost the same within an acceptable range of variation, for example, due to manufacturing processes. The term "substantially" can be used herein to reflect this meaning. For example, items described as "substantially the same", "substantially equal", or "substantially flat" may be exactly the same, equal, or flat, or may be the same, equal, or flat within an acceptable range of variation, for example, due to manufacturing processes.

[0098] In the present disclosure, a semiconductor element generally refers to an element that can function by utilizing semiconductor characteristics, and electro-optical elements, light-emitting display elements, semiconductor circuits, and electronic elements are all included in the category of semiconductor elements.

[0099] It should be noted that in the description of the present disclosure, above or up corresponds to the arrow direction of the Z direction, and below or down corresponds to the direction opposite to the arrow direction of the Z direction.

[0100] Figure 1 A method 10 for manufacturing a semiconductor element 1A is shown in the form of a flowchart according to an embodiment of the present disclosure. Figure 2 A top view schematic diagram of an intermediate semiconductor element is shown according to an embodiment of the present disclosure. Figure 3 Showing a cross-sectional schematic diagram drawn along Figure 2 lines A-A' and B-B' in Figure 4 A top view schematic diagram of an intermediate semiconductor element is shown according to an embodiment of the present disclosure. Figure 5 Showing a cross-sectional schematic diagram drawn along Figure 4 lines A-A' and B-B' in

[0101] Referring to Figures 1 to 5 , in step S11, a substrate 101 can be provided, an isolation layer 103 can be formed in the substrate 101 to define a plurality of active regions AA, and a plurality of word line structures 200 located in the substrate 101 and intersecting with these active regions AA can be formed.

[0102] Referring to Figure 2 and Figure 3 , the substrate 101 can include a bulk semiconductor substrate. The bulk semiconductor substrate can include, for example, elemental semiconductors such as silicon or germanium; compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other III-V group compound semiconductors or II-VI group compound semiconductors; or combinations thereof.

[0103] In some embodiments, the semiconductor substrate 101 may include a semiconductor-on-insulator substrate that includes, from bottom to top, a handle substrate, an insulating layer, and a topmost semiconductor material layer. The handle substrate and the topmost semiconductor material layer may include the same materials as the bulk semiconductor substrate described above. The insulating layer may be a crystalline or amorphous dielectric material, such as an oxide and / or a nitride. For example, the insulating layer may be a dielectric oxide, such as silicon oxide. As another example, the insulating layer may be a dielectric nitride, such as silicon nitride or boron nitride. As yet another example, the insulating layer may include a stack of a dielectric oxide and a dielectric nitride, such as a stack of silicon oxide and silicon nitride or boron nitride in any order. The insulating layer may have a thickness between about 10 nm and about 200 nm. The insulating layer may eliminate leakage current between adjacent elements in the substrate 101 and reduce the parasitic capacitance associated with the source / drain.

[0104] It should be noted that, in the description of the present disclosure, the term "about" modifying the amounts of ingredients, components, or reactants employed in the present disclosure refers to, for example, variations in amounts that may occur through typical measurement and liquid handling procedures used for preparing concentrates or solutions. Additionally, variations may result from inadvertent errors in measurement procedures, differences in the manufacture, source, or purity of the ingredients used in the manufacture of the compositions or the practice of the methods. In one aspect, the term "about" refers to within 10% of the reported value. In another aspect, the term "about" refers to within 5% of the reported value. In yet another aspect, the term "about" refers to within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

[0105] Referring to Figure 2 and Figure 3 , an isolation layer 103 may be formed in the substrate 101. A series of deposition processes may be performed to deposit a pad oxide layer (not shown) and a pad nitride layer (not shown) on the substrate 101. A lithography process and subsequent etching processes, such as anisotropic dry etching, may be performed to form trenches that pass through the pad oxide layer, the pad nitride layer, and extend into the substrate 101. An insulating material may be deposited into the trenches and a planarization process, such as chemical mechanical polishing, may be subsequently performed until the top surface of the substrate 101 is exposed to remove excess fill material, provide a substantially flat surface for subsequent processing steps, and simultaneously form the isolation layer 103. The insulating material may be, for example, silicon oxide or other applicable insulating materials. The isolation layer 103 may define the active regions AA in the substrate 101.

[0106] It should be noted that in the description of the present disclosure, the surface of an element (or component) located at the highest vertical level along the Z-axis is referred to as the top surface of the element (or component). The surface of an element (or component) located at the lowest vertical level along the Z-axis is referred to as the bottom surface of the element (or component).

[0107] It should be noted that each of these active regions AA may include a part of the substrate 101 and the space above this part of the substrate 101. Describing an element as being disposed on the active region AA means that the element is disposed on the top surface of this part of the substrate 101. Describing an element as being disposed in the active region AA means that the element is disposed in this part of the substrate 101. However, the top surface of the element may be flush with the top surface of this part of the substrate 101. Describing an element as being disposed above the active region AA means that the element is disposed above the top surface of this part of the substrate 101.

[0108] Referring to Figure 2 and Figure 3 , a plurality of impurity regions 105 can be respectively formed in these active regions AA. In some embodiments, the fabrication technique of these impurity regions 105 may include an implantation process. That is, these impurity regions 105 can be transformed from a part of these active regions AA. The dopant of the implantation process may include a p-type impurity (dopant) or an n-type impurity (dopant). A p-type dopant can be added to an intrinsic semiconductor material to create valence electron defects. In a silicon-containing substrate, examples of p-type dopants (i.e., impurities) include, but are not limited to, boron, aluminum, gallium, or indium. An n-type dopant can be added to an intrinsic semiconductor material to contribute free electrons to the intrinsic semiconductor material. In a silicon-containing substrate, examples of n-type dopants (i.e., impurities) include, but are not limited to, antimony, arsenic, or phosphorus. In some embodiments, the dopant concentration of these impurity regions 105 can be between approximately 1E19 atoms / cm^3 and approximately 1E21 atoms / cm^3. After the implantation process, these impurity regions 105 can have an electrical type such as n-type or p-type.

[0109] Referring to Figure 4 and Figure 5, multiple character line trenches TR can be formed in the substrate 101 to define the positions of the character line structures 200. The fabrication techniques for the character line trenches TR can include a photolithography process and a subsequent etching process. In some embodiments, in a top-down perspective view, the character line trenches TR can have a linear cross-sectional profile and extend along the direction X and through the impurity regions 105 (or intersect the impurity regions 105). For example, each impurity region 105 can intersect two character line trenches TR. The character line trenches TR can divide each of the impurity regions 105 into a plurality of common source regions 105-1 and a plurality of drain regions 105-3. For one impurity region 105, a common source region 105-1 can be formed between two character line trenches TR, and two drain regions 105-3 can be respectively formed between the isolation layer 103 and the two character line trenches TR.

[0110] Referring to Figure 4 and Figure 5 , the character line structures 200 (e.g., two character line structures 200) can be respectively formed in the character line trenches TR (e.g., two character line trenches TR). For the sake of brevity, clarity, and convenience of description, only one character line structure 200 is described. The character line structure 200 can include a character line dielectric layer 201, a character line barrier layer 203, a character line conductive layer 205, and a character line capping layer 207.

[0111] Referring to Figure 4 and Figure 5 , the character line dielectric layer 201 can be conformally formed on the inner surface of the character line trench TR. The character line dielectric layer 201 can have a U-shaped cross-sectional profile. In other words, the character line dielectric layer 201 can be formed inwardly in the active region AA. In some embodiments, the fabrication techniques for the character line dielectric layer 201 can include a thermal oxidation process. For example, the character line dielectric layer 201 can be formed by oxidizing the inner surface of the character line trench TR. In some embodiments, the fabrication techniques for the character line dielectric layer 201 can include a deposition process such as chemical vapor deposition or atomic layer deposition. The character line dielectric layer 201 can include a high-k (high dielectric constant) material, an oxide, a nitride, a oxynitride, or a combination of the foregoing. In some embodiments, after depositing a pad polysilicon layer (not shown for clarity), the character line dielectric layer 201 can be formed by radical oxidation of the pad polysilicon layer. In some embodiments, after forming a pad silicon nitride layer (not shown for clarity), the character line dielectric layer 201 can be formed by radical oxidation of the pad silicon nitride layer.

[0112] In some embodiments, the high-k dielectric material may include a hafnium-containing material. The hafnium-containing material may be, for example, hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination of the foregoing. In some embodiments, the high-k dielectric material may be, for example, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, or a combination of the foregoing.

[0113] Referring to Figure 4 and Figure 5 , a word line barrier layer 203 may be conformally formed on the word line dielectric layer 201 and within the word line trench TR. In some embodiments, the word line barrier layer 203 may include, for example, titanium nitride, titanium, or a combination of the foregoing. In some embodiments, the word line barrier layer 203 may include, for example, titanium nitride. In some embodiments, the fabrication technique of the word line barrier layer 203 may include, for example, atomic layer deposition, physical vapor deposition, chemical vapor deposition, or other applicable deposition processes.

[0114] Referring to Figure 4 and Figure 5 , a word line conductive layer 205 may be formed on the word line barrier layer 203 and within the word line trench TR. In some embodiments, in order to form the word line conductive layer 205, a conductive layer (not shown for clarity) may be formed to fill the word line trench TR, and then a recess process may be performed. The recess process may be performed as an etch-back process or as a planarization process and an etch-back process sequentially. The word line conductive layer 205 may have a recessed shape that partially fills the word line trench TR. That is, the top surface of the word line conductive layer 205 may be lower than the top surface of the substrate 101.

[0115] In some embodiments, the word line conductive layer 205 may include a metal, a metal nitride, or a combination of the foregoing. For example, the word line conductive layer 205 may include titanium nitride, tungsten, or titanium nitride / tungsten. After conformally forming titanium nitride, titanium nitride / tungsten may have a structure in which the word line trench TR is partially filled with tungsten. Titanium nitride or tungsten may be used alone in the word line conductive layer 205. In some embodiments, the word line conductive layer 205 may include, for example, a conductive material such as doped polysilicon, doped polygermanium, doped polysilicon germanium, or a combination of the foregoing. In some embodiments, the word line conductive layer 205 may include, for example, tungsten, aluminum, titanium, copper, similar materials, or a combination of the foregoing.

[0116] Referring to Figure 4 and Figure 5, a dielectric material (not shown) can be deposited, for example, by chemical vapor deposition to completely fill the character line trench TR and cover the top surface of the substrate 101. A planarization process, such as chemical mechanical polishing, can be performed to provide a substantially flat surface for subsequent processing steps and form the character line covering layer 207. In some embodiments, the character line covering layer 207 can include silicon nitride or other applicable dielectric materials.

[0117] Figure 6 A top view schematic diagram showing an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 7 Showing along Figure 6 The cross-sectional schematic diagrams drawn along the lines A-A' and B-B' in Figure 8 A top view schematic diagram showing an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 9 Showing along Figure 8 The cross-sectional schematic diagrams drawn along the lines A-A' and B-B' in Figure 10 A top view schematic diagram showing an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 11 Showing along Figure 10 The cross-sectional schematic diagrams drawn along the lines A-A' and B-B' in. It should be noted that for clarity, some elements are omitted in the top view.

[0118] Referring to Figure 1 and Figures 6 to 11 , in step S13, a plurality of bit line structures 300 can be formed on the substrate 101, and a plurality of spacer structures 400 can be formed on the side surfaces 300S of the bit line structures.

[0119] Referring to Figure 6 and Figure 7 , a bottom dielectric layer 107 can be formed on the substrate 101. In some embodiments, the bottom dielectric layer 107 can include a material having an etching selectivity with respect to the substrate 101 and the isolation layer 103. In some embodiments, the bottom dielectric layer 107 can include, for example, silicon nitride, boron nitride, boron silicon nitride, boron phosphorus nitride, silicon carbon boron nitride, or a combination of the foregoing. In some embodiments, the bottom dielectric layer 107 can include, for example, silicon nitride. In some embodiments, the manufacturing technique of the bottom dielectric layer 107 can include, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other applicable deposition processes.

[0120] Referring to Figure 6 and Figure 7, a plurality of bit line contacts 309 can be formed, each of which correspondingly passes through the bottom dielectric layer 107 and extends to the common source regions 105-1. In some embodiments, the bit line contacts 309 can include, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (e.g., titanium nitride), transition metal aluminides, or combinations of the foregoing. In some embodiments, the bit line contacts 309 can have a square cross-sectional profile in a top-down perspective view, but are not limited to this shape. In some embodiments, the bit line contacts 309 can have a rectangular, circular, or other applicable shape cross-sectional profile in a top-down perspective view.

[0121] Referring to Figure 8 and Figure 9 , the bit line structures 300 can be formed on the bottom dielectric layer 107 and are respectively and electrically connected to the bit line contacts 309. In a top-down perspective view, the bit line structures 300 can extend along the direction Y and be separated from each other. In other words, in a top-down perspective view, the bit line structures 300 can intersect the word line structures 200. For the sake of brevity, clarity, and convenience of description, only one bit line structure 300 is described. In some embodiments, the bit line structure 300 can include a bit line top conductive layer 301 and a bit line covering layer 307.

[0122] The bit line top conductive layer 301 can be formed on the bit line contact 309 and be electrically connected to the bit line contact 309. In some embodiments, the bit line top conductive layer 301 can include, for example, titanium nitride, tungsten, titanium, nickel, platinum, tantalum, cobalt, silver, copper, aluminum, other applicable conductive materials, or combinations of the foregoing. The bit line covering layer 307 can be formed on the bit line top conductive layer 301. In some embodiments, the bit line covering layer 307 can include, for example, silicon nitride or other applicable insulating materials.

[0123] Referring to Figure 10 and Figure 11 , the spacer structures 400 can be formed on the side surfaces 300S of the bit line structures 300. In other words, in a top-down perspective view, the spacer structures 400 can extend along the direction Y. For the sake of brevity, clarity, and convenience of description, only one spacer structure 400 is described. In some embodiments, the spacer structure 400 can include an in-bit line spacer 401, a mid-bit line spacer 403, and an out-bit line spacer 405.

[0124] The in-bitline spacer 401 may be formed on the side surface 300S of the bitline structure 300. In some embodiments, the in-bitline spacer 401 may include the same material as the bitline capping layer 307. In some embodiments, the in-bitline spacer 401 may include, for example, silicon nitride or other applicable insulating materials. In some embodiments, the in-bitline spacer 401 may be formed by conformally depositing a layer of insulating material (not shown) on top of the bottom dielectric layer 107 and subsequent anisotropic etching processes.

[0125] The intermediate bitline spacer 403 may be conformally formed on the in-bitline spacer 401. In some embodiments, the intermediate bitline spacer 403 may include, for example, silicon oxide or other applicable insulating oxides. In some embodiments, the intermediate bitline spacer 403 may be formed by conformally depositing a layer of insulating oxide (not shown) on top of the bottom dielectric layer 107 and subsequent anisotropic etching processes.

[0126] The out-bitline spacer 405 may be conformally formed on the intermediate bitline spacer 403. In some embodiments, the out-bitline spacer 405 may include the same material as the in-bitline spacer 401 or the bitline capping layer 307. In some embodiments, the out-bitline spacer 405 may include, for example, silicon nitride or other applicable insulating materials. In some embodiments, the out-bitline spacer 405 may be formed by conformally depositing a layer of insulating material (not shown) on top of the bottom dielectric layer 107 and subsequent anisotropic etching processes.

[0127] In some embodiments, the in-bitline spacer 401 may be optional. That is, the intermediate bitline spacer 403 may be directly formed on the side surface 300S of the bitline structure 300.

[0128] Figure 12 A top view schematic diagram showing an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 13 Showing along Figure 12 the cross-sectional schematic diagrams drawn along lines A-A' and B-B' in Figure 14 A top view schematic diagram showing an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 15 and Figure 16 According to an embodiment of the present disclosure, a cross-sectional schematic diagram drawn along lines A-A' and B-B' in Figure 14 is shown, showing a partial process of fabricating the semiconductor element 1A. Figure 17 A top view schematic diagram showing an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 18 Showing along Figure 17 the cross-sectional schematic diagrams drawn along lines A-A' and B-B' in

[0129] Reference Figure 1 and Figures 12 to 18 In step S15, a sacrificial layer 801 can be formed to cover the bit line structures 300 and the spacer structures 400. A first mask layer 701 including a linear pattern P1 can be formed on the sacrificial layer 801 to partially expose the sacrificial layer 801, the bit line structures 300, and the spacer structures 400. The sacrificial layer 801 can be selectively removed to form a plurality of separation openings OP1, and a plurality of separation layers 601 can be formed in the separation openings OP1.

[0130] Reference Figure 12 and Figure 13 A sacrificial layer 801 can be formed over the bottom dielectric layer 107 to cover the bit line structures 300 and the spacer structures 400. In some embodiments, the sacrificial layer 801 can include a material that has an etching selectivity with respect to, for example, the bit line outer spacer 405 or the bit line capping layer 307. In some embodiments, the sacrificial layer 801 can include, for example, silicon oxynitride, silicon nitride oxide, or other applicable materials. In some embodiments, the fabrication technique of the sacrificial layer 801 can include, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, or other applicable deposition processes. In some embodiments, a planarization process, such as chemical mechanical polishing, can be performed until the top surface 307TS of the bit line structures 300 is exposed to remove excess material and provide a substantially flat surface for subsequent processing steps.

[0131] It should be noted that in the description of the present disclosure, silicon oxynitride refers to a substance that contains silicon, nitrogen, and oxygen and in which the proportion of oxygen is greater than the proportion of nitrogen. Silicon nitride oxide refers to a substance that contains silicon, oxygen, and nitrogen and in which the proportion of nitrogen is greater than the proportion of oxygen.

[0132] Reference Figure 12 and Figure 13 A first mask layer 701 can be formed on the sacrificial layer 801. In some embodiments, the first mask layer 701 can be a photoresist layer. In a top-down perspective view, the linear pattern P1 of the first mask layer 701 can include a plurality of rectangular spaces that extend along the direction X and are alternately arranged along the direction Y. Through these spaces, the sacrificial layer 801, the bit line structures 300, and the spacer structures 400 can be partially exposed.

[0133] Reference Figure 14 and Figure 15, the sacrificial layer 801 exposed by the linear pattern P1 of the first mask layer 701 can be selectively removed. In some embodiments, the removal of the sacrificial layer 801 can be achieved by an anisotropic etching process, such as an anisotropic dry etching process. After removing the sacrificial layer 801, these separation openings OP1 can be formed in the positions of the sacrificial layer 801 exposed by the linear pattern P1 of the first mask layer 701. Then, after forming these separation openings OP1, the first mask layer 701 can be removed.

[0134] Referring Figure 16 , a layer of separation material 803 can be formed over the sacrificial layer 801 to completely fill these separation openings OP1. In some embodiments, the separation material 803 can be a material that has an etching selectivity with respect to the sacrificial layer 801. In some embodiments, the separation material 803 can be the same material as the bit line capping layer 307 or the bit line outer spacer 405. In some embodiments, the separation material 803 can be, for example, silicon nitride or other applicable insulating materials. In some embodiments, the fabrication technique for this layer of separation material 803 can include, for example, chemical vapor deposition or other applicable deposition processes.

[0135] Referring Figure 17 and Figure 18 , a planarization process, such as chemical mechanical polishing, can be performed to remove the excess material and provide a substantially flat surface for subsequent processing steps, and transform this layer of separation material 803 into multiple separation layers 601. In a top-down perspective view, each of these separation layers 601 can have a linear (or rectangular or square) cross-sectional profile extending along the direction X. These separation layers 601 can be alternately arranged along the direction X, with each corresponding bit line structure 300 located between two adjacent separation layers 601. Along the direction Y, these separation layers 601 can be alternately arranged, with the sacrificial layer 801 inserted therebetween. In a top-down perspective view, the arrangement of these separation layers 601 and these bit line structures 300 can divide the sacrificial layer 801 into multiple segments.

[0136] For the sake of concise, clear, and convenient description, only one layer of separation layer 601 is described. In some embodiments, after the planarization process, the in-bit line spacer 401, the in-bit line intermediate spacer 403, and the bit line outer spacer 405 can be exposed. The top surface 601TS of the separation layer 601, the top surface 401TS of the in-bit line spacer 401, the top surface 403TS of the in-bit line intermediate spacer 403, the top surface 405TS of the bit line outer spacer 405, and the top surface 307TS of the bit line capping layer 307 can be substantially coplanar.

[0137] In some embodiments, after the planarization process, the bit line outer spacer 405 (not shown) may cover the bit line inner spacer 401 and the bit line middle spacer 403. In this case, the top surface 405TS of the bit line outer spacer 405 and the top surface 307TS of the bit line covering layer 307 may be substantially coplanar.

[0138] Figure 19 A top view schematic diagram showing an intermediate semiconductor element according to an embodiment of the present disclosure. Figures 20 to 23 According to an embodiment of the present disclosure, shown along Figure 19 the line A-A' and B-B' in Figure 24 A top view schematic diagram showing an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 25 and Figure 26 According to an embodiment of the present disclosure, shown along Figure 24 the line A-A' and B-B' in

[0139] Referring to Figure 1 and Figures 19 to 27 , in step S17, the sacrificial layer 801 may be selectively removed to form a plurality of contact openings OP2, a plurality of unit contact structures 500 may be formed in the contact openings OP2, and a top insulating layer 109 may be formed to cover the bit line structures 300, the spacer structures 400, and the unit contact structures 500.

[0140] Referring to Figure 19 and Figure 20 , the sacrificial layer 801 may be selectively removed by an etching process. For example, the removal of the sacrificial layer 801 may be achieved by an anisotropic etching process. After removing the sacrificial layer 801, the contact openings OP2 may be formed in the positions previously occupied by the sacrificial layer 801 (in a plurality of segments). For the sake of brevity, clarity, and convenience of description, only one contact opening OP2 is described. In a cross-sectional perspective view, the contact opening OP2 may be disposed on the bottom dielectric layer 107. In a top view perspective view, the contact opening OP2 may be surrounded by two adjacent spacer layers 601 along the direction Y and may be surrounded by two adjacent bit line structures 300 (or spacer structures 400 disposed on the side surfaces 300S of two adjacent bit line structures 300) along the direction X.

[0141] Referring to Figure 21, a punch-through process can be performed to remove a portion of the bottom dielectric layer 107 exposed by the contact openings OP2. In some embodiments, the punch-through process can be an anisotropic dry etching process. The punch-through process can extend the contact openings OP2 downward to the substrate 101. After the punch-through process, the drain regions 105-3 can be exposed through the contact openings OP2.

[0142] Referring Figure 22 , a layer of liner material 805 can be conformally formed to cover the substrate 101, the bit line structures 300, the spacer structures 400, and the isolation layer 601. In some embodiments, the liner material 805 can include doped polysilicon, doped polygermanium, or doped polysilicon germanium. In some embodiments, the liner material 805 can include a p-type dopant or an n-type dopant. In some embodiments, the fabrication technique of the layer of liner material 805 can include atomic layer deposition, chemical vapor deposition, or other applicable deposition processes. By using doped polysilicon, doped polygermanium, or doped polysilicon germanium as the liner material 805 of the unit contact structure 500, junction leakage can be reduced. As a result, the performance of the semiconductor device 1A can be improved.

[0143] Referring Figure 23 , a layer of a first conductive material 807 can be formed on the layer of liner material 805 and completely fill the contact openings OP2. In some embodiments, the first conductive material 807 can be a material with good conductivity (or a material with better conductivity than doped polysilicon, doped polygermanium, or doped polysilicon germanium). In some embodiments, the first conductive material 807 can be, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (e.g., titanium nitride), transition metal aluminides, or a combination of the foregoing. In some embodiments, the first conductive material 807 can be, for example, titanium nitride, titanium, tungsten, or a combination of the foregoing. By using a material with good conductivity, the sheet resistance of the unit contact structure 500 can be reduced. As a result, the performance of the semiconductor device 1A can be improved.

[0144] Referring Figure 24 and Figure 25 , an etch-back process can be performed to remove a portion of the liner material 805 and the first conductive material 807. After the etch-back process, the remaining liner material 805 is respectively transformed into a plurality of liner layers 501 within the contact openings OP2. The remaining first conductive material 807 is respectively transformed into a plurality of contact layers 503 within the contact openings OP2.

[0145] For simplicity, clarity, and convenience of description, only one liner 501 and one contact layer 503 are described. In some embodiments, in a cross-sectional perspective view, the top surface 503TS of the contact layer and the top surface 501TS of the liner may be substantially coplanar. The top surface 503TS of the contact layer and the top surface 501TS of the liner may be lower than the top surface 307TS of the bit line covering layer 307 (i.e., the top surface of the bit line structure 300). In some embodiments, in a top-down perspective view, the liner 501 may have a square-ring-shaped or rectangle-ring-shaped cross-sectional profile. The contact layer 503 may have a square or rectangular cross-sectional profile. The liner 501 and the contact layer 503 together form a unit contact structure 500. The unit contact structure 500 may be electrically connected to the corresponding drain region 105-3.

[0146] Referring to Figure 26 , a top insulating layer 109 may be formed over the substrate 101 to cover the spacer layers 601, the unit contact structures 500, the spacer structures 400, and the bit line structures 300. In some embodiments, the top insulating layer 109 may include the same material as the bit line covering layer 307. In some embodiments, the top insulating layer 109 may include, for example, silicon nitride or other applicable insulating materials.

[0147] Using a liner 501 including doped polysilicon, doped polygermanium, or doped silicon-germanium can be used to reduce the junction leakage of the unit contact structure 500. In addition, using a contact layer 503 including materials such as titanium nitride, tungsten, or titanium can effectively reduce the sheet resistance of the unit contact structure 500. These enhancements together can improve the performance of the semiconductor device 1A.

[0148] Figures 27 to 29 Cross-sectional schematic views showing semiconductor devices 1B, 1C, and 1D according to some embodiments of the present disclosure.

[0149] As Figure 27 shown, the semiconductor device 1B may have a structure similar to that Figure 26 shown. Figure 27 Elements that are the same or similar to those in Figure 26 have been denoted with the same reference numerals, and repeated descriptions have been omitted.

[0150] In the semiconductor device 1B, the bit line structure 300 may include a bit line bottom conductive layer 305, a bit line intermediate conductive layer 303, a bit line top conductive layer 301, and a bit line covering layer 307.

[0151] The bit line bottom conductive layer 305 can be disposed on the bit line contact 309. In some embodiments, the bit line bottom conductive layer 305 can include, for example, doped polysilicon, doped polygermanium, or doped silicon germanium, or a combination of the foregoing. In some embodiments, the dopant for the bit line bottom conductive layer 305 can include boron, aluminum, gallium, indium, antimony, arsenic, or phosphorus.

[0152] The bit line intermediate conductive layer 303 can be disposed on the bit line bottom conductive layer 305. In some embodiments, the bit line intermediate conductive layer 303 can include, for example, titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide. In some embodiments, the bit line intermediate conductive layer 303 can have a thickness between about 2 nm and about 20 nm.

[0153] The bit line top conductive layer 301 can be disposed on the bit line intermediate conductive layer 303. In some embodiments, the bit line top conductive layer 301 can include, for example, titanium, nickel, platinum, tantalum, cobalt, silver, copper, aluminum, other applicable conductive materials, or a combination of the foregoing.

[0154] The bit line cover layer 307 can be disposed on the bit line top conductive layer 301. In some embodiments, the bit line cover layer 307 can include, for example, silicon nitride or other applicable insulating materials.

[0155] Referring to Figure 28 , the semiconductor element 1C can have a structure similar to Figure 26 shown. Figure 28 In Figure 26 the same or similar elements as those in

[0156] In the semiconductor element 1C, the spacer structures 400 can include a plurality of in-bit-line spacers 401, a plurality of air gaps 407, and a plurality of out-of-bit-line spacers 405. The in-bit-line spacers 401 can be respectively disposed on the side surfaces 300S of the bit line structure 300. The out-of-bit-line spacers 405 can be respectively disposed on the in-bit-line spacers 401. The air gaps 407 can be disposed between the in-bit-line spacers 401 and the out-of-bit-line spacers 405. The use of the air gaps 407 can reduce the dielectric constant of the spacer structure 400. As a result, the parasitic capacitance between adjacent conductive components (e.g., adjacent bit line structures 300) can be reduced.

[0157] Referring to Figure 29 , the semiconductor element 1D can have a structure similar to Figure 26 shown. Figure 29 In Figure 26Identical or similar elements are denoted by the same reference signs, and repeated descriptions are omitted.

[0158] In the semiconductor element 1D, there is no word line barrier layer 203 as shown in Figure 26 The word line conductive layer 205 may be directly disposed on the word line dielectric layer 201. In this embodiment, the word line conductive layer 205 may include titanium nitride.

[0159] One aspect of the present disclosure provides a unit contact structure, which includes: a contact layer located on a substrate and surrounded by a plurality of bit line structures and a plurality of spacer layers; and a liner layer located between the contact layer and the substrate, between the contact layer and the bit line structures, and between the contact layer and the spacer layers. A top surface of the contact layer and a top surface of the liner layer are substantially coplanar. The liner layer includes doped polysilicon, doped polygermanium, or doped polysilicon germanium. The contact layer includes tungsten, titanium, or titanium nitride.

[0160] Another aspect of the present disclosure provides a semiconductor element, which includes: a substrate; two bit line structures formed on the substrate, extending along a first direction and separated from each other; two spacer layers located on the substrate, extending along a second direction perpendicular to the first direction and separated from each other, and simultaneously contacting the two bit line structures; and a unit contact structure. The unit contact structure includes: a contact layer located on the substrate and surrounded by the two bit line structures and the two spacer layers; and a liner layer located between the substrate and the contact layer, between the two bit line structures and the contact layer, and between the two spacer layers and the contact layer. A top surface of the liner layer and a top surface of the contact layer are substantially coplanar. The liner layer includes doped polysilicon, doped polygermanium, or doped polysilicon germanium. The contact layer includes tungsten, titanium, or titanium nitride.

[0161] Another aspect of the present disclosure provides a method for manufacturing a semiconductor element, which includes: providing a substrate; forming two bit line structures on the substrate, extending along a first direction and separated from each other; forming a plurality of spacer structures on side surfaces of the two bit line structures; forming two spacer layers on the substrate, extending along a second direction perpendicular to the first direction and separated from each other, thereby generating a contact opening combined with the spacer structures; conformally forming a liner layer in the contact opening; and forming a contact layer on the liner layer and in the contact opening. The liner layer includes doped polysilicon, doped polygermanium, or doped polysilicon germanium. The contact layer includes tungsten, titanium, or titanium nitride. The liner layer and the contact layer together constitute a unit contact structure.

[0162] Due to the design of the semiconductor device of the present disclosure, junction leakage of the cell contact structure 500 can be reduced by adopting a layer 501 including doped polysilicon, doped polycrystalline germanium, or doped polysilicon germanium. In addition, sheet resistance of the cell contact structure 500 can be reduced by adopting a contact layer 503 including titanium nitride, tungsten, or titanium. As a result, the performance of the semiconductor device 1A can be improved.

[0163] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the above-described processes can be implemented in different ways, and many of the above-described processes can be replaced by other processes or combinations of the foregoing.

[0164] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art can understand from the disclosure of the present disclosure that existing or future-developed processes, machines, manufactures, compositions of matter, means, methods, or steps that perform the same function or achieve substantially the same result as the corresponding embodiments described herein can be used in accordance with the present disclosure. Accordingly, these processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A method for manufacturing a semiconductor device, comprising: providing a substrate; forming two bit line structures on the substrate, extending along a first direction and separated from each other; forming a plurality of spacer structures on sides of the two bit line structures; forming two isolation layers on the substrate, extending along a second direction perpendicular to the first direction and separated from each other, thereby creating a contact opening combined with the spacer structures; conformally forming a liner layer in the contact opening; and forming a contact layer on the liner layer and within the contact opening, wherein the liner layer comprises doped polysilicon, doped polygermanium, or doped polysilicon germanium, wherein the contact layer comprises tungsten, titanium, or titanium nitride, and wherein the liner layer and the contact layer together constitute a unit contact structure.

2. The manufacturing method according to claim 1, wherein forming the two isolation layers comprises: forming a sacrificial layer on the substrate to cover the two bit line structures and the spacer structures; performing a first planarization process until upper surfaces of the two bit line structures are exposed; forming a first mask layer on the sacrificial layer, wherein the first mask layer comprises a linear pattern partially exposing the sacrificial layer, the spacer structures, and the two bit line structures; selectively removing the sacrificial layer to form two isolation layer openings; removing the first mask layer; forming a layer of isolation material to completely fill the two isolation layer openings and cover the two bit line structures and the spacer structures; and performing a second planarization process until upper surfaces of the two bit line structures are exposed and the sacrificial layer is exposed, to convert the layer of isolation material into the two isolation layers.

3. The manufacturing method according to claim 2, wherein the sacrificial layer comprises silicon oxynitride or silicon nitride oxide.

4. The manufacturing method according to claim 2, wherein the layer of isolation material comprises silicon nitride.

5. The manufacturing method according to claim 2, further comprising: selectively removing the sacrificial layer to form the contact opening.

6. The manufacturing method according to claim 5, wherein forming the spacer structures comprises: forming a plurality of in-bit-line spacers on sides of the two bit line structures; forming a plurality of between-bit-line spacers on the in-bit-line spacers; and forming a plurality of out-of-bit-line spacers on the between-bit-line spacers.

7. The manufacturing method according to claim 6, wherein the in-bit-line spacers and the between-bit-line spacers comprise the same material.

8. The manufacturing method according to claim 7, wherein the between-bit-line spacers comprise silicon oxide.

9. The manufacturing method according to claim 6, wherein the in-bit-line spacers comprise silicon nitride.

10. The manufacturing method according to claim 1, wherein the liner layer comprises an n-type dopant.

11. The manufacturing method according to claim 1, wherein the liner layer comprises a p-type dopant.

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