Square flat leadless packaging structure

Abstract

The invention provides a quad flat no-lead packaging structure. The quad flat no-lead packaging structure comprises a lead frame, a semiconductor tube core, a packaging material and a cooling fin, the lead frame includes a die pad and a plurality of contacts surrounding the die pad. A semiconductor die is disposed on the die pad and electrically connected to the plurality of contacts, where a shortest distance between the semiconductor die and a first side of the die pad is shorter than a shortest distance between the semiconductor die and a second side of the die pad, and the first side is opposite the second side. An encapsulation material encapsulates the lead frame and the semiconductor die and partially exposes the plurality of contacts, and a heat sink disposed over the encapsulation material, where the heat sink has a coefficient of thermal expansion that is less than a coefficient of thermal expansion of the lead frame.

Description

[0001] This divisional application is a divisional application of the invention patent application with the application date of May 28, 2021, the application number of 202110590120.1, and the invention name of "Quad Flat No-Lead Package Structure". Technical Field

[0002] The present invention relates to a package structure. More specifically, the present invention relates to a quad flat no-lead package structure. Background Art

[0003] The semiconductor industry has experienced rapid growth due to the continuous increase in the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.). Primarily, this increase in integration density comes from the repeated reduction of the minimum feature size, which allows more components to be integrated into a given area. With the recent growth in the demand for even smaller electronic devices, there has emerged a need for packaging technologies for smaller and more innovative semiconductor dies.

[0004] As the demand for smaller electronic products increases, the electronics industry must continuously research and develop higher-density electronic packaging. Various technologies have been developed to meet the requirements for higher quality and reliability improvement, and various chip scale package (CSP) technologies have been developed for high-density packaging.

[0005] Based on a lead frame and for low pin count devices, the quad flat no-lead (QFN) package is one of these CSP technologies. The main characteristic of the QFN package is that it does not consist of external leads, thus shortening the transmission distance and reducing the resistance to improve signal transmission.

[0006] Due to the mismatch of the coefficients of thermal expansion (CTE) of different materials of the package, package warpage may occur. If not controlled, warpage may damage the QFN package and result in a reduced yield of semiconductor manufacturing. There is a need in the art for a structure and manufacturing method for a QFN package with reduced warpage. Summary of the Invention

[0007] Therefore, the present invention aims at a quad flat no-lead package structure with less warpage.

[0008] The present invention provides a quad flat no-lead (QFN) package structure, which includes a lead frame, a semiconductor die, and an encapsulation material. The lead frame includes a die pad and a plurality of contacts surrounding the die pad. The semiconductor die is disposed on the die pad and electrically connected to the plurality of contacts, wherein the shortest distance between the semiconductor die and the first side of the die pad is shorter than the shortest distance between the semiconductor die and the second side of the die pad, and the first side and the second side are opposite to each other. The encapsulation material encapsulates the lead frame and the semiconductor die and partially exposes the plurality of contacts, wherein the aspect ratio of the QFN package structure is generally equal to or greater than 3.

[0009] According to an embodiment of the present invention, the QFN package structure further includes a plurality of conductive wires connected between the semiconductor die and the plurality of contacts.

[0010] According to an embodiment of the present invention, the plurality of contacts include a plurality of first contacts closer to the first side and a plurality of second contacts closer to the second side, and the plurality of conductive wires include a plurality of first conductive wires connected between the semiconductor die and the plurality of first contacts, and a plurality of second conductive wires connected between the semiconductor die and the plurality of second contacts.

[0011] According to an embodiment of the present invention, each of the plurality of first conductive wires is generally equal to or shorter than each of the plurality of second conductive wires.

[0012] According to an embodiment of the present invention, each of the plurality of first conductive wires is generally equal to or shorter than 1000 micrometers.

[0013] According to an embodiment of the present invention, the QFN package structure further includes a ground ring surrounding the periphery of the die pad, and a plurality of ground wires connected between the semiconductor die and the ground ring.

[0014] According to an embodiment of the present invention, the plurality of ground wires include a plurality of first ground wires connected between the semiconductor die and a part of the ground ring on the first side, and a plurality of second ground wires connected between the semiconductor die and another part of the ground ring on the second side.

[0015] According to an embodiment of the present invention, each of the plurality of first ground wires is shorter than each of the plurality of second ground wires.

[0016] According to an embodiment of the present invention, the QFN package structure further includes a warpage control metal layer disposed above the encapsulation material.

[0017] According to an embodiment of the present invention, the difference between the coefficient of thermal expansion (CTE) of the warpage control metal layer and the CTE of the lead frame is generally equal to or less than 10%.

[0018] According to an embodiment of the present invention, the warpage control metal layer and the lead frame are located on two opposite sides of the encapsulation material.

[0019] According to an embodiment of the present invention, the QFN package structure further includes a solder mask layer disposed between the warpage control metal layer and the encapsulation material.

[0020] According to an embodiment of the present invention, the lead frame further includes a plurality of connecting bars connected to the die pad and extending outward to the outer edge of the encapsulation material.

[0021] According to an embodiment of the present invention, at least one of the connecting bars is connected to the first side or the second side of the die pad.

[0022] According to an embodiment of the present invention, the die pad further includes a plurality of depressions disposed on a blank area where no semiconductor die is disposed.

[0023] According to an embodiment of the present invention, the plurality of depressions are disposed along the second side.

[0024] According to an embodiment of the present invention, the thickness of the semiconductor die is generally equal to or greater than 10 mils.

[0025] According to an embodiment of the present invention, the maximum thickness of the lead frame is generally equal to or greater than 8 mils.

[0026] According to an embodiment of the present invention, the thickness of the encapsulation material is generally equal to or greater than 0.6 mm.

[0027] According to an embodiment of the present invention, the QFN package structure further includes a die attach film disposed between the semiconductor die and the die pad.

[0028] The present invention provides a QFN package structure, including a lead frame, a semiconductor die, an encapsulation material, and a warpage control metal layer. The lead frame includes a die pad and a plurality of contacts surrounding the die pad. The semiconductor die is disposed on the die pad and electrically connected to the plurality of contacts. The encapsulation material encapsulates the lead frame and the semiconductor die and partially exposes the plurality of contacts, wherein the aspect ratio of the QFN package structure is generally equal to or greater than 3. The warpage control metal layer is disposed above the encapsulation material.

[0029] According to an embodiment of the present invention, the difference between the CTE of the warpage control metal layer and the CTE of the lead frame is generally equal to or less than 10%.

[0030] According to an embodiment of the present invention, the warpage control metal layer and the lead frame are located on two opposite sides of the encapsulation material.

[0031] According to an embodiment of the present invention, the QFN package structure further includes a solder mask layer disposed between the warpage control metal layer and the encapsulation material.

[0032] According to an embodiment of the present invention, the shortest distance between the semiconductor die and the first side of the die pad is shorter than the shortest distance between the semiconductor die and the second side of the die pad, and the first side and the second side are opposite to each other.

[0033] Based on the above, the QFN package structure is designed to have a relatively high aspect ratio (equal to or greater than about 3) to have better space utilization. Additionally, for a QFN package structure with a relatively high aspect ratio, the QFN package structure suffers from more severe warping. Therefore, the QFN package structure may further include a warpage control metal layer disposed above the encapsulation material, and the difference between the CTE of the warpage control metal layer and the CTE of the lead frame is substantially equal to or less than 10%. Thus, the warpage control metal layer can not only contribute to heat dissipation of the QFN package structure, but also provide support and mechanical strength to the QFN package structure and reduce the warpage of the QFN package structure.

[0034] To better understand the foregoing, several embodiments with accompanying drawings are described in detail below. Description of the Drawings

[0035] The accompanying drawings are included to provide a further understanding of the present invention, and the accompanying drawings are incorporated into and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present invention and, together with the description, are used to explain the principles of the present invention.

[0036] Figure 1 Schematic top view of a QFN package structure according to some embodiments of the present invention;

[0037] Figure 2 Schematic cross-sectional view of a QFN package structure according to some embodiments of the present invention;

[0038] Figure 3 Schematic top view of a QFN package structure according to another embodiment of the present invention;

[0039] Figure 4 Schematic top view of a QFN package structure according to still another embodiment of the present invention.

[0040] Description of the Reference Numerals in the Drawings

[0041] 100, 100a, 100b: Quad Flat No-Lead package structure;

[0042] 110: Lead frame;

[0043] 112: Die pad;

[0044] 114: Contact;

[0045] 114a: First contact;

[0046] 114b: Second contact;

[0047] 116: Connecting rod;

[0048] 120: Semiconductor die;

[0049] 122: Active surface;

[0050] 124: Back surface;

[0051] 126: Bonding pad;

[0052] 130: Encapsulation material;

[0053] 140: Conductive wire;

[0054] 142: First conductive wire;

[0055] 144: Second conductive wire;

[0056] 150: Ground wire;

[0057] 152: First ground wire;

[0058] 154: Second ground wire;

[0059] 160: Warpage control metal layer;

[0060] 162: Solder mask layer;

[0061] 164: Barrier layer;

[0062] 170: Die attach film;

[0063] 1121: Grounding ring;

[0064] 1122: Depression;

[0065] 1161, 1162: Connecting rod;

[0066] D1, D2: Shortest distance;

[0067] S1: First side;

[0068] S2: Second side. Detailed implementation

[0069] The present invention will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. As used herein, the terms such as "on", "above", "below", "in front of", "behind", "on the left side of", and "on the right side of" are for the purpose of describing the directions in the drawings only and are not intended to limit the present invention. Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are shown in the accompanying drawings. In addition, in the following embodiments, the same or similar reference numerals denote the same or similar components.

[0070] Figure 1 A schematic top view showing a QFN package structure according to some embodiments of the present invention. Figure 2 A schematic cross-sectional view showing a QFN package structure according to some embodiments of the present invention. A package configuration called quad flat no-lead (QFN) package is similar to QFP. However, the corresponding contacts (leads) do not extend out of the QFN package. Utilizing the characteristics of hidden leads and tight adhesion to the circuit board during bonding, the QFN package meets the requirements of the light, thin, simple, and compact configuration of modern electrical components (especially components used in mobile electronic devices such as smartphones, tablet PCs, or laptop computers).

[0071] Reference Figure 1 , in some embodiments, a quad flat no-lead (QFN) package structure 100 may include a lead frame 110, a semiconductor die 120, and an encapsulation material 130. In some embodiments, the lead frame 110 includes a die pad 112 and a plurality of contacts 114 surrounding the die pad 112. The lead frame 110 has an upper surface and a lower surface opposite to the upper surface. It should be noted that the setting of the upper surface and the lower surface is for the convenience of description only and does not represent the physical direction of the lead frame 110. In some embodiments, the contacts 114 of the lead frame 110 may be a plurality of leads disposed around the die pad 112. Methods and manufacturing tools known in the art can be used to form the lead frame 110, and materials known in the art can be used to form the lead frame 110. In some embodiments, copper (Cu), copper alloy materials, and a wide range of metal and metal alloy materials can be used to make the lead frame 110 to suit specific applications. The lead frame 110 can be made of any suitable material for semiconductor chip packaging. Of course, specific materials can be used for certain packages for specific purposes.

[0072] In some embodiments, the semiconductor die 120 has an active surface 122, a back surface 124 opposite the active surface 122, and a plurality of bonding pads 126 formed on the active surface 122 of the semiconductor die 120. In some embodiments, the semiconductor die 120 is disposed on the die pad 112 and electrically connected to the contacts 114 of the lead frame 110. In one embodiment, the back surface 124 of the semiconductor die 120 is adhered to the upper surface of the die pad 112. The QFN package structure 100 may further include a plurality of conductive wires 140 that connect between the semiconductor die 120 and the contacts (leads) 114. More specifically, the conductive wires 140 electrically connect the bonding pads 126 of the semiconductor die 120 to the contacts 114 of the lead frame 110. That is, the semiconductor die 120 is disposed and bonded to the contacts 114 of the lead frame 110 by wire bonding technology. In some embodiments, the encapsulant material 130 encapsulates a portion of the lead frame 110 and the semiconductor die 120. In one embodiment, the encapsulant material 130 encapsulates the semiconductor die 120, the conductive wires 140, the upper surface of the die pad 112, and the upper surface 114 of the contacts 114. In some embodiments, the lower surface of the die pad 112 and the lower surface of the contacts 114 are at least partially exposed by the encapsulant material 130 for further connection.

[0073] In some embodiments, for better space (layout) utilization, the aspect ratio of the QFN package structure 100 is designed as a rectangular package. That is, the QFN package structure 100 is designed to have a higher aspect ratio (larger length-to-width ratio). For example, the aspect ratio of the QFN package structure 100 can be approximately equal to or greater than 2.3. In an embodiment of the present invention, the aspect ratio of the QFN package structure 100 is generally equal to or greater than 3. Under the condition of having the same number of pins (leads) and pin pitch, compared with the conventional square QFN package, the package size (occupied area) of the QFN package structure 100 with a higher aspect ratio can be reduced by up to about 25%. Additionally, with the configuration of the QFN package structure 100 having a higher aspect ratio, the number of QFN packages that can be produced from each leadframe strip can be increased. Therefore, the productivity of the QFN package structure 100 can be improved, and on the other hand, the production cost of the QFN package structure 100 can be reduced.

[0074] According to some embodiments of the present invention, the die pad 112 may have a first side S1 and a second side S2 that face each other. In an embodiment of the QFN package structure 100 having a rectangular shape (i.e., having a high aspect ratio), the die pad 112 correspondingly has a rectangular shape. In the embodiments of the present invention, the first side S1 and the second side S2 are the two long side edges of the die pad 112. In some embodiments, the shortest distance D1 between the semiconductor die 120 and the first side S1 of the die pad 112 is shorter than the shortest distance D2 between the semiconductor die 120 and the second side S2 of the die pad 112. In other words, the semiconductor die 120 is placed on the die pad 112 in an asymmetric manner. That is, the semiconductor die 120 is offset (deviated) from the central long axis of the die pad 112.

[0075] Therefore, the contacts 114 may include a plurality of first contacts 114a and a plurality of second contacts 114b. The first contacts 114a are closer to the first side S1, while the second contacts 114b are closer to the second side S2. Similarly, the conductive lines 140 include a plurality of first conductive lines 142 and a plurality of second conductive lines 144, where the first conductive lines 142 are connected between the semiconductor die 120 and the plurality of first contacts 114a, and the second conductive lines 144 are connected between the semiconductor die 120 and the second contacts 114b. Therefore, each of the first conductive lines 142 is generally equal to or shorter than each of the second conductive lines 144 to reduce the impedance of the first conductive lines 142. For example, each of the first conductive lines 142 is generally equal to or shorter than 1000 microns. For an embodiment of the semiconductor die 120 that is a driver IC (such as a mini-LED or a micro-LED) for a display, components (such as switches or MOSs) that are highly sensitive to impedance may be placed on the side of the semiconductor die 120 closer to the first side S1 so that the impedance can be reduced and the electrical performance of the semiconductor die 120 can be significantly improved.

[0076] In some embodiments, the QFN package structure 100 may further include a ground ring 1121 surrounding the periphery of the die pad 112, and a plurality of ground wires 150 connected between the semiconductor die 120 and the ground ring 1121. Thus, the ground pad of the semiconductor die 120 is connected to the ground ring 1121 via the ground wires 150 to be grounded. In some embodiments, the ground ring 1121 may be a silver ring plated on the die pad 112. In an embodiment where the semiconductor die 120 is offset toward the first side S1 of the die pad 112, the ground wires 150 include a plurality of first ground wires 152 and a plurality of second ground wires 154, where the first ground wires 152 are connected between the semiconductor die 120 and a portion of the ground ring 1121 on the first side S1, and the second ground wires 154 are connected between the semiconductor die 120 and another portion of the ground ring 1121 on the second side S2. Accordingly, each of the first ground wires 152 is shorter than each of the second ground wires 154 to reduce the impedance of the first ground wires 152. For example, each of the first ground wires 152 is generally equal to or shorter than 600 microns.

[0077] In embodiments of the QFN package structure 100 having a higher aspect ratio, the QFN package structure 100 may suffer from more severe warping. Accordingly, the QFN package structure 100 may further include a warpage control metal layer 160 disposed above the encapsulation material 130. In some embodiments, the warpage control metal layer 160 may be a heat sink. Thus, the warpage control metal layer 160 can not only contribute to heat dissipation of the QFN package structure 100, but also provide support and mechanical strength to the QFN package structure 100. In some embodiments, the warpage control metal layer 160 and the lead frame 110 are located on two opposite sides of the encapsulation material 130, and the difference between the coefficient of thermal expansion (CTE) of the warpage control metal layer 160 and the CTE of the lead frame 110 is generally equal to or less than 10%. In other words, the encapsulation material 130 is disposed between the lead frame 110 and the warpage control metal layer 160 having similar CTEs. Further, since the CTE of the warpage control metal layer 160 is similar to the CTE of the lead frame 110, the problems of thermal stress and warping caused by the CTS mismatch between the lead frame 110 and the encapsulation material 130 can be further improved.

[0078] In some embodiments, a barrier layer 164, such as a nickel / chromium layer, may be disposed (deposited) over the warp control metal layer 160 to prevent oxidation of the warp control metal layer (e.g., copper layer) 160. The warp control metal layer 160 may be bonded to the encapsulant material 130 during a molding process via thermocompression (lamination). In some embodiments, a solder mask layer 162 may be disposed between the encapsulant material 130 and the warp control metal layer 160 to enhance the bond between the encapsulant material 130 and the warp control metal layer 160. The configuration of the warp control metal layer 160 reduces the thermal resistance of the QFN package structure 100 by about 10% or more than 10%.

[0079] In some embodiments, the lead frame 110 further includes a plurality of tie bars 116 that are connected to the die pad 112 and extend outwardly to the outer edge of the encapsulant material 130. Generally, the tie bars 116 project outside the encapsulant material 130 during the molding process to connect the die pad 112 to, for example, a lead frame strip. After the molding process, the protruding portions of the tie bars 116 are removed by a cutting or singulation process or the like. In some embodiments, the tie bars 116 may have the shape of lead fingers and may be formed from, for example, a foil or in the form of separately molded components. In some embodiments, the tie bars 116 may be disposed at the corners of the die pad 112 that extend outwardly to the outer edge of the encapsulant material 130, as shown in Figure 1 as depicted therein.

[0080] According to some embodiments of the present invention, for a QFN package structure that suffers from more severe warping (such as a QFN package structure having a higher aspect ratio), a portion of the components may be adjusted to reduce the warping of the package. For example, the thickness T1 of the semiconductor die 120 is generally equal to or greater than 10 mils, the maximum thickness T2 of the lead frame 110 is generally equal to or greater than 8 mils, and the thickness T3 of the encapsulant material 130 is generally equal to or greater than 0.6 mm. However, the reference numerals shown above are for illustrative purposes only. The present invention is not limited thereto. In some embodiments, the semiconductor die 120 may be attached to the die pad 112 via a die attach film 170 instead of a conventional silver paste to further reduce the warping of the QFN package structure 100a. That is, the QFN package structure 100a may further include a die attach film 170 disposed between the semiconductor die 120 and the die pad 112.

[0081] Figure 3 A schematic top view of a QFN package structure according to another embodiment of the present invention is shown. It should be noted that the QFN package structure 100a shown in Figure 3 contains the same as previously utilized Figure 1 and Figure 2The disclosed QFN package structure 100 has many identical or similar features. For the purposes of clarity and simplicity, the detailed description of identical or similar features may be omitted, and identical or similar reference numerals denote identical or similar components. The QFN package structure 100a shown in Figure 3 is described below with respect to the main differences between the QFN package structure 100 shown in Figure 1 and Figure 2 and the QFN package structure 100.

[0082] Referring to Figure 3 , in some embodiments, for QFN package structures that suffer from more severe warping (such as QFN package structures with a higher aspect ratio), a portion of the connecting rod 116 from the connecting rods 116 disposed at the corners of the die pad 112, at least one of the connecting rods 116 may be connected to the first side S1 or the second side S2 of the die pad 112. For example, the connecting rod 116 may include a plurality of connecting rods 1161 disposed at the corners of the die pad 112, and at least one connecting rod 1162 disposed at the first side S1 or the second side S2 of the die pad 112 (connected to the first side S1 or the second side S2). In an embodiment of the present invention, the connecting rod 116 includes a plurality of connecting rods 1162 disposed at both the first side S1 and the second side S2 of the die pad 112. That is, for QFN package structures with a higher aspect ratio, some of the connecting rods 116 may be disposed at the long sides S1, S2 of the die pad 112 to provide mechanical strength and thereby reduce warping.

[0083] Figure 4 Fig. shows a schematic top view of a QFN package structure according to still another embodiment of the present invention. It should be noted that the QFN package structure 100b shown in Figure 4 has many identical or similar features to the QFN package structures 100, 100a disclosed in the previous embodiments. For the purposes of clarity and simplicity, the detailed description of identical or similar features may be omitted, and identical or similar reference numerals denote identical or similar components. The main differences between the QFN package structure 100b shown in Figure 4 and the QFN package structures 100, 100a disclosed in the previous embodiments are described below.

[0084] Referring to Figure 4, in some embodiments, the die pad 112 may further include a plurality of recesses 1122 disposed on the void areas therein where no semiconductor die 120 is disposed. For example, in an embodiment where the semiconductor die 120 is shifted (offset) toward the first side S1 of the die pad 112, the recesses 1122 may be disposed along the second side S2 of the die pad 112. The recesses 1122 are concave portions recessed toward the lower surface of the die pad 112, and the encapsulation material 130 fills the recesses 1122 when encapsulating the QFN package structure 100b. Thus, the configuration of the recesses 1122 increases the contact area between the encapsulation material 130 and the die pad 112, so as to improve the bonding strength between the encapsulation material 130 and the lead frame 110. Therefore, the problem of delamination between the encapsulation material 130 and the lead frame 110 is reduced, and the reliability of the QFN package structure is improved.

[0085] In summary, the QFN package structure is designed to have a relatively high aspect ratio (equal to or greater than about 3) for better space (layout) utilization. Additionally, the semiconductor die is offset (shifted) toward the long side of the die pad to shorten the conductive lines on the long side, so as to reduce the impedance and significantly improve the electrical performance of the semiconductor die.

[0086] Furthermore, for a QFN package structure with a relatively high aspect ratio, the QFN package structure may suffer from more severe warping. Thus, the QFN package structure may further include a warpage control metal layer disposed above the encapsulation material, and the difference between the CTE of the warpage control metal layer and the CTE of the lead frame is generally equal to or less than 10%. Therefore, the warpage control metal layer can not only contribute to the heat dissipation of the QFN package structure, but also provide support and mechanical strength to the QFN package structure and reduce the warping of the QFN package structure.

[0087] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A quad flat no-lead package structure, characterized in that, Comprising: A lead frame, including a die pad and a plurality of contacts surrounding the die pad; A semiconductor die, disposed on the die pad and electrically connected to the plurality of contacts, wherein the shortest distance between the semiconductor die and the first side of the die pad is shorter than the shortest distance between the semiconductor die and the second side of the die pad, and the first side and the second side are opposite to each other; An encapsulation material, encapsulating the lead frame and the semiconductor die and partially exposing the plurality of contacts; And A heat sink, disposed above the encapsulation material, wherein the coefficient of thermal expansion of the heat sink is less than the coefficient of thermal expansion of the lead frame.

2. The quad flat no-lead package structure according to claim 1, wherein It further includes a plurality of conductive wires, and the plurality of conductive wires are connected between the semiconductor die and the plurality of contacts.

3. The quad flat no-lead package structure according to claim 2, wherein The plurality of contacts include a plurality of first contacts closer to the first side of the die pad and a plurality of second contacts closer to the second side of the die pad. The plurality of conductive wires include a plurality of first conductive wires connected between the semiconductor die and the plurality of first contacts, and a plurality of second conductive wires connected between the semiconductor die and the plurality of second contacts.

4. The quad flat no-lead package structure according to claim 3, characterized in that Each of the plurality of first conductive wires is equal to or shorter than each of the plurality of second conductive wires.

5. The quad flat no-lead package structure according to claim 3, characterized in that Each of the plurality of first conductive wires is equal to or shorter than 1000 microns.

6. The quad flat no-lead package structure according to claim 1, wherein It further includes a ground ring surrounding the periphery of the die pad, and a plurality of ground wires connected between the semiconductor die and the ground ring.

7. The quad flat no-lead package structure according to claim 6, wherein The plurality of ground wires include a plurality of first ground wires connected between the semiconductor die and a part of the ground ring on the first side of the die pad, and a plurality of second ground wires connected between the semiconductor die and another part of the ground ring on the second side of the die pad.

8. The quad flat no-lead package structure according to claim 7, characterized in that Each of the plurality of first ground wires is shorter than each of the plurality of second ground wires.

9. The quad flat no-lead package structure according to claim 1, wherein, The difference between the coefficient of thermal expansion of the heat sink and the coefficient of thermal expansion of the lead frame is equal to or less than 10%.

10. The quad flat no-lead package structure according to claim 1, wherein The heat sink and the lead frame are located on two opposite sides of the encapsulation material.

11. The quad flat no-lead package structure according to claim 1, wherein It further includes a solder mask layer, and the solder mask layer is disposed between the heat sink and the encapsulation material.

12. The quad flat no-lead package structure according to claim 1, wherein, The lead frame further includes a plurality of connecting rods, and the plurality of connecting rods are connected to the die pad and extend outward to the outer edge of the encapsulation material.

13. The quad flat no-lead package structure according to claim 12, wherein At least one of the connecting rods is connected to the first side or the second side of the die pad.

14. The quad flat no-lead package structure according to claim 1, wherein, The die pad further includes a plurality of depressions, and the plurality of depressions are disposed on the blank area where the semiconductor die is not disposed.

15. The quad flat no-lead package structure according to claim 14, wherein, The plurality of depressions are disposed along the second side of the die pad.

16. The quad flat no-lead package structure according to claim 1, characterized in that, The thickness of the semiconductor die is equal to or greater than 10 mils.

17. The quad flat no-lead package structure according to claim 1, wherein The maximum thickness of the lead frame is equal to or greater than 8 mils.

18. The quad flat no-lead package structure according to claim 1, wherein, The thickness of the encapsulation material is equal to or greater than 0.6 mm.

19. The quad flat no-lead package structure according to claim 1, wherein It further includes a die attach film, and the die attach film is disposed between the semiconductor die and the die pad.

20. The quad flat no-lead package structure according to claim 1, wherein The aspect ratio of the quad flat no-lead package structure is equal to or greater than 3.

21. A quad flat no-lead package structure, characterized in that, Comprising: A lead frame, including a die pad and a plurality of contacts surrounding the die pad; A semiconductor die, disposed on the die pad and electrically connected to the plurality of contacts; And An encapsulation material, encapsulating the lead frame and the semiconductor die and partially exposing the plurality of contacts; And A heat sink, disposed above the encapsulation material, wherein a coefficient of thermal expansion of the heat sink is less than a coefficient of thermal expansion of the lead frame.

22. The quad flat no-lead package structure according to claim 21, wherein A difference between the coefficient of thermal expansion of the heat sink and the coefficient of thermal expansion of the lead frame is equal to or less than 10%.

23. The quad flat no-lead package structure according to claim 21, wherein The heat sink and the lead frame are located on two opposite sides of the encapsulation material.

24. The quad flat no-lead package structure according to claim 21, characterized in that, A solder mask layer is further included, and the solder mask layer is disposed between the heat sink and the encapsulation material.

25. The quad flat no-lead package structure according to claim 21, wherein, A shortest distance between a first side of the semiconductor die and the die pad is shorter than a shortest distance between a second side of the semiconductor die and the die pad, and the first side and the second side are opposite to each other.

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