TSV structure and circuit thereof

Abstract

The invention provides a through silicon via structure and a circuit thereof. A substrate has a first surface and a second surface, and the second surface is opposite to the first surface. A through silicon via extends from the first surface to the second surface of the substrate. An N-type doped region surrounds the TSV and extends from the first surface to the second surface of the substrate. A P-type well region is formed in the substrate and surrounds the N-type doped region. And the P-type doped region is formed in the P-type well region and surrounds the N-type doped region. A junction of the P-type well region and the N-type doped region forms an electrostatic discharge protection diode.

Description

Technical Field

[0001] The present invention relates to a through-silicon via (TSV) structure, and more particularly to a through-silicon via structure having an electrostatic discharge protection diode. Background Art

[0002] As the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) continues to improve, the semiconductor process nodes are scaled down. Along with the increasing demands for miniaturization, high speed, large bandwidth, low power consumption, and low latency, the demand for semiconductor chip packaging technology is also increasing day by day.

[0003] Three-dimensional (3D) circuits are a solution to the bottleneck in the development of two-dimensional circuits. 3D circuits use through-silicon vias (TSVs) as electrical connection paths to implement wafer or chip stack structures. Therefore, the length of metal wires and the impedance of wiring / traces can be shortened, and the chip area can be reduced, having the advantages of small size, high integration, high efficiency, low power consumption, and low cost.

[0004] Since electrostatic discharge can damage 3D circuits, it is necessary to provide electrostatic discharge protection for the through-silicon vias of 3D circuits. Summary of the Invention

[0005] Embodiments of the present invention provide a through-silicon via structure. A substrate has a first surface and a second surface, the second surface being opposite to the first surface. A through-silicon via extends from the first surface of the substrate to the second surface. An N-type doped region surrounds the through-silicon via and extends from the first surface of the substrate to the second surface. A P-type well region is formed in the substrate and surrounds the N-type doped region. A P-type doped region is formed in the P-type well region and surrounds the N-type doped region. A junction between the P-type well region and the N-type doped region forms an electrostatic discharge protection diode.

[0006] An embodiment of the present invention provides a circuit. The circuit includes a substrate and a plurality of through-silicon via (TSV) structures. The conductive substrate has a first surface and a second surface, and the second surface is opposite to the first surface. The TSV structure includes a TSV, an N-type doped region, a P-type well region, and a P-type doped region. The TSV extends from the first surface of the substrate to the second surface. The N-type doped region surrounds the TSV and extends from the first surface of the substrate to the second surface. The P-type well region is formed in the substrate and surrounds the N-type doped region. The P-type doped region is formed in the P-type well region and surrounds the N-type doped region. A junction of the P-type well region and the N-type doped region forms an electrostatic discharge (ESD) protection diode. The TSV of a first TSV structure among the plurality of TSV structures is electrically connected to a power line, and the P-type doped region of the first TSV structure is electrically connected to an input / output line. The TSV of a second TSV structure among the plurality of TSV structures is electrically connected to the input / output line, and the P-type doped region of the second TSV structure is electrically connected to a ground line.

[0007] The present invention provides a through-silicon via structure with stronger electrostatic discharge protection ability and significantly improved wafer area utilization efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 An electrostatic discharge (ESD) protection circuit provided according to the present invention.

[0009] Figure 2 A package structure of a three-dimensional circuit according to some embodiments of the present invention.

[0010] Figures 3A - 3E Cross-sectional schematic diagrams corresponding to different intermediate stages of manufacturing a through-silicon via structure according to some embodiments of the present invention.

[0011] Figure 4 A top view of a through-silicon via structure according to some embodiments of the present invention.

[0012] Figure 5A An electrostatic discharge protection circuit according to some embodiments of the present invention.

[0013] Figure 5B A connection configuration diagram of a through-silicon via structure in an electrostatic discharge protection circuit according to some embodiments of the present invention.

[0014] REFERENCE NUMERALS:

[0015] 10: Electrostatic discharge protection circuit

[0016] 12: Power line

[0017] 14: Input / output line

[0018] 16: Ground line

[0019] 20: Secondary protection unit

[0020] 22, 33, 34: P-type transistor

[0021] 24, 36, 38: N-type transistor

[0022] 23, 33, 35, 37, 39: Resistor

[0023] 30: Output driving unit

[0024] 40: Main protection unit

[0025] 50a - 50c: Through-silicon via

[0026] 100: Circuit

[0027] 110: Encapsulation substrate

[0028] 120: Bump

[0029] 130a - 130d: Chip

[0030] 140: Micro-bump

[0031] 150, 150a - 150c: Through-silicon via structure

[0032] 210: Substrate

[0033] 212: First surface

[0034] 214: Second surface

[0035] 220: Deep N-well region

[0036] 230: P-well region

[0037] 240: P-type doped region

[0038] 243: Opening

[0039] 245: Pad

[0040] 250: N-type doped region

[0041] 270: Through-silicon via

[0042] 275: Contact

[0043] 280: Dielectric hard mask layer

[0044] 290, 292: Metal wire

[0045] 310: Electrostatic discharge protection circuit

[0046] D1: Pull-up diode

[0047] D2: Pull-down diode

[0048] DESD: Electrostatic Discharge Protection Diode

[0049] H1, H2: Thickness

[0050] IO: Input or Output Signal

[0051] W1, W2: Length

[0052] VDD: Power Supply Signal

[0053] VSS: Ground Signal Detailed Implementation Manner

[0054] Figure 1 It is an electrostatic discharge (ESD) protection circuit 10 of the circuit shown in the present invention. The electrostatic discharge protection circuit 10 is used to provide electrostatic discharge protection for the input or output (I / O) pins of the circuit. The electrostatic discharge protection circuit 10 includes a main protection unit 40, a secondary protection unit 20, and an output driving unit 30. The main protection unit 40 includes a pull-up diode D1 and a pull-down diode D2. The anode of the pull-up diode D1 is coupled to the through-silicon via 50b through the input or output line 14, and the cathode of the pull-up diode D1 is coupled to the through-silicon via 50a through the power supply line 12. The anode of the pull-down diode D2 is coupled to the through-silicon via 50c through the ground line 16, and the cathode of the pull-down diode D2 is coupled to the through-silicon via 50b through the input or output line 14. In the circuit, the power supply signal VDD from other wafers, chips, or substrates will enter the power supply line 12 through the through-silicon via 50a. In addition, the ground signal VSS from other wafers, chips, or substrates will enter the ground line 16 through the through-silicon via 50c. In the input mode, the input or output signal IO from other wafers, chips, or substrates will enter the input or output line 14 through the through-silicon via 50b. In the output mode, the input or output signal IO from the internal circuit on the input or output line 14 will be transmitted to other wafers, chips, or substrates through the through-silicon via 50b.

[0055] The secondary protection unit 20 includes a P-type transistor 22, an N-type transistor 24, and a resistor 23. The secondary protection unit 20 is coupled to the input or output line 14 through the resistor 23. The output driving unit 30 includes P-type transistors 32 and 34, N-type transistors 36 and 38, and resistors 33, 35, 37, and 39. In the electrostatic discharge protection circuit 10, the circuits of the secondary protection unit 20 and the output driving unit 30 are an embodiment, and the actual circuit configuration can be adjusted according to different applications of the input or output pins of the circuit.

[0056] When an electrostatic discharge event of a positive charge occurs at an input or output pin of a circuit, the electrostatic current from the input or output pin will flow from the silicon via hole 50b to the silicon via hole 50a through the pull-up diode D1. When an electrostatic discharge event of a negative charge occurs at the input or output pin of the circuit, the electrostatic current from the input or output pin will flow from the silicon via hole 50b to the silicon via hole 50c through the pull-down diode D2. To increase the electrostatic discharge protection ability, the pull-up diode D1 and the pull-down diode D2 need to be designed as large sizes. In a conventional electrostatic discharge protection circuit, the layout areas of the pull-up diode D1 and the pull-down diode D2 are larger than the layout area of a silicon via hole.

[0057] Figure 2 The package structure of the three-dimensional circuit 100 according to some embodiments of the present invention. In the circuit 100, the silicon via hole structures 150 of the chip (or wafer) 130c and the chip (or wafer) 130d are connected to the chip (or wafer) 130b via micro bumps 140. In addition, the silicon via hole structure 150 of the chip 130b is connected to the chip (or wafer) 130a via micro bumps 140. Furthermore, the silicon via hole structure 150 of the chip 130a is connected to the package substrate 110 via bumps 120 so as to be connected to corresponding pins or pads (not shown).

[0058] Figures 3A - 3E A cross-sectional schematic diagram corresponding to different intermediate stages of manufacturing the silicon via hole structure 150 according to some embodiments of the present invention. The silicon via hole structure 150 includes a silicon via hole combined with an electrostatic discharge protection diode. Therefore, compared with Figure 1 the silicon via holes 50a, 50b and 50c, the silicon via hole structure 150 has stronger electrostatic discharge protection ability.

[0059] Refer to Figure 3A , a substrate 210 is provided. The material of the substrate 210 may include, for example, a semiconductor material. In other embodiments, the substrate 210 is a silicon-on-insulator substrate. The substrate 210 has a first surface 212 and a second surface 214, and the second surface 214 is opposite to the first surface 212. For example, the first surface 212 is the upper surface of the substrate 210, and the second surface 214 is the lower surface of the substrate 210.

[0060] A deep N-type well region (DNW) 220 is formed in a substrate 210, and a P-type well region (PW) 230 is formed in the deep N-type well region 220. Doping is performed on the P-type well region 230 to form a P-type doped region (P+) 240. In this embodiment, the upper surfaces of the deep N-type well region 220, the P-type well region 230, and the P-type doped region 240 are coplanar with a first surface 212 of the substrate 210. In some embodiments, under the application of the same signal to the substrate 210 and the P-type doped region 240, the silicon via structure 150 may omit the deep N-type well region 220.

[0061] A dielectric hard mask layer 280 is formed over the first surface 212 of the substrate 210. In some embodiments, the dielectric hard mask layer 280 is formed of a dielectric material such as silicon oxide (SiO), silicon oxynitride (SiON), silicon nitride (SiN), and / or other suitable dielectric materials. In some embodiments, the dielectric hard mask layer 280 is formed of tetraethyl orthosilicate (TEOS) oxide. In some embodiments, the dielectric hard mask layer 280 may be an inter-layer dielectric (ILD).

[0062] Reference Figure 3B , An etching process is performed to form an opening 243, and a liner 245 is formed in the opening 243. In some embodiments, the liner 245 may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The opening 243 and the liner 245 extend from the dielectric hard mask layer 280 to the substrate 210 and penetrate through the P-type well region 230 and the deep N-type well region 220.

[0063] Reference Figure 3C , The liner 245 is removed, and doping is performed on the opening 243 to form an N-type doped region (N+) 250. Thus, the N-type doped region 250 extends from the first surface 212 of the substrate 210 into the substrate 210.

[0064] Reference Figure 3D, a conductive material is formed in the opening 243 to form a through-silicon via 270. The material of the through-silicon via 270 may include copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. In addition, a contact 275 is formed in the dielectric hard mask layer 280, and the contact 275 is formed above the P-type doped region 240. In some embodiments, the contact 275 is formed of a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, their alloys and / or their multilayers. The formation of the contact 275 may include forming a plurality of contact openings in the dielectric hard mask layer 280, filling the conductive material into the contact openings, and performing a planarization process (such as Chemical Mechanical Polish (CMP)). The top surfaces of the contact 275 and the through-silicon via 270 are flush with the top surface of the dielectric hard mask layer 280.

[0065] An interconnection structure is formed above the dielectric hard mask layer 280. For simplicity of illustration, only the metal lines 290 and 292 formed in the lowest metal layer of the interconnection structure are shown. The metal line 290 is formed above the through-silicon via 270, and the metal line 292 is formed above the contact 275. In an embodiment of the present invention, the through-silicon via 270 penetrates through the dielectric hard mask layer 280 and contacts the metal line 290, so that the metal line 290 is electrically connected to the through-silicon via 270. In addition, the metal line 292 is electrically connected to the P-type doped region 240 via the contact 275.

[0066] Reference Figure 3E , a thinning process is performed on the second surface 214 of the substrate 210. The thinning process may include a planarization process (chemical mechanical polishing), an etch-back process, or a combination thereof, etc. The substrate 210 can be thinned to shorten the length of the through-silicon via 270. In some embodiments, the thickness H1 of the through-silicon via 270 penetrating through the substrate 210 is approximately 50 micrometers (μm), that is, the thickness of the substrate 210 from the first surface 212 to the second surface 214 is H1. In this embodiment, the dimension of the through-silicon via 270 in the direction of the first surface 212 of the substrate 210 is greater than the dimension in the direction of the second surface 214 of the substrate 210, that is, length W1 > length W2. In some embodiments, the dimension of the through-silicon via 270 in the direction of the first surface 212 of the substrate 210 is equal to the dimension in the direction of the second surface 214 of the substrate 210, that is, length W1 = length W2.

[0067] In the through-silicon via structure 150, the P-type well region 230 and the deep N-type well region 220 are separated from the through-silicon via 270 by the N-type doped region 250. In addition, a junction of the P-type well region 230 and the N-type doped region 250 forms an electrostatic discharge protection diode DESD. When the thickness H2 of the P-type well region 230 increases, the junction of the electrostatic discharge protection diode DESD also increases. It should be noted that in the circuit, the voltage applied to the metal line 270 is greater than the voltage applied to the metal line 292.

[0068] Figure 4 FIG. is a top view of the through-silicon via structure 150 according to some embodiments of the present invention. A cross-sectional view of the through-silicon via structure 150 along line A-A' can be referred to Figure 3E . In Figure 4 , the configurations of the contacts 275 and the metal lines 290 and 292 are omitted to simplify the description.

[0069] Referring simultaneously to Figure 3E and Figure 4 , the through-silicon via 270 is disposed at the center of the through-silicon via structure 150. In this embodiment, the through-silicon via 270 has a circular layout. In other embodiments, the through-silicon via 270 may have a polygon layout, such as a quadrilateral, a hexagon, an octagon, etc. In addition, when the side length of the through-silicon via 270 in the layout increases, the PN junction of the electrostatic discharge protection diode DESD also increases. In addition, the through-silicon via 270 extends from the upper surface of the dielectric hard mask layer 280 to the second surface 214 of the substrate 210.

[0070] The N-type doped region 250 forms a ring in the top view (layout). The through-silicon via 270 is completely surrounded by the N-type doped region 250, and the through-silicon via 270 is in direct contact with the N-type doped region 250. The N-type doped region 250 extends from the first surface 212 of the substrate 210 to the second surface 214 of the substrate 210, that is, the N-type doped region 250 penetrates the substrate 210.

[0071] The P-type doped region 240 forms a ring in the top view (layout), and the N-type doped region 250 is surrounded by the P-type doped region 240. In this embodiment, the N-type doped region 250 is also surrounded by the P-type well region 230, and the N-type doped region 250 and the P-type doped region 240 are separated by the P-type well region 230. In addition, the P-type well region 230 is surrounded by the deep N-type well region 220. In some embodiments, the P-type doped region 240 is in contact with the N-type doped region 250.

[0072] The upper surfaces of the deep N-well region 220, the P-well region 230, the P-doped region 240, and the N-doped region 250 are coplanar with the first surface 212 of the substrate 210. The lower surface of the P-doped region 240 is higher than the lower surface of the P-well region 230, and the lower surface of the P-well region 230 is higher than the lower surface of the deep N-well region 220. In other words, the lower surface of the deep N-well region 220 is between the lower surface of the P-well region 230 and the second surface 214 of the substrate 210. The lower surfaces of the N-doped region 250 and the silicon via 270 are coplanar with the second surface 214 of the substrate 210.

[0073] Figure 5A An electrostatic discharge protection circuit 310 according to some embodiments of the present invention. The electrostatic discharge protection circuit 310 is used to provide electrostatic discharge protection for the input or output pins of the circuit. The electrostatic discharge protection circuit 310 includes a secondary protection unit 20 and an output driving unit 30. In the circuit, the power supply signal VDD from other wafers, chips, or substrates will enter the internal circuit (not shown) of the circuit through the silicon via structure 150a and the power line 12. In addition, the ground signal VSS from other wafers, chips, or substrates will enter the internal circuit of the circuit through the silicon via structure 150c and the ground line 16. In the input mode, the input or output signal IO from other wafers, chips, or substrates will enter the internal circuit of the circuit through the silicon via structure 150b and the input or output line 14. In the output mode, the input or output signal IO from the internal circuit will be transmitted to other wafers, chips, or substrates through the input or output line 14 and the silicon via structure 150b. As previously described, the silicon via structures 150a, 150b, and 150c include silicon vias 270 combined with electrostatic discharge protection diodes DESD.

[0074] Compared with Figure 1 the electrostatic discharge protection circuit 10, Figure 5A the electrostatic discharge protection circuit 310 does not include a primary protection unit 40. In Figure 5A the electrostatic discharge protection circuit 310, the pull-up diode D1 and the pull-down diode D2 are respectively provided by the electrostatic discharge protection diodes DESD of the silicon via structures 150a and 150b.

[0075] Figure 5B A connection configuration diagram of the silicon via structures 150a, 150b, and 150c in the electrostatic discharge protection circuit 310 according to some embodiments of the present invention. The manufacturing process of the silicon via structures 150a, 150b, and 150c is as Figures 3A - 3E described.

[0076] In Figure 5BIn [the figure], the metal line 290 of the through-silicon via structure 150a is coupled to the power supply line 12, and the metal line 292 of the through-silicon via structure 150a is coupled to the input or output line 14. In the through-silicon via structure 150a, the through-silicon via 270 is electrically connected to the power supply terminal of other wafers, chips or substrates through bumps or micro-bumps (not shown) located on the second surface 214 of the substrate 210. In the through-silicon via structure 150a, the anode of the electrostatic discharge protection diode DESD is coupled to the input or output line 14, and the cathode of the electrostatic discharge protection diode DESD is coupled to the power supply line 12. The electrostatic discharge protection diode DESD of the through-silicon via structure 150a can serve as the pull-up diode D1. In other words, in the electrostatic discharge protection circuit 310, the pull-up diode D1 is integrated in the through-silicon via structure 150a.

[0077] The metal line 290 of the through-silicon via structure 150b is coupled to the input or output line 14, and the metal line 292 of the through-silicon via structure 150b is coupled to the ground line 16. In the through-silicon via structure 150b, the through-silicon via 270 is electrically connected to the input or output terminal of other wafers, chips or substrates through bumps or micro-bumps (not shown) located on the second surface 214 of the substrate 210. In some embodiments, the substrate 210 is a P-type substrate and is coupled to the ground terminal. In the through-silicon via structure 150b, the substrate 210 and the P-type doped region 240 are simultaneously coupled to the ground terminal, and the through-silicon via structure 150b can omit the deep N-well region 220. In the through-silicon via structure 150b, the anode of the electrostatic discharge protection diode DESD is coupled to the ground line 16, and the cathode of the electrostatic discharge protection diode DESD is coupled to the input or output line 14. Therefore, the electrostatic discharge protection diode DESD of the through-silicon via structure 150b can serve as the pull-down diode D2. In other words, in the electrostatic discharge protection circuit 310, the pull-down diode D2 is integrated in the through-silicon via structure 150b.

[0078] The metal lines 290 and 292 of the through-silicon via structure 150c are coupled to the ground line 16. In the through-silicon via structure 150c, the through-silicon via 270 is electrically connected to the ground terminal of other wafers, chips or substrates through bumps or micro-bumps (not shown) on the second surface 214 of the substrate 210.

[0079] In the through-silicon via structure 150c, the anode and cathode of the electrostatic discharge protection diode DESD are together coupled to the ground line 16. Therefore, the electrostatic discharge protection diode DESD of the through-silicon via structure 150c does not conduct. In some embodiments, the through-silicon via structure 150c can be replaced by Figure 1 the through-silicon via 50c.

[0080] In an embodiment of the present invention, by using the N-type doped region 250 to surround the silicon through hole 270, an electrostatic discharge protection diode DESD with a large junction can be formed between the P-type well region 230 and the N-type doped region 250. Compared with the conventional silicon through hole that requires additional use of large-area pull-up diodes and pull-down diodes to provide electrostatic discharge protection, the silicon through hole structure 150 can combine the electrostatic discharge protection diode DESD with the silicon through hole 270, thus greatly reducing the layout area of the circuit to improve the utilization efficiency of the wafer area.

[0081] Although the present invention has been described above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the appended claims.

Claims

1. A through-silicon via structure, characterized in that, Comprising: A substrate having a first surface and a second surface, wherein the second surface is opposite to the first surface; A through-silicon via extending from the first surface of the substrate to the second surface; An N-type doped region surrounding the through-silicon via and extending from the first surface of the substrate to the second surface; A P-type well region formed in the substrate and surrounding the N-type doped region; and A P-type doped region formed in the P-type well region and surrounding the N-type doped region, wherein a junction of the P-type well region and the N-type doped region forms an electrostatic discharge protection diode.

2. The through-silicon via structure according to claim 1, wherein Further comprising: A deep N-type well region formed in the substrate and surrounding the P-type well region, wherein an upper surface of the deep N-type well region is coplanar with the first surface of the substrate, and a lower surface of the deep N-type well region is between a lower surface of the P-type well region and the second surface of the substrate.

3. The through-silicon via structure according to claim 1, characterized in that Further comprising: A dielectric hard mask layer formed on the first surface of the substrate; and A metal layer formed on the dielectric hard mask layer, wherein the through-silicon via penetrates through the dielectric hard mask layer and contacts a first metal line of the metal layer.

4. The silicon through - via structure according to claim 3, characterized in that, Further comprising: A contact formed in the dielectric hard mask layer and located above the P-type doped region, wherein a second metal line of the metal layer is electrically connected to the P-type doped region via the contact.

5. The through-silicon via structure according to claim 4, characterized in that, When the first metal line is electrically connected to an input or output line, the second metal line is electrically connected to a ground line, and the electrostatic discharge protection diode is a pull-down diode between the input or output line and the ground line.

6. A circuit with a through-silicon via structure, characterized in that, Comprising: A substrate having a first surface and a second surface, wherein the second surface is opposite to the first surface; And A plurality of through-silicon via structures, each comprising; A through-silicon via extending from the first surface of the substrate to the second surface; An N-type doped region surrounding the through-silicon via and extending from the first surface of the substrate to the second surface; A P-type well region formed in the substrate and surrounding the N-type doped region; and A P-type doped region formed in the P-type well region and surrounding the N-type doped region, wherein a junction of the P-type well region and the N-type doped region forms an electrostatic discharge protection diode, wherein the through-silicon via of a first through-silicon via structure of the plurality of through-silicon via structures is electrically connected to a power supply line, and the P-type doped region of the first through-silicon via structure is electrically connected to an input or output line, wherein the through-silicon via of a second through-silicon via structure of the plurality of through-silicon via structures is electrically connected to the input or output line, and the P-type doped region of the second through-silicon via structure is electrically connected to a ground line.

7. The circuit of the silicon through hole structure according to claim 6, characterized in that, The electrostatic discharge protection diode of the first through-silicon via structure is a pull-up diode between the power supply line and the input or output line.

8. The circuit of the through-silicon via structure according to claim 6, wherein In each of the through-silicon via structures, an upper surface of the P-type well region is coplanar with the first surface of the substrate, and a lower surface of the P-type well region is higher than the second surface of the substrate.

9. The circuit of the silicon through via structure according to claim 6, characterized in that Each of the through-silicon via structures further comprises: A deep N-type well region is formed in the above-mentioned substrate and surrounds the above-mentioned P-type well region. Wherein the upper surface of the deep N-type well region is coplanar with the first surface of the substrate, and the lower surface of the deep N-type well region is between the lower surface of the P-type well region and the second surface of the substrate.

10. The circuit of the through-silicon via structure according to claim 6, wherein Further comprising: A dielectric hard mask layer is formed on the first surface of the substrate; and A metal layer is formed on the dielectric hard mask layer. Wherein in each of the above-mentioned silicon via structures, the silicon via penetrates the dielectric hard mask layer and contacts a first metal line of the metal layer.

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