A method for suppressing high-frequency harmonics on inverter buses

Abstract

The application discloses an inverter bus high-frequency harmonic suppression method, comprising the following steps: based on the modulation mode of comparing the modulation wave with the carrier wave on the alternating current side, calculating the ripple on the alternating current side in real time; according to the calculation result of the ripple on the alternating current side, calculating the first duty cycle of the direct current side modulation wave, and calculating the second duty cycle required for compensating the high-frequency harmonic of the bus on the alternating current side; if the value of the second duty cycle meets the requirement of the first duty cycle, the carrier wave on the alternating current side is reversely injected into the direct current side modulation wave, so that the direct current side modulation wave is phase-shifted to compensate the high-frequency harmonic of the bus on the alternating current side. The application has the beneficial effects that the application can effectively improve the stability of the system by reversely injecting the carrier wave on the alternating current side into the direct current side modulation wave to suppress the bus high-frequency harmonic, and can effectively reduce the number of capacitors used in the system and prolong the service life of the capacitors.

Description

Technical Field

[0001] This application relates to the field of inverter technology, and in particular to a method for suppressing high-frequency harmonics on the inverter bus. Background Technology

[0002] Current technologies primarily suppress inverter harmonics by increasing the control methods of the switching transistors or by optimizing the AC side of the inverter using harmonic suppression algorithms. However, existing harmonic suppression methods have the following drawbacks: current methods mainly target grid-side harmonics and lack suppression of bus harmonics; furthermore, they require additional hardware in the inverter architecture, increasing inverter costs. Summary of the Invention

[0003] One objective of this application is to provide a method for suppressing high-frequency harmonics on the inverter bus that can solve at least one of the defects in the above-mentioned background art.

[0004] To achieve at least one of the above objectives, the technical solution adopted in this application is as follows: a method for suppressing high-frequency harmonics on an inverter bus, comprising the following steps: calculating the AC-side ripple in real time based on a modulation method that compares the modulated wave with the carrier wave on the AC side; calculating the first duty cycle of the DC-side modulated wave according to the calculation result of the AC-side ripple, and simultaneously calculating the second duty cycle required for compensation of high-frequency harmonics on the AC-side bus; if the value of the second duty cycle meets the requirement of the first duty cycle, injecting the AC-side carrier wave in reverse into the DC-side modulated wave, thereby causing the DC-side modulated wave to generate a phase shift to compensate for the high-frequency harmonics on the AC-side bus.

[0005] Preferably, the AC side ripple includes positive and negative bus current ripples of equal and symmetrical amplitude; the AC side ripple is filtered to obtain the corresponding high-frequency harmonics; the high-frequency harmonic I corresponding to a single bus current ripple. out The calculation formula is: I out =S(a)×I(a)+S(b)×I(b)+S(c)×I(c); where S(a), S(b) and S(c) represent the switching states of the three-phase switching transistors of the inverter, and I(a), I(b) and I(c) represent the three-phase current values ​​of the inverter.

[0006] Preferably, the inverter includes multiple power generation units, multiple DC / DC units, and DC / AC units; each power generation unit is connected in parallel with the corresponding DC / DC unit and DC / AC unit; the formula for calculating the first duty cycle D0 corresponding to the operation of a single DC / DC unit is: V out ×(1-D0)=V in Among them, V out V represents the output voltage of the DC / DC unit.in This indicates the output voltage of the power generation unit.

[0007] Preferably, the minimum value of the AC side harmonics that needs to be turned on within one switching cycle T of the DC / AC unit is used as the second duty cycle D1.

[0008] Preferably, the carrier reverse injection process in an N-channel DC / DC unit scenario is as follows: compare the sum of N first duty cycles D0, N×D0, with the value of the second duty cycle D1; if N×D0≤D1, no carrier reverse injection is required; if N×D0>D1, calculate the value of N0 that satisfies the inequality N0×D0>D1>(N0-1)×D0; based on the calculated value of N0, inject the AC side carrier in reverse into the modulation wave corresponding to the N0 DC / DC units.

[0009] Preferably, for the reverse injection of the AC side carrier, the injection time T for each DC / DC unit is... a The calculation formula is: T a =T / N0.

[0010] Preferably, during the reverse carrier injection process, the temperature of the IGBT unit of the DC / DC unit is detected; if the temperature of the IGBT unit exceeds a set threshold, the number of reverse carrier injection paths N0 is increased or the carrier injection time is decreased.

[0011] Preferably, when N-N0≥1, if the temperature of the IGBT unit exceeds the set threshold, the number of carrier reverse injection paths N0 is increased by one.

[0012] Preferably, when N=N0, if the temperature of the IGBT unit exceeds a set threshold, the carrier injection time T will be reduced. a Reduce to 60%~80% of the initial value.

[0013] Preferably, the carrier injection time T a Reduced to 70% of the initial value.

[0014] Compared with the prior art, the beneficial effects of this application are as follows:

[0015] This application suppresses high-frequency harmonics on the bus by injecting a DC-side modulated wave into the AC-side carrier in reverse, thereby effectively improving system stability; at the same time, it can also effectively reduce the number of capacitors used in the system and increase the lifespan of the capacitors. Attached Figure Description

[0016] Figure 1 This is a flowchart illustrating the workflow of this application.

[0017] Figure 2 This is a schematic diagram of the inverter topology architecture of this application.

[0018] Figure 3 This is a schematic diagram of the waveform structure of the carrier wave and the modulation wave in this application.

[0019] Figure 4 This is a schematic diagram of the harmonic structure of the positive busbar in this application.

[0020] Figure 5 This is a schematic diagram of the high-frequency harmonic structure of the positive bus in this application.

[0021] Figure 6 This is a schematic diagram of the high-frequency harmonic structure of the DC / DC unit in this application under normal conditions. Detailed Implementation

[0022] The present application will now be further described in conjunction with specific embodiments. It should be noted that, in the description of this specification, the use of terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicates that the specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms should not be construed as necessarily referring to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0023] In the description of this application, it should be noted that the terms "center", "lateral", "longitudinal", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., which indicate the orientation and positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and should not be construed as limiting the specific protection scope of this application.

[0024] It should be noted that the terms "first," "second," etc., in the specification and claims of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0025] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0026] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0027] The terms “comprising” and “having”, and any variations thereof, in the specification and claims of this application are intended to cover non-exclusive inclusion, for example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product, or device.

[0028] One preferred embodiment of this application, such as Figure 1 As shown, a method for suppressing high-frequency harmonics on an inverter bus includes the following steps: Based on a modulation scheme where the modulated wave is compared with the carrier wave on the AC side, the AC side ripple is calculated in real time. Based on the calculation result of the AC side ripple, the first duty cycle D0 of the DC side modulated wave is calculated, and simultaneously, the second duty cycle D1 required for high-frequency harmonic compensation on the AC side bus is calculated. If the value of the second duty cycle D1 meets the requirement of the first duty cycle D0, the AC side carrier wave is injected in reverse into the DC side modulated wave, thereby causing a phase shift in the DC side modulated wave to compensate for the high-frequency harmonics on the AC side bus, thus suppressing the high-frequency harmonics on the AC side bus.

[0029] Understandably, during inverter operation, the bus requires a large number of film capacitors to suppress high-frequency harmonics. In practical applications, since capacitors are not ideal models, the limiting factor in film capacitor selection is often not their ability to support bus voltage, but rather their ability to handle ripple current. If the selected capacitor's overcurrent capacity is insufficient, it will cause the capacitor to overheat and its lifespan to decrease. When high-frequency ripple is excessive, a larger volume is usually required to accommodate more film capacitors to meet their overcurrent capacity. However, the installation space in the inverter is often insufficient to accommodate large-volume film capacitors, and large-volume film capacitors can also hinder heat dissipation within the inverter.

[0030] In this embodiment, taking advantage of the inverter's AC-to-DC crossover characteristic, the AC harmonics of the inverter bus thin-film capacitors, i.e., the AC-side ripple, are first calculated. Then, the phase shift of the DC-side multi-channel modulation waves is used to compensate for the harmonics on the AC side. This reduces high-frequency harmonics in the inverter capacitors, extends capacitor lifespan, and lowers the inverter's design capacitance requirements. Simultaneously, suppressing high-frequency harmonics also improves the system's operational stability.

[0031] It should be understood that there are various types of inverter topologies, such as photovoltaic power generation systems and wind power generation systems. For ease of understanding, this application will use a photovoltaic power generation system as an example to provide a simple description of the specific structure of the inverter topology. Figure 2 As shown, the inverter topology includes N (N>1) PV units as power generation units, N DC / DC units, and one DC / AC unit; each PV unit is connected in parallel to the DC side of the corresponding DC / DC unit and the DC / AC unit, and the AC side of the DC / AC unit is connected to the power grid. Figure 2 In the inverter topology shown, the high-frequency harmonics on the bus mainly come from the switching transistors of the DC / DC unit on the DC side and the DC / AC unit on the AC side of the inverter.

[0032] It should also be noted that the inverter controls the AC-side DC / AC unit by employing the intersection of a carrier wave and a modulation wave. Taking DPWM modulation as an example, the waveform structure of the carrier wave and the modulation wave is as follows: Figure 3 As shown; where the low-frequency component is the 50Hz modulated wave and the high-frequency component is the carrier wave. The specific intersection method between the carrier wave and the modulated wave is a well-known technique to those skilled in the art, and therefore will not be described in detail here.

[0033] In this embodiment, the calculation of the AC side ripple is mainly to obtain the high-frequency harmonics of the bus. The AC side ripple includes the positive bus current ripple and the negative bus current ripple. For ease of calculation, it can be assumed that the power factor is 1, at which point the voltage and current are in phase. As can be seen from the inverter topology, the harmonic amplitudes of the positive bus POS and the negative bus NEG are the same and symmetrical. To simplify the process, the bus current harmonics I will be calculated using the positive bus POS harmonics as an example. out The calculation.

[0034] The current ripple output from the positive bus POS mainly consists of three parts: the DC component of the DC / DC side ripple, the high-frequency component of the DC / DC side ripple, and the high-frequency component of the DC / AC side harmonics. The DC component of the DC / DC side ripple is the effective value of the PV unit output current; the high-frequency component of the DC / DC side ripple is mainly composed of… Figure 2 The switching transistor T corresponding to the DC / DC unit a1 It is generated by switching the circuit on and off. The high-frequency components of the harmonics on the DC / AC side are mainly generated by... Figure 2 This is generated by the alternating on and off of the switching transistors T1 and T5 corresponding to the DC / DA unit.

[0035] For modulation methods, when the absolute value of the carrier wave is less than the modulating wave, the corresponding switch is turned on; when the absolute value of the carrier wave is less than the modulating wave, the corresponding switch is turned off. The on / off states of the three-phase switches in the DC / AC unit can be represented by S(a), S(b), and S(c). The current harmonics of the positive bus POS are as follows: Figure 4 As shown, its period is a third harmonic of the modulating wave. Since the positive bus POS and the negative bus NEG output at different times, the current harmonic I of the positive bus POS... out It is a superposition of high-frequency and low-frequency components.

[0036] It should be understood that after obtaining the bus current harmonics, since the DC component of the DC / DC side ripple is the effective value of the PV unit output current, the DC component of the DC / DC side ripple can be directly filtered out; the low-frequency component of the DC / DC side ripple can be filtered out using the DC side bus capacitor. The harmonics after filtering out the DC / DC side DC component and the low-frequency component are then processed by... Figure 2 When the bus capacitor C1 corresponding to the DC / AC unit outputs, the high-frequency harmonic I corresponding to the positive bus at this time... out This refers to the harmonics corresponding to the bus capacitor C1. The specific calculation formula is: I out =S(a)×I(a)+S(b)×I(b)+S(c)×I(c); where I(a), I(b), and I(c) represent the three-phase current values ​​on the AC side of the inverter, respectively. The high-frequency harmonic I corresponding to the positive bus at this time... out The waveform is as follows Figure 5 As shown.

[0037] In this embodiment, obtaining the first duty cycle D0 includes the following process: Under the actual operating conditions of the photovoltaic inverter, each DC / DC unit operates by comparing the carrier wave with the modulated wave. In practical applications, the number of PV modules connected to different DC / DC units is the same, so the voltage corresponding to each DC / DC unit can be considered the same. Therefore, when the DC / DC unit performs MPPT tracking, the bus voltage V output by the DC / DC unit... out and the voltage V output by the PV module in The relationship is: V out ×(1-D)=V in .

[0038] Where D represents the duty cycle, used to generate the PWM signal for controlling the DC / DC unit. If the DC bus voltage V... out Given a value, the operating voltage V of the PV module can be adjusted by changing the duty cycle D. in Adjustments are made to stabilize it at the maximum power point. At this point, according to the law of conservation of energy, the input and output power are approximately equal. Therefore, with a fixed duty cycle D, the current relationship between the input and output sides of the DC / DC unit is: I in ×(1-D)=I out Among them, I out I represents the output current of the DC / DC unit. in This represents the current on the input side of the DC / DC unit, i.e., the output current of the PV module.

[0039] It should be understood that, under the condition that the PV module output voltage Vin is stable and the grid voltage is stable, parameter I in V out and I out The value is only related to the duty cycle D; then the duty cycle D is the first duty cycle D0 with a fixed value.

[0040] In this embodiment, the second duty cycle D1 is obtained by taking the minimum value of the AC side harmonics that need to be turned on within one switching cycle T of the DC / AC unit as the second duty cycle D1.

[0041] Understandably, after obtaining the corresponding first duty cycle D0 and second duty cycle D1, if compensation for high-frequency harmonics on the bus is required, it is only necessary to inject the second duty cycle D1 in reverse into the DC side of the inverter, thereby adjusting the first duty cycle D0. The specific adjustment process must conform to the volt-second product balance principle; that is, as... Figure 2 As shown, the DC / DC unit includes an inductor and a switching transistor T. a1When the inductor meets the operating conditions and will not saturate due to bias, the voltage V applied across the inductor is... L Multiply by the conduction time T ON Equal to the voltage V across the inductor at the moment of turn-off L Multiply by the off time T OFF And within one switching cycle T, the inductor voltage V L The integral over time is 0. This can be specifically expressed by the following formula:

[0042] V L ×T ON =-V L ×T OFF ; .

[0043] Those skilled in the art should understand that when it is necessary to compensate for and suppress high-frequency harmonics on the bus, in an N-channel DC / DC unit scenario, it is necessary to ensure that as many DC / DC units as possible operate near their maximum power point. Therefore, if... Figure 1 As shown, the carrier reverse injection process in an N-channel DC / DC unit scenario is as follows: The sum of N first duty cycles D0, N×D0, is compared with the value of the second duty cycle D1. If N×D0≤D1, no carrier reverse injection is needed; if N×D0>D1, the value of N0 satisfying the inequality N0×D0>D1>(N0-1)×D0 is calculated. Based on the calculated N0 value, the AC-side carrier is reverse-injected into the modulation wave corresponding to the N0 DC / DC units.

[0044] To make it easier to understand, we will provide a detailed explanation using specific parameters below.

[0045] Assuming N is 7, calculate the first duty cycle D0 for each DC / DC unit when the DC / DC unit is stable, and simultaneously calculate the second duty cycle D1 required for AC side harmonic compensation.

[0046] If D0×N≤D1, it means that the inverter's power demand is very small and the demand for capacitor ripple current capability is also very small. Therefore, DC-side compensation for AC-side is not used.

[0047] If D0×N>D1, it means that the inverter's power demand is very high at this time. Then, first determine the number of channels N0 that need to be compensated, and calculate the minimum number of channels that can meet the ripple current. If it is calculated that D0×6>D1>D0×5, then select N0=6 channels for compensation, and then inject the second duty cycle D1 in reverse into the six modulation waves for compensation.

[0048] It is understandable that for the reverse injection of the AC side carrier, the injection time T for each DC / DC unit is... a The calculation formula is: Ta =T / N0.

[0049] In this embodiment, during carrier reverse injection, the value of the first duty cycle D0 on the DC side will increase, meaning the conduction time of the IGBT unit acting as a switch in the DC / DC unit will increase. This causes the temperature of the IGBT unit in the DC / DC unit to gradually rise. Therefore, during carrier reverse injection, it is necessary to detect the temperature of the IGBT unit in the DC / DC unit. If the temperature of the IGBT unit exceeds a set threshold, the number of carrier reverse injection paths N0 needs to be increased or the carrier injection time needs to be decreased.

[0050] It should be understood that the specific value of the threshold corresponding to the temperature of the IGBT unit during operation can be selected according to the actual needs of those skilled in the art, and therefore no specific limitation is made here. When the temperature of the IGBT unit exceeds the set threshold, if the number of carrier reverse injection paths is increased, the duration of each injected carrier can be reduced, thereby reducing the temperature of the IGBT unit.

[0051] Specifically, when the temperature of the IGBT unit does not exceed the set threshold, the reverse injection time of the second duty cycle D1 is T. a Therefore, the power of all DC / DC units on the DC side can be equivalent to N0×T. a When the temperature of the IGBT unit exceeds the set threshold, X-channel carrier reverse injection is added; then the power of all DC / DC units on the DC side can be equivalent to (N0+X)×T. a Therefore, with the total output remaining constant, we have N0×T a =(N0+X)×T a ´,T a = [N0 / (N0+X)]×T a That is, after increasing the number of carrier reverse injection paths, the carrier reverse injection time T a The temperature of the IGBT cell will decrease.

[0052] Of course, the temperature of the IGBT unit can also be reduced by directly decreasing the carrier injection duration. Increasing or decreasing the carrier injection time for the number of carrier reverse injection paths N0 can both meet the requirements of this application. However, considering the overall stability of the system, the two cooling methods can be selected based on the number of carrier reverse injection paths. The specific selection process is as follows:

[0053] When N - N0 ≥ 1, if the temperature of the IGBT unit exceeds the set threshold, the number of carrier reverse injection paths N0 is increased by one. When N = N0, if the temperature of the IGBT unit exceeds the set threshold, the carrier injection time T is reduced. a Reduced to 60%~80% of the initial value. For the carrier injection time T... a The specific degree of reduction can be selected according to the actual needs of those skilled in the art, preferably reducing the carrier injection time T. a Reduced to 70% of the initial value.

[0054] The basic principles, main features, and advantages of this application have been described above. Those skilled in the art should understand that this application is not limited to the above embodiments. The embodiments and descriptions in the specification are merely the principles of this application. Various changes and modifications can be made to this application without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claims. The scope of protection claimed by this application is defined by the appended claims and their equivalents.

Claims

1. A method of high frequency harmonic suppression of an inverter bus, characterized by, The method comprises the following steps: Real-time calculation of the AC side ripple based on the modulation mode of comparing the modulation wave with the carrier wave on the AC side; According to the calculation result of the AC side ripple, the first duty cycle of the DC side modulation wave is calculated, and the second duty cycle required for the compensation of the high-frequency harmonic of the AC side bus is calculated; If the value of the second duty cycle meets the requirement of the first duty cycle, the AC side carrier wave is injected reversely into the DC side modulation wave, so as to make the DC side modulation wave generate a phase shift to compensate the high-frequency harmonic of the AC side bus; The inverter comprises a plurality of power generation units, a plurality of DC / DC units and a DC / AC unit; each power generation unit is connected in parallel with the DC / DC unit and the DC / AC unit through a corresponding path; The duty cycle of the DC / DC unit when working is the first duty cycle D0; The minimum value of the turn-on of the AC side harmonic in a switching cycle T of the DC / AC unit is taken as the second duty cycle D1; The carrier reverse injection process under the N-path DC / DC unit scenario is as follows: The sum of N first duty cycles D0 and N×D0 is compared with the value of the second duty cycle D1; If N×D0≤D1, no reverse injection of the carrier is required; If N×D0>D1, the value of N0 satisfying the inequality N0×D0>D1>(N0-1)×D0 is calculated; According to the calculated value of N0, the AC side carrier wave is injected reversely into the modulation wave corresponding to the N0-path DC / DC unit.

2. The method of claim 1, wherein the high frequency harmonic suppression is performed on the DC bus of the inverter. The AC side ripple comprises positive bus current ripple and negative bus current ripple which are equal in amplitude and symmetrical in positive and negative; the corresponding high-frequency harmonic is obtained by filtering the AC side ripple; The high-frequency harmonic I corresponding to the single bus current ripple out The calculation formula is: out I = S(a) x I(a) + S(b) x I(b) + S(c) x I(c); Wherein, S(a), S(b) and S(c) represent the switching state of the three-phase switch tube of the inverter, and I(a), I(b) and I(c) represent the three-phase current value of the inverter.

3. The method of claim 1, wherein the high frequency harmonic suppression is performed on the DC bus of the inverter. The calculation formula of the corresponding first duty cycle D0 when the single DC / DC unit works is: V out ×(1-D0) = V in ; where V out represents the output voltage of the DC / DC unit, V in represents the output voltage of the power generation unit.

4. The method of claim 1, wherein the high frequency harmonics are suppressed in the range of 2.5 kHz to 5 kHz. For the reverse injection of the AC side carrier, the injection time T of each DC / DC unit corresponds to N0 a The calculation formula is: T a = T / N0.

5. The method of claim 1, wherein, During the reverse injection of the carrier, the temperature of the IGBT unit of the DC / DC unit is detected; If the temperature of the IGBT unit exceeds the set threshold, the number of paths N0 of the reverse injection of the carrier is increased or the injection time of the carrier is reduced.

6. The method of claim 5, wherein the high frequency harmonics are suppressed by, When N-N0≥1, if the temperature of the IGBT unit exceeds the set threshold, the number of paths N0 of the reverse injection of the carrier is increased by one.

7. The method of claim 5, wherein the high frequency harmonics are suppressed by a factor of 10. When N=N0, if the temperature of the IGBT unit exceeds a set threshold value, the injection time T of the carrier is reduced to 60% to 80% of the initial value. a reduced to 60% to 80% of the initial value.

8. The method of claim 7, wherein the high frequency harmonic suppression is performed on the DC bus of the inverter. The injection time T of the carrier is reduced by 70% of the initial value. a to 70% of the initial value.

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