Soft start circuit capable of adjusting start time and start method

Abstract

The invention discloses a soft start circuit capable of adjusting start time and a start method. The circuit comprises a control circuit, a slope generation circuit, a soft start time control circuit and an output clamping circuit. According to the invention, the capacitor Cp is firstly charged and then discharged to control the discharge current of the capacitor Cp, so that the output end of the slope generation circuit outputs a voltage signal of slope drop, then amplitude limiting is carried out by a source follower structure of the transistor N1, and the amplitude-limited voltage signal of slope drop is reversed through the transistor N7 and the transistor N13; and through the output clamping circuit, the soft start voltage is finally output, and the soft start effect is achieved. The soft start time is adjustable; the high and low levels of the third input end, the fourth input end, the fifth input end and the sixth input end of the soft start time control circuit determine whether the resistor R4, the resistor R5, the resistor R6 and the resistor R7 are connected to the circuit, so that the soft start time is changed. The circuit is completely integrated in the chip, and an external large capacitor is not needed.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog integrated circuits, and particularly relates to a soft start circuit and a start method with adjustable start time, which are applied to a switching power converter. Background Art

[0002] At present, electronic products of switching power supplies are becoming increasingly rich, and the requirements for power chips are becoming more and more diverse, resulting in higher and higher requirements for chips. During the power-on process of an actual chip, since the reference voltage rises extremely fast, a very large inrush current is generated in the circuit, which may burn out the circuit. To avoid such problems, the vast majority of switching power supply chips use a soft start circuit.

[0003] Most soft start circuits charge an external large capacitor with a small current, so that the voltage of the external large capacitor rises slowly to obtain a suitable soft start voltage; the soft start time depends on the charging current magnitude and the capacitance value of the external large capacitor; however, the prior art cannot adjust the soft start time according to different scenarios, and relies on a current source Is with a very small current value, and also requires an external large capacitor, which is time-consuming and laborious. Summary of the Invention

[0004] Object of the Invention: The object of the present invention is to provide a soft start circuit and a start method with adjustable start time. The soft start circuit can be integrated on-chip, does not require an external large capacitor, and can adjust the soft start time at the same time.

[0005] Technical Solution: A soft start circuit with adjustable start time according to the present invention includes: a control circuit, a ramp generation circuit, a soft start time control circuit, and an output clamping circuit; as Figure 2 shown in the block diagram;

[0006] The first output terminal of the control circuit is connected to the input terminal of the ramp generation circuit, and the second output terminal of the control circuit is connected to the first input terminal of the soft start time control circuit. The control circuit generates a control signal for the ramp generation circuit and the soft start time control circuit;

[0007] The function of the control circuit is: to output a control signal with a high level from 0 to 18 μs and a low level after 18 μs; to control the charging and discharging of the capacitor of the ramp generation circuit, and ensure that the soft start time control circuit only works when the capacitor in the ramp generation circuit discharges;

[0008] The output terminal of the ramp generation circuit is connected to the second input terminal of the soft start time control circuit, and the output terminal of the ramp generation circuit generates a falling ramp voltage and connects it to the second input terminal of the soft start time control circuit;

[0009] The function of the ramp generation circuit is: to generate a falling ramp voltage signal and perform amplitude limiting processing on this falling ramp voltage signal;

[0010] The first input terminal of the soft start time control circuit is connected to the second output terminal of the control circuit; the levels of the third input terminal, the fourth input terminal, the fifth input terminal, and the sixth input terminal of the soft start time control circuit control the rising speed of the voltage signal output by the output terminal of the soft start time control circuit.

[0011] The functions of the soft start time control circuit are as follows: The first function is to reverse the voltage signal input to the second input terminal of the soft start time control circuit, converting the falling ramp voltage signal into a rising ramp voltage signal, as Figure 5 shown; the second function is to control the rising time of the reversed rising ramp voltage signal.

[0012] The first input terminal of the output clamping circuit is connected to the external reference voltage Vref, the second input terminal of the output clamping circuit is connected to the output terminal of the soft start time control circuit, and the output clamping circuit clamps the slowly rising voltage signal at its second input terminal to the external reference voltage Vref connected to its first input terminal and outputs it from the output terminal of the output clamping circuit.

[0013] The function of the output clamping circuit is to clamp the ramp-rising voltage signal input to its second input terminal, that is, to keep the voltage value unchanged after the rising ramp voltage signal rises to the external reference voltage Vref and finally output it.

[0014] The specific implementation method is as Figure 3 shown in the circuit diagram. The implementation idea is to use the capacitor Cp to charge first and then discharge, and at the same time control the discharge current of the capacitor Cp to make the output terminal of the ramp generation circuit output a ramp-falling voltage signal. Then, the source follower structure of the transistor N1 is used for amplitude limiting, and the ramp-falling voltage signal after amplitude limiting is reversed through the transistors N7 and N13; then, the transistors M5, M6, M7, and M8 are used to determine whether the resistors R4, R5, R6, and R7 are connected to the soft start time control circuit, so as to change the soft start time. Finally, the soft start function is realized through the output clamping circuit.

[0015] It should be noted that when the third input terminal, the fourth input terminal, the fifth input terminal, and the sixth input terminal of the soft start time control circuit all input low levels, the resistors R4, R5, R6, and R7 are all connected to the circuit, and the rising ramp delay time is the longest, which is 857 μs; when one of the third input terminal, the fourth input terminal, the fifth input terminal, and the sixth input terminal of the soft start time control circuit inputs a high level, the rising ramp delay time is 720 μs; when two of the third input terminal, the fourth input terminal, the fifth input terminal, and the sixth input terminal of the soft start time control circuit input high levels, the rising ramp delay time is 570 μs; when three of the third input terminal, the fourth input terminal, the fifth input terminal, and the sixth input terminal of the soft start time control circuit input high levels, the rising ramp delay time is 390 μs; as Figure 6 shown in the curve.

[0016] Circuit connection method:

[0017] The control circuit includes transistor P1, transistor P2, transistor P6, transistor P7, resistor R1, transistor P11, transistor P12, transistor P16, transistor N9, and capacitor Cc;

[0018] The gate of transistor P1 is connected to the gate of transistor P2. The common terminal where the source of transistor P1 and the source of transistor P2 are connected is connected to the power supply. The common terminal where the gate of transistor P1 and the gate of transistor P2 are connected is connected to one end of resistor R1. The drain of transistor P1 and the drain of transistor P2 are respectively connected to the source of transistor P6 and the source of transistor P7;

[0019] The gate of transistor P6 is connected to the gate of transistor P7. The common terminal of the gate of transistor P6 and the gate of transistor P7 is connected to the other end of resistor R1;

[0020] The other end of resistor R1 is connected to an external reference current source;

[0021] The source of transistor P11 is connected to the drain of transistor P7. The gate of transistor P11 is connected to the drain of transistor P11;

[0022] One end of capacitor Cc is connected to the drain of transistor P11, and the other end of the capacitor is connected to ground;

[0023] Transistor P12, its gate is connected to the drain of transistor P16, its source is connected to the power supply, and its drain is connected to the common terminal where the drain of transistor P11 and one end of capacitor Cc are connected;

[0024] Transistor P16, its gate is connected to the drain of transistor P12, its source is connected to the power supply, and its drain is connected to the gate of transistor P12;

[0025] Transistor N9, whose gate is connected to the common terminal where the drain of transistor P11 and one end of capacitor Cc are connected, whose drain is connected to the gate of transistor P12, and whose source is connected to the ground;

[0026] The control circuit outputs a control signal to charge and discharge the capacitor Cc of the ramp generation circuit, so that the ramp generation circuit can output a voltage signal with a descending ramp at its first output terminal; when the soft start time control circuit discharges the capacitor, the soft start time control circuit adjusts the soft start time according to the high and low potentials of the third input terminal, the fourth input terminal, the fifth input terminal, and the sixth input terminal.

[0027] Preferably, the ramp generation circuit includes transistor P3, transistor P4, transistor P8, transistor P9, transistor M1, transistor M2, transistor M3, resistor R2, resistor R3, capacitor Cp, transistor N4, transistor N5, transistor N10, transistor N11, transistor N6, and transistor N12;

[0028] Transistor P3, whose gate is connected to the gates of transistor P1 and transistor P2, whose source is connected to the power supply, and whose drain is connected to the source of transistor M8;

[0029] Transistor P4, whose gate is connected to the gate of transistor P3, whose source is connected to the power supply, and whose drain is connected to the source of transistor P9;

[0030] Transistor P8, whose gate is connected to the gates of transistor P6 and transistor P7, whose source is connected to the drain of transistor P3, and whose drain is connected to the source of transistor M1;

[0031] Transistor M9, whose gate is connected to the gates of transistor P6 and transistor P7, whose source is connected to the drain of transistor P4, and whose drain is connected to the source of transistor M2;

[0032] Transistor M1, whose gate is connected to the gate of transistor P12, whose drain is connected to one end of resistor R2, and whose source is connected to the drain of transistor P8;

[0033] Resistor R2, one end of which is connected to the drain of transistor M1 and the other end of which is connected to the drain of transistor N4;

[0034] Capacitor Cp, one end of which is connected to the source of transistor M2 and the other end of which is connected to the ground;

[0035] Resistor R3, one end of which is connected to one end of capacitor Cp and the other end of which is connected to the ground;

[0036] Transistor N4, whose gate is connected to the gate of transistor N5, whose drain is connected to resistor R2, and whose source is connected to the drain of transistor N4;

[0037] Transistor N5, whose gate is connected to the gate of transistor N4, whose source is connected to the drain of transistor N11, and whose drain is connected to the other end of resistor R3;

[0038] Transistor N10, whose gate is connected to the gate of transistor N11, whose drain is connected to the source of transistor N4, and whose source is connected to ground;

[0039] Transistor N11, whose gate is connected to the gate of transistor N11, and whose drain is connected to the source of transistor N5;

[0040] Transistor M3, whose gate is connected to the gate of transistor M2, whose source is connected to the power supply, and whose drain is connected to the drain of transistor N1;

[0041] Transistor N1, whose gate is connected to one end of resistor R3, whose drain is connected to the drain of transistor M3, and whose source is connected to the drain of transistor N6;

[0042] Transistor N6, whose gate is connected to the drain of transistor N1, and whose source is connected to the drain of transistor N12;

[0043] Transistor N12, whose gate is connected to the drain of transistor N12, and whose source is connected to ground;

[0044] When the capacitor Cp discharges, control the discharge current of the capacitor Cp to linearly decrease the gate voltage of transistor N1, and then limit the potential of its gate voltage through the source follower of transistor N1, so that the output end of the ramp generation circuit outputs a linearly decreasing voltage signal;

[0045] Preferably, the soft start time control circuit includes transistor P5, transistor P10, transistor M5, transistor M6, transistor M7, transistor M8, resistor R4, resistor R4, resistor R6, resistor R7, transistor M4, transistor N7, transistor N13, capacitor Cs;

[0046] Transistor P5, whose gate and drain are connected to the power supply, and whose drain is connected to the gate and drain of transistor P10;

[0047] Transistor P10, whose gate is connected to the drain of transistor P10, and whose drain is connected to the source of transistor M5 and one end of resistor R4;

[0048] Resistor R4, one end of which is connected to the source of transistor M5, and the other end of which is connected to the drain of transistor M5;

[0049] Transistor M5, whose gate is connected to the outside through the third input terminal of the soft start time control circuit, whose source is connected to one end of resistor R4, and whose drain is connected to the other end of resistor R4;

[0050] A resistor R5, one end of which is connected to the source of the transistor M6 and the other end of which is connected to the drain of the transistor M6;

[0051] A transistor M6, the gate of which is connected to the outside through the fourth input terminal of the soft start time control circuit, the source of which is connected to one end of the resistor R5, and the drain of which is connected to the other end of the resistor R5;

[0052] A resistor R6, one end of which is connected to the source of the transistor M7 and the other end of which is connected to the drain of the transistor M7;

[0053] A transistor M7, the gate of which is connected to the outside through the fifth input terminal of the soft start time control circuit, the source of which is connected to one end of the resistor R6, and the drain of which is connected to the other end of the resistor R6;

[0054] A resistor R7, one end of which is connected to the source of the transistor M8 and the other end of which is connected to the drain of the transistor M8;

[0055] A transistor M8, the gate of which is connected to the outside through the sixth input terminal of the soft start time control circuit, the source of which is connected to one end of the resistor R7, and the drain of which is connected to the other end of the resistor R7;

[0056] A transistor M4, the gate of which is connected to the gate of the transistor M3, the source of which is connected to the other end of the resistor R7, and the drain of which is connected to the source of the transistor N7;

[0057] A transistor M7, the gate of which is connected to the drain of the transistor N6, the source of which is connected to the drain of the transistor M4, and the drain of which is connected to the drain of the transistor N13;

[0058] A transistor N13, the gate of which is connected to the drain of the transistor N6, the drain of which is connected to the drain of the transistor N7, and the source of which is connected to the ground;

[0059] A capacitor Cs, one end of which is connected to the drain of the transistor N13 and the other end of which is connected to the ground;

[0060] The transistor N7 and the transistor N13 form an inverter, which functions to invert the input signal of the second input terminal of the soft start circuit; the soft start time is controlled by the transistors M5, M5, M7, M8, the resistors R4, R5, R6, R7;

[0061] Preferably, the output clamping circuit includes transistors P13, P14, N2, N3, N8, N14, P15, N15;

[0062] A transistor P13, the gate of which is connected to the transistor P14, the source of which is connected to the power supply, and the drain of which is connected to the gate of the transistor P13;

[0063] A transistor P14, whose gate is connected to the gate of transistor P13, whose source is connected to a power supply, and whose drain is connected to the drain of transistor N3;

[0064] A transistor N2, whose gate is connected to the outside through the first input terminal of an output clamping circuit, whose drain is connected to the drain of transistor P13, and whose source is connected to the drain of transistor N8;

[0065] A transistor N3, whose gate is connected to the drain of transistor N15, whose drain is connected to the drain of transistor P14, and whose source is connected to the drain of transistor N8;

[0066] A transistor N8, whose gate is connected to the gate of transistor N5, whose drain is connected to the source of transistor N2, and whose source is connected to the drain of transistor N14;

[0067] A transistor N14, whose gate is connected to the gate of transistor N11, whose drain is connected to the source of transistor N8, and whose source is connected to the ground;

[0068] A transistor P15, whose gate is connected to the outside through the first input terminal of the output clamping circuit, whose gate is connected to the drain of transistor P14, and whose drain is connected to the source of transistor N15;

[0069] A transistor N15, whose gate is connected to the drain of transistor P14, whose drain is connected to the gate of transistor N3, and whose source is connected to the drain of transistor P15;

[0070] The output clamping circuit compares the voltage of its first input terminal and the voltage of its second input terminal. When the voltage of the second input terminal of the output clamping circuit is higher, the output terminal of the output clamping circuit outputs the signal of the output terminal of the soft start time control circuit; when the voltage of the second input terminal of the output clamping circuit is lower, the output terminal of the output clamping circuit outputs the signal of its second input terminal, so as to achieve the effect of voltage clamping.

[0071] The present invention also discloses a starting method for a soft start circuit with an adjustable starting time, including the following steps:

[0072] Step 1: Construct a soft-start circuit with adjustable start time, including a control circuit, a ramp generation circuit, a soft-start time control circuit, and an output clamping circuit; the reference current of the external circuit is connected to the first input terminal of the control circuit, and the first output terminal of the control circuit is connected to the input terminal of the ramp generation circuit; the second output terminal of the control circuit is connected to the first input terminal of the soft-start time control circuit; the output terminal of the ramp generation circuit is connected to the second input terminal of the soft-start time control circuit; the external circuit is connected to the third, fourth, fifth, and sixth input terminals of the soft-start time control circuit to control the soft-start time; the output terminal of the soft-start time control circuit is connected to the second input terminal of the output clamping circuit, and the external circuit is connected to the first input terminal of the output clamping circuit;

[0073] Step 2: Through the charge and discharge of capacitor Cp and the amplitude limiting of transistor N1, a slowly decreasing ramp signal is output from the output terminal of the ramp generation circuit, and then inverted by the soft-start time control circuit. Whether resistors R4, R5, R6, and R7 are connected to the circuit is determined by the high and low levels of the third, fourth, fifth, and sixth input terminals of the soft-start control circuit, achieving the effect of controlling the soft-start time;

[0074] Step 3: Output through the first output terminal of the output clamping circuit; there is no need to externally connect a large off-chip capacitor to realize the function of soft start.

[0075] Further, the control circuit includes transistors P1, P2, P6, P7 that act as a current mirror, as well as an external reference current source Idc, a bias resistor R1, transistors P11, P12, P16, N9, and a capacitor Cc; transistors P2 and P7 copy the current of Idc to charge capacitor Cc. At this time, the voltage at one end of capacitor Cc rises, and the voltage at one end of capacitor Cc is then input to the gate connected to transistors N9 and P16, inverted by the inverter composed of transistors N9 and P16, and output from the drain of transistor N9, that is, output from the output terminal of the control circuit; the voltage signal output from the drain of transistor N9 is a high-level signal from 0 to 18 μs and a low-level signal after 18 μs.

[0076] Further, the ramp generation circuit 2 includes transistors P3, P4, P8, P9, N4, N5, N10, N11 acting as current mirrors, transistors M1, M2, bias resistors R2, R3, and capacitor Cp. When the first output terminal of the control circuit outputs a high level, the gate of transistor M2 is at a high level, transistor M2 turns on, and the current flowing through the drains of transistors P4 and P9 charges capacitor Cp. The charging time is 18 μs, causing the voltage of the upper plate of capacitor Cp to reach 3V. When the first output terminal of the control circuit outputs a low level, the gate of transistor M1 is at a low level, transistor M1 turns on, the gate of transistor M2 is at a low level, and transistor M2 turns off. One end of capacitor Cp is connected to one end of R3, and capacitor Cp discharges. The discharge current is equal to the current of the drains of transistors N4 and N10 copied by transistors N5 and N11. When the first output terminal of the control circuit outputs a high level, transistor M3 turns off and transistor N1 does not work. When the first output terminal of the control circuit outputs a low level, transistor M3 turns on, and transistor N1 acts as a source follower. Together with transistor N6 and transistor N12, it limits the discharge voltage at one end of capacitor Cp, i.e., VN1D = VN1G - VN1TH. The minimum value of the source voltage of transistor N1 is VN6TH + VN12TH. The output terminal of the ramp generation circuit outputs a descending ramp voltage signal after 18 μs.

[0077] Furthermore, the soft start time control circuit includes transistors P5, P10, M4, M5, M6, M7, M8, N7, N13, resistors R4, R5, R6, R7, and capacitor Cs; when the second output terminal of the control circuit is at a high level, that is, before 18 us, transistor M4 is turned off, and the first output terminal of the soft start circuit outputs a low level; when the second output terminal of the control circuit is at a low level, that is, after 18 us, transistor M4 is turned on, a falling ramp signal is input to the second input terminal of the soft start time control circuit, and a slowly rising ramp signal is output from the output terminal of the soft start time control circuit; transistors N7 and N13 function to reverse the voltage signal, reverse the voltage signal input to the first input terminal of the soft start time control circuit, and output a slowly rising ramp signal at the first output terminal of the soft start time control circuit; resistors R4, R5, R6, R7, and capacitor Cs function to delay the voltage signal; transistors M5, M6, M7, M8 function to control the delay time; when low levels are input to the third input terminal, fourth input terminal, fifth input terminal, and sixth input terminal of the soft start time control circuit, resistors R4, R5, R6, R7 are all connected to the circuit, and the rising ramp delay time is the longest, which is 857 us; when a high level is input to one of the third input terminal, fourth input terminal, fifth input terminal, and sixth input terminal of the soft start time control circuit, the rising ramp delay time is 720 us; when high levels are input to two of the third input terminal, fourth input terminal, fifth input terminal, and sixth input terminal of the soft start time control circuit, the rising ramp delay time is 570 us; when high levels are input to three of the third input terminal, fourth input terminal, fifth input terminal, and sixth input terminal of the soft start time control circuit, the rising ramp delay time is 390 us; the output terminal of the soft start time control circuit outputs a ramp rising voltage signal with an adjustable rising time.

[0078] Furthermore, the output clamping circuit includes transistors P13, P14, N2, N3, N8, N14, P15, N15; the first input terminal of the output clamping circuit is connected to an external reference voltage, and the second input terminal is connected to the output of the first output terminal of the soft start time control circuit; the source terminal of transistor P15 is connected to the external reference voltage; transistors P13, P14, N2, N3, N8, N14 form an OTA. When the external reference voltage is greater than the gate voltage of transistor N3, the drain of transistor N3 outputs a high level, transistor N15 conducts, and transistor P15 turns off, and Vout outputs a slowly rising voltage signal; when the external reference voltage is less than the gate voltage of transistor N3, the drain of transistor N3 outputs a low level, transistor N15 turns off, and transistor P15 conducts, and Vout outputs the external reference voltage.

[0079] Beneficial effects: Compared with the prior art, the present invention has the following remarkable advantages:

[0080] 1. A soft start method is proposed. By first charging and then discharging the capacitor Cp, the discharge current of the capacitor Cp is controlled, so that a voltage signal with a descending slope is output at the output end of the ramp generation circuit. Then, it is limited by the source follower structure of the transistor N1. The limited voltage signal with a descending slope is inverted through the transistors N7 and N13. Finally, through the output clamping circuit, a soft start voltage is output, achieving the effect of soft start.

[0081] 2. The soft start time is adjustable. The high and low levels of the third input terminal, the fourth input terminal, the fifth input terminal, and the sixth input terminal of the soft start time control circuit determine whether the resistors R4, R5, R6, and R7 are connected to the circuit, thereby changing the soft start time.

[0082] 3. The circuit is fully integrated inside the chip and does not require an external large capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0083] Figure 1 is the schematic diagram of the soft start in the prior art;

[0084] Figure 2 is the structural block diagram of the start method of a soft start circuit with adjustable start time;

[0085] Figure 3 is the circuit schematic diagram of a soft start circuit and a start method with adjustable start time provided in the embodiment;

[0086] Figure 4 is the waveform curve diagram of the key nodes of the control circuit and the ramp generation circuit in the embodiment;

[0087] Figure 5 is the simulation curve diagram of the descending ramp voltage signal and the ascending ramp voltage signal in the embodiment;

[0088] Figure 6 is the simulation curve diagram of the ascending ramp delay time under four delay times in the example;

[0089] Figure 7 is the simulation curve diagram of the output voltage under four delay times in the example. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0090] The technical solution of the present invention will be further described below with reference to the drawings.

[0091] For the prior art, as Figure 1 shown, one end of the current source Is is connected to the power supply VDD, and the other end is connected to one end of the capacitor C. The other end of the capacitor C is connected to the ground. At the same time as one end of the capacitor C and the other end of the current source Is, it is connected to the output port Vout; the current source Is charges the capacitor C.

[0092] According to the capacitor charging formula: C×Vout=Is×△T

[0093] Where C represents the capacitance value of the capacitor, Vout represents the voltage at one end of the capacitor, that is, the voltage of the output port; Is represents the current magnitude of the current source, and △T represents the charging time of the capacitor C; it can be obtained that:

[0094] Vout=Is×△T / C

[0095] Therefore, according to the formula, the voltage Vout of the output port rises slowly, achieving the effect of soft start; however, the prior art cannot adjust the soft start time according to different scenarios, relies on a current source Is with a very small current value, and also requires an external large capacitor, which is time-consuming and laborious.

[0096] Based on this, the present invention provides a soft start circuit and a start method with adjustable start time, as Figure 2 shown. In the ramp generation circuit, the capacitor Cp is first charged and then discharged, and a descending ramp signal is output from the second output terminal; since the capacitor Cp needs to be charged first, the voltage value during the charging of the capacitor Cc does not need to be output from the output terminal of the ramp generation circuit, and only the descending ramp signal is input to the second input terminal of the soft start time control circuit; therefore, a control circuit is required to control that only the discharge voltage of the capacitor Cc is output from the output terminal of the ramp generation circuit, and only the discharge voltage of the capacitor Cc is input to the second input terminal of the soft start time control circuit.

[0097] Specifically, the soft start time control circuit has two functions; the first function is to invert the voltage signal input to the second input terminal of the soft start time control circuit; the second function is to delay the inverted voltage signal and control the delay time, and the output terminal of the soft start time control circuit is connected to the second input terminal of the output clamping circuit;

[0098] Specifically, the first input terminal of the output clamping circuit is connected to the external reference voltage Vref, and the output clamping circuit clamps the voltage signal input to its second input terminal at the external reference voltage Vref input to the first input terminal of the output clamping circuit.

[0099] Next, in combination with Figure 3 the circuit schematic diagram of a soft start circuit and a start method with adjustable start time provided by the embodiment of the present invention shown below, the control circuit 1 will be described:

[0100] The control circuit 1 includes transistors P1, P2, P6, P7 which act as a current mirror, an external reference current source Idc, a bias resistor R1, transistors P11, P12, P16, N9 and a capacitor Cc; transistors P2, P7 copy the current of Idc to charge the capacitor Cc. At this time, the voltage at one end of the capacitor Cc rises, and the voltage at one end of the capacitor Cc is then input to the gate connected to transistors N9 and P16, inverted by the inverter composed of transistors N9 and P16, and output from the drain of transistor N9, that is, output from the output end of the control circuit;

[0101] Specifically, the voltage signal output from the drain of transistor N9 is a high-level signal from 0 to 18 us and a low-level signal after 18 us, as Figure 4 shown in Curve 1. The function of transistor P12 is to ensure that when the time is greater than 18 us, the output at the drain of transistor N9 remains low-level continuously, that is, the signal at the output end of the control circuit is high-level from 0 to 18 us and low-level after 18 us.

[0102] Combined with Figure 3 the circuit schematic diagram of an adjustable start-up time soft start circuit and start method provided by the embodiment of the present invention shown, the ramp generation circuit 2 is described as follows:

[0103] The ramp generation circuit 2 includes transistors P3, P4, P8, P9, N4, N5, N10, N11 which act as a current mirror, transistors M1, M2, bias resistors R2, R3, and a capacitor Cp.

[0104] Specifically, when the first output end of the control circuit outputs a high level, the gate of transistor M2 is at a high level, transistor M2 is turned on, and the current flowing through the drains of transistors P4 and P9 charges the capacitor Cp; the charging time is 18 us, so that the voltage of the upper plate of the capacitor Cp reaches 3V, as Figure 4 shown in Curve 2;

[0105] Specifically, when the first output end of the control circuit outputs a low level, the gate of transistor M1 is at a low level, transistor M1 is turned on, the gate of transistor M2 is at a low level, and transistor M2 is turned off; one end of the capacitor Cp is connected to one end of R3, and the capacitor Cp discharges, and the discharge current is equal to the current of the drains of transistors N4 and N10 copied by transistors N5 and N11; at this time, the discharge voltage at one end of the capacitor Cp is as Figure 4 shown in Curve 2;

[0106] It should be noted that when the first output terminal of the control circuit outputs a high level, the transistor M3 is turned off and the transistor N1 does not work; when the first output terminal of the control circuit outputs a low level, the transistor M3 is turned on, and the transistor N1 acts as a source follower. Together with the transistors N6 and N12, the discharge voltage at one end of the capacitor Cp is limited, that is, VN1D = VN1G - VN1TH; the minimum value of the source voltage of the transistor N1 is VN6TH + VN12TH.

[0107] That is to say, the output terminal of the ramp generation circuit outputs a descending ramp voltage signal after 18 us; as Figure 4 shown in Curve 3.

[0108] Combined with Figure 3 the circuit schematic diagram of a soft start circuit and a start method with adjustable start time provided by the embodiment of the present invention shown in the figure, the soft start time control circuit 3 will be described:

[0109] The soft start time control circuit 3 includes transistors P5, P10, M4, M5, M6, M7, M8, N7, N13, resistors R4, R5, R6, R7, and a capacitor Cs.

[0110] Specifically, when the second output terminal of the control circuit is at a high level, that is, before 18 us, the transistor M4 is turned off and the first output terminal of the soft start circuit outputs a low level; when the second output terminal of the control circuit is at a low level, that is, after 18 us, the transistor M4 is turned on, the second input terminal of the soft start time control circuit inputs a descending ramp signal, and the output terminal of the soft start time control circuit outputs a slowly rising ramp signal.

[0111] It should be noted that the transistors N7 and N13 act to reverse the voltage signal, reverse the voltage signal input to the first input terminal of the soft start time control circuit, and output a slowly rising ramp signal at the first output terminal of the soft start time control circuit, as Figure 5 shown in the curve.

[0112] It should also be noted that resistors R4, R5, R6, R7 and capacitor Cs play a role in delaying the voltage signal; transistors M5, M6, M7, M8 play a role in controlling the delay time; when low levels are input to the third input terminal, fourth input terminal, fifth input terminal, and sixth input terminal of the soft start time control circuit, resistors R4, R5, R6, R7 are all connected to the circuit, and the rising ramp delay time is the longest, which is 857 μs; when a high level is input to one of the third input terminal, fourth input terminal, fifth input terminal, and sixth input terminal of the soft start time control circuit, the rising ramp delay time is 720 μs; when high levels are input to two of the third input terminal, fourth input terminal, fifth input terminal, and sixth input terminal of the soft start time control circuit, the rising ramp delay time is 570 μs; when high levels are input to three of the third input terminal, fourth input terminal, fifth input terminal, and sixth input terminal of the soft start time control circuit, the rising ramp delay time is 390 μs; as Figure 6 shown in the curve.

[0113] That is to say, the output terminal of the soft start time control circuit outputs a ramp-up voltage signal with an adjustable rising time.

[0114] Combined with Figure 3 the circuit schematic diagram of a soft start circuit and a start method with an adjustable start time provided by the embodiment of the present invention shown in the figure, the output clamp control circuit 4 will be described:

[0115] The output clamp circuit includes transistors P13, P14, N2, N3, N8, N14, P15, N15.

[0116] Specifically, the first input terminal of the output clamp circuit is connected to an external reference voltage, and the second input terminal is connected to the output of the first output terminal of the soft start time control circuit; the source terminal of transistor P15 is connected to the external reference voltage;

[0117] It should be noted that transistors P13, P14, N2, N3, N8, N14 form an OTA. When the external reference voltage is greater than the gate voltage of transistor N3, the drain of transistor N3 outputs a high level, transistor N15 conducts, and transistor P15 turns off, and Vout outputs a slowly rising voltage signal; when the external reference voltage is less than the gate voltage of transistor N3, the drain of transistor N3 outputs a low level, transistor N15 turns off, and transistor P15 conducts, and Vout outputs the external reference voltage, as Figure 7 shown in the curve.

[0118] In an embodiment of the present invention, through the charging and discharging of the capacitor Cp and the amplitude limiting of the transistor N1, a slowly decreasing ramp signal is output from the output end of the ramp generation circuit, and then reversed by the soft start time control circuit. By determining whether the resistors R4, R5, R6, and R7 are connected to the circuit according to the high and low levels of the third, fourth, fifth, and sixth input ends of the soft start control circuit, the effect of controlling the soft start time is achieved; finally, it is output from the first output end of the output clamping circuit; the function of soft start is realized, without the need to externally connect a large off-chip capacitor, greatly reducing the inrush current, and the start time can be adjusted within a certain range to meet the needs of different usage scenarios.

[0119] In summary, the present invention provides an adjustable start time soft start circuit and a start method. The reference current of the external circuit is connected to the first input end of the control circuit, and the first output end of the control circuit is connected to the input end of the ramp generation circuit; the second output end of the control circuit is connected to the first input end of the soft start time control circuit; the output end of the ramp generation circuit is connected to the second input end of the soft start time control circuit; the external circuit is connected to the third, fourth, fifth, and sixth input ends of the soft start time control circuit to control the soft start time; the output end of the soft start time control circuit is connected to the second input end of the output clamping circuit, and the external circuit is connected to the first input end of the output clamping circuit. Through the charging and discharging of the capacitor Cp and the amplitude limiting of the transistor N1, a slowly decreasing ramp signal is output from the output end of the ramp generation circuit, and then reversed by the soft start time control circuit. By determining whether the resistors R4, R5, R6, and R7 are connected to the circuit according to the high and low levels of the third, fourth, fifth, and sixth input ends of the soft start control circuit, the effect of controlling the soft start time is achieved; finally, it is output from the first output end of the output clamping circuit; the function of soft start is realized, without the need to externally connect a large off-chip capacitor, greatly reducing the inrush current, and the start time can be adjusted within a certain range to meet the needs of different usage scenarios.

Claims

1. A soft start circuit with adjustable start time, characterized in that, It includes a control circuit, a ramp generation circuit, a soft-start time control circuit, and an output clamping circuit; the input terminal of the control circuit receives a reference current from an external circuit, the first output terminal of the control circuit is connected to the input terminal of the ramp generation circuit, the second output terminal of the control circuit is connected to the first input terminal of the soft-start time control circuit, and the control circuit generates control signals for the ramp generation circuit and the soft-start time control circuit; the output terminal of the ramp generation circuit is connected to the second input terminal of the soft-start time control circuit, and the output terminal of the ramp generation circuit generates a falling ramp voltage and connects it to the second input terminal of the soft-start time control circuit; the first input terminal of the soft-start time control circuit is connected to the second output terminal of the control circuit; the levels of the third, fourth, fifth, and sixth input terminals of the soft-start time control circuit control the rising speed of the voltage signal output by the output terminal of the soft-start time control circuit; the first input terminal of the output clamping circuit is connected to an external reference voltage Vref, the second input terminal of the output clamping circuit is connected to the output terminal of the soft-start time control circuit, and the output clamping circuit clamps the voltage signal at its second input terminal to the external reference voltage Vref connected to its first input terminal and outputs it from the output terminal of the output clamping circuit.

2. The soft start circuit with adjustable start time according to claim 1, characterized in that, The control circuit includes transistor P1, transistor P2, transistor P6, transistor P7, resistor R1, transistor P11, transistor P12, transistor P16, transistor N9, and capacitor Cc; The gate of transistor P1 is connected to the gate of transistor P2, the common terminal where the source of transistor P1 and the source of transistor P2 are connected is connected to the power supply, the common terminal where the gate of transistor P1 and the gate of transistor P2 are connected is connected to one end of resistor R1, and the drain of transistor P1 and the drain of transistor P2 are respectively connected to the source of transistor P6 and the source of transistor P7; The gate of transistor P6 is connected to the gate of transistor P7, and the common terminal of the gate of transistor P6 and the gate of transistor P7 is connected to the other end of resistor R1; The other end of resistor R1 is connected to an external reference current source; The source of transistor P11 is connected to the drain of transistor P7, and the gate of transistor P11 is connected to its own drain; One end of capacitor Cc is connected to the drain of transistor P11, and the other end of the capacitor is connected to ground; Transistor P12, whose gate is connected to the drain of transistor P16, whose source is connected to the power supply, and whose drain is connected to the common terminal where the drain of transistor P11 and one end of capacitor Cc are connected; Transistor P16, whose gate is connected to the drain of transistor P12, whose source is connected to the power supply, and whose drain is connected to the gate of transistor P12; Transistor N9, whose gate is connected to the common terminal where the drain of transistor P11 and one end of capacitor Cc are connected, whose drain is connected to the gate of transistor P12, and whose source is connected to ground.

3. The soft start circuit with adjustable start time according to claim 1, characterized in that The ramp generation circuit includes transistor P3, transistor P4, transistor P8, transistor P9, transistor M1, transistor M2, transistor M3, resistor R2, resistor R3, capacitor Cp, transistor N4, transistor N5, transistor N10, transistor N11, transistor N6, and transistor N12; Transistor P3, whose gate is connected to the gates of transistor P1 and transistor P2, whose source is connected to the power supply, and whose drain is connected to the source of transistor M8; Transistor P4, whose gate is connected to the gate of transistor P3, whose source is connected to the power supply, and whose drain is connected to the source of transistor P9; Transistor P8, whose gate is connected to the gates of transistor P6 and transistor P7, whose source is connected to the drain of transistor P3, and whose drain is connected to the source of transistor M1; Transistor M9, whose gate is connected to the gates of transistor P6 and transistor P7, whose source is connected to the drain of transistor P4, and whose drain is connected to the source of transistor M2; Transistor M1, whose gate is connected to the gate of transistor P12, whose drain is connected to one end of resistor R2, and whose source is connected to the drain of transistor P8; Resistor R2, one end of which is connected to the drain of transistor M1 and the other end of which is connected to the drain of transistor N4; Capacitor Cp, one end of which is connected to the source of transistor M2 and the other end of which is connected to the ground; Resistor R3, one end of which is connected to one end of capacitor Cp and the other end of which is connected to the ground; Transistor N4, whose gate is connected to the gate of transistor N5, whose drain is connected to resistor R2, and whose source is connected to the drain of transistor N4; Transistor N5, whose gate is connected to the gate of transistor N4, whose source is connected to the drain of transistor N11, and whose drain is connected to the other end of resistor R3; Transistor N10, whose gate is connected to the gate of transistor N11, whose drain is connected to the source of transistor N4, and whose source is connected to the ground; Transistor N11, whose gate is connected to the gate of transistor N11, whose drain is connected to the source of transistor N5; Transistor M3, whose gate is connected to the gate of transistor M2, whose source is connected to the power supply, and whose drain is connected to the drain of transistor N1; Transistor N1, whose gate is connected to one end of resistor R3, whose drain is connected to the drain of transistor M3, and whose source is connected to the drain of transistor N6; Transistor N6, whose gate is connected to the drain of transistor N1, and whose source is connected to the drain of transistor N12; Transistor N12, whose gate is connected to the drain of transistor N12, and whose source is connected to the ground.

4. A soft start circuit with adjustable start time according to claim 1, characterized in that, The soft start time control circuit includes transistor P5, transistor P10, transistor M5, transistor M6, transistor M7, transistor M8, resistor R4, resistor R4, resistor R6, resistor R7, transistor M4, transistor N7, transistor N13, and capacitor Cs; Transistor P5, whose gate and drain are connected to the power supply, and whose drain is connected to the gate and drain of transistor P10; Transistor P10, whose gate is connected to the drain of transistor P10, and whose drain is connected to the source of transistor M5 and one end of resistor R4; Resistor R4, one end of which is connected to the source of transistor M5, and the other end of which is connected to the drain of transistor M5; Transistor M5, whose gate is connected to the outside through the third input terminal of the soft start time control circuit, whose source is connected to one end of resistor R4, and whose drain is connected to the other end of resistor R4; Resistor R5, one end of which is connected to the source of transistor M6, and the other end of which is connected to the drain of transistor M6; Transistor M6, whose gate is connected to the outside through the fourth input terminal of the soft start time control circuit, whose source is connected to one end of resistor R5, and whose drain is connected to the other end of resistor R5; Resistor R6, one end of which is connected to the source of transistor M7, and the other end of which is connected to the drain of transistor M7; Transistor M7, whose gate is connected to the outside through the fifth input terminal of the soft start time control circuit, whose source is connected to one end of resistor R6, and whose drain is connected to the other end of resistor R6; Resistor R7, one end of which is connected to the source of transistor M8, and the other end of which is connected to the drain of transistor M8; Transistor M8, whose gate is connected to the outside through the sixth input terminal of the soft start time control circuit, whose source is connected to one end of resistor R7, and whose drain is connected to the other end of resistor R7; Transistor M4, whose gate is connected to the gate of transistor M3, whose source is connected to the other end of resistor R7, and whose drain is connected to the source of transistor N7; Transistor M7, whose gate is connected to the drain of transistor N6, whose source is connected to the drain of transistor M4, and whose drain is connected to the drain of transistor N13; Transistor N13, whose gate is connected to the drain of transistor N6, whose drain is connected to the drain of transistor N7, and whose source is connected to the ground; Capacitor Cs, one end of which is connected to the drain of transistor N13, and the other end of which is connected to the ground.

5. The soft start circuit with adjustable start time according to claim 1, characterized in that, The output clamping circuit includes transistor P13, transistor P14, transistor N2, transistor N3, transistor N8, transistor N14, transistor P15, transistor N15; Transistor P13, whose gate is connected to transistor P14, whose source is connected to the power supply, and whose drain is connected to the gate of transistor P13; Transistor P14, whose gate is connected to the gate of transistor P13, whose source is connected to the power supply, and whose drain is connected to the drain of transistor N3; Transistor N2, whose gate is connected to the outside through the first input terminal of the output clamping circuit, whose drain is connected to the drain of transistor P13, and whose source is connected to the drain of transistor N8; Transistor N3, whose gate is connected to the drain of transistor N15, whose drain is connected to the drain of transistor P14, and whose source is connected to the drain of transistor N8; Transistor N8, whose gate is connected to the gate of transistor N5, whose drain is connected to the source of transistor N2, and whose source is connected to the drain of transistor N14; Transistor N14, whose gate is connected to the gate of transistor N11, whose drain is connected to the source of transistor N8, and whose source is connected to the ground; Transistor P15, whose gate is externally connected through the first input terminal of the output clamping circuit, whose gate is connected to the drain of transistor P14, and whose drain is connected to the source of transistor N15; Transistor N15, whose gate is connected to the drain of transistor P14, whose drain is connected to the gate of transistor N3, and whose source is connected to the drain of transistor P15.

6. A starting method for a soft starting circuit with adjustable starting time according to claim 1, characterized in that, It includes the following steps: Step 1: Construct a soft-start circuit with adjustable start time including a control circuit, a ramp generation circuit, a soft-start time control circuit, and an output clamping circuit; the reference current of the external circuit is connected to the first input terminal of the control circuit, and the first output terminal of the control circuit is connected to the input terminal of the ramp generation circuit; the second output terminal of the control circuit is connected to the first input terminal of the soft-start time control circuit; the output terminal of the ramp generation circuit is connected to the second input terminal of the soft-start time control circuit; the external circuit is connected to the third, fourth, fifth, and sixth input terminals of the soft-start time control circuit to control the soft-start time; the output terminal of the soft-start time control circuit is connected to the second input terminal of the output clamping circuit, and the external circuit is connected to the first input terminal of the output clamping circuit; Step 2: Through the charge and discharge of capacitor Cp and the amplitude limiting of transistor N1, a slowly decreasing ramp signal is output from the output terminal of the ramp generation circuit, and then inverted by the soft-start time control circuit. Whether resistors R4, R5, R6, and R7 are connected to the circuit is determined by the high and low levels of the third, fourth, fifth, and sixth input terminals of the soft-start control circuit, achieving the effect of controlling the soft-start time; Step 3: Output through the first output terminal of the output clamping circuit.

7. The method according to claim 6, characterized in that, The control circuit includes transistors P1, P2, P6, P7 that act as a current mirror, as well as an external reference current source Idc, a bias resistor R1, transistors P11, P12, P16, N9, and a capacitor Cc; Transistors P2 and P7 copy the current of Idc to charge capacitor Cc. At this time, the voltage at one end of capacitor Cc rises, and the voltage at one end of capacitor Cc is then input to the gate connected to transistors N9 and P16, inverted by the inverter composed of transistors N9 and P16, and output from the drain of transistor N9, that is, output from the output terminal of the control circuit; The voltage signal output from the drain of transistor N9 is a high-level signal from 0 to 18 μs and a low-level signal after 18 μs.

8. The method according to claim 6, wherein The ramp generation circuit 2 includes transistors P3, P4, P8, P9, N4, N5, N10, N11 which act as a current mirror, transistors M1, M2, bias resistors R2, R3, and a capacitor Cp. When the first output terminal of the control circuit outputs a high level, the gate of transistor M2 is at a high level, transistor M2 turns on, and the current flowing through the drains of transistors P4 and P9 charges the capacitor Cp. The charging time is 18 μs, causing the voltage of the upper plate of capacitor Cp to reach 3V. When the first output terminal of the control circuit outputs a low level, the gate of transistor M1 is at a low level, transistor M1 turns on, the gate of transistor M2 is at a low level, and transistor M2 turns off. One end of capacitor Cp is connected to one end of R3, and capacitor Cp discharges. The discharge current is equal to the current of the drains of transistors N4 and N10 replicated by transistors N5 and N11. When the first output terminal of the control circuit outputs a high level, transistor M3 turns off and transistor N1 does not work. When the first output terminal of the control circuit outputs a low level, transistor M3 turns on, and transistor N1 acts as a source follower and, together with transistor N6 and transistor N12, limits the discharge voltage at one end of capacitor Cp, i.e., VN1D = VN1G - VN1TH; The minimum value of the source voltage of transistor N1 is VN6TH + VN12TH. The output terminal of the ramp generation circuit outputs a decreasing ramp voltage signal after 18 μs.

9. The method according to claim 6, wherein The soft start time control circuit includes transistors P5, P10, M4, M5, M6, M7, M8, N7, N13, resistors R4, R5, R6, R7, and a capacitor Cs. When the second output terminal of the control circuit is at a high level, i.e., before 18 μs, transistor M4 turns off, and the first output terminal of the soft start circuit outputs a low level. When the second output terminal of the control circuit is at a low level, i.e., after 18 μs, transistor M4 turns on, the second input terminal of the soft start time control circuit inputs a decreasing ramp signal, and the output terminal of the soft start time control circuit outputs a slowly rising ramp signal; Transistors N7 and N13 act to reverse the voltage signal, reversing the voltage signal input to the first input terminal of the soft start time control circuit and outputting a slowly rising ramp signal at the first output terminal of the soft start time control circuit. Resistors R4, R5, R6, R7, and capacitor Cs act to delay the voltage signal; Transistors M5, M6, M7, and M8 play a role in controlling the delay time; when low levels are input to the third input terminal, fourth input terminal, fifth input terminal, and sixth input terminal of the soft-start time control circuit, resistors R4, R5, R6, and R7 are all connected to the circuit, and the rising ramp delay time is the longest, which is 857 μs; when a high level is input to one of the third input terminal, fourth input terminal, fifth input terminal, and sixth input terminal of the soft-start time control circuit, the rising ramp delay time is 720 μs; when high levels are input to two of the third input terminal, fourth input terminal, fifth input terminal, and sixth input terminal of the soft-start time control circuit, the rising ramp delay time is 570 μs; when high levels are input to three of the third input terminal, fourth input terminal, fifth input terminal, and sixth input terminal of the soft-start time control circuit, the rising ramp delay time is 390 μs; the output terminal of the soft-start time control circuit outputs a ramp-up voltage signal with an adjustable rising time.

10. The method according to claim 6, wherein The output clamping circuit includes transistors P13, P14, N2, N3, N8, N14, P15, and N15; the first input terminal of the output clamping circuit is connected to an external reference voltage, and the second input terminal is connected to the output of the first output terminal of the soft-start time control circuit; the source terminal of transistor P15 is connected to the external reference voltage; transistors P13, P14, N2, N3, N8, and N14 form an OTA. When the external reference voltage is greater than the gate voltage of transistor N3, the drain of transistor N3 outputs a high level, transistor N15 conducts, and transistor P15 turns off, and Vout outputs a slowly rising voltage signal; when the external reference voltage is less than the gate voltage of transistor N3, the drain of transistor N3 outputs a low level, transistor N15 turns off, and transistor P15 conducts, and Vout outputs the external reference voltage.

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