Oscillator chip and manufacturing method thereof

Abstract

The invention provides an oscillator chip and a manufacturing method thereof. The manufacturing method of the oscillator chip comprises the following steps. Providing a quartz wafer, wherein the quartz wafer is provided with a first surface and a second surface opposite to the first surface; a first etching process is performed on the quartz wafer to form a plurality of recessed platform portions, and the plurality of recessed platform portions have a first thickness. The quartz wafer is singulated to form a plurality of oscillator sub-chips, wherein each of the plurality of oscillator sub-chips includes one of a plurality of recessed platform portions. And performing a second etching process on the plurality of oscillation sub-chips so as to form chamfers on the edges of the plurality of oscillation sub-chips.

Description

Technical Field

[0001] The present invention relates to a chip and a manufacturing method thereof, and particularly to an oscillator chip and a manufacturing method thereof. Background Art

[0002] A quartz oscillator is an electronic component used to generate an oscillation frequency. As electronic products tend to be thinner, lighter, shorter, and smaller, the size of the quartz oscillator has been continuously reduced. However, during the cutting process of the quartz oscillator, cracks exceeding 5 micrometers are likely to occur at the cutting edge, resulting in the situation that the quartz oscillator is prone to fragmentation when subjected to an external impact, thus affecting the reliability of the quartz oscillator. Therefore, how to improve the reliability of the quartz oscillator is a problem to be solved currently. Summary of the Invention

[0003] The present invention is directed to an oscillator chip and a manufacturing method thereof, which can reduce cracks at the cutting edge and thus improve the reliability.

[0004] According to an embodiment of the present invention, a manufacturing method of an oscillator chip includes the following steps. Provide a quartz wafer, the quartz wafer having a first surface and a second surface opposite to the first surface. Perform a first etching process on the quartz wafer to form a plurality of inverted mesa portions, and the plurality of inverted mesa portions have a first thickness. Singulate the quartz wafer to form a plurality of oscillator chips, wherein each of the plurality of oscillator chips includes one of the plurality of inverted mesa portions. Perform a second etching process on the plurality of oscillator chips to chamfer the edges of the plurality of oscillator chips.

[0005] In an embodiment of the present invention, the above-mentioned second etching process is an isotropic etching process.

[0006] In an embodiment of the present invention, after performing the second etching process on the plurality of oscillator chips, the plurality of inverted mesa portions have a third thickness, and the third thickness is less than the first thickness.

[0007] In an embodiment of the present invention, the ratio of the third thickness to the first thickness is less than 0.9.

[0008] In an embodiment of the present invention, performing the first etching process on the quartz wafer includes the following steps. Form a first recess on the first surface of the quartz wafer. Form a second recess on the second surface of the quartz wafer, wherein the first recess corresponds to the second recess.

[0009] In an embodiment of the present invention, the above manufacturing method further includes forming a mask layer on the first surface and the second surface of the quartz wafer, wherein the mask layer includes a plurality of openings, and the positions of the plurality of openings define the positions of a plurality of recessed platform portions. The step of performing the first etching process on the quartz wafer includes immersing the quartz wafer in an etching solution to remove a part of the quartz wafer not covered by the mask layer.

[0010] In an embodiment of the present invention, the step of forming the plurality of openings in the mask layer includes forming a patterned photoresist layer on the mask layer; using the patterned photoresist layer as a mask to remove the mask layer not covered by the patterned photoresist layer to form a plurality of openings, thereby exposing part of the first surface and the second surface of the quartz wafer; and removing the patterned photoresist layer.

[0011] In an embodiment of the present invention, the step of singulating the quartz wafer includes defining a dicing lane in the quartz wafer using a laser; and using wet etching to singulate the quartz wafer into a plurality of resonator chips along the dicing lane.

[0012] The resonator chip of the present invention includes a recessed platform portion and a peripheral portion. The peripheral portion laterally surrounds the recessed platform portion, wherein the thickness of the recessed platform portion is less than the thickness of the peripheral portion. There is at least one chamfer structure between the top surface or the bottom surface and the outer side surface of the peripheral portion.

[0013] In an embodiment of the present invention, the angle between the at least one chamfer structure and the top surface or the bottom surface is between 95 degrees and 125 degrees.

[0014] In an embodiment of the present invention, the edge of the peripheral portion has a notch.

[0015] In an embodiment of the present invention, the depth of the notch is less than 4 micrometers.

[0016] In an embodiment of the present invention, the at least one chamfer structure includes a first chamfer structure and a second chamfer structure, which are respectively located at the peripheral portions on opposite sides of the recessed platform portion, wherein the first chamfer structure is an inclined surface connecting the bottom surface and the outer side surface of the peripheral portion, and the second chamfer structure is an inclined surface connecting the top surface and the outer side surface of the peripheral portion.

[0017] Based on the above, the resonator chip of the present invention forms the recessed platform portion through two etching processes, and can modify the edge of the resonator chip while forming a recessed platform portion with a predetermined thickness, so as to reduce crack generation, reduce the possibility of chip breakage due to external force impact, and thereby improve its reliability. Description of the Drawings

[0018] Figures 1A to 1L is a cross-sectional schematic view of a manufacturing method of a resonator chip according to an embodiment of the present invention.

[0019] Figure 2 is Figure 1L a top view of an oscillator chip.

[0020] Figure 3 is a schematic cross-sectional view of a packaging structure according to an embodiment of the present invention. Detailed Description of the Invention

[0021] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings and the description to refer to the same or like parts.

[0022] Exemplary embodiments of the present invention will be described fully hereinafter with reference to the drawings, but the present invention can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, for the sake of clarity, the size and thickness of each region, part, and layer may not be drawn to scale.

[0023] Directional terms mentioned herein, such as "upper", "lower", "front", "rear", "left", "right", etc., are with reference to the directions of the drawings. Therefore, the directional terms used are for illustration purposes only and are not intended to limit the present invention.

[0024] In the following embodiments, the same or similar components will be denoted by the same or similar reference numerals, and their detailed descriptions will be omitted. In addition, features in different embodiments can be combined with each other without conflict, and simple equivalent changes and modifications made according to this specification or the scope of the patent application still fall within the scope of this patent.

[0025] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various components, parts, regions, layers, and / or portions, these components, parts, regions, and / or portions should not be limited by these terms. These terms are used to distinguish one component, part, region, layer, or portion from another. Thus, the first component, part, region, layer, or portion discussed below may be referred to as a second component, part, region, layer, or portion without departing from the teachings herein.

[0026] Figures 1A to 1L is a schematic cross-sectional view of a manufacturing method of an oscillator chip according to an embodiment of the present invention.

[0027] Please refer to Figure 1A , a quartz wafer 100 is provided, and the quartz wafer 100 has a first surface 100a and a second surface 100b opposite to the first surface 100a. In some embodiments, the quartz wafer 100 may be a single crystal structure.

[0028] Then, a mask layer 110 is formed on the first surface 100a and the second surface 100b of the quartz wafer 100. In some embodiments, the mask layer 110 includes a metallic material such as gold, chromium, nickel, copper, or other suitable metallic materials. In some embodiments, the mask layer 110 can be formed by chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0029] Please refer to Figure 1B , and a photoresist layer 120 is formed on the mask layer 110. In some embodiments, the photoresist layer 120 can be formed by spin coating, chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0030] Please refer to Figure 1C , using a photomask (not shown) as a mask, the photoresist layer 120 is exposed and developed to form a patterned photoresist layer 120'. The patterned photoresist layer 120' can define a recessed platform region IM to be etched subsequently.

[0031] Please refer to Figure 1D , using the patterned photoresist layer 120' as a mask, the mask layer 110 that is not covered by the patterned photoresist layer 120' is removed to form a plurality of openings OP, exposing a part of the first surface 100a and the second surface 100b of the quartz wafer 100. For example, wet etching can be used to immerse the obtained structure in an etching solution with a high etching selectivity to the mask layer 110 to remove the mask layer 110 that is not covered by the patterned photoresist layer 120'. However, the present invention is not limited thereto, and other suitable methods can also be used to remove the mask layer 110 that is not covered by the patterned photoresist layer 120'.

[0032] Please refer to Figure 1E , the patterned photoresist layer 120' is removed. In some embodiments, the patterned photoresist layer 120' can be removed through ashing process, wet etching process, dry etching process, chemical mechanical polishing process, or other suitable means.

[0033] Please refer to Figure 1F , using the mask layer 110 as a mask, a first etching process is performed on the quartz wafer 100 to form a plurality of recessed platform portions 102, and the unetched part of the quartz wafer 100 is also referred to as the peripheral portion 104. The recessed platform portion 102 has a first thickness H1, and the peripheral portion 104 has a second thickness H2, and the first thickness H1 is less than the second thickness H2. In some embodiments, the ratio of the first thickness H1 to the second thickness H2 is about between 0.45 and 0.65.

[0034] In some embodiments, the first etching process is a wet etching process. For example, the quartz wafer 100 can be immersed in an etching solution to selectively remove a portion of the quartz wafer 100 that is not covered by the mask layer 110, so as to form a first recess R1 on the first surface 100a of the quartz wafer 100 in the recessed platform region IM and a second recess R2 on the second surface 100b of the quartz wafer 100. The first recess R1 and the second recess R2 correspond to each other. In some embodiments, the depth of the first recess R1 is substantially the same as the depth of the second recess R2, but the present invention is not limited thereto. In some embodiments, the etching solution used in the first etching process can be an etching solution having a high etching selectivity for the quartz wafer 100.

[0035] In some embodiments, the quartz wafer 100 has a relatively high etching rate in the direction of its lattice growth, such that a portion of the quartz wafer 100 located under the mask layer 110 is also etched. For example, in Figure 1F the left side of the first recess R1 extends under the mask layer 110, such that the left and right sides of the first recess R1 are asymmetrical to each other; and the right side of the second recess R2 extends under the mask layer 110, such that the left and right sides of the second recess R2 are asymmetrical to each other. In some embodiments, the bottom surface and the sidewall of the first recess R1 form an angle φ1 and an angle φ2, wherein the angle φ1 and the angle φ2 have different angles. For example, the angle of the angle φ1 is greater than the angle of the angle φ2. In some embodiments, the bottom surface and the sidewall of the second recess R2 form an angle φ3 and an angle φ4, wherein the angle φ3 and the angle φ4 have different angles. For example, the angle of the angle φ4 is greater than the angle of the angle φ3.

[0036] After the quartz wafer 100 undergoes the first etching process, a recessed platform portion 102 is initially formed. At this time, the recessed platform portion 102 is not the predetermined thickness that the final oscillator chip desires to achieve. The first thickness H1 of the recessed platform portion 102 can be between 1.1 times and 1.5 times the predetermined thickness of the oscillator chip.

[0037] Please refer to Figure 1G , and remove the mask layer 110. In some embodiments, the mask layer 110 can be removed through a wet etching process, a dry etching process, a chemical mechanical polishing process, or other suitable means.

[0038] Please refer to Figure 1H and Figure 1I , and singulate the monolithic quartz wafer 100 to form a plurality of oscillator chips 100A, wherein each of the plurality of oscillator chips 100A includes one of the plurality of recessed platform portions 102. Specifically, in Figure 1HIn this process, a dividing channel 100' is defined in the quartz wafer 100 by using a laser 200. The quartz wafer 100 can be divided into a plurality of oscillator chips 100A according to the dividing channel 100'. The path along which the laser 200 scans on the quartz wafer 100 is the path of the dividing channel 100'. Since the laser 200 has high energy, the laser-treated quartz wafer 100 (i.e., the dividing channel 100') can be metamorphosed, for example, into a twin crystal structure, making the properties of the dividing channel 100' different from those of the non-laser-treated quartz wafer 100.

[0039] After that, in Figure 1I a wet etching process is used to selectively etch the dividing channel 100' so that the quartz wafer 100 is divided into a plurality of oscillator chips 100A along the dividing channel 100'. Since the properties of the dividing channel 100' are different from those of the non-laser-treated quartz wafer 100, the dividing channel 100' can be etched by selecting an etching solution with an appropriate etching selectivity ratio to divide the quartz wafer 100 into a plurality of oscillator chips 100A. For example, the etching solution can include ammonium bifluoride or other suitable etching solutions.

[0040] Please refer to Figure 1J for frequency measurement of the recessed platform portion 102 of the oscillator chip 100A to calculate the time required for the subsequent etching process to reach a predetermined frequency. For example, a space charge measurement system 210 can be used to measure the frequency of the recessed platform portion 102 of the oscillator chip 100A, and then based on the difference between the obtained frequency and the desired frequency value, calculate the time required for the subsequent etching process to reach the recessed platform portion 102 with a predetermined thickness.

[0041] Please refer to Figure 1K and Figure 1L for a second etching process on the oscillator chip 100A to etch the recessed platform portion 102 to a predetermined thickness and form a chamfered structure 106 on the edge of the oscillator chip 100A to modify the edge of the oscillator chip 100A to reduce crack generation. In Figure 1K for clarity, the outline of the oscillator chip 100A before the second etching process is shown by a dashed line, and the outline of the oscillator chip 100A after the second etching process is shown by a solid line.

[0042] In some embodiments, the second etching process is an isotropic etching process, such as a wet etching process. Accordingly, each surface of the oscillator chip 100A is etched to form a recessed platform portion 102 having a third thickness H3 and a peripheral portion 104 having a fourth thickness H4, where the third thickness H3 is less than the first thickness H1 and the fourth thickness H4 is less than the second thickness H2. In some embodiments, the ratio of the third thickness H3 to the first thickness H1 is less than 0.9 or less than 0.88. In some embodiments, the ratio of the third thickness H3 to the first thickness H1 is between 0.8 and 0.9. In this way, the oscillator chip 100A can achieve the effect of edge modification and a predetermined thickness of the recessed platform portion 102 through the second etching process.

[0043] In some embodiments, since the etching rate of the oscillator chip 100A is relatively fast in the lattice growth direction thereof, a chamfer structure 106 is likely to be formed at the edge of the oscillator chip 100A in the lattice growth direction, and the first recess R1 and the second recess R2 are etched more in the lattice growth direction. For example, in Figure 1L the peripheral portion 104 includes a first portion 1041 and a second portion 1042, which are respectively located on opposite sides of the recessed platform portion 102. The first recess R1 is etched more in the direction towards the first portion 1041 (compared with the direction towards the second portion 1042), and the second recess R2 is etched more in the direction towards the second portion 1042 (compared with the direction towards the first portion 1041), such that the left and right sides of the first recess R1 are asymmetrical with each other, and the left and right sides of the second recess R2 are asymmetrical with each other. On the other hand, the oscillator chip 100A includes two chamfer structures (such as a first chamfer structure 106a and a second chamfer structure 106b) respectively located between the bottom surface 104b and the outer side surface 104c of the first portion 1041 of the peripheral portion 104 and between the top surface 104a and the outer side surface 104c of the second portion 1042. In some embodiments, there is no chamfer structure between the top surface 104a and the outer side surface 104c of the first portion 1041 of the peripheral portion 104, and there is no chamfer structure between the bottom surface 104b and the outer side surface 104c of the second portion 1042 of the peripheral portion 104, that is, the top surface 104a and the outer side surface 104c of the first portion 1041 of the peripheral portion 104 are substantially perpendicular to each other, and the bottom surface 104b and the outer side surface 104c of the second portion 1042 of the peripheral portion 104 are substantially perpendicular to each other. However, the present invention is not limited thereto. In other embodiments, there may also be chamfer structures between the top surface 104a and the outer side surface 104c of the first portion 1041 of the peripheral portion 104 and between the bottom surface 104b and the outer side surface 104c of the second portion 1042 of the peripheral portion 104.

[0044] Based on the above, the fabrication of the oscillator chip 100A of this embodiment can be roughly completed. Since the recessed platform portion 102 of the oscillator chip 100A is formed by two etching processes, the recessed platform portion 102 is initially formed in the first etching process, and then in the second etching process, the recessed platform portion 102 is etched to the required thickness and the edge of the oscillator chip 100A is modified simultaneously, which can reduce crack generation and thus improve the reliability of the oscillator chip 100A.

[0045] Figure 2 is Figure 1L a top view of the oscillator chip. Figure 1L It may be a cross-sectional view cut along Figure 2 line A-A’ of. Specifically, Figure 1L is a cross-sectional view cut along the short side direction D1 of the oscillator chip 100A.

[0046] Please refer to Figure 1L and Figure 2 . The oscillator chip 100A includes a recessed platform portion 102 and a peripheral portion 104. The peripheral portion 104 laterally surrounds the recessed platform portion 102, and the thickness of the recessed platform portion 102 (i.e., the third thickness H3) is less than the thickness of the peripheral portion (i.e., the fourth thickness H4). There is at least one chamfer structure 106 between the top surface 104a or the bottom surface 104b of the peripheral portion 104 and the outer side surface 104c.

[0047] In some embodiments, the thickness of the recessed platform portion 102 (i.e., the third thickness H3) is between 5 micrometers and 20 micrometers, but the present invention is not limited thereto, and the thickness of the recessed platform portion 102 can be adjusted according to actual requirements.

[0048] The peripheral portion 104 may include a first portion 1041, a second portion 1042, a third portion 1043, and a fourth portion 1044 respectively connected to the four sides of the recessed platform portion 102. The first portion 1041 is opposite to the second portion 1042, and the third portion 1043 is opposite to the fourth portion 1044. For example, in Figure 2In it, the first part 1041 is located on the left side of the concave platform part 102, the second part 1042 is located on the right side of the concave platform part 102, the third part 1043 is located on the upper side of the concave platform part 102, and the fourth part 1044 is located on the lower side of the concave platform part 102. In some embodiments, the width of the fourth part 1044 is wider than the widths of the first part 1041, the second part 1042, and the third part 1043 to serve as a connection part with other components in the subsequent encapsulation structure. (The width of the first part 1041 refers to the distance between the edge of the first part 1041 and the edge of the concave platform part 102 closest to the first part 1041 as viewed from the top view; the width of the second part 1042 refers to the distance between the edge of the second part 1042 and the edge of the concave platform part 102 closest to the second part 1042 as viewed from the top view; the width of the third part 1043 refers to the distance between the edge of the third part 1043 and the edge of the concave platform part 102 closest to the third part 1043 as viewed from the top view; the width of the fourth part 1044 refers to the distance between the edge of the fourth part 1044 and the edge of the concave platform part 102 closest to the fourth part 1044 as viewed from the top view.)

[0049] In some embodiments, the chamfer structure 106 is, for example, an inclined plane connected to the top surface 104a or the bottom surface 104b and the outer side surface 104c of the peripheral part 104. Specifically, in Figure 1L it, the oscillator chip 100A includes two chamfer structures (for example, the first chamfer structure 106a and the second chamfer structure 106b) respectively located at the peripheral parts 104 (for example, the first part 1041 and the second part 1042) on the opposite sides of the concave platform part 102. The first chamfer structure 106a is, for example, an inclined plane connected between the bottom surface 104b and the outer side surface 104c of the first part 1041 of the peripheral part 104, and the first chamfer structure 106a has an included angle θ1 with the bottom surface 104b of the first part 1041. The second chamfer structure 106b is, for example, an inclined plane connected between the top surface 104a and the outer side surface 104c of the second part 1042 of the peripheral part 104, and the second chamfer structure 106b has an included angle θ2 with the top surface 104a of the second part 1042. In some embodiments, the included angle θ1 and the included angle θ2 can be respectively between 95 degrees and 125 degrees. In this way, the possibility of cracks appearing at the edges of the oscillator chip 100A can be reduced.

[0050] In some embodiments, the top surface 104a of the first part 1041 and the outer side surface 104c have an included angle θ3, and the included angle θ1 is substantially greater than the included angle θ3; the bottom surface 104b of the second part 1042 and the outer side surface 104c have an included angle θ4, and the included angle θ2 is substantially greater than the included angle θ4.

[0051] In some embodiments, the top surface 104a of the first part 1041 is substantially perpendicularly connected to the outer side surface 104c, and the bottom surface 104b of the second part 1042 is substantially perpendicularly connected to the outer side surface 104c. In some embodiments, the included angle θ3 and the included angle θ4 can be respectively between 85 degrees and 115 degrees, but the present invention is not limited thereto.

[0052] In some embodiments, after the above process, as Figure 1L shown, the bottom surface of the first recess R1 and the side wall form opposite included angles φ1' and φ2' in the short side direction D1, where the angle of the included angle φ1' is greater than the angle of the included angle φ2', and the bottom surface of the second recess R2 and the side wall form opposite included angles φ3' and φ4' in the short side direction D1, where the angle of the included angle φ4' is greater than the angle of the included angle φ3'. In some embodiments, the included angle φ1' and the included angle φ4' can be respectively between 140 degrees and 170 degrees, but the present invention is not limited thereto. In some embodiments, the included angle φ2' and the included angle φ3' can be respectively between 92 degrees and 112 degrees, but the present invention is not limited thereto. In some embodiments, the included angle φ1' and the included angle φ3' are respectively located on both sides of the recessed platform portion 102 and are opposite to each other, while the included angle φ2' and the included angle φ4' are respectively located on both sides of the recessed platform portion 102 and are opposite to each other.

[0053] In some embodiments, the third part 1043 and the fourth part 1044 of the peripheral part 104 basically do not have a chamfer structure (refer to the cross-sectional view shown in Figure 3 ). That is to say, the top surface 104a and the bottom surface 104b of the third part 1043 and the fourth part 1044 are basically perpendicularly connected to the outer side surface 104c respectively, but the present invention is not limited thereto.

[0054] In some embodiments, as Figure 2 shown, the edge L1 of the first part 1041 and / or the edge L2 of the second part 1042 of the peripheral part 104 may have a notch v. In some embodiments, the depth h of the notch v is less than 4 micrometers. In this way, even if the oscillator chip 100A is subjected to an external force impact, it can still be within its stress tolerance range, thereby reducing the possibility of fragments. In this article, the depth h of the notch v refers to the vertical distance between the tip of the notch v and the edge where the notch v is located. In Figure 2 only a notch v is schematically shown on the edge L2 of the second part 1042, but it is not used to limit the present invention. There may be one or more notches v on the edge L1 of the first part 1041 and on the edge L2 of the second part 1042 respectively.

[0055] Figure 3 is a schematic cross-sectional view of a packaging structure according to an embodiment of the present invention. It must be noted here that Figure 3 the embodiments ofFigure 1L Component labels and partial content of the embodiments, where the same or similar labels are used to represent the same or similar components, and the description of the same technical content is omitted. For the description of the omitted part, reference can be made to the foregoing embodiments and will not be elaborated herein. Figure 3 The oscillator chip 100A shown in Figure 2 can be a cross-sectional view cut along line B-B' of Figure 3 That is, the oscillator chip 100A shown in

[0056] Please refer to Figure 3 , the package structure 10 includes an oscillator chip 100A, a first electrode 130, a second electrode 140, a base 150, and an upper cover 160. The oscillator chip 100A can be Figure 1L the oscillator chip 100A as described above. For related content, reference can be made to the foregoing and will not be elaborated herein. The first electrode 130 and the second electrode 140 can be respectively disposed on opposite surfaces of the recessed platform portion 102 of the oscillator chip 100A. For example, the first electrode 130 is located on the top surface of the recessed platform portion 102, and the second electrode 140 is located on the bottom surface of the recessed platform portion 102. The area of the recessed platform portion 102 between the first electrode 130 and the second electrode 140 is the vibration area, and the thickness of the recessed platform portion 102 can determine the oscillation frequency of this vibration area. In some embodiments, the first electrode 130 and the second electrode 140 can respectively extend along the top surface and the bottom surface of the recessed platform portion 102 to the peripheral portion 104 of the oscillator chip 100A. In some embodiments, the oscillator chip 100A, the first electrode 130, and the second electrode 140 can form a resonator or an oscillator.

[0057] The base 150 has a receiving space 152 for the oscillator chip 100A to be disposed in the receiving space 152. The upper cover 160 is disposed on the base 150 to cover the oscillator chip 100A and enclose the receiving space 152. In some embodiments, the package structure 10 may further include a seal ring or an adhesive layer 170 to seal the upper cover 160 and the base 150. In some embodiments, the oscillator chip 100A can be adhered to the base 150 through an adhesive 180 at the fourth part 1044 of the peripheral portion 104 of the oscillator chip 100A. That is to say, the first part 1041, the second part 1042, and the third part 1043 of the peripheral portion 104 of the oscillator chip 100A are substantially suspended. The adhesive 180 is, for example, a conductive adhesive to connect the first electrode 130 and the second electrode 140 to corresponding pads (not shown) or circuits (not shown) in the base 150.

[0058] The encapsulation structure 10 shows an application mode of the oscillator chip 100A. Since the cracks at the edge of the oscillator chip 100A are reduced, the possibility of chip fragmentation due to external force impact can be decreased, thereby improving the reliability of the encapsulation structure 10.

[0059] In summary, the oscillator chip of the present invention forms a recessed platform portion through two etching processes. While forming a recessed platform portion with a predetermined thickness, the edge of the oscillator chip can be modified to reduce crack generation, decrease the possibility of chip fragmentation due to external force impact, and thereby improve its reliability.

[0060] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A manufacturing method of an oscillator chip, characterized in that, Comprising: Providing a quartz wafer having a first surface and a second surface opposite to the first surface; Performing a first etching process on the quartz wafer to form a plurality of recessed platform portions, and the plurality of recessed platform portions having a first thickness; Singulating the quartz wafer to form a plurality of oscillator chips, wherein each of the plurality of oscillator chips includes one of the plurality of recessed platform portions; And Performing a second etching process on the plurality of oscillator chips to form chamfers on the edges of the plurality of oscillator chips.

2. The manufacturing method of the oscillator chip according to claim 1, characterized in that, The second etching process is an isotropic etching process.

3. The manufacturing method of the oscillator chip according to claim 1, characterized in that, After performing the second etching process on the plurality of oscillator chips, the plurality of recessed platform portions have a third thickness, and the third thickness is less than the first thickness.

4. The manufacturing method of the oscillator chip according to claim 3, characterized in that, The ratio of the third thickness to the first thickness is less than 0.

9.

5. The manufacturing method of the oscillator chip according to claim 1, characterized in that, Performing the first etching process on the quartz wafer includes: Forming a first recess on the first surface of the quartz wafer; and Forming a second recess on the second surface of the quartz wafer, wherein the first recess corresponds to the second recess.

6. The manufacturing method of the oscillator chip according to claim 1, characterized in that, Further comprising: Forming a mask layer on the first surface and the second surface of the quartz wafer, wherein the mask layer includes a plurality of openings, and the positions of the plurality of openings define the positions of the plurality of recessed platform portions, wherein the step of performing the first etching process on the quartz wafer includes: Immersing the quartz wafer in an etching solution to remove a portion of the quartz wafer not covered by the mask layer.

7. The manufacturing method of the oscillator chip according to claim 6, characterized in that, The step of forming the plurality of openings of the mask layer includes: Forming a patterned photoresist layer on the mask layer; Using the patterned photoresist layer as a mask to remove the mask layer not covered by the patterned photoresist layer to form the plurality of openings and expose a portion of the first surface and the second surface of the quartz wafer; and Removing the patterned photoresist layer.

8. The manufacturing method of the oscillator chip according to claim 1, characterized in that The step of singulating the quartz wafer includes: Defining scribe lanes on the quartz wafer using a laser; and Using wet etching to divide the quartz wafer along the scribe lanes into the plurality of oscillator chips.

9. An oscillator chip, characterized in that, Comprising: A recessed platform portion; and A peripheral portion laterally surrounding the recessed platform portion, wherein the thickness of the recessed platform portion is less than the thickness of the peripheral portion, wherein there is at least one chamfer structure between the top surface or the bottom surface of the peripheral portion and the outer side surface.

10. The oscillator chip according to claim 9, characterized in that, The angle between the at least one chamfer structure and the top surface or the bottom surface is between 95 degrees and 125 degrees.

11. The oscillator chip according to claim 9, characterized in that, The edge of the peripheral portion has a notch.

12. The oscillator chip according to claim 11, characterized in that, The depth of the notch is less than 4 micrometers.

13. The oscillator chip according to claim 9, characterized in that, The at least one chamfer structure includes: A first chamfer structure and a second chamfer structure, respectively located on the peripheral portions on opposite sides of the recessed platform portion, wherein the first chamfer structure is an inclined surface connecting the bottom surface and the outer side surface of the peripheral portion, and the second chamfer structure is an inclined surface connecting the top surface and the outer side surface of the peripheral portion.

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