Circuit and method for reducing direct current bias voltage offset of operational amplifier

Abstract

The invention relates to a circuit and a method for reducing direct current bias voltage excursion of an operational amplifier, the circuit comprises a pre-amplification circuit, the pre-amplification circuit is connected with one end of an equivalent model circuit, the other end of the equivalent model circuit is connected with a charge pump, and the charge pump is connected with the charge pump. The pre-amplification circuit comprises a pre-amplifier, a first diode (D1), a second diode (D2), a reference voltage source (Vcm), a resistor module (R) and an adjusting module (EC). The pre-amplifier is used for amplifying an output signal of the equivalent model circuit; the resistance module (R) is used for reducing nonlinear changes of equivalent resistance of the first diode (D1) and the second diode (D2) under different working conditions; the adjusting module (EC) is used for dynamically detecting the output direct-current level of the pre-amplifier and stabilizing the output direct-current level within the range of the reference voltage source (Vcm). According to the invention, the output DC voltage of the pre-amplifier can be automatically detected.

Description

Technical Field

[0001] The present invention relates to the field of operational amplifier design, and particularly to a circuit method for reducing DC bias voltage offset in an operational amplifier. Background Art

[0002] Operational amplifiers are widely used in integrated circuits to provide signal amplification for each unit module and enhance the signal driving ability. In a microelectromechanical system (MEMS) signal conditioning chip, MEMS is a passive device with weak signal driving ability. The role of the operational amplifier is to collect the output signal of MEMS and achieve two functions: pre-amplifying the signal (pre-amplify) and having adjustable gain; enhancing the signal driving ability to drive the subsequent circuit.

[0003] However, in the prior art, generally, the resistance value of the equivalent resistance in MEMS is very large, and the equivalent resistance of the diode is also very large. And with the change of the working conditions of MEMS, the value of the equivalent resistance changes by dozens to hundreds of times, resulting in a large change in the input DC voltage of the preamplifier. Similarly, under different conditions, the equivalent resistance of the diode also changes greatly, which will also cause a large change in the input DC bias voltage of the preamplifier, resulting in a large change in the output DC voltage of the preamplifier. A large change in the input DC voltage of the preamplifier will reduce the ability of the preamplifier to receive the signal of MEMS, cause a large change in the output DC voltage, affect the signal processing ability of the subsequent circuit, and reduce the overall performance of the signal conditioning chip. Summary of the Invention

[0004] The main purpose of the present invention is to provide a circuit and method for reducing DC bias voltage offset in an operational amplifier, which can automatically detect the output DC voltage of the preamplifier and stabilize the output DC voltage, thereby improving the ability of the preamplifier to receive MEMS signals.

[0005] To achieve the above object, the present invention provides a circuit for reducing DC bias voltage offset in an operational amplifier, including a preamplification circuit. One end of the preamplification circuit is connected to one end of an equivalent model circuit, and the other end of the equivalent model circuit is connected to a charge pump. The preamplification circuit includes: A preamplifier, a first diode (D1), a second diode (D2), a reference voltage source (Vcm), a resistor module (R), and an adjustment module (EC); The input terminal (Vin) of the preamplifier is respectively connected to the equivalent model circuit, one end of the first diode (D1), and one end of the second diode (D2). The output terminal (Vout) of the preamplifier is connected to the input terminal of the adjustment module (EC) for amplifying the output signal of the equivalent model circuit. One end of the resistor module (R) is respectively connected to the other end of the first diode (D1) and the other end of the second diode (D2). The other end of the resistor module (R) is connected to the output terminal (Voe) of the adjustment module for reducing the non-linear change of the equivalent resistance of the first diode (D1) and the second diode (D2) under different operating conditions. The output terminal (Voe) of the adjustment module (EC) is also connected to the reference voltage source (Vcm) for dynamically detecting the output DC level of the preamplifier and stabilizing the output DC level within the range of the reference voltage source (Vcm).

[0006] Further, the adjustment module (EC) includes an error amplifier (EA). The inverting input terminal (Vcin) of the error amplifier (EA) is connected to the output terminal (Vout) of the preamplifier. The non-inverting input terminal of the error amplifier (EA) is connected to the reference voltage source (Vcm). The output terminal (Voe) of the error amplifier (EA) is connected to the other end of the resistor module (R).

[0007] Further, the adjustment module (EC) includes a charge pump (CHP). The charge pump (CHP) is respectively connected to the output terminal (Vout) of the preamplifier and the reference voltage source (Vcm). The output terminal (Voe) of the charge pump (CHP) is connected to the other end of the resistor module (R).

[0008] Further, the resistor module (R) includes: a first field-effect transistor (SW0), a second field-effect transistor (SW1), a third field-effect transistor (SW2), a first resistor (R0), a second resistor (R1), and a third resistor (R2). The first resistor (R0), the second resistor (R1), and the third resistor (R2) are connected in series in sequence. One end of the first resistor (R0) is connected to the other ends of the first diode (D1) and the second diode (D2) respectively. The other end of the first resistor (R0) is connected to one end of the second resistor (R1). The source electrode of the first field effect transistor (SW0) is connected to the output terminal (Voe) of the regulation module (EC). The drain electrode of the first field effect transistor (SW0) is connected to one end of the second resistor. The source electrode of the second field effect transistor (SW1) is connected to the drain electrode of the first field effect transistor (SW0). The drain electrode of the second field effect transistor (SW1) is connected to one end of the third resistor. The source electrode of the third field effect transistor (SW2) is connected to the drain electrode of the second field effect transistor (SW1). The drain electrode of the third field effect transistor (SW2) is connected to one end of the third resistor (R2), the other end of the first diode (D1), and the other end of the second diode (D2) respectively.

[0009] Further, the resistor module (R) includes: a first field effect transistor (SW0), a second field effect transistor (SW1), a third field effect transistor (SW2), a fourth field effect transistor (P0), a fifth field effect transistor (P1), and a sixth field effect transistor (P2); The output terminal (Voe) of the regulation module (EC) is connected to the source electrode of the first field effect transistor (SW0) and the drain electrode of the fourth field effect transistor (P0) respectively. The drain electrode of the fifth field effect transistor (P1) is connected to the drain electrode of the first field effect transistor (SW0), the gate electrode of the fourth field effect transistor (P0), and the source electrode of the fourth field effect transistor (P0) respectively. The source electrode of the second field effect transistor (SW1) is connected to the drain electrode of the first field effect transistor (SW0). The drain electrode of the sixth field effect transistor (P2) is connected to the drain electrode of the second field effect transistor (SW1), the gate electrode of the fourth field effect transistor (P0), and the source electrode of the fourth field effect transistor (P0) respectively. The drain electrode of the third field effect transistor (SW2) is connected to the source electrode of the sixth field effect transistor (P2), the gate electrode of the sixth field effect transistor (P2), the other end of the first diode (D1), and the other end of the second diode (D2) respectively.

[0010] Further, the resistor module (R) includes: a fourth field effect transistor (P0), a fifth field effect transistor (P1), a sixth field effect transistor (P2), a first capacitor (C0), a second capacitor (C1), and a third capacitor (C2); The output terminal (Voe) of the adjustment module (EC) is connected to the drain of the fourth field effect transistor (P0). The source of the fourth field effect transistor (P0) is respectively connected to the drain of the fifth field effect transistor (P1) and one end of the first capacitor (C0). The source of the fifth field effect transistor (P1) is respectively connected to the drain of the sixth field effect transistor (P2) and one end of the second capacitor (C1). The source of the sixth field effect transistor (P2) is respectively connected to one end of the third capacitor (C2), the other end of the first diode (D1), and the other end of the second diode (D2).

[0011] The present invention also provides a method for reducing the DC bias voltage offset of an operational amplifier, which is applied to the above circuit for reducing the DC bias voltage offset of an operational amplifier. The method is characterized in that it includes: The equivalent model circuit receives the DC bias voltage provided by the charge pump. The equivalent model circuit processes the DC bias voltage and provides an input signal for the preamplifier circuit. The preamplifier circuit amplifies the input signal and outputs a DC level within a preset level range. When it is detected that the DC level exceeds the range of the reference voltage source (Vcm), the adjustment module (EC) outputs an adjustment signal and dynamically adjusts the preamplifier through the resistor module (R), the first diode (D1), and the second diode (D2), so as to stabilize the DC level output by the preamplifier within the range of the reference voltage source.

[0012] Furthermore, it also includes: By adjusting the resistance value of the resistor module (R), the non-linear changes of the first diode (D1) and the second diode (D2) are stabilized. A circuit and method for reducing the DC bias voltage offset of an operational amplifier provided by the present invention have the following beneficial effects: In the present invention, the output signal of the equivalent model circuit is amplified by the preamplifier circuit, and the adjustment module can automatically and dynamically detect the output DC level of the preamplifier and stabilize it within the range of the reference voltage source, thereby reducing the offset of the DC voltage and achieving a stable output of the DC bias voltage. The resistor module is connected between the first diode and the second diode. By reducing the non-linear changes of their equivalent resistances under different working conditions, the linear performance of the entire circuit is improved, the error and distortion are reduced, and the accuracy and stability of the operational amplifier are improved. The adjustment module dynamically detects and adjusts the output DC level of the preamplifier to keep it within the range of the reference voltage source, thereby maintaining the stability of the output signal, avoiding the adverse effects of the drift of the DC bias voltage on signal processing and transmission, and improving the ability of the preamplifier to receive MEMS signals. Description of the Drawings

[0013] Figure 1It is the first schematic diagram of a circuit for reducing the DC bias voltage offset of an operational amplifier according to the present invention; Figure 2 It is the second schematic diagram of a circuit for reducing the DC bias voltage offset of an operational amplifier according to the present invention; Figure 3 It is the third schematic diagram of a circuit for reducing the DC bias voltage offset of an operational amplifier according to the present invention; Figure 4 It is the first schematic diagram of the resistor module (R) of the circuit for reducing the DC bias voltage offset of an operational amplifier in an embodiment of the present invention; Figure 5 It is the second schematic diagram of the resistor module (R) of the circuit for reducing the DC bias voltage offset of an operational amplifier in an embodiment of the present invention; Figure 6 It is the third schematic diagram of the resistor module (R) of the circuit for reducing the DC bias voltage offset of an operational amplifier in an embodiment of the present invention.

[0014] The realization, functional features and advantages of the object of the present invention will be further described with reference to the embodiments and the accompanying drawings. Detailed implementation manners

[0015] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0016] Next, with reference to the accompanying drawings and specific implementation manners, the present invention will be further described.

[0017] Refer to Figure 1 As shown, the present invention provides a circuit for reducing the DC bias voltage offset of an operational amplifier, including a preamplifier circuit, an equivalent model circuit and a charge pump. Among them, the equivalent model circuit includes: an equivalent resistor (Rp), a first equivalent capacitor (Cp1), a second equivalent capacitor (Cp2) and a variable capacitor (Cms). Among them, the first equivalent capacitor (Cp1), the second equivalent capacitor (Cp2) and the variable capacitor (Cms) are connected in series in sequence. One end of the equivalent resistor (Rp) is connected to one end of the first equivalent capacitor (Cp1), the other end of the equivalent resistor (Rp) is connected to one end of the second equivalent capacitor (Cp2), the other end of the first equivalent capacitor (Cp1) is connected to the charge pump at the interface (VB), and the other end of the second equivalent capacitor (Cp2) is connected to the preamplifier circuit.

[0018] The preamplifier circuit includes: A pre - amplifier, a first diode (D1), a second diode (D2), a reference voltage source (Vcm), a resistor module (R), and an adjustment module (EC); The input terminal (Vin) of the pre - amplifier is respectively connected to an equivalent model circuit, one end of the first diode (D1), and one end of the second diode (D2). The output terminal (Vout) of the pre - amplifier is connected to the input terminal of the adjustment module (EC) for amplifying the output signal of the equivalent model circuit; One end of the resistor module (R) is respectively connected to the other end of the first diode (D1) and the other end of the second diode (D2). The other end of the resistor module (R) is connected to the output terminal (Voe) of the adjustment module (EC) for reducing the non - linear change of the equivalent resistance of the first diode (D1) and the second diode (D2) under different working conditions; The output terminal (Voe) of the adjustment module (EC) is also connected to the reference voltage source (Vcm) for dynamically detecting the output DC level of the pre - amplifier and stabilizing the output DC level within the range of the reference voltage source (Vcm).

[0019] A circuit for reducing the DC bias voltage offset of an operational amplifier provided by the present invention amplifies the output signal of an equivalent model circuit through a pre - amplification circuit. The adjustment module can automatically and dynamically detect the output DC level of the pre - amplifier and stabilize it within the range of the reference voltage source, thereby reducing the offset of the DC voltage and achieving a stable output DC bias voltage. The resistor module is connected between the first diode and the second diode, and by reducing the non - linear change of their equivalent resistance under different working conditions, it improves the linear performance of the entire circuit, reduces errors and distortions, and improves the accuracy and stability of the operational amplifier. The adjustment module dynamically detects and adjusts the output DC level of the pre - amplifier to keep it within the range of the reference voltage source, thereby maintaining the stability of the output signal, avoiding the adverse effects of the drift of the DC bias voltage on signal processing and transmission, and improving the ability of the pre - amplifier to receive MEMS signals.

[0020] Refer to Figure 2 As shown, in one embodiment, the adjustment module (EC) includes an error amplifier (EA); The negative input terminal (Vcin) of the error amplifier (EA) is connected to the output terminal (Vout) of the pre - amplifier. The positive input terminal of the error amplifier (EA) is connected to the reference voltage source (Vcm). The output terminal (Voe) of the error amplifier (EA) is connected to the other end of the resistor module (R). The error amplifier (EA) is also respectively connected to the positive power supply (VP) and the negative power supply (VN).

[0021] In this embodiment, by setting the adjustment module (EC) as an error amplifier (EA), the error amplifier (EA) accurately detects the signal output by the pre-amplifier module, and based on the detection result, transmits the feedback signal to the resistor module (R). The pre-amplifier module is automatically adjusted by the resistor module (R), thereby improving the amplification accuracy and stability of the circuit. By connecting the non-inverting input terminal of the error amplifier (EA) to the reference voltage source (Vcm), the DC level output by the pre-amplifier can be dynamically detected, and the output DC level is stabilized within the range of the reference voltage source, thereby reducing the DC bias voltage offset. At the same time, the error amplifier (EA) can reduce the non-linear variation in the circuit, better compensate for the error in the output signal of the pre-amplifier (pre-amplifier), and reduce the influence of the error on the resistor module, thereby improving the linear performance of the circuit. At the same time, the error amplifier (EA) operates between the positive power supply (VP) and the negative power supply (VN), has a large output swing and strong loop regulation ability, and can adapt to the changes of the equivalent resistor (Rp) and the first diode (D1) and the second diode (D2), and the circuit robustness is significantly enhanced.

[0022] Refer to Figure 3 As shown, in one embodiment, the adjustment module (EC) includes a charge pump (CHP); The charge pump (CHP) is respectively connected to the output terminal (Vout) of the pre-amplifier and the reference voltage source (Vcm), and the output terminal (Voe) of the charge pump (CHP) is connected to the other end of the resistor module (R).

[0023] In this embodiment, by setting the adjustment module (EC) as a charge pump (CHP), the charge pump (CHP) accurately detects the signal output by the pre-amplifier module, and based on the detection result, transmits the feedback signal to the resistor module (R). The pre-amplifier module (pre-amplifier) is automatically adjusted by the resistor module (R), thereby improving the amplification accuracy and stability of the circuit. By connecting the charge pump (CHP) to the reference voltage source (Vcm), the DC level output by the pre-amplifier can be dynamically detected, and the output DC level is stabilized within the range of the reference voltage source, thereby reducing the DC bias voltage offset. At the same time, the charge pump (CHP) can reduce the non-linear variation in the circuit, better compensate for the error in the output signal of the pre-amplifier (pre-amplifier), and reduce the influence of the error on the resistor module, thereby improving the linear performance of the circuit.

[0024] Refer to Figure 4As shown, in one embodiment, the resistor module (R) includes: a first field-effect transistor (SW0), a second field-effect transistor (SW1), a third field-effect transistor (SW2), a first resistor (R0), a second resistor (R1), a third resistor (R2), a first control signal (S0) corresponding to the first field-effect transistor (SW0), a second control signal (S1) corresponding to the second field-effect transistor (SW1), and a third control signal (S3) corresponding to the third field-effect transistor (SW2); The first resistor (R0), the second resistor (R1), and the third resistor (R2) are connected in series in sequence. One end of the first resistor (R0) is connected to the other ends of the first diode (D1) and the second diode (D2) respectively. The other end of the first resistor (R0) is connected to one end of the second resistor (R1). The source of the first field-effect transistor (SW0) is connected to the output terminal (Voe) of the regulation module (EC). The drain of the first field-effect transistor (SW0) is connected to one end of the second resistor. The source of the second field-effect transistor (SW1) is connected to the drain of the first field-effect transistor (SW0). The drain of the second field-effect transistor (SW1) is connected to one end of the third resistor. The source of the third field-effect transistor (SW2) is connected to the drain of the second field-effect transistor (SW1). The drain of the third field-effect transistor (SW2) is connected to one end of the third resistor (R2), the other end of the first diode (D1), and the other end of the second diode (D2).

[0025] In this embodiment, by connecting the first resistor (R0), the second resistor (R1), and the third resistor (R2) in series in sequence, it can be equivalent to a large resistor. By controlling the conduction states of the field-effect transistors (SW0, SW1, SW2) through the corresponding three control signals (S0, S1, and S2), the resistance value of this large resistor can be dynamically adjusted. The conduction states of different field-effect transistors can change the series path of the resistors, thereby achieving different resistance values, and thus the gain and working state of the circuit can be adjusted according to needs. By adjusting the resistance value of the large resistor formed by the equivalent of the three resistors, the characteristics of the circuit, such as the amplification factor and frequency response, can be precisely controlled. This helps to optimize the performance of the circuit and make it more in line with the design requirements. By using the combination of field-effect transistors and three resistors connected in series, the non-linear changes in the circuit and the influence of the non-linear changes in the resistance value on the circuit performance are reduced, and the linear performance and stability of the circuit are improved.

[0026] Refer to Figure 5As shown, in one embodiment, the resistance module (R) includes: a first field-effect transistor (SW0), a second field-effect transistor (SW1), a third field-effect transistor (SW2), a fourth field-effect transistor (P0), a fifth field-effect transistor (P1), a sixth field-effect transistor (P2), a first control signal (S0) corresponding to the first field-effect transistor (SW0), a second control signal (S1) corresponding to the second field-effect transistor (SW1), and a third control signal (S3) corresponding to the third field-effect transistor (SW2); The output terminal (Voe) of the adjustment module (EC) is respectively connected to the source of the first field-effect transistor (SW0) and the drain of the fourth field-effect transistor (P0). The drain of the fifth field-effect transistor (P1) is respectively connected to the drain of the first field-effect transistor (SW0), the gate of the fourth field-effect transistor (P0), and the source of the fourth field-effect transistor (P0). The source of the second field-effect transistor (SW1) is connected to the drain of the first field-effect transistor (SW0). The drain of the sixth field-effect transistor (P2) is respectively connected to the drain of the second field-effect transistor (SW1), the gate of the fourth field-effect transistor (P0), and the source of the fourth field-effect transistor (P0). The drain of the third field-effect transistor (SW2) is respectively connected to the source of the sixth field-effect transistor (P2), the gate of the sixth field-effect transistor (P2), the other end of the first diode (D1), and the other end of the second diode (D2).

[0027] In this embodiment, the three field-effect transistors (P0, P1, P2) are connected in series and equivalent to three resistors in series. The three field-effect transistors (SW0, SW1, SW2) act as PMOS switches and replace pure resistors, enabling the conduction states of the three PMOS field-effect transistors (SW0, SW1, SW2) and the three field-effect transistors (P0, P1, P2) to be controlled by the three corresponding control signals (S0, S1, and S2), achieving different resistance values. Thus, the gain and working state of the circuit can be adjusted as needed, and the characteristics of the circuit, such as amplification factor, frequency response, etc., can be precisely controlled, which helps to optimize the performance of the circuit and make it more in line with the design requirements. And through the combination of field-effect transistors and diodes, multi-level control can be achieved, and more complex circuit adjustment and control functions can be realized through the connection between different field-effect transistors and diodes.

[0028] Refer to Figure 6As shown, in one embodiment, the resistor module (R) includes: a fourth field-effect transistor (P0), a fifth field-effect transistor (P1), a sixth field-effect transistor (P2), a first capacitor (C0), a second capacitor (C1), a third capacitor (C2), a fourth control signal (CK1) corresponding to the fourth field-effect transistor (P0), a fifth control signal (CK2) corresponding to the fifth field-effect transistor (P1), and a sixth control signal (CK3) corresponding to the sixth field-effect transistor (P2); The output terminal (Voe) of the adjustment module (EC) is connected to the drain of the fourth field-effect transistor (P0). The source of the fourth field-effect transistor (P0) is respectively connected to the drain of the fifth field-effect transistor (P1) and one end of the first capacitor (C0). The source of the fifth field-effect transistor (P1) is respectively connected to the drain of the sixth field-effect transistor (P2) and one end of the second capacitor (C1). The source of the sixth field-effect transistor (P2) is respectively connected to one end of the third capacitor (C2), the other end of the first diode (D1), and the other end of the second diode (D2).

[0029] In this embodiment, three field-effect transistors (P0, P1, P2) are used as PMOS switches, and three capacitors (C0, C1, C2) are used as switched capacitors to achieve a resistance equivalent to that of the resistor module (R). Three control signals (CK1, CK2, CK3) are used as clock signals for controlling the PMOS switches. By controlling the frequencies of the three control signals (CK1, CK2, CK3), the conduction states of the field-effect transistors (P0, P1, P2) are controlled to dynamically adjust the resistance value of the equivalent resistor. The conduction states of different field-effect transistors can change the series path of the resistor module, thereby achieving different resistance values, enabling the gain and operating state of the circuit to be adjusted as needed. Through the three capacitors (C0, C1, C2), the high-frequency characteristics of the circuit are optimized. The capacitors are connected in parallel with the resistor module to form a filter, which can filter out high-frequency noise and interference, improve the stability and anti-interference ability of the circuit, and at the same time reduce the number and complexity of components in the circuit, lowering costs and power consumption.

[0030] The present invention also provides a method for reducing the DC bias voltage offset of an operational amplifier, which is applied to a circuit for reducing the DC bias voltage offset of an operational amplifier. The method includes: The equivalent model circuit receives the DC bias voltage provided by the charge pump. The equivalent model circuit processes the DC bias voltage and provides an input signal to the preamplifier circuit. The preamplifier circuit amplifies the input signal and outputs a DC level within a preset level range. The DC level output includes a common-mode level. In the preamplifier circuit, the adjustment module (EC) detects the DC level. When it detects that the DC level exceeds the range of the reference voltage source (Vcm), the adjustment module (EC) outputs an adjustment signal and dynamically adjusts the preamplifier through the resistor module (R), the first diode (D1), and the second diode (D2), stabilizing the DC level output by the preamplifier within the range of the reference voltage source.

[0031] A method for reducing the DC bias voltage offset of an operational amplifier provided by the present invention. The equivalent model circuit receives the DC bias voltage provided by the charge pump. The equivalent model circuit processes the DC bias voltage and provides an input signal to the preamplifier circuit. The preamplifier circuit amplifies the input signal and outputs a DC level within a preset level range. The adjustment module detects the output common-mode level. When it detects that the DC level exceeds the range of the reference voltage source, the adjustment module outputs an adjustment signal and dynamically adjusts the preamplifier through the resistor module, the first diode, and the second diode, stabilizing the DC level output by the preamplifier within the range of the reference voltage source, thereby reducing the DC bias voltage offset. By monitoring the working state of the circuit, when the DC level exceeds the range of the reference voltage source, the adjustment module will issue an adjustment signal to adjust the preamplifier through the resistor module and the diode, enabling the circuit to perform dynamic adjustment according to the actual situation and keeping the output DC level stable. By stabilizing the output DC level of the preamplifier within the range of the reference voltage source, the stability and accuracy of the circuit are improved, the error and drift of the DC bias voltage offset are reduced, making the operational amplifier more reliable and precise during operation, and improving the ability of the preamplifier to receive MEMS signals.

[0032] In one embodiment, it further includes: By adjusting the resistance value of the resistor module (R), the non-linear changes of the first diode (D1) and the second diode (D2) are stabilized.

[0033] In this embodiment, by adjusting the resistance value of the resistor module, the resistor module compensates for the non-linear changes under different working conditions, thereby reducing the DC bias voltage offset and reducing the influence of the non-linear changes, making the output DC level of the circuit more stable and accurate.

[0034] The above are only the preferred embodiments of the present invention, and do not limit the patent scope of the present invention accordingly. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present invention, or directly or indirectly applied in other related technical fields, shall be similarly included in the patent protection scope of the present invention.

Claims

1. A circuit for reducing the DC bias voltage offset of an operational amplifier, characterized in that, It includes a preamplifier circuit, the preamplifier circuit is connected to one end of an equivalent model circuit, and the other end of the equivalent model circuit is connected to a charge pump. The preamplifier circuit includes: A preamplifier, a first diode (D1), a second diode (D2), a reference voltage source (Vcm), a resistor module (R), and an adjustment module (EC); The input terminal (Vin) of the preamplifier is respectively connected to the equivalent model circuit, one end of the first diode (D1), and one end of the second diode (D2). The output terminal (Vout) of the preamplifier is connected to the input terminal of the adjustment module (EC) for amplifying the output signal of the equivalent model circuit; One end of the resistor module (R) is respectively connected to the other end of the first diode (D1) and the other end of the second diode (D2). The other end of the resistor module (R) is connected to the output terminal (Voe) of the adjustment module for reducing the non-linear change of the equivalent resistance of the first diode (D1) and the second diode (D2) under different working conditions; The output terminal (Voe) of the adjustment module (EC) is also connected to the reference voltage source (Vcm) for dynamically detecting the output DC level of the preamplifier and stabilizing the output DC level within the range of the reference voltage source (Vcm).

2. The circuit for reducing the DC bias voltage offset of an operational amplifier according to claim 1, wherein The adjustment module (EC) includes an error amplifier (EA); The negative-phase input terminal (Vcin) of the error amplifier (EA) is connected to the output terminal (Vout) of the preamplifier. The positive-phase input terminal of the error amplifier (EA) is connected to the reference voltage source (Vcm). The output terminal (Voe) of the error amplifier (EA) is connected to the other end of the resistor module (R).

3. The circuit for reducing the DC bias voltage offset of an operational amplifier according to claim 1, wherein The adjustment module (EC) includes a charge pump (CHP); The charge pump (CHP) is respectively connected to the output terminal (Vout) of the preamplifier and the reference voltage source (Vcm). The output terminal (Voe) of the charge pump (CHP) is connected to the other end of the resistor module (R).

4. The circuit for reducing the DC bias voltage offset of an operational amplifier according to claim 1, wherein The resistor module (R) includes: a first field-effect transistor (SW0), a second field-effect transistor (SW1), a third field-effect transistor (SW2), a first resistor (R0), a second resistor (R1), and a third resistor (R2); The first resistor (R0), the second resistor (R1), and the third resistor (R2) are connected in series in sequence. One end of the first resistor (R0) is connected to the other ends of the first diode (D1) and the second diode (D2) respectively. The other end of the first resistor (R0) is connected to one end of the second resistor (R1). The source of the first field-effect transistor (SW0) is connected to the output terminal (Voe) of the regulation module (EC). The drain of the first field-effect transistor (SW0) is connected to one end of the second resistor. The source of the second field-effect transistor (SW1) is connected to the drain of the first field-effect transistor (SW0). The drain of the second field-effect transistor (SW1) is connected to one end of the third resistor. The source of the third field-effect transistor (SW2) is connected to the drain of the second field-effect transistor (SW1). The drain of the third field-effect transistor (SW2) is connected to one end of the third resistor (R2), the other end of the first diode (D1), and the other end of the second diode (D2) respectively.

5. The circuit for reducing the DC bias voltage offset of an operational amplifier according to claim 1, wherein The resistor module (R) includes: a first field-effect transistor (SW0), a second field-effect transistor (SW1), a third field-effect transistor (SW2), a fourth field-effect transistor (P0), a fifth field-effect transistor (P1), and a sixth field-effect transistor (P2); The output terminal (Voe) of the regulation module (EC) is connected to the source of the first field-effect transistor (SW0) and the drain of the fourth field-effect transistor (P0) respectively. The drain of the fifth field-effect transistor (P1) is connected to the drain of the first field-effect transistor (SW0), the gate of the fourth field-effect transistor (P0), and the source of the fourth field-effect transistor (P0) respectively. The source of the second field-effect transistor (SW1) is connected to the drain of the first field-effect transistor (SW0). The drain of the sixth field-effect transistor (P2) is connected to the drain of the second field-effect transistor (SW1), the gate of the fourth field-effect transistor (P0), and the source of the fourth field-effect transistor (P0) respectively. The drain of the third field-effect transistor (SW2) is connected to the source of the sixth field-effect transistor (P2), the gate of the sixth field-effect transistor (P2), the other end of the first diode (D1), and the other end of the second diode (D2) respectively.

6. A circuit for reducing the DC bias voltage offset of an operational amplifier according to claim 1, characterized in that, The resistor module (R) includes: a fourth field-effect transistor (P0), a fifth field-effect transistor (P1), a sixth field-effect transistor (P2), a first capacitor (C0), a second capacitor (C1), and a third capacitor (C2); The output terminal (Voe) of the adjustment module (EC) is connected to the drain of the fourth field effect transistor (P0). The source of the fourth field effect transistor (P0) is respectively connected to the drain of the fifth field effect transistor (P1) and one end of the first capacitor (C0). The source of the fifth field effect transistor (P1) is respectively connected to the drain of the sixth field effect transistor (P2) and one end of the second capacitor (C1). The source of the sixth field effect transistor (P2) is respectively connected to one end of the third capacitor (C2), the other end of the first diode (D1), and the other end of the second diode (D2).

7. A method for reducing the DC bias voltage offset of an operational amplifier, applied to the circuit for reducing the DC bias voltage offset of an operational amplifier in claim 1, characterized in that, The method includes: The equivalent model circuit receives the DC bias voltage provided by the charge pump. The equivalent model circuit processes the DC bias voltage and provides an input signal for the preamplifier circuit. The preamplifier circuit amplifies the input signal and outputs a DC level within a preset level range. The adjustment module (EC) in the preamplifier circuit detects the DC level. When it is detected that the DC level exceeds the range of the reference voltage source (Vcm), the adjustment module (EC) outputs an adjustment signal and dynamically adjusts the preamplifier through the resistance module (R), the first diode (D1), and the second diode (D2), so as to stabilize the DC level output by the preamplifier within the range of the reference voltage source.

8. The method for reducing the DC bias voltage offset of an operational amplifier according to claim 7, wherein It further includes: By adjusting the resistance value of the resistance module (R), the non-linear changes of the first diode (D1) and the second diode (D2) are stabilized.

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