Biasing circuit and power amplification circuit

Abstract

The application provides a bias circuit and a power amplification circuit, wherein the bias circuit comprises a first active device, a second active device, a first capacitor, a third active device, a second capacitor and a feedback circuit; the feedback circuit is used for reducing the impedance of the bias circuit. The bias circuit in the application can improve the linearity of the power amplification circuit under a large-bandwidth modulation signal when the bias circuit is applied to a power amplifier, and the efficiency of the power amplification circuit is not reduced.

Description

Technical Field

[0001] This invention relates to the field of wireless communication technology, and in particular to a bias circuit and a power amplifier circuit. Background Technology

[0002] like Figure 1 The diagram shown is a schematic of a power amplifier provided by the prior art. The power amplifier 100 in the prior art mainly includes an input matching module 101, a driver stage module 102, an interstage matching module 103, an amplification stage module 104, an output matching module 105 connected in sequence, and a driver stage bias module 106 and an amplification stage bias module 107 connected to the driver stage module 102 and the amplification stage module 104, respectively. At the same time, the power amplifier 100 also has an input resistor R1 connected to the input terminal of the input matching module 101 and an output resistor R2 connected to the output terminal of the output matching module 105.

[0003] The input matching module 101 mainly converts the external 50 ohms into the input impedance of the input stage, the inter-stage matching module 103 is used to improve the driving capability of the driver stage module 102, the output matching module 105 is used to convert the optimal output impedance of the power amplifier 100 into a 50-ohm impedance, and the driver stage bias module 106 and the amplification stage bias module 107 are mainly used to provide a suitable DC operating point for the power amplifier 100.

[0004] With the development of communication protocols, the debugging bandwidth of power amplifier 100 has increased from 40MHz to 100MHz. It mainly considers the fundamental frequency impedance. Therefore, the linearity under large bandwidth modulation signals will deteriorate sharply due to the memory effect of power amplifier 100.

[0005] In order to improve the linearity of power amplifier 100 under wide bandwidth modulation signals, the common method in the prior art is to increase the saturation power of power amplifier 100. Although this method can improve the linearity of power amplifier 100 under wide bandwidth modulation signals, it will also bring about the problem of low efficiency. Summary of the Invention

[0006] To address the shortcomings of the prior art, this invention proposes a bias circuit and a power amplifier circuit to solve the problem that the existing methods used to improve the linearity of power amplifiers result in low efficiency.

[0007] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0008] In a first aspect, the present invention provides a bias circuit, which includes a first active device, a second active device, a first capacitor, a third active device, a second capacitor, and a feedback circuit.

[0009] The input end of the first active device is used to access a power supply;

[0010] The input end of the second active device is connected to the first output end of the first active device, and the first output end of the second active device is grounded.

[0011] The first end of the first capacitor is connected to the second output end of the first active device, and the second end of the first capacitor is grounded.

[0012] The first input end of the third active device is connected to the first end of the first capacitor, the second input end of the third active device is used to access a supply voltage, and the output end of the third active device is used to output a bias signal; the first active device, the second active device, and the third active device together constitute a current mirror circuit, which is used to output a stable bias current or bias voltage according to the accessed power supply.

[0013] The first end of the second capacitor is connected to the second output end of the second active device, and the second end of the second capacitor is grounded.

[0014] The input end of the feedback circuit is connected to the first end of the second capacitor, the output end of the feedback circuit is connected to the output end of the third active device, and the feedback circuit is used to reduce the impedance of the bias circuit.

[0015] Preferably, the first active device is a first triode, the second active device is a second triode, and the third active device is a third triode.

[0016] The collector of the first triode serves as the input end of the first active device, the emitter of the first triode serves as the first output end of the first active device, and the base of the first triode serves as the second output end of the first active device; the collector of the first triode is connected to the base of the first triode.

[0017] The collector of the second triode serves as the input end of the second active device, the emitter of the second triode serves as the first output end of the second active device, and the base of the second triode serves as the second output end of the second triode.

[0018] The base of the third triode serves as the first input end of the third active device, the collector of the third triode serves as the second input end of the third active device, and the emitter of the third triode serves as the output end of the third triode.

[0019] Preferably, the first active device is a first triode, the second active device is a second triode, and the third active device is a third triode.

[0020] the collector of the first triode as an input terminal of the first active device, the emitter of the first triode as a first output terminal of the first active device, and the base of the first triode as a second output terminal of the first active device; the collector of the first triode is connected to the base of the first triode;

[0021] the collector of the second triode as an input terminal of the second active device, the emitter of the second triode as a first output terminal of the second active device, and the base of the second triode as a second output terminal of the second triode; the collector of the second triode is connected to the base of the second triode;

[0022] the base of the third triode as a first input terminal of the third active device, the collector of the third triode as a second input terminal of the third active device, and the emitter of the third triode as an output terminal of the third triode.

[0023] Preferably, the first active device is a first diode, the second active device is a second triode, and the third active device is a third triode.

[0024] the anode of the diode as an input terminal of the first active device and a second output terminal of the first active device, and the cathode of the diode as a first output terminal of the first active device;

[0025] the collector of the second triode as an input terminal of the second active device, the emitter of the second triode as a first output terminal of the second active device, and the base of the second triode as a second output terminal of the second triode;

[0026] the base of the third triode as a first input terminal of the third active device, the collector of the third triode as a second input terminal of the third active device, and the emitter of the third triode as an output terminal of the third triode.

[0027] Preferably, the first active device is a first diode, the second active device is a second triode, and the third active device is a third triode.

[0028] the anode of the diode as an input terminal of the first active device and a second output terminal of the first active device, and the cathode of the diode as a first output terminal of the first active device;

[0029] The collector of the second triode is the input terminal of the second active device, the emitter of the second triode is the first output terminal of the second active device, and the base of the second triode is the second output terminal of the second triode; the collector of the second triode is connected to the base of the second triode.

[0030] The base of the third triode is the first input terminal of the third active device, the collector of the third triode is the second input terminal of the third active device, and the emitter of the third triode is the output terminal of the third triode.

[0031] Preferably, the first active device is a first diode, the second active device is a second diode, and the third active device is a third triode.

[0032] The anode of the diode is the input terminal of the first active device and the second output terminal of the first active device, and the cathode of the diode is the first output terminal of the first active device.

[0033] The anode of the second diode is the input terminal of the second active device and the second output terminal of the second active device, and the cathode of the second diode is the first output terminal of the second active device.

[0034] The base of the third triode is the first input terminal of the third active device, the collector of the third triode is the second input terminal of the third active device, and the emitter of the third triode is the output terminal of the third triode.

[0035] Preferably, the feedback circuit includes a first resistor; the first end of the first resistor is the input terminal of the feedback circuit, and the second end of the first resistor is the output terminal of the feedback circuit.

[0036] Preferably, the feedback circuit further includes a third capacitor; the first end of the third capacitor is connected to the first end of the first resistor, and the second end of the third capacitor is connected to the second end of the first resistor.

[0037] Preferably, the feedback circuit further includes an inductor; the first end of the inductor is connected to the first end of the third capacitor, and the second end of the inductor is connected to the second end of the third capacitor.

[0038] Preferably, the feedback circuit includes an inductor; the first end of the inductor is connected to the first end of the first resistor, and the second end of the inductor is connected to the second end of the first resistor.

[0039] In a second aspect, the present application provides a power amplifier circuit, which comprises an input matching circuit, a driver stage circuit, a first bias circuit, an inter-stage matching circuit, an amplification stage circuit, a second bias circuit and an output matching circuit; the first bias circuit and the second bias circuit are both the bias circuit as described above.

[0040] An input end of the input matching circuit is configured to receive a radio frequency signal.

[0041] A first input end of the driver stage circuit is connected to an output end of the input matching circuit.

[0042] An output end of the first bias circuit is connected to a second input end of the driver stage circuit.

[0043] An input end of the inter-stage matching circuit is connected to an output end of the driver stage circuit.

[0044] A first input end of the amplification stage circuit is connected to an output end of the inter-stage matching circuit.

[0045] An output end of the second bias circuit is connected to a second input end of the amplification stage circuit.

[0046] An input end of the output matching circuit is connected to an output end of the amplification stage circuit, and an output end of the output matching circuit is configured to output a radio frequency signal.

[0047] Compared with the prior art, the bias circuit in the present application improves the linearity of the power amplifier circuit under a large bandwidth modulation signal without reducing the efficiency of the power amplifier circuit by designing a first active device, a second active device, a first capacitor, a third active device, a second capacitor and a feedback circuit, and limiting the connection mode of each device, and limiting the feedback circuit to reduce the impedance of the bias circuit. BRIEF DESCRIPTION OF DRAWINGS

[0048] The present application will be described in detail below with reference to the accompanying drawings. The above and other aspects of the present application will become more apparent and more readily appreciated by referring to the following detailed description, taken in conjunction with the accompanying drawings, in which:

[0049] Figure 1 A schematic diagram of a power amplifier provided by the prior art;

[0050] Figure 2 A circuit diagram of the bias circuit provided by the first embodiment of the present application, which comprises a first feedback circuit;

[0051] Figure 3 A circuit diagram of the bias circuit provided by the second embodiment of the present application, which comprises a first feedback circuit;

[0052] Figure 4 The circuit diagram of the bias circuit provided for the embodiment three of the present application, which includes the first feedback circuit;

[0053] Figure 5 The circuit diagram of the bias circuit provided for the embodiment four of the present application, which includes the first feedback circuit;

[0054] Figure 6 The circuit diagram of the bias circuit provided for the embodiment five of the present application, which includes the first feedback circuit;

[0055] Figure 7 The circuit diagram of the second feedback circuit in the bias circuit provided for the embodiments one to five of the present application;

[0056] Figure 8 The circuit diagram of the third feedback circuit in the bias circuit provided for the embodiments one to five of the present application;

[0057] Figure 9 The circuit diagram of the fourth feedback circuit in the bias circuit provided for the embodiments one to five of the present application;

[0058] Figure 10 The baseband impedance simulation diagram of the bias circuit provided for the embodiment one of the present application;

[0059] Figure 11 The schematic diagram of the power amplification circuit provided for the embodiment six of the present application. DETAILED DESCRIPTION

[0060] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application; the description and claims herein and the above description of drawings herein utilize terms such as "including" and "having" and variations thereof that are intended to be broad and encompass the terms "consisting of" and "consisting essentially of." The terms "first," "second," and the like, as used herein do not denote any order, quantity, or importance, but rather are used to distinguish one element from another.

[0061] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase "in an embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily all directed to the same embodiments. Those of skill in the art will recognize, upon careful reading of the specification, that embodiments described herein can be readily combined with other embodiments.

[0062] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0063] Example 1

[0064] This invention provides a bias circuit 200, combined with Figure 2 , Figures 7-10 As shown, it includes a first active device H1, a second active device H2, a first capacitor C1, a third active device H3, a second capacitor C2, and a feedback circuit 201.

[0065] The input terminal of the first active device H1 is used to connect to the power supply.

[0066] The input terminal of the second active device H2 is connected to the first output terminal of the first active device H1, and the first output terminal of the second active device H2 is grounded.

[0067] The first terminal of the first capacitor C1 is connected to the second output terminal of the first active device H1, and the second terminal of the first capacitor C1 is grounded.

[0068] The first input terminal of the third active device H3 is connected to the first terminal of the first capacitor C1, the second input terminal of the third active device H3 is used to connect to the power supply voltage VBAT, and the output terminal of the third active device H3 is used to output the bias signal.

[0069] The first terminal of the second capacitor C2 is connected to the second output terminal of the second active device H2, and the second terminal of the second capacitor C2 is grounded.

[0070] The input terminal of the feedback circuit 201 is connected to the first terminal of the second capacitor C2, and the output terminal of the feedback circuit 201 is connected to the output terminal of the third active device H3. The feedback circuit 201 is used to reduce the impedance of the bias circuit 200.

[0071] When an external power supply inputs a current Iin to the bias circuit 200, i.e., the first active device H1 is used to input the current Iin, the output bias signal is the bias current Iout, i.e., the output terminal of the third active device H3 is used to output the bias current Iout; when an external power supply inputs a voltage Vin to the bias circuit 200, i.e., the first active device H1 is used to input the voltage Vin, the output bias signal is the bias voltage Vout, i.e., the output terminal of the third active device H3 is used to output the bias voltage Vout.

[0072] In the bias circuit 200 of the embodiment, the first active device H1, the second active device H2 and the third active device H3 form a current mirror circuit for outputting or providing a stable bias current Iout or bias voltage Vout according to the accessed power supply; the first capacitor C1 and the second capacitor C2 serve as radio frequency filtering capacitors for providing a radio frequency ground path so that the radio frequency signal does not affect the first active device H1 and the second active device H2 of the direct current bias to stabilize the direct current operating point; the existence of the feedback circuit 201 can reduce the impedance of the bias circuit 200, i.e. the baseband impedance and harmonic impedance of the bias circuit 200, so that when the bias circuit 200 is applied to a power amplifier circuit, the baseband impedance and harmonic impedance of the bias signal input end of the drive stage circuit and the power stage circuit can be reduced, thereby improving the linearity of the power amplifier circuit under a large bandwidth modulation signal and without reducing the efficiency of the power amplifier circuit.

[0073] The impedance relationship of the bias circuit 200 in the embodiment is as follows:

[0074] ;

[0075] Among them, Z Z is the impedance of the bias circuit 200; g m2 gm2 is the transconductance of the second active device H2; ω ω is the angular frequency; C be2 Cbe2 is the be junction parasitic capacitance of the second active device H2, and the be junction is the junction between the base and the emitter of the corresponding transistor; g m3 gm3 is the transconductance of the third active device H3; C be3 Cbe3 is the be junction parasitic capacitance of the third active device H3; β A is the current amplification factor of the second active device H2; C 1 is the capacitance value of the first capacitor C1.

[0076] If only the baseband impedance is considered, the baseband impedance frequency is relatively low, so some parameters of the parasitic capacitance can be removed, and the above impedance relationship can be simplified as:

[0077] ;

[0078] Through the derivation of the simplified impedance relationship, it can be obtained that the baseband impedance is very low and close to short circuit.

[0079] For example, Figure 10As shown in the figure, the horizontal coordinate is the frequency of 10.00 MHz to 100.00 MHz, and the vertical coordinate is the baseband impedance of the bias circuit 200; the frequency freq of the m1 point is 10.00 MHz, R.S(1,1) is 0.55 / 178.578; the baseband impedance is 6.332+j0.610.

[0080] In this embodiment, as shown in the figure, the first active device H1 is a first triode, the second active device H2 is a second triode, and the third active device H3 is a third triode. Figure 2

[0081] The collector of the first triode is the input terminal of the first active device H1, the emitter of the first triode is the first output terminal of the first active device H1, and the base of the first triode is the second output terminal of the first active device H1; the collector of the first triode is connected to the base of the first triode.

[0082] The collector of the second triode is the input terminal of the second active device H2, the emitter of the second triode is the first output terminal of the second active device H2, and the base of the second triode is the second output terminal of the second triode.

[0083] The base of the third triode is the first input terminal of the third active device H3, the collector of the third triode is the second input terminal of the third active device H3, and the emitter of the third triode is the output terminal of the third triode.

[0084] In this embodiment, as shown in the figure, the feedback circuit 201 includes a first resistor R1; the first end of the first resistor R1 is the input terminal of the feedback circuit 201, and the second end of the first resistor R1 is the output terminal of the feedback circuit 201. Figures 2-6 As a second optional embodiment of the feedback circuit 201, as shown in the figure, on the basis of the first optional embodiment, the feedback circuit 201 further includes a third capacitor C3; the first end of the third capacitor C3 is connected to the first end of the first resistor R1, and the second end of the third capacitor C3 is connected to the second end of the first resistor R1.

[0085] Figure 7 As a third optional embodiment of the feedback circuit 201, as shown in the figure, on the basis of the second optional embodiment, the feedback circuit 201 further includes an inductor L; the first end of the inductor L is connected to the first end of the third capacitor C3, and the second end of the inductor L is connected to the second end of the third capacitor C3.

[0086] As a fourth optional embodiment of the feedback circuit 201, as shown in the figure, on the basis of the third optional embodiment, the feedback circuit 201 further includes a fourth capacitor C4; the first end of the fourth capacitor C4 is connected to the first end of the inductor L, and the second end of the fourth capacitor C4 is connected to the second end of the inductor L. Figure 8

[0087] As a fourth optional embodiment of the feedback circuit 201, as shown in the figure, on the basis of the third optional embodiment, the feedback circuit 201 further includes a fourth capacitor C4; the first end of the fourth capacitor C4 is connected to the first end of the inductor L, and the second end of the fourth capacitor C4 is connected to the second end of the inductor L. Figure 9 ​​​As shown, on the basis of the first alternative embodiment, the feedback circuit 201 comprises an inductor L; a first end of the inductor L is connected to a first end of the first resistor R1, and a second end of the inductor L is connected to a second end of the first resistor R1.

[0088] The feedback circuit 201 is selected according to different frequency bands and required harmonic impedances, and any one of the first alternative embodiment, the second alternative embodiment, the third alternative embodiment and the fourth alternative embodiment can be selected.

[0089] Compared with the prior art, the bias circuit 200 in the application is designed by the first active device H1, the second active device H2, the first capacitor C1, the third active device H3, the second capacitor C2 and the feedback circuit 201, and the connection mode of each device is limited, and the feedback circuit 201 is also limited to reduce the impedance of the bias circuit 200. Thus, when the bias circuit 200 is applied to the power amplification circuit, the linearity of the power amplification circuit under a large bandwidth modulation signal can be improved, and the efficiency of the power amplification circuit will not be reduced.

[0090] Embodiment two

[0091] The bias circuit 300 in the embodiment is different from the bias circuit 200 in the embodiment one, as shown in the figure, Figure 3 The collector of the second triode is also connected to the base of the second triode.

[0092] Embodiment three

[0093] The bias circuit 400 in the embodiment is different from the bias circuit 200 in the embodiment one, as shown in the figure, Figure 4 The first active device H41 is a first diode, the second active device H2 is also a second triode, and the third active device H3 is also a third triode.

[0094] The anode of the diode simultaneously serves as the input end of the first active device H41 and the second output end of the first active device H41, and the cathode of the diode serves as the first output end of the first active device H41.

[0095] The collector of the second triode serves as the input end of the second active device H2, the emitter of the second triode serves as the first output end of the second active device H2, and the base of the second triode serves as the second output end of the second triode.

[0096] The base of the third triode serves as the first input end of the third active device H3, the collector of the third triode serves as the second input end of the third active device H3, and the emitter of the third triode serves as the output end of the third triode.

[0097] Embodiment four

[0098] The bias circuit 500 in this embodiment differs from the bias circuit 400 in Embodiment 3 in that, for example... Figure 5 As shown, the collector of the second transistor is also connected to the base of the second transistor.

[0099] Example 5

[0100] The bias circuit 600 in this embodiment differs from the bias circuit 200 in Embodiment 3 in that, for example... Figure 6 As shown, the first active device H61 is the first diode, the second active device H62 is the second diode, and the third active device H3 is also the third transistor.

[0101] The positive terminal of the diode serves as both the input terminal and the second output terminal of the first active device H61, while the negative terminal of the diode serves as the first output terminal of the first active device H61.

[0102] The positive terminal of the second diode serves as both the input terminal and the second output terminal of the second active device H62, while the negative terminal of the second diode serves as the first output terminal of the second active device H62.

[0103] The base of the third transistor serves as the first input terminal of the third active device H3, the collector of the third transistor serves as the second input terminal of the third active device H3, and the emitter of the third transistor serves as the output terminal of the third transistor.

[0104] Example 6

[0105] This invention provides a power amplifier circuit 700, combined with... Figure 11 As shown, it includes an input matching circuit 701, a driver stage circuit 702, a first bias circuit 703, an inter-stage matching circuit 704, an amplifier stage circuit 705, a second bias circuit 706, and an output matching circuit 707; the first bias circuit 703 and the second bias circuit 706 are both bias circuits of any one of the above embodiments one to five.

[0106] The input terminal of the input matching circuit 701 is used to receive radio frequency signals.

[0107] The first input terminal of the driver stage circuit 702 is connected to the output terminal of the input matching circuit 701.

[0108] The output of the first bias circuit 703 is connected to the second input of the driver stage circuit 702.

[0109] The input of the interstage matching circuit 704 is connected to the output of the driver stage circuit 702.

[0110] The first input terminal of the amplifier stage circuit 705 is connected to the output terminal of the interstage matching circuit 704.

[0111] The output end of the second bias circuit 706 is connected to the second input end of the amplification stage circuit 705.

[0112] The input end of the output matching circuit 707 is connected to the output end of the amplification stage circuit 705, and the output end of the output matching circuit 707 is used to output a radio frequency signal.

[0113] In addition, the power amplification circuit 700 is further provided with a second resistor R2 and a third resistor R3.

[0114] The first end of the second resistor R2 is connected to the input end of the input matching circuit 701, and the second end of the second resistor R2 is grounded.

[0115] The first end of the third resistor R3 is connected to the output end of the output matching circuit 707, and the second end of the third resistor R3 is grounded.

[0116] Since the power amplification circuit 700 in the embodiment adopts the bias circuit in any one of the above-mentioned embodiments one to five, the non-linear components generated by the power tube and the driving tube due to the second, third and high-order non-linear parameters inside the tube can be effectively reduced by the bias circuit in any one of the above-mentioned embodiments one to five, so as to improve the linearity under a large bandwidth modulation signal, and the efficiency of the power amplification circuit 700 will not be reduced.

[0117] Since the power amplification circuit 700 in the embodiment adopts the bias circuit in any one of the above-mentioned embodiments one to five, the power amplification circuit 700 in the embodiment can also achieve the technical effects achieved by the bias circuit in any one of the above-mentioned embodiments one to five, which will not be described here.

[0118] It should be noted that the above-described various embodiments with reference to the accompanying drawings are only used to illustrate the present application and not to limit the scope of the present application, and those skilled in the art should understand that the modifications or equivalent replacements of the present application without departing from the spirit and scope of the present application should be covered within the scope of the present application. In addition, unless otherwise indicated by the context, the word in singular form includes the plural form, and vice versa. In addition, unless otherwise specified, all or part of any embodiment can be used in combination with all or part of any other embodiment.

Claims

1. A bias circuit, characterized in that, The bias circuit includes a first active device, a second active device, a first capacitor, a third active device, a second capacitor, and a feedback circuit. The input terminal of the first active device is used to connect to a power source; The input terminal of the second active device is connected to the first output terminal of the first active device, and the first output terminal of the second active device is grounded. The first terminal of the first capacitor is connected to the second output terminal of the first active device, and the second terminal of the first capacitor is grounded. The first input terminal of the third active device is connected to the first terminal of the first capacitor, the second input terminal of the third active device is used to connect to the power supply voltage, and the output terminal of the third active device is used to output a bias signal. The first active device, the second active device, and the third active device together form a current mirror circuit, which is used to output a stable bias current or bias voltage according to the power supply connected to it. The first terminal of the second capacitor is connected to the second output terminal of the second active device, and the second terminal of the second capacitor is grounded. The input terminal of the feedback circuit is connected to the first terminal of the second capacitor, and the output terminal of the feedback circuit is connected to the output terminal of the third active device. The feedback circuit is used to reduce the impedance of the bias circuit. The feedback circuit includes a first resistor; a first end of the first resistor serves as the input terminal of the feedback circuit, and a second end of the first resistor serves as the output terminal of the feedback circuit. The impedance of the bias circuit includes the baseband impedance and harmonic impedance. The impedance relationship of the bias circuit is as follows: ； in, Z The impedance of the bias circuit; g m2 The transconductance of the second active device; ω Angular frequency; C be2 This refers to the parasitic capacitance of the be-e junction of the second active device; g m3 The transconductance of the third active device; C be3 The parasitic capacitance of the be-e junction of the third active device; β This is the current amplification factor of the second active device; C 1 represents the capacitance value of the first capacitor.

2. The bias circuit as described in claim 1, characterized in that, The first active device is a first transistor, the second active device is a second transistor, and the third active device is a third transistor; The collector of the first transistor serves as the input terminal of the first active device, the emitter of the first transistor serves as the first output terminal of the first active device, and the base of the first transistor serves as the second output terminal of the first active device; the collector of the first transistor is connected to the base of the first transistor. The collector of the second transistor serves as the input terminal of the second active device, the emitter of the second transistor serves as the first output terminal of the second active device, and the base of the second transistor serves as the second output terminal of the second transistor. The base of the third transistor serves as the first input terminal of the third active device, the collector of the third transistor serves as the second input terminal of the third active device, and the emitter of the third transistor serves as the output terminal of the third transistor.

3. The bias circuit as described in claim 1, characterized in that, The first active device is a first transistor, the second active device is a second transistor, and the third active device is a third transistor; The collector of the first transistor serves as the input terminal of the first active device, the emitter of the first transistor serves as the first output terminal of the first active device, and the base of the first transistor serves as the second output terminal of the first active device; the collector of the first transistor is connected to the base of the first transistor. The collector of the second transistor serves as the input terminal of the second active device, the emitter of the second transistor serves as the first output terminal of the second active device, and the base of the second transistor serves as the second output terminal of the second transistor; the collector of the second transistor is connected to the base of the second transistor. The base of the third transistor serves as the first input terminal of the third active device, the collector of the third transistor serves as the second input terminal of the third active device, and the emitter of the third transistor serves as the output terminal of the third transistor.

4. The bias circuit as described in claim 1, characterized in that, The first active device is a first diode, the second active device is a second transistor, and the third active device is a third transistor; The positive terminal of the diode serves as both the input terminal and the second output terminal of the first active device, while the negative terminal of the diode serves as the first output terminal of the first active device. The collector of the second transistor serves as the input terminal of the second active device, the emitter of the second transistor serves as the first output terminal of the second active device, and the base of the second transistor serves as the second output terminal of the second transistor. The base of the third transistor serves as the first input terminal of the third active device, the collector of the third transistor serves as the second input terminal of the third active device, and the emitter of the third transistor serves as the output terminal of the third transistor.

5. The bias circuit as described in claim 1, characterized in that, The first active device is a first diode, the second active device is a second transistor, and the third active device is a third transistor; The positive terminal of the diode serves as both the input terminal and the second output terminal of the first active device, while the negative terminal of the diode serves as the first output terminal of the first active device. The collector of the second transistor serves as the input terminal of the second active device, the emitter of the second transistor serves as the first output terminal of the second active device, and the base of the second transistor serves as the second output terminal of the second transistor; the collector of the second transistor is connected to the base of the second transistor. The base of the third transistor serves as the first input terminal of the third active device, the collector of the third transistor serves as the second input terminal of the third active device, and the emitter of the third transistor serves as the output terminal of the third transistor.

6. The bias circuit as described in claim 1, characterized in that, The first active device is a first diode, the second active device is a second diode, and the third active device is a third transistor; The positive terminal of the diode serves as both the input terminal and the second output terminal of the first active device, while the negative terminal of the diode serves as the first output terminal of the first active device. The positive terminal of the second diode serves as both the input terminal and the second output terminal of the second active device, while the negative terminal of the second diode serves as the first output terminal of the second active device. The base of the third transistor serves as the first input terminal of the third active device, the collector of the third transistor serves as the second input terminal of the third active device, and the emitter of the third transistor serves as the output terminal of the third transistor.

7. The bias circuit as described in claim 1, characterized in that, The feedback circuit further includes a third capacitor; the first end of the third capacitor is connected to the first end of the first resistor, and the second end of the third capacitor is connected to the second end of the first resistor.

8. The bias circuit as described in claim 7, characterized in that, The feedback circuit also includes an inductor; the first end of the inductor is connected to the first end of the third capacitor, and the second end of the inductor is connected to the second end of the third capacitor.

9. The bias circuit as described in claim 1, characterized in that, The feedback circuit further includes an inductor; a first end of the inductor is connected to a first end of the first resistor, and a second end of the inductor is connected to a second end of the first resistor.

10. A power amplifier circuit, characterized in that, The power amplifier circuit includes an input matching circuit, a driver stage circuit, a first bias circuit, an inter-stage matching circuit, an amplifier stage circuit, a second bias circuit, and an output matching circuit; the first bias circuit and the second bias circuit are both bias circuits as described in any one of claims 1 to 9. The input terminal of the input matching circuit is used to receive radio frequency signals; The first input terminal of the driver stage circuit is connected to the output terminal of the input matching circuit; The output of the first bias circuit is connected to the second input of the driver stage circuit; The input terminal of the inter-stage matching circuit is connected to the output terminal of the driver stage circuit; The first input terminal of the amplifier stage circuit is connected to the output terminal of the interstage matching circuit. The output of the second bias circuit is connected to the second input of the amplifier stage circuit; The input terminal of the output matching circuit is connected to the output terminal of the amplifier stage circuit, and the output terminal of the output matching circuit is used to output radio frequency signals.

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