Cross-chip multipath MAC address learning and synchronization method and system
By setting up the bus and CPU control address tables in a dual-chip FPGA switch, and synchronizing and managing address table entries are achieved using the cross-chip interface, the synchronization problem of address tables between dual-chip FPGAs is solved, the switching capacity and processing rate of the switch are improved, and the requirements of satellite Internet systems are adapted.
Patent Information
- Application Number
- CN202510478791.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-16
- Publication Date
- 2025-07-18
AI Technical Summary
In a satellite-based switch built with a dual-chip FPGA, how to achieve efficient management and synchronization of address tables between two FPGAs to ensure the normal operation of address learning and table lookup functions of layer two exchanges has become a key problem that needs to be broken through in the current technical field.
By setting the bus address table and CPU control address table on the bus of each chip FPGA, collecting the address table entries of the bus address update buffer, and synchronizing and managing the address table entries through the cross-chip Aurora interface and PCIE interface, and using the CPU control address table for maintenance and management.
The synchronization of address tables between two FPGAs is realized, ensuring the maintenance and management of switch address tables, improving switching capacity and processing speed, and adapting to the needs of satellite Internet systems.
Smart Images
Figure CN120342980A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of communication technologies, and particularly relates to a cross-chip multi-channel MAC address learning and synchronization method and system. Background Art
[0002] With the rapid evolution of communication technologies, satellite Internet has become an indispensable supplement to terrestrial communication systems due to its significant advantages such as wide coverage, flexible networking, and rapid response, and has conformed to the development trend of 6G mobile communication integrating space and ground, connecting all things, and enabling intelligent perception. As a key node in the satellite Internet system, on-board switching equipment faces the severe challenges of a sharp increase in access devices and a rapid growth in network traffic, and urgently needs to have a larger switching capacity and a higher line speed processing rate.
[0003] To ensure stable operation in the harsh space environment, on-board switching equipment must adopt aerospace-grade FPGA devices. However, the storage resources of aerospace-grade FPGA chips are limited. If redundant backup resources are reserved for key modules, the capacity of on-board switches built with a single FPGA will be greatly limited. Therefore, using two FPGAs in combination to share the resource overhead has become an effective solution, by jointly implementing the functions of on-board switches on two FPGAs, thereby expanding the number of ports and increasing the switching capacity.
[0004] Address learning is one of the core functions of on-board switches, and the process of dynamically constructing and maintaining the MAC address table is crucial. The MAC address table records the MAC addresses of each device in the network and their corresponding switch ports. Through address learning, the switch can quickly determine the forwarding path of data packets, thereby avoiding unnecessary broadcasts. However, in the two-FPGA architecture, how to achieve efficient management and synchronization of the address tables on the two FPGAs to ensure the normal operation of the address learning and look-up table functions for layer 2 switching has become a key problem that urgently needs to be solved in the current technical field. Summary of the Invention
[0005] To solve the above problems existing in the prior art, the present invention provides a cross-chip multi-channel MAC address learning and synchronization method and system. The technical problems to be solved by the present invention are achieved through the following technical solutions:
[0006] The present invention provides a cross-chip multi-channel MAC address learning and synchronization method, which is applicable to switches built with two FPGAs. A CPU is set in the FPGA to control the address table, and a corresponding bus address table is set on each bus of the FPGA. The method includes:
[0007] Parsing the data frame received by the port to obtain address information, performing look-up table, address learning, and updating the bus address table of the current bus according to the address information;
[0008] Send the updated address entry in the bus address table to the bus address update buffer of this bus;
[0009] Collect the address entries in all bus address update buffers of the current FPGA as FPGA updated address entries, and send the FPGA updated address entries to the FPGA address update buffer of another FPGA;
[0010] When the bus detects that there are address entries to be updated in at least one of the bus address update buffers of other buses, the FPGA address update buffer, and the CPU address update buffer, poll and read the address entries to be updated and store them in the bus address table of this bus to achieve address synchronization;
[0011] Among them, the CPU control address table is used to collect the updated address entries of all buses of two FPGAs and the static address table entries of the switch; the CPU address update buffer is used to store the static address table entries.
[0012] The present invention also provides a cross-chip multi-channel MAC address learning and synchronization system, which is applicable to the cross-chip multi-channel MAC address learning and synchronization method described in any of the above embodiments. The system includes multiple address learning modules, multiple address update modules, an address learning cross-chip channel, and a CPU. Each bus corresponds to an address learning module and an address update module; among them,
[0013] The address learning module is used to parse the data frame received by the port to obtain address information, perform table lookup and address learning according to the address information, and send the updated address entry in the bus address table to the bus address update buffer of this bus;
[0014] The address learning cross-chip channel is used to collect the address entries in all bus address update buffers of the current FPGA as FPGA updated address entries, and send the FPGA updated address entries to the FPGA address update buffer of another FPGA;
[0015] The address update module is used to update the bus address table of this bus according to the address learning of the address learning module, and when the bus detects that there are address entries to be updated in at least one of the bus address update buffers of other buses, the FPGA address update buffer, and the CPU address update buffer, poll and read the address entries to be updated and store them in the bus address table of this bus to achieve address synchronization;
[0016] The CPU is used to configure static address entries for the switch, and periodically query and compare the CPU control address tables of the two FPGAs, and maintain the CPU control address table and the bus address table according to the query and comparison results.
[0017] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0018] The cross-chip multi-channel MAC address learning and synchronization method of the present invention solves the problem of synchronizing the address tables between two FPGAs by collecting all bus addresses of the current FPGA to update the address entries in the buffer and sending them to the FPGA address update buffer of another FPGA. The CPU control address table is used to collect the updated address entries of all buses of the two FPGAs and the static address entries of the switch. Subsequently, the upper-layer CPU can maintain and manage the CPU control address table to achieve the maintenance and management of the switch address table.
[0019] The above description is only an overview of the technical solution of the present invention. In order to be able to understand the technical means of the present invention more clearly, it can be implemented according to the content of the specification. And in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable, the following specifically gives preferred embodiments and, in conjunction with the accompanying drawings, details are described as follows. Brief Description of the Drawings
[0020] Figure 1 is a flowchart of a cross-chip multi-channel MAC address learning and synchronization method provided by an embodiment of the present invention;
[0021] Figure 2 is a schematic diagram of the format of the internal address entries of a switch provided by an embodiment of the present invention;
[0022] Figure 3 is a block diagram of the structure of a cross-chip multi-channel MAC address learning and synchronization system provided by an embodiment of the present invention. Detailed Embodiments
[0023] In order to further elaborate on the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, the following, in conjunction with the accompanying drawings and specific embodiments, details a cross-chip multi-channel MAC address learning and synchronization method and system proposed according to the present invention.
[0024] The foregoing and other technical contents, features and effects of the present invention can be clearly presented in the following detailed description in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and specific understanding of the technical means and effects adopted by the present invention to achieve the predetermined purpose can be obtained. However, the accompanying drawings are only for reference and illustration purposes and are not used to limit the technical solution of the present invention.
[0025] In a first aspect, an embodiment of the present invention provides a method for cross-chip multi-channel MAC address learning and synchronization. This method is applicable to a switch constructed by two FPGAs. A CPU control address table is set in the FPGA, and a corresponding bus address table is set on each bus of the FPGA. Please refer to Figure 1 , Figure 1 is a flowchart of a method for cross-chip multi-channel MAC address learning and synchronization provided by an embodiment of the present invention. As Figure 1 shown, the method for cross-chip multi-channel MAC address learning and synchronization in this embodiment may include the following steps:
[0026] Step 1: Parse the data frame received by the port to obtain address information, and perform table lookup, address learning, and update of the bus address table of this bus according to the address information.
[0027] In this embodiment, the address information includes a destination MAC address and a source MAC address. Step 1 specifically includes:
[0028] Step 1.1: Parse the Ethernet frame header of the data frame to obtain the destination MAC address and the source MAC address, learn the mapping between the source MAC address and its corresponding port, generate an updated address table entry, and update the bus address table of this bus according to the updated address table entry.
[0029] In this embodiment, for the data frame received by the port, the destination MAC address and the source MAC address are parsed according to the Ethernet frame format. Hash operations are respectively performed on the destination MAC address and the source MAC address, and the mapping calculation from the 48-bit MAC address to the 10-bit hash index value is completed through the CRC function. The mapping value is used as the index of the bus address table, and the source MAC address of the data frame and the corresponding port number are recorded to generate an updated address table entry.
[0030] Please refer to Figure 2 , Figure 2 is a schematic diagram of the format of an internal address table entry of a switch provided by an embodiment of the present invention. The format of the address table entry in this embodiment includes fields such as age, is_from_other, valid, sour_mac, and port. Among them, the age field is an aging flag, the is_from_other field indicates whether the address table entry is an update from other buses, the valid field indicates whether the address table entry is valid, the sour_mac field indicates the source MAC address of the address table entry, and the port field indicates the port number corresponding to the source MAC address of the address table entry.
[0031] Step 1.2: Query the bus address table of this bus according to the destination MAC address. If an address table entry consistent with the destination MAC address is found, forward the data frame to the corresponding port according to the port number in the address table entry.
[0032] In this embodiment, the 10-bit mapping value calculated after hashing the destination MAC address is used as the index of the bus address table. The address entry at this position is retrieved from the bus address table. If the MAC address stored in the address entry is the same as the destination MAC, the port number in the address entry is extracted as the lookup result, and the switch forwards it to the specified port according to the port number.
[0033] Step 1.3: If no address entry matching the destination MAC address is found, the data frame is broadcast to all ports. The mapping between its MAC address and the port is learned based on the responding ports, and an updated address entry is generated. The bus address table of this bus is updated according to the updated address entry.
[0034] In this embodiment, if the MAC address stored in the address entry at the position found in the bus address table according to the 10-bit mapping value calculated after hashing the destination MAC address is not the same as the destination MAC, it indicates that the forwarding relationship of this destination MAC address has not been learned in the bus address table of the current bus of the switch. Eventually, the switch will broadcast the data frame to all ports. Then, the source MAC address and port number of this port are learned based on the responding port, an updated address entry is generated, and it is written to the position in the bus address table corresponding to the 10-bit value after hashing the source MAC address.
[0035] It should be noted that for the newly learned address entry, both its age and valid fields are 1.
[0036] It can be understood that for the switch in this embodiment, when it is powered on or reset, the address table of each bus needs to be initialized. The specific method is to write all zeros to the content of each address entry to ensure that the content of all address tables is empty in the initial state. At the same time, the register storing the MAC address of the previous port needs to be reset.
[0037] Step 2: Send the updated address entry in the bus address table to the bus address update buffer of this bus.
[0038] Specifically, Step 2 includes: determining whether the source MAC address of the updated address entry in the bus address table is repeated with the source MAC address of the data frame received by the port last time. If not, the updated address entry is sent to the bus address update buffer of this bus.
[0039] In this embodiment, the register is used to record the source MAC address received at the previous port, and it is determined whether the source MAC address of the currently updated address entry is the same as the source MAC address of the data frame received at the previous port. If they are the same, it will not be finally sent to the bus address update buffer where this bus is located. If they are different, it means that a new address entry is learned. Then, the is_from_other field in the address entry is set to 1, and then the updated address entry is sent to the bus address update buffer.
[0040] Step 3: Collect the address entries of all bus address update buffers of the current FPGA as the FPGA address update entries, and send the FPGA address update entries to the FPGA address update buffer of another FPGA.
[0041] Specifically, step 3 includes:
[0042] Step 3.1: Collect the address entries of all bus address update buffers of the current FPGA to obtain the FPGA address update entries of the current FPGA, and pack the FPGA address update entries into a data stream in AXI-Stream format.
[0043] Step 3.2: Send the data stream to another FPGA through the cross-chip Aurora interface. After the current FPGA restores the format of the received data stream, it stores it in the FPGA address update buffer.
[0044] In this embodiment, the addresses between two FPGAs are synchronized through the cross-chip Aurora interface. For the sending side, the address entries of all bus address update buffers of the local FPGA collected are packed into a data stream in AXI-Stream format and sent to another FPGA through the high-speed Aurora cross-chip interface. On the receiving side, the data stream received from the cross-chip Aurora interface is restored to the address entry format, and the obtained address entries are sent to the FPGA address update buffer. Subsequently, the address tables of the two FPGAs are synchronized through address updates.
[0045] Step 4: When the bus detects that there are address entries to be updated in at least one of the address update buffers, namely the bus address update buffer, the FPGA address update buffer, and the CPU address update buffer of other buses, poll and read the address entries to be updated and store them in the bus address table of this bus to achieve address synchronization.
[0046] In this embodiment, the CPU control address table is used to collect the updated address entries of all buses of two FPGAs and the static address entries of the switch; the CPU address update buffer is used to store the static address entries.
[0047] In this embodiment, each bus of the FPGA monitors in real time the address entry data in all bus address update buffers, FPGA address update buffers, and CPU address update buffers of this FPGA. When a pending address entry to be updated is detected, it polls and reads the address entry data and updates it to the bus address table of this bus, completing the synchronization of the address table.
[0048] In an optional embodiment, the cross-chip multi-channel MAC address learning and synchronization method of this embodiment further includes: periodically traversing all address entries in the bus address table corresponding to each bus, and aging the address entries learned by this bus according to preset conditions.
[0049] Exemplarily, during the process of traversing the bus address table, the age field and is_from_other field in the address entry are detected. If the is_from_other field is 1, it means that the address entry comes from another bus and no aging operation is performed. If the is_from_other field is 0, the age field is further judged. If the age field is 1, the age field in the address entry is set to 0, indicating that the address entry has been read; if the age field is 0, it means that the address entry has not been refreshed within the aging time, that is, the time reserved for the address entry has exceeded the aging time, and the address entry will be cleared.
[0050] In an optional embodiment, the cross-chip multi-channel MAC address learning and synchronization method of this embodiment further includes: periodically querying and comparing the CPU control address tables of two FPGAs, and maintaining the CPU control address table and the bus address table according to the query and comparison results.
[0051] It can be understood that a CPU read / write interface, such as a PCIE interface, is provided on the FPGA. The upper-layer CPU can maintain and update the MAC address table of the switch in real time, and at the same time, the CPU can also configure static address entries for the switch.
[0052] In this embodiment, a CPU control address table is set for each FPGA for the CPU to read and write the table. The CPU control address table also collects the address table entry data from other ordinary bus address update buffers and cross-chip FPGA address update buffers. The CPU regularly reads the content of the CPU control address table through the PCIE interface, maintains an address table in the upper-layer software, and compares the differences in the CPU control address tables read from the two FPGAs. Usually, the differences in the CPU control address tables are mainly due to possible bit errors during cross-chip transfer. Therefore, the CPU compares the is_from_other fields in the different address table entries to determine whether the address table entry is from the other chip or this chip, and takes the address table entry updated by this chip as the standard, and completes the synchronization of the address table on this basis. For the incorrect address table entries, the CPU will configure the table through the PCIE interface, and finally complete the synchronization of the entire switch address table.
[0053] In this embodiment, the cross-chip Aurora interface is used to solve the problem of synchronizing the address tables between two FPGAs, and the upper-layer CPU completes the maintenance and management of the switch address table through the PCIE interface. Even if the content of the address table entry is incorrect during cross-chip transfer, the CPU regularly reads the CPU control address table on the FPGA to detect whether the address tables in the two FPGAs are synchronized, and completes the error correction and overwrite writing of the address table, so that the address tables inside the switch are synchronized.
[0054] The cross-chip multi-channel MAC address learning and synchronization method according to the embodiment of the present invention solves the problem of synchronizing the address tables between two FPGAs by collecting the address table entries of all bus address update buffers of the current FPGA and sending them to the FPGA address update buffer of another FPGA. The CPU control address table is used to collect the updated address table entries of all buses of the two FPGAs and the static address table entries of the switch. Subsequently, the upper-layer CPU can maintain and manage the CPU control address table to achieve the maintenance and management of the switch address table.
[0055] In a second aspect, an embodiment of the present invention provides a cross-chip multi-channel MAC address learning and synchronization system, which is applicable to the cross-chip multi-channel MAC address learning and synchronization method provided in the first aspect.
[0056] Please refer to Figure 3 , Figure 3 which is a structural block diagram of a cross-chip multi-channel MAC address learning and synchronization system provided by an embodiment of the present invention. As Figure 3 shown, the cross-chip multi-channel MAC address learning and synchronization system of this embodiment includes: a plurality of address learning modules, a plurality of address update modules, an address learning cross-chip channel, and a CPU. Each bus corresponds to an address learning module and an address update module.
[0057] Among them, the address learning module is used to parse the data frame received by the port to obtain address information, perform table lookup and address learning according to the address information, and send the updated address entry in the bus address table to the bus address update buffer of this bus.
[0058] In this embodiment, reading and writing to the bus address table are required for address learning, table lookup, and update of the bus in the FPGA.
[0059] In this embodiment, an address filtering module and an aging module are provided in the address learning module. Among them, the address filtering module is used to determine whether the source MAC address of the updated address entry in the bus address table is the same as the source MAC address of the data frame received by the port last time. If they are not the same, the updated address entry is sent to the bus address update buffer of this bus; the aging module periodically traverses all address entries in the bus address table corresponding to each bus, and ages the address entries learned on this bus according to preset conditions. It can be understood that a table lookup module is also provided in the address learning module, which is used to perform table lookup using the obtained address information after receiving a data frame.
[0060] Specifically, the aging module is responsible for maintaining the updated address entries on this bus. When an address entry exceeds the aging time, the aging module will delete the address entry. At the same time, the deleted entry will also be updated to the address update module to notify the address tables of other buses that the deletion operation has been completed synchronously. The table lookup module is mainly responsible for finding the forwarding relationship of the data frame entering the switch, and finding the destination forwarding port of the current data frame by accessing the bus address table of this bus. The address filtering module is responsible for filtering the address entry data sent to the address update module, filtering out the repeatedly learned and updated address entries, and only updating the address entries learned for the first time. At the same time, the address learning module will also learn the correspondence between the source MAC address of the input data frame and the port.
[0061] Among them, the cross-chip address learning channel is used to collect the address entries in all bus address update buffers of the current FPGA as the FPGA updated address entries, and send the FPGA updated address entries to the FPGA address update buffer of another FPGA.
[0062] Specifically, the cross-chip address learning channel serves as an address communication channel between two FPGAs. On the sending side, the cross-chip address learning channel is used to collect the updated address entry data on all buses of this FPGA, pack them into a data stream in AXI-Stream format, and then send it to the Aurora interface, and send it to another FPGA through the Aurora interface; on the receiving side, the cross-chip address learning channel is responsible for restoring the data stream in the Aurora interface to the address entry format, and finally sending it to the FPGA address update buffer of this chip.
[0063] Among them, the address update module is used to update the bus address table of this bus according to the address learning of the address learning module, and when the bus detects that there is at least one address update buffer in the bus address update buffer, FPGA address update buffer, and CPU address update buffer of other buses with address table entries to be updated, it polls and reads the address table entries to be updated and stores them in the bus address table of this bus to achieve address synchronization.
[0064] Specifically, the address update module first stores the updated address table entries on other buses in the corresponding buffer, and when the address learning module initiates a read request, it then sends the updated address table entry data to the address learning module.
[0065] Among them, the CPU is used to configure static address table entries for the switch, and regularly query and compare the CPU control address tables of two FPGAs, and maintain the CPU control address table and the bus address table according to the query and comparison results.
[0066] In this embodiment, the CPU control address table collects the address table entry data of all buses on this FPGA and another FPGA, and at the same time responds to the table reading request initiated by the CPU, and the CPU completes the reading and configuration of the address table on the FPGA through the PCIE interface.
[0067] Specifically, when the CPU initiates a request to traverse table entries, the table entries in the CPU control address table are sent to the CPU through the PCIE interface in ascending order of addresses. When the CPU initiates a write table request, the write table information sent by the CPU is rectified into the format of address table entries and written into the CPU control address table. While completing the update and writing of the CPU control address table, the address table entries configured by the CPU are sent to the bus address update buffer of other buses, so that the bus address tables of other buses can also respond to the configuration requests of the CPU.
[0068] For the specific content and corresponding beneficial effects of the cross-chip multi-channel MAC address learning and synchronization system, please refer to the relevant content of the cross-chip multi-channel MAC address learning and synchronization method provided in the first aspect, which will not be elaborated here.
[0069] It should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variant are intended to cover non-exclusive inclusion, so that an article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the article or device comprising said element. Similar words such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The orientation or positional relationship indicated by "upper", "lower", "left", "right", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention.
[0070] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. means that the specific features or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.
[0071] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can be made, and all should be regarded as belonging to the protection scope of the present invention.
Claims
1. A cross-chip multi-channel MAC address learning and synchronization method, characterized in that Applicable to a switch constructed by two FPGAs, where a CPU control address table is set in each FPGA, and a corresponding bus address table is set on each bus of the FPGA; the method includes: Parse the data frame received by the port to obtain address information, perform look-up table, address learning, and update the bus address table of this bus according to the address information; Send the updated address table entry in the bus address table to the bus address update buffer of this bus; Collect the address table entries of all bus address update buffers of the current FPGA as the FPGA update address table entries, and send the FPGA update address table entries to the FPGA address update buffer of another FPGA; When the bus detects that there are address table entries to be updated in at least one of the bus address update buffers of other buses, the FPGA address update buffer, and the CPU address update buffer, poll and read the address table entries to be updated and store them in the bus address table of this bus to achieve address synchronization; Among them, the CPU control address table is used to collect the updated address table entries of all buses of the two FPGAs and the static address table entries of the switch; the CPU address update buffer is used to store the static address table entries.
2. The cross-chip multi-channel MAC address learning and synchronization method according to claim 1, wherein The address information includes the destination MAC address and the source MAC address.
3. The cross-chip multi-channel MAC address learning and synchronization method according to claim 2, characterized in that, Parsing the received data frame to obtain address information, performing look-up table, address learning, and updating the bus address table of this bus according to the address information includes: Parse the Ethernet frame header of the data frame to obtain the destination MAC address and the source MAC address, learn the mapping between the source MAC address and its corresponding port, generate an updated address table entry, and update the bus address table of this bus according to the updated address table entry; Query the bus address table of this bus according to the destination MAC address. If an address table entry identical to the destination MAC address is found, forward the data frame to the corresponding port according to the port number in the address table entry; If no address table entry identical to the destination MAC address is found, broadcast the data frame to all ports, learn the mapping between its MAC address and the port according to the responsive port, generate an updated address table entry, and update the bus address table of this bus according to the updated address table entry.
4. The cross-chip multi-channel MAC address learning and synchronization method according to claim 3, wherein The format of the address table entry includes fields such as age, is_from_other, valid, sour_mac, and port. Among them, the age field is the aging flag, the is_from_other field indicates whether the address table entry is from the update of other buses, the valid field indicates whether the address table entry is valid, the sour_mac field indicates the source MAC address of the address table entry, and the port field indicates the port number corresponding to the source MAC address of the address table entry.
5. The cross-chip multi-channel MAC address learning and synchronization method according to claim 4, characterized in that Sending the updated address table entry in the bus address table to the bus address update buffer of this bus includes: Determine whether the source MAC address of the updated address entry in the bus address table is the same as the source MAC address of the data frame received by the previous port. If they are not the same, send the updated address entry to the bus address update buffer of this bus.
6. The cross-chip multi-channel MAC address learning and synchronization method according to claim 4, wherein Collect the address entries in all bus address update buffers of the current FPGA as the FPGA updated address entries, and send the FPGA updated address entries to the FPGA address update buffer of another FPGA, including: Collect the address entries in all bus address update buffers of the current FPGA to obtain the FPGA updated address entries of the current FPGA, and pack the FPGA updated address entries into a data stream in AXI-Stream format; Send the data stream to another FPGA through the cross-chip Aurora interface, and the current FPGA stores the data stream in the FPGA address update buffer after format recovery.
7. The method for cross-chip multi-channel MAC address learning and synchronization according to claim 1, characterized in that It further includes: periodically traversing all address entries in the bus address table corresponding to each bus, and aging the address entries learned by this bus according to preset conditions.
8. The cross-chip multi-channel MAC address learning and synchronization method according to claim 1, wherein It further includes: Periodically query and compare the CPU control address tables of the two FPGAs, and maintain the CPU control address table and the bus address table according to the query and comparison results.
9. A cross-chip multi-channel MAC address learning and synchronization system, characterized in that Applicable to the cross-chip multiplexed MAC address learning and synchronization method according to any one of claims 1-8. The system includes multiple address learning modules, multiple address update modules, an address learning cross-chip channel, and a CPU. Each bus corresponds to an address learning module and an address update module; wherein, The address learning module is used to parse the data frame received by the port to obtain address information, perform table lookup and address learning according to the address information, and send the updated address entry in the bus address table to the bus address update buffer of this bus; The address learning cross-chip channel is used to collect the address entries in all bus address update buffers of the current FPGA as the FPGA updated address entries, and send the FPGA updated address entries to the FPGA address update buffer of another FPGA; The address update module is used to update the bus address table of this bus according to the address learning of the address learning module, and when it is detected that there are address entries to be updated in at least one of the bus address update buffer of other buses, the FPGA address update buffer, and the CPU address update buffer of this bus, poll and read the address entries to be updated and store them in the bus address table of this bus to achieve address synchronization; The CPU is used to configure static address entries for the switch, and periodically query and compare the CPU control address tables of the two FPGAs, and maintain the CPU control address table and the bus address table according to the query and comparison results.
10. The cross-chip multi-channel MAC address learning and synchronization system according to claim 9, characterized in that, An address filtering module and an aging module are provided in the address learning module, wherein, The address filtering module is used to determine whether the source MAC address of the updated address entry in the bus address table is the same as the source MAC address of the data frame received at the previous port. If they are not the same, the updated address entry is sent to the bus address update buffer of this bus. The aging module periodically traverses all address entries in the bus address table corresponding to each bus and ages the address entries learned by this bus according to preset conditions.