Intelligent reconfigurable wireless communication physical layer architecture and dynamic configuration method
Through the ARM+FPGA collaborative architecture and MAB algorithm, intelligent adaptive modulation and hardware reconstruction of wireless communication systems are realized, solving the communication performance problems of the traditional wireless physical layer in complex environments, improving system throughput and reducing bit error rate.
Patent Information
- Application Number
- CN202510545695.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-28
- Publication Date
- 2025-07-18
AI Technical Summary
Traditional wireless physical layer design cannot cope with complex and changeable wireless environments in real time, resulting in degradation of communication performance and interruption of connections. The existing reconfigurable wireless physical layer lacks intelligent learning and adaptive optimization capabilities.
The ARM+FPGA collaborative architecture is adopted, combined with the multi-arm gambling machine (MAB) online learning algorithm, to realize adaptive optimization of dynamic channel selection and modulation schemes, and parameter adjustments are performed at the hardware level through dynamic partial reconstruction (DPR) technology.
Improve system throughput, reduce bit error rate, and reduce energy consumption to adapt to dynamic changes in complex wireless environments.
Smart Images
Figure CN120343584A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of wireless communication, and particularly relates to an intelligent reconfigurable wireless communication physical layer architecture and a dynamic configuration method. Background Art
[0002] With the rapid development of wireless communication technology, the demand for network performance is getting higher and higher, requiring support for high throughput, low latency, and large-scale device connections. However, traditional wireless physical layer designs use modulation and coding schemes with fixed parameters, usually relying on upper-layer protocols for adaptation, and it is difficult to respond to complex and changeable wireless environments in real time. For example, when the traditional wireless physical layer faces dynamically changing channel conditions (such as signal fading, interference, changes in user density, etc.), it often cannot quickly adjust transmission parameters, resulting in a decline in communication performance and even connection interruptions. In recent years, some researchers have proposed the concepts of software-defined radio and reconfigurable wireless physical layer, but most current reconfigurable wireless physical layer solutions only provide hardware-level reconfigurability and lack intelligent learning and adaptive optimization capabilities, so they cannot achieve optimal communication in complex environments and cannot meet the multi-scenario adaptability of wireless communication. Therefore, there is an urgent need for an implementation method of a wireless communication physical layer with self-learning ability and hardware dynamic reconfiguration ability to solve the technical problems. Summary of the Invention
[0003] In view of the above problems, the present invention provides an intelligent reconfigurable wireless physical layer architecture and a dynamic configuration method based on the collaborative design of hardware and software. This method integrates hardware reconfigurability and online learning ability, enabling the wireless communication system to adaptively optimize transmission parameters in a dynamic environment, thereby improving system throughput, reducing the bit error rate, and reducing energy consumption.
[0004] The technical solution adopted by the present invention is as follows:
[0005] An intelligent reconfigurable wireless communication physical layer architecture, comprising: a system processing module, an online learning and optimization module, a programmable logic FPGA module, and a dynamic partial reconfiguration DPR module;
[0006] The system processing module includes an ARM processor, a high-speed storage unit, and an on-chip interconnect bus; it is used for intelligent channel selection and modulation mode optimization, communicates with the programmable logic FPGA module to achieve dynamic adjustment of wireless physical layer parameters, and triggers the dynamic partial reconfiguration DPR module to perform hardware reconfiguration on the physical layer module.
[0007] The programmable logic FPGA module includes a wireless transceiver, a modulation and demodulation module, a channel coding and decoding module, an OFDM waveform processing module, and a synchronization and channel estimation module; it is used for wireless signal transmission, modulation and demodulation, channel coding, OFDM transformation operations, and dynamically switching different physical layer parameters through DPR and real-time collecting wireless channel information.
[0008] The ARM processor of the system processing module is provided with an online learning and optimization module, including a hardware acceleration unit for the upper confidence bound algorithm, a reward value storage unit, and a channel evaluation and decision-making unit; it is used for adaptively selecting the optimal channel in a dynamic wireless environment to improve communication quality.
[0009] The online learning and optimization module adopts the multi-armed bandit MAB algorithm.
[0010] The adaptive selection of the optimal channel is as follows: combining physical layer feedback, optimizing the exploration and exploitation strategies of the MAB algorithm, calculating the average throughput, bit error rate, and interference situation of the channel according to historical data, and optimizing the channel selection strategy.
[0011] In the programmable logic FPGA module, the physical layer parameters include but are not limited to modulation methods or channel coding schemes; the wireless channel information includes but is not limited to signal-to-noise ratio, bit error rate, and throughput.
[0012] The programmable logic FPGA module is provided with a dynamic partial reconfiguration DPR module, including a device configuration unit, a reconfigurable area, and a partial configuration bitstream storage unit; it is used to control the FPGA through the device configuration unit to achieve dynamic hardware replacement of the wireless physical layer module, store multiple predefined physical layer configuration bitstreams; and load the optimal configuration according to changes in the communication environment during operation; optimize the physical layer resource allocation through the DPR mechanism without interrupting communication.
[0013] The AXI-Lite bus is used for control signal transmission between the ARM and the FPGA; the AXI-Stream bus is used for data transmission of the internal physical layer of the FPGA; the UART interface is used for data debugging and monitoring.
[0014] A dynamic configuration method for an intelligent reconfigurable wireless communication physical layer architecture includes the following steps:
[0015] The ARM processor loads the multi-armed bandit MAB algorithm, initializes the wireless channel state and key parameters; the FPGA module loads the default physical layer configuration; enables the initial channel and starts transmitting data;
[0016] During the communication process, the online learning and optimization module continuously monitors the wireless channel state and key parameters, and calculates the reward value R of the current channel n ; where PR is the power of the received pilot; P T is the power of the transmitted pilot; for the currently selected channel k, k ∈ {1, 2, …, K}, update the cumulative reward of this channel in time slot n: X(k, n) = X(k, n - 1) + R n ; update the number of times this channel is selected in time slot n: T(k, n) = T(k, n - 1) + 1; adopt the upper confidence bound algorithm to evaluate the long-term benefits of each channel;
[0017] The ARM processor automatically switches to the 16-QAM or QPSK mode according to the channel quality, triggering the dynamic partial reconfiguration DPR module to switch the modulation scheme without interrupting the communication; if the interference of the current channel increases or the quality decreases, select a new optimal channel according to the MAB algorithm, and control the programmable logic FPGA module to perform channel switching at the physical layer;
[0018] The dynamic partial reconfiguration DPR module receives the ARM trigger, dynamically updates the physical layer architecture of the FPGA module through the device configuration unit, and quickly reconfigures the FPGA module.
[0019] The wireless channel state and key parameters include but are not limited to the number of available channels K, the initialized QPSK modulation mode, and the channel quality evaluation index.
[0020] Further, the upper confidence bound algorithm includes:
[0021] Calculate the quality factor QF of channel k:
[0022]
[0023] where: the exploration factor α ∈ (0.5, 2);
[0024] Calculate the QF values of all channels and select the channel with the largest QF for data transmission.
[0025] The present invention has the following beneficial effects and advantages:
[0026] (1) Adopt the ARM+FPGA cooperative architecture, where the ARM processor is responsible for high-level decision-making, and the FPGA realizes reconfigurable wireless signal processing. Through the DPR technology, physical parameters such as the modulation scheme and channel selection can be dynamically reconfigured to adapt to different communication requirements.
[0027] (2) Integrate the multi-armed bandit (MAB) online learning algorithm, dynamically adjust physical parameters in different wireless environments, intelligent wireless channel selection and adaptive modulation scheme, automatically select the optimal channel and modulation method, improve system throughput and reduce the bit error rate. Description of the Drawings
[0028] Figure 1 This is an architecture diagram of an intelligent reconfigurable wireless physical layer of the present invention.
[0029] Figure 2 This is a flowchart of the dynamic configuration method for the wireless physical layer of the present invention.
[0030] Figure 3 This is a decision flowchart of the MAB algorithm of the present invention. Detailed implementation manners
[0031] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following will describe the specific implementation methods of the present invention in detail with reference to the accompanying drawings. Many specific details are set forth in the following description in order to fully understand the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without departing from the connotation of the invention. Therefore, the present invention is not limited by the specific implementations disclosed below.
[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present invention belongs. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The following will further describe the present invention in detail with reference to the accompanying drawings and embodiments.
[0033] Technical solution:
[0034] Example 1. An intelligent reconfigurable wireless physical layer architecture includes:
[0035] (1) A processing system module, including an ARM processor (dual-core Cortex-A9), a high-speed storage unit (DDR, SRAM), and an on-chip interconnect bus (AXI bus).
[0036] It is mainly responsible for running the multi-armed bandit (MAB) algorithm, performing intelligent channel selection and modulation mode optimization, communicating with the programmable logic (FPGA) module through the AXI bus, realizing dynamic adjustment of wireless physical layer parameters, triggering the dynamic partial reconfiguration (DPR) module, and performing hardware reconfiguration on the physical layer module to optimize performance.
[0037] (2) A programmable logic (FPGA) module, including a wireless transceiver, a modulation and demodulation module, a channel coding and decoding module, an OFDM waveform processing module, and a synchronization and channel estimation module.
[0038] Primarily responsible for handling wireless signal transmission, including operations such as modulation and demodulation, channel coding, and OFDM transformation. Dynamically switch different physical layer parameters through DPR technology, such as modulation methods (QPSK, 16-QAM) or channel coding schemes. Collect wireless channel information, such as signal-to-noise ratio, bit error rate, and throughput, and provide real-time feedback to the processing system module.
[0039] (3) The dynamic partial reconfiguration (DPR) module, including a device configuration unit, a reconfigurable area, and a partial configuration bitstream storage unit. The dynamic partial reconfiguration (DPR) module is set on the programmable logic (FPGA) module.
[0040] Mainly control partial areas of the FPGA through the device configuration unit to achieve dynamic hardware replacement of the wireless physical layer module. Store multiple predefined physical layer configuration bitstreams and load the optimal configuration according to changes in the communication environment during operation. Through the DPR mechanism, optimize physical layer resource allocation without interrupting communication and improve flexibility.
[0041] (4) The multi-armed bandit (MAB) online learning and optimization module, including a hardware acceleration unit for the upper confidence bound algorithm, a reward value storage unit, and a channel evaluation and decision unit. The online learning and optimization module is set on the ARM processor.
[0042] Primarily responsible for adaptively selecting the optimal channel in a dynamic wireless environment to improve communication quality. Calculate the average throughput, bit error rate, and interference situation of the channel based on historical data and optimize the channel selection strategy. Combine physical layer feedback to optimize the exploration and exploitation strategies of the MAB algorithm and improve learning efficiency.
[0043] (5) The high-speed data interaction interface module, including the AXI-Lite bus ( control signal transmission), the AXI-Stream bus (physical layer data transmission inside the FPGA), and the UART interface (data debugging and monitoring).
[0044] Enable high-speed communication between the ARM processor and the FPGA to ensure that MAB decisions can affect the wireless physical layer configuration in real time. Optimize the internal data flow of the physical layer, reduce the latency of signal processing, and increase data throughput. Support external monitoring and debugging, and can adjust MAB learning parameters in real time to improve system intelligence.
[0045] Example 2, a method for dynamically configuring a wireless physical layer, includes the following steps:
[0046] The first step: System initialization
[0047] (1) At system startup, the ARM processor loads the Multi-Armed Bandit (MAB) algorithm and initializes the wireless channel environment parameters, such as the number of available channels K, the initialized QPSK modulation mode, the channel quality evaluation metrics, etc.
[0048] (2) Load the default physical layer configuration on the FPGA side, including the modulation and demodulation module, the OFDM waveform processing module, the channel coding module, etc.
[0049] (3) Enable the initial channel (default channel 1) and start transmitting data.
[0050] Step 2: Wireless environment perception and online learning
[0051] (1) Channel state acquisition
[0052] During the communication process, continuously monitor the wireless channel state, collect key parameters (signal-to-noise ratio, bit error rate, throughput, interference situation), and calculate the reward value R of the current channel n ;
[0053] Among them, P R is the power of the received pilot; P T is the power of the transmitted pilot.
[0054] These parameters are transmitted to the ARM processor through the AXI-Lite interface.
[0055] (2) Parameter update
[0056] For the currently selected channel k, k ∈ {1, 2,..., K}, update the cumulative reward:
[0057] X(k,n) = X(k,n - 1) + R n ;
[0058] Update the number of times this channel has been selected:
[0059] T(k,n) = T(k,n - 1) + 1
[0060] Where:
[0061] Wireless communication time slot n: The entire wireless communication process is divided into N time slots, that is, n ∈ {1, 2,..., N}.
[0062] Reward value storage X(k,n): Store the cumulative income of channel k at time slot n.
[0063] Attempt number storage T(k,n): Record the number of times channel k has been selected at time slot n.
[0064] (3) MAB algorithm decision
[0065] 1) The Upper Confidence Bound (UCB) algorithm is adopted to evaluate the long-term benefits of each channel. Calculate the Quality Factor (QF) of channel k:
[0066]
[0067] Where:
[0068] The exploration factor α, α ∈ (0.5, 2);
[0069] 2) Channel selection
[0070] Calculate the QF values of all channels and select the channel with the largest QF:
[0071]
[0072] This channel will be used for data transmission later.
[0073] Step 3: Intelligent modulation and channel dynamic switching
[0074] By exploring and trying different channels and modulation schemes to understand their performance, and by exploiting to select the best channel and modulation method to optimize the communication quality.
[0075] (1) Adaptive switching of modulation mode
[0076] If the channel quality is good (high SNR): Automatically switch to 16-QAM to increase the data transmission rate.
[0077] If the channel quality is poor (low SNR): Switch to QPSK to enhance the anti-interference ability.
[0078] Due to burst interference or spectrum reuse conflicts, etc., low SNR will be generated. Set an SNR threshold to distinguish high SNR or low SNR.
[0079] The FPGA dynamically adjusts the modulation module and switches the modulation scheme without interrupting the communication through the DPR technology.
[0080] (2) Optimal channel selection
[0081] If the interference of the current channel increases or the quality deteriorates, select a new optimal channel according to the MAB algorithm. Notify the FPGA through the AXI interface and perform channel switching at the physical layer.
[0082] The judgment of increased interference or deteriorated quality can be set with thresholds or percentages manually for evaluation.
[0083] Step 4: Dynamic Partial Reconfiguration (DPR)
[0084] (1) Trigger the DPR mechanism
[0085] If the physical layer detects a sharp decline in channel quality (such as burst interference or spectrum reuse conflict), the ARM side triggers the DPR mechanism.
[0086] Dynamically update the physical layer architecture of the FPGA side through the device configuration unit, for example:
[0087] 1) Replace with a new channel coding scheme
[0088] 2) Adjust the OFDM subcarrier spacing
[0089] 3) Replace the filter parameters
[0090] (2) Fast reconfiguration
[0091] Through DPR, the physical layer can complete module updates in milliseconds without system reboot or communication interruption.
[0092] The present invention is based on the ARM+FPGA architecture, and realizes the deep integration of dynamic partial reconfiguration and online machine learning through software and hardware co-design. The architecture of the present invention supports the dynamic switching of OFDM waveforms and QPSK / 16-QAM modulation methods, and uses the MAB algorithm to optimize channel selection in real time. It realizes efficient wireless channel selection, adaptive modulation and dynamic hardware reconfiguration. The architecture can adjust communication parameters in real time in a dynamically changing wireless environment, improve system throughput and reduce the bit error rate.
[0093] The above are only the preferred embodiments of the present invention, and do not impose any limitations on the present invention. Any simple modifications, changes and equivalent structural changes made to the above embodiments according to the technical essence of the present invention still fall within the protection scope of the technical solution of the present invention.
Claims
1. An intelligent reconfigurable wireless communication physical layer architecture, characterized in that, Including: A system processing module, an online learning and optimization module, a programmable logic FPGA module, and a dynamic partial reconfiguration DPR module; The system processing module includes an ARM processor, a high-speed storage unit, and an on-chip interconnect bus; It is used for intelligent channel selection and modulation mode optimization, communicates with the programmable logic FPGA module to achieve dynamic adjustment of wireless physical layer parameters, and triggers the dynamic partial reconfiguration DPR module to perform hardware reconfiguration on the physical layer module; The programmable logic FPGA module includes a wireless transceiver, a modulation and demodulation module, a channel coding and decoding module, an OFDM waveform processing module, and a synchronization and channel estimation module; it is used for wireless signal transmission, modulation and demodulation, channel coding, OFDM transformation operations, and dynamically switching different physical layer parameters through DPR and real-time acquisition of wireless channel information.
2. The intelligent reconfigurable radio communication physical layer architecture according to claim 1, characterized in that The ARM processor of the system processing module is provided with an online learning and optimization module, including a hardware acceleration unit for the upper confidence bound algorithm, a reward value storage unit, and a channel evaluation and decision-making unit; it is used for adaptively selecting the optimal channel in a dynamic wireless environment to improve communication quality.
3. The intelligent reconfigurable wireless communication physical layer architecture according to claim 2, characterized in that, The online learning and optimization module adopts the multi-armed bandit MAB algorithm.
4. An intelligent reconfigurable wireless communication physical layer architecture according to claim 2, characterized in that The adaptive selection of the optimal channel is as follows: combining the physical layer feedback, optimizing the exploration and exploitation strategies of the MAB algorithm, calculating the average throughput, bit error rate, and interference situation of the channel according to historical data, and optimizing the channel selection strategy.
5. An intelligent reconfigurable wireless communication physical layer architecture according to claim 1, characterized in that, In the programmable logic FPGA module, the physical layer parameters include but are not limited to the modulation mode or channel coding scheme; the wireless channel information includes but is not limited to the signal-to-noise ratio, bit error rate, and throughput.
6. The intelligent reconfigurable wireless communication physical layer architecture according to claim 1, wherein The programmable logic FPGA module is provided with a dynamic partial reconfiguration DPR module, including a device configuration unit, a reconfigurable area, and a partial configuration bitstream storage unit; it is used to control the FPGA through the device configuration unit to achieve dynamic hardware replacement of the wireless physical layer module, store multiple predefined physical layer configuration bitstreams; and load the optimal configuration according to the change of the communication environment during operation; optimize the physical layer resource allocation through the DPR mechanism without interrupting communication.
7. An intelligent reconfigurable wireless communication physical layer architecture according to claim 1, characterized in that, The AXI-Lite bus is used for the transmission of control signals between the ARM and the FPGA; the AXI-Stream bus is used for the data transmission of the internal physical layer of the FPGA; the UART interface is used for data debugging and monitoring.
8. A dynamic configuration method for an intelligent reconfigurable wireless communication physical layer architecture, characterized in that, Including the following steps: The ARM processor loads the multi-armed bandit MAB algorithm, initializes the wireless channel state and key parameters; the FPGA module loads the default physical layer configuration; enables the initial channel and starts transmitting data; During the communication process, the online learning and optimization module continuously monitors the wireless channel state and key parameters, and calculates the reward value R of the current channel n ; where P R is the power of the received pilot; P T is the power of the transmitted pilot; for the currently selected channel k, k ∈ {1, 2,..., K}, update the cumulative reward of this channel at time slot n: X(k, n) = X(k, n - 1) + R n ; update the number of times this channel is selected at time slot n: T(k, n) = T(k, n - 1) + 1; use the upper confidence bound algorithm to evaluate the long-term benefits of each channel; The ARM processor automatically switches to the 16-QAM or QPSK mode according to the channel quality, triggers the dynamic partial reconfiguration DPR module to switch the modulation scheme without interrupting communication; if the interference of the current channel increases or the quality decreases, selects a new optimal channel according to the MAB algorithm, and controls the programmable logic FPGA module to perform channel switching at the physical layer; The dynamic partial reconfiguration DPR module receives the ARM trigger, and dynamically updates the physical layer architecture of the FPGA module through the device configuration unit to quickly reconfigure the FPGA module.
9. The intelligent reconfigurable wireless communication physical layer architecture according to claim 8, characterized in that The wireless channel state and key parameters include but are not limited to the number of available channels K, the initialized QPSK modulation mode, and the channel quality evaluation index.
10. An intelligent reconfigurable wireless communication physical layer architecture according to claim 8, characterized in that, The upper confidence bound algorithm includes: Calculating the quality factor QF of channel k: where: the exploration factor α ∈ (0.5, 2); Calculate the QF values of all channels and select the channel with the largest QF value for data transmission.