Semiconductor device and method of manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a method of manufacturing the same. The semiconductor device may include: a gate structure including conductive layers and insulating layers alternately stacked; a metal channel layer extending through the gate structure; a first semiconductor channel layer extending through the gate structure and connected to the metal channel layer; and a ferroelectric layer surrounding the metal channel layer and the first semiconductor channel layer.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to an electronic device, and more particularly, to a semiconductor device and a method of manufacturing a semiconductor device. Background Art

[0002] The integration degree of a semiconductor device is mainly determined by the area occupied by a unit memory cell. Recently, as the improvement of the integration degree of a semiconductor device in which memory cells are formed as a single layer on a substrate has reached a limit, three-dimensional semiconductor devices in which memory cells are stacked on a substrate have been proposed. In addition, in order to improve the operation reliability of three-dimensional semiconductor devices, various structures and manufacturing methods are being developed. Summary of the Invention

[0003] According to an embodiment of the present disclosure, a three-dimensional semiconductor device (hereinafter simply referred to as a semiconductor device) may include: a gate structure including a conductive layer and an insulating layer alternately stacked; a metal channel layer extending through the gate structure; a first semiconductor channel layer located in the gate structure and connected to the metal channel layer; and a ferroelectric layer surrounding the metal channel layer and the first semiconductor channel layer.

[0004] According to an embodiment of the present disclosure, a semiconductor device may include: a bit line; a memory string including a ferroelectric memory cell and a drain select transistor, the ferroelectric memory cell including a metal channel layer and the drain select transistor including a first semiconductor channel layer; a word line connected to the ferroelectric memory cell; and a drain select line connected to the drain select transistor and controlling the connection between the memory string and the bit line.

[0005] According to an embodiment of the present disclosure, a method of manufacturing a semiconductor device may include the steps of: forming a stack including a first material layer and a second material layer alternately stacked; forming a first opening in the stack; forming a ferroelectric layer in the first opening; forming a metal channel layer in the ferroelectric layer; forming a second opening by partially etching the metal channel layer; and forming a first semiconductor channel layer in the second opening.

[0006] According to an embodiment of the present disclosure, a method of manufacturing a semiconductor device may include the steps of: forming a source line; forming a source select line on the source line; forming a stack including a first material layer and a second material layer alternately stacked on the source select line; forming an opening extending through the stack and the source select line to the source line; forming a second semiconductor channel layer in the opening that passes through the source select line and is connected to the source line; forming a metal channel layer in the opening that extends through the stack and is connected to the second semiconductor channel layer; and forming a first semiconductor channel layer in the opening that extends through the stack and is connected to the metal channel layer. Brief Description of the Drawings

[0007] Figure 1 is a circuit diagram illustrating a cell array of a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 2A and Figure 2B is a diagram illustrating a method of operating a semiconductor device according to an embodiment of the present disclosure.

[0009] Figures 3A to 3C is a diagram illustrating the structure and operation of a semiconductor device according to an embodiment of the present disclosure.

[0010] Figures 4A to 4C is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 5 is a circuit diagram illustrating a cell array of a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 6A and Figure 6B is a diagram illustrating a method of operating a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 7 is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0014] Figures 8A to 8F is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Detailed Description

[0015] Various embodiments of the present disclosure provide a semiconductor device having a stable structure and improved characteristics and a method of manufacturing the semiconductor device.

[0016] The integration degree of a semiconductor device can be increased by three-dimensional stacked memory cells. In addition, a semiconductor device having a stable structure and improved reliability can be provided.

[0017] Hereinafter, embodiments according to the technical spirit of the present disclosure will be described with reference to the accompanying drawings.

[0018] Figure 1 is a circuit diagram illustrating a cell array of a semiconductor device according to an embodiment of the present disclosure.

[0019] Refer to Figure 1, a semiconductor device may include bit lines BL1 to BLk, memory strings MS, word lines WL1 to WLn, and drain select lines DSL. Each memory string MS may include at least one drain select transistor DST and a plurality of ferroelectric memory cells MC1 to MCn. Here, the ferroelectric memory cells MC1 to MCn may be ferroelectric tunnel junction (FTJ) elements. The word lines WL1 to WLn may be connected to the gate electrodes of the ferroelectric memory cells MC1 to MCn. The drain select line DSL may be connected to the gate electrode of the drain select transistor DST. Here, k and n may be integers of 1 or greater.

[0020] The drain select transistor DST may control the connection between the memory string MS and the bit line BL. The drain select transistor DST may include a semiconductor channel layer. In an embodiment, the semiconductor channel layer may include polysilicon.

[0021] The ferroelectric memory cells MC1 to MCn may store data according to the polarization state of the ferroelectric layer. The ferroelectric memory cells MC1 to MCn may include a channel layer having a carrier mobility greater than that of the semiconductor channel layer of the drain select transistor DST. The ferroelectric memory cells MC1 to MCn may include a metal channel layer. In an embodiment, the metal channel layer may include a metal such as titanium or tungsten.

[0022] According to the above configuration, the memory integration of the semiconductor device can be increased by increasing the number of ferroelectric memory cells MC1 to MCn included in the memory string MS. Since the ferroelectric memory cells MC1 to MCn include a metal channel layer having a large carrier mobility, the operation speed can be improved. In addition, by using the drain select transistor DST as a switch, the selected memory string and the unselected memory string can be distinguished and operated.

[0023] In addition, the cell array according to an embodiment of the present disclosure can be used for analog computing in memory operations. Referring to Equation 1, by mapping the voltages applied to the word lines WL1 to WLn to an input vector and mapping the conductance of the ferroelectric memory cell MC to a weight vector, an output vector output through the bit line BL can be calculated by performing a multiply-accumulate (MAC) operation. Therefore, the cell array can be used to perform the analog operations required for AI operations inside the memory.

[0024] [Equation 1]

[0025]

[0026] Figure 2A and Figure 2B are diagrams illustrating a method of operating a semiconductor device according to an embodiment of the present disclosure. Hereinafter, descriptions overlapping with the above may be omitted.

[0027] Referring to Figure 2A , during an erase operation, a conduction voltage can be applied to the drain select lines DSL1 and DSL2, and a ground voltage can be applied to the bit lines BL1 and BL2. Here, the conduction voltage can be about 2V. Thus, the memory strings MS1 to MS4 can be connected to the bit lines BL1 and BL2, and the channel potentials of the memory strings MS1 to MS4 can have a ground level. An erase voltage Vers can be applied to the word lines WL1 to WLn. Here, the erase voltage Vers can be a negative voltage. Thus, the ferroelectric layers of the ferroelectric memory cells MC1 to MCn can have a first polarization state. Therefore, an erase operation can be performed on all the memory strings MS1 to MS4 belonging to the memory block.

[0028] Referring to Figure 2B , during a programming operation, a conduction voltage can be applied to the selected first drain select line DSL1 and a first bit line voltage can be applied to the selected first bit line BL1. Here, the first bit line voltage can be a ground voltage. Thus, the channel potential of the selected first memory string MS1 can have a ground level.

[0029] A programming voltage Vpgm can be applied to the selected word line WL2, and a pass voltage Vpass can be applied to the unselected word lines WL1 and WL3 to WLn. Here, the programming voltage Vpgm can be a positive voltage, and the pass voltage Vpass can be Vpgm / 2. Thus, the ferroelectric layer of the selected second memory cell MC2 can have a second polarization state through the programming voltage Vpgm. Therefore, a programming operation can be performed on the selected second memory cell MC2.

[0030] In addition, among the unselected memory strings MS2 to MS4, the second memory string MS2 can share the first drain select line DSL1 with the selected first memory string MS1 and can not share the first bit line BL1. Therefore, a second bit line voltage higher than the first bit line voltage can be applied to the unselected second bit line BL2. Here, the second bit line voltage can be the operating voltage Vcc. Thus, the drain select transistor DST can be turned off and the channel of the second memory string MS2 can be floated. The floated channel can be boosted with respect to the programming voltage Vpgm and the pass voltage Vpass, and the programming operation of the unselected second memory string MS2 can be prohibited.

[0031] Among the unselected memory strings MS2 to MS4, the third memory string MS3 can not share the first drain select line DSL1 with the selected first memory string MS1 and can share the first bit line BL1. Therefore, a ground voltage can be applied to the unselected second drain select line DSL2, and the programming operation of the unselected third memory string MS3 can be prohibited.

[0032] Among the unselected memory strings MS2 to MS4, the fourth memory string MS4 may not share the first drain select line DSL1 with the selected first memory string MS1 and may not share the first bit line BL1. A ground voltage may be applied to the unselected second drain select line DSL2, and a second bit line voltage higher than the first bit line voltage may be applied to the unselected second bit line BL2. In an embodiment, the second bit line voltage may be Vpgm / 2. Thereby, the programming operation of the unselected fourth memory string MS4 may be prohibited.

[0033] Figures 3A to 3C is a diagram illustrating the structure and operation of a semiconductor device according to an embodiment of the present disclosure. Figure 3B and Figure 3C is Figure 3A an enlarged view of region A in. Hereinafter, descriptions overlapping with the above may be omitted.

[0034] Referring to Figure 3A , the semiconductor device may include a gate structure GST, a metal channel layer 35, a first semiconductor channel layer 36, and a ferroelectric layer 34. The semiconductor device may also include at least one of an interface layer 33 and an insulating core 37.

[0035] The gate structure GST may include a conductive layer 31 and an insulating layer 32 that are alternately stacked. The ferroelectric layer 34 may pass through the gate structure GST. The metal channel layer 35 may extend through the lower part of the gate structure GST, and the first semiconductor channel layer 36 may extend through the upper part of the gate structure GST. The first semiconductor channel layer 36 may be located above the metal channel layer, wherein the lower surface of the first semiconductor channel layer 36 contacts the outside (side part 35A) of the upper surface of the metal channel layer 35.

[0036] The ferroelectric layer 34 may laterally surround the side surfaces of the metal channel layer 35 and the side surfaces of the first semiconductor channel layer 36.

[0037] In an embodiment, the conductive layer 31 may be a word line and / or a drain select line. In an embodiment, at least one uppermost conductive layer 31 among the conductive layers 31 may be a drain select line, and the remaining conductive layers 31 may be word lines. The conductive layer 31 may include a conductive material such as, for example, polysilicon, tungsten (W), or molybdenum (Mo). In an embodiment, the conductive layer 31 may include a barrier layer 31A and a metal layer 31B in the barrier layer 31A. The barrier layer 31A may include a metal nitride such as, for example, titanium nitride (TiN), and the metal layer 31B may include tungsten (W).

[0038] The metal channel layer 35 may extend through the gate structure GST. The metal channel layer 35 may include a first metal layer 35A, a barrier layer 35B, and a second metal layer 35C, all of which also extend through the gate structure GST in a direction perpendicular to the conductive layer 31 and the insulating layer 32. The barrier layer 35B may surround the second metal layer 35C, and the first metal layer 35A may surround the barrier layer 35B. In an embodiment, the first metal layer 35A may include titanium (Ti), the barrier layer 35B may include a metal nitride such as titanium nitride (TiN) for example, and the second metal layer 35C may include tungsten (W).

[0039] The first semiconductor channel layer 36 may be located in the gate structure GST. The first semiconductor channel layer 36 may be located above the metal channel layer 35. The first semiconductor channel layer 36 may extend through the gate structure GST and may be connected to the metal channel layer 35. The first semiconductor channel layer 36 may include a polysilicon layer 36A and a metal silicide layer 36B. The metal silicide layer 36B may be located between the polysilicon layer 36A and the metal channel layer 35. Figure 3A An embodiment is shown in which the metal silicide layer 36B is formed at the interface between the first metal layer 35A and the first semiconductor channel layer 36, but the metal silicide layer may be formed at the interface between the barrier layer 35B and the first semiconductor channel layer 36 or at the interface between the second metal layer 35C and the first semiconductor channel layer 36. During the silicidation reaction, the reactivity of the first metal layer 35A, the barrier layer 35B, and the second metal layer 35C may be different, and a relatively thick metal silicide layer 36B may be formed at the interface between the first metal layer 35A and the first semiconductor channel layer 36. An ohmic contact may be formed between the first semiconductor channel layer 36 and the metal channel layer 35 through the metal silicide layer 36B.

[0040] The insulating core 37 may be located in the first semiconductor channel layer 36. The first semiconductor channel layer 36 may surround the sidewalls of the insulating core 37 and extend between the insulating core 37 and the metal channel layer 35. In an embodiment, the insulating core 37 may include an insulating material such as an oxide or a nitride for example.

[0041] The ferroelectric layer 34 may surround the first semiconductor channel layer 36 and the metal channel layer 35. The ferroelectric layer 34 may include hafnium oxide (HfO), hafnium zirconium oxide (HfZrO), etc.

[0042] The interface layer 33 may surround the ferroelectric layer 34. The interface layer 33 may include a dielectric material such as, for example, tantalum oxide (Ta2O5). When a high-pressure heat treatment process is performed after forming the tantalum oxide layer, oxygen bonds in the tantalum oxide layer may be broken and oxygen vacancies Vo++ of positive ions may be generated. Due to the oxygen vacancies Vo++ in the interface layer 33, an imprinting field may be applied to the ferroelectric layer 34, and the ferroelectric memory cell may have a self-rectifying characteristic.

[0043] According to the above structure, the ferroelectric memory cell MC may be located in a region where the metal channel layer 35 intersects with the conductive layer 31. The ferroelectric memory cells MC may be stacked along the metal channel layer 35. The drain select transistor DST may be located in a region where the first semiconductor channel layer 36 intersects with the conductive layer 31. The ferroelectric memory cells MC and at least one drain select transistor DST stacked along the metal channel layer 35 and the first semiconductor channel layer 36 connected to each other may constitute a memory string.

[0044] Refer to Figure 3B , during an erase operation, an erase voltage Vers may be applied to the word line WL, and the ferroelectric layer 34 may be polarized to a first polarization state by the erase voltage Vers. Accordingly, an erase operation may be performed on the ferroelectric memory cells MC included in the memory block at once.

[0045] Refer to Figure 3C , during a program operation, a program voltage Vpgm may be applied to the selected word line sel_WL, and a voltage Vpass may be applied to the unselected word line unsel_WL. Thereby, the ferroelectric layer 34 of the selected ferroelectric memory cell MC may be switched to a second polarization state, and the ferroelectric layer 34 of the unselected ferroelectric memory cell MC may maintain the first polarization state. Accordingly, a program operation may be performed only on the selected ferroelectric memory cell MC.

[0046] Figures 4A to 4C is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Hereinafter, descriptions overlapping with the above may be omitted.

[0047] Refer to Figure 4A, a stack ST can be formed on a substrate 40. The stack ST may include a first material layer 41 and a second material layer 42 alternately stacked above the substrate 40. The lowermost second material layer 42 may be in contact with the substrate 40. The uppermost second material layer 42 may be the topmost layer of the stack ST. The first material layer 41 may be used to form gate lines such as, for example, word lines and drain select lines. In an embodiment, at least one uppermost first material layer 41 may be used to form drain select lines, and the remaining first material layer 41 may be used to form word lines. The first material layer 41 may include a sacrificial material such as, for example, a nitride or a conductive material such as, for example, polysilicon or metal. The second material layer 42 may insulate the stacked gate lines from each other. The second material layer 42 may also be used to insulate the stack ST from the substrate 40 and to insulate the stack ST from structures located above the stack ST. The second material layer 42 may include an insulating material such as, for example, an oxide or a nitride. The second material layer 42 may include air gaps. Subsequently, a first opening OP1 may be formed in the stack ST. The first opening OP1 may extend through the stack ST and may have a depth that exposes the substrate 40. Subsequently, an interface layer 43 may be formed in the first opening OP1. The interface layer 43 may be conformally formed along the inner surface of the first opening OP1. The interface layer 43 may be conformally formed on the inner wall and the lower surface of the first opening OP1. The lower surface of the first opening refers to the bottom wall surface of the first opening OP1. The interface layer 43 may include a dielectric material such as, for example, tantalum oxide (Ta2O5).

[0048] Subsequently, a ferroelectric layer 44 may be formed in the first opening OP1. The ferroelectric layer 44 may be conformally formed along the profile of the interface layer 43. The ferroelectric layer 44 may be formed on the inner wall and the lower surface of the first opening OP1.

[0049] Subsequently, a metal channel layer 45 may be formed in the first opening OP1. The metal channel layer 45 may be formed to fill the first opening OP1. The metal channel layer 45 may be formed as a single layer or multiple layers. The metal channel layer 45 may include a first metal layer 45A, a barrier layer 45B, and a second metal layer 45C. In an embodiment, the first metal layer 45A may be conformally formed along the profile of the ferroelectric layer 44, the barrier layer 45B may be conformally formed along the profile of the first metal layer 45A, and the second metal layer 45C may be formed in the barrier layer 45B. The barrier layer 45B may surround the sidewalls and the lower surface of the second metal layer 45C, and the first metal layer 45A may surround the sidewalls and the lower surface of the barrier layer 45B. The ferroelectric layer 44 may surround the sidewalls and the lower surface of the metal channel layer 45.

[0050] Refer to Figure 4B, the second opening OP2 can be formed by etching a part of the metal channel layer 45. In an embodiment, a wet etching process can be used to etch the metal channel layer 45. The part of the metal channel layer 45 corresponding to the drain select line can be removed.

[0051] Referring to Figure 4C , the first semiconductor channel layer 46 can be formed in the second opening OP2. The first semiconductor channel layer 46 can be conformally formed along the inner surface of the second opening OP2. The first semiconductor channel layer 46 can be conformally formed along the profiles of the ferroelectric layer 44 and the metal channel layer 45. In an embodiment, after the first semiconductor channel layer 46 is formed by depositing a polysilicon layer, a heat treatment process can be performed. Through the heat treatment process, the silicon of the first semiconductor channel layer 46 and the metal of the metal channel layer 45 can react, and a metal silicide layer 46A can be formed through a silicidation reaction. The metal silicide layer 46A can be formed at the part of the first semiconductor channel layer 46 in contact with the metal channel layer 45. Thus, the first semiconductor channel layer 46 can be partially silicided, and an ohmic contact can be formed between the metal channel layer 45 and the first semiconductor channel layer 46. In an embodiment, the first semiconductor channel layer 46 and the first metal layer 45A can react, and thus titanium silicide can be formed. The first semiconductor channel layer 46 including the polysilicon layer 46B and the metal silicide layer 46A located between the polysilicon layer 46B and the metal channel layer 45 can be formed.

[0052] Subsequently, the insulating core 47 can be formed in the first semiconductor channel layer 46. The second opening OP2 can be filled with the insulating core 47. The insulating core 47 can include an insulating material such as, for example, polysilazane (PSZ), oxide, or nitride.

[0053] Subsequently, the first material layer 41 can be replaced with a third material layer 49. In an embodiment, after the third opening OP3 is formed by removing the first material layer 41, the third material layer 49 can be formed in the third opening OP3. The third material layer 49 can be a gate line and can include a conductive material such as, for example, metal. After a barrier layer 49A is formed in the third opening P3, a metal layer 49B can be formed in the barrier layer 49A. The barrier layer 49A can include titanium nitride (TiN), and the metal layer 49B can include tungsten (W).

[0054] Thus, a gate stack GST including alternately stacked second material layers 42 and third material layers 49 can be formed. A ferroelectric memory cell can be formed in the region where the third material layer 49 intersects the metal channel layer 45, and a drain select transistor can be formed in the region where the first semiconductor channel layer 46 intersects the third material layer 49.

[0055] When the first material layer 41 includes a conductive material, the process of replacing the first material layer 41 with the third material layer 49 can be omitted. In this case, the first material layer 41 can be used as a gate line, and the stack ST can be used as a gate structure GST.

[0056] According to the above manufacturing method, a ferroelectric memory cell including a metal channel layer 45 and a drain select transistor including a first semiconductor channel layer 46 can be formed.

[0057] Figure 5 It is a circuit diagram illustrating a cell array of a semiconductor device according to an embodiment of the present disclosure. Hereinafter, descriptions overlapping with the above may be omitted.

[0058] Refer to Figure 5 , the semiconductor device may include bit lines BL1 to BLk, memory strings MS, word lines WL1 to WLn, drain select lines DSL, and source select lines SSL. The semiconductor device may further include a source line SL, and the memory string MS may be connected between the bit line BL and the source line SL.

[0059] Each memory string MS may include at least one drain select transistor DST, a plurality of ferroelectric memory cells MC1 to MCn, and at least one source select transistor SST. The ferroelectric memory cells MC1 to MCn may be FTJ elements. The word lines WL1 to WLn may be connected to the gate electrodes of the ferroelectric memory cells MC1 to MCn. The drain select line DSL may be connected to the gate electrode of the drain select transistor DST. The source select line SSL may be connected to the gate electrode of the source select transistor SST. Here, k and n may be integers of 1 or greater.

[0060] The drain select transistor DST may control the connection between the memory string MS and the bit line BL. The drain select transistor DST may include a first semiconductor channel layer. In an embodiment, the first semiconductor channel layer may include polysilicon.

[0061] The source select transistor SST may control the connection between the memory string MS and the source line SL. The source select transistor SST may include a second semiconductor channel layer. In an embodiment, the second semiconductor channel layer may include polysilicon.

[0062] The ferroelectric memory cells MC1 to MCn may store data according to the polarization state of the ferroelectric layer. The ferroelectric memory cells MC1 to MCn may include a channel layer having a carrier mobility greater than that of the first semiconductor channel layer and / or the second semiconductor channel layer. The ferroelectric memory cells MC1 to MCn may include a metal channel layer. In an embodiment, the metal channel layer may include a metal such as titanium or tungsten.

[0063] According to the above configuration, the memory integration degree of the semiconductor device can be increased by increasing the number of ferroelectric memory cells MC1 to MCn included in the memory string MS. Since the ferroelectric memory cells MC1 to MCn include a metal channel layer having a large carrier mobility, the operation speed can be increased. By using the drain select transistor DST as a switch, the selected memory string and the unselected memory string can be distinguished and operated. In addition, by using the source select transistor SST as a switch, the connection between the memory string MS and the source line SL can be controlled.

[0064] Figure 6A and Figure 6B is a diagram illustrating a method of operating a semiconductor device according to an embodiment of the present disclosure. Hereinafter, descriptions overlapping with the above may be omitted.

[0065] Referring to Figure 6A , during an erase operation, a conduction voltage may be applied to the drain select lines DSL1 and DSL2, and a ground voltage may be applied to the bit lines BL1 and BL2. A conduction voltage may be applied to the source select line SSL, and a ground voltage may be applied to the source line SL. Accordingly, the memory strings MS1 to MS4 may be connected to the bit lines BL1 and BL2 at the ground level and the source line SL at the ground level, and the channel potential of the memory strings MS1 to MS4 may have the ground level. An erase voltage Vers may be applied to the word lines WL1 to WLn. Accordingly, the ferroelectric layers of the ferroelectric memory cells MC1 to MCn may have a first polarization state. Therefore, an erase operation may be performed on all the memory strings MS1 to MS4 belonging to the memory block.

[0066] Referring to Figure 6B , a ground voltage may be applied to the source select line SSL, and a source voltage having a level higher than the ground level may be applied to the source line SL. Here, the source voltage may be about 2V. Accordingly, the source select transistor SST may be turned off. A conduction voltage may be applied to the selected first drain select line DSL1 and a first bit line voltage may be applied to the selected first bit line BL1. Here, the first bit line voltage may be a ground voltage. Accordingly, the channel potential of the selected first memory string MS1 may have the ground level.

[0067] A programming voltage Vpgm may be applied to the selected word line WL2, and a pass voltage Vpass may be applied to the unselected word lines WL1 and WL3 to WLn. Here, the pass voltage Vpass may be Vpgm / 2. Accordingly, the ferroelectric layer of the selected second memory cell MC2 may have a second polarization state. Therefore, a programming operation may be performed on the selected second memory cell MC2.

[0068] Among the unselected memory strings MS2 to MS4, the second memory string MS2 may share the first drain select line DSL1 with the selected first memory string MS1 and may not share the first bit line BL1. Accordingly, a second bit line voltage higher than the first bit line voltage may be applied to the unselected second bit line BL2. Here, the second bit line voltage may be an operating voltage Vcc. As a result, the drain select transistor DST may be turned off and the channel of the second memory string MS2 may be floated. The floated channel may be boosted with respect to a programming voltage Vpgm and a pass voltage Vpass, and programming operations of the unselected second memory string MS2 may be prohibited.

[0069] Among the unselected memory strings MS2 to MS4, the third memory string MS3 may not share the first drain select line DSL1 with the selected first memory string MS1, and may share the first bit line BL1. Accordingly, a ground voltage may be applied to the unselected second drain select line DSL2, and programming operations of the unselected third memory string MS3 may be prohibited.

[0070] Among the unselected memory strings MS2 to MS4, the fourth memory string MS4 may not share the first drain select line DSL1 with the selected first memory string MS1, and may not share the first bit line BL1. A ground voltage may be applied to the unselected second drain select line DSL2, and a second bit line voltage higher than the first bit line voltage may be applied to the unselected second bit line BL2. In an embodiment, the second bit line voltage may be Vpgm / 2. As a result, programming operations of the unselected fourth memory string MS4 may be prohibited.

[0071] Figure 7 FIG. is a diagram illustrating a structure of a semiconductor device according to an embodiment of the present disclosure. Hereinafter, descriptions overlapping with the above may be omitted.

[0072] Referring to Figure 7 , the semiconductor device may include a gate structure GST, a metal channel layer 75, a first semiconductor channel layer 76, and a ferroelectric layer 74. The semiconductor device may include at least one of a substrate 60, an insulating layer 61, a source line 62, a buffer layer 63, a source select line 64, a second semiconductor channel layer 66, a second insulating core 67, an interface layer 73, and a first insulating core 77.

[0073] The gate structure GST may include a conductive layer 71 and an insulating layer 72 that are alternately stacked. In an embodiment, the conductive layer 71 may be a word line or a drain select line. The conductive layer 71 may include a barrier layer 71A and a metal layer 71B in the barrier layer 71A.

[0074] The source line 62 can be located between the substrate 70 and the gate structure GST. The source line 62 can include a conductive material such as, for example, polysilicon. The source select line 64 can be located between the source line 62 and the gate structure GST. The source select line 64 can include a conductive material such as, for example, polysilicon. The buffer layer 63 can be located between the source line 62 and the source select line 64. The buffer layer 63 can insulate the source line 62 and the source select line 64 from each other, and can include an insulating material such as, for example, an oxide. The insulating layer 61 can be located between the substrate 60 and the source line 62. The insulating layer 61 can insulate the substrate 60 and the source line 62 from each other, and can include an insulating material such as, for example, an oxide.

[0075] The metal channel layer 75 can extend through the gate structure GST. The metal channel layer 75 can include a first metal layer 75A, a barrier layer 75B, and a second metal layer 75C. The barrier layer 75B can surround the second metal layer 75C, and the first metal layer 75A can surround the barrier layer 75B. In an embodiment, the first metal layer 75A can include titanium (Ti), the barrier layer 75B can include a metal nitride such as, for example, titanium nitride (TiN), and the second metal layer 75C can include tungsten (W).

[0076] The first semiconductor channel layer 76 can extend through the gate structure GST and can be connected to the metal channel layer 75. The first semiconductor channel layer 76 can include a polysilicon layer 76A and a metal silicide layer 76B. The metal silicide layer 76B can be located between the polysilicon layer 76A and the metal channel layer 75. The first insulating core 77 can be located in the first semiconductor channel layer 76.

[0077] The second semiconductor channel layer 66 can extend through the source select line 64 and can be connected to the metal channel layer 75 and the source line 62. The second semiconductor channel layer 66 can pass through the source select line 64 and the buffer layer 63 and can extend into the source line 62. The second insulating core 67 can be located in the second semiconductor channel layer 66.

[0078] The second semiconductor channel layer 66 can include a first semiconductor pattern 66A and a second semiconductor pattern 66B. The second semiconductor pattern 66B can connect the source line 62 and the metal channel layer 75. The first semiconductor pattern 66A can partially surround the sidewalls of the second semiconductor pattern 66B. The first semiconductor pattern 66A can be located between the second semiconductor pattern 66B and the ferroelectric layer 74.

[0079] The second semiconductor channel layer 66 can include polysilicon. The second semiconductor channel layer 66 can include a metal silicide layer 66C in a portion in contact with the metal channel layer 75. Thus, an ohmic contact can be formed between the second semiconductor channel layer 66 and the metal channel layer 75.

[0080] The ferroelectric layer 74 may surround the first semiconductor channel layer 76, the metal channel layer 75, and the second semiconductor channel layer 66. The ferroelectric layer 74 may surround the first semiconductor pattern 66A and expose the second semiconductor pattern 66B. The interface layer 73 may surround the ferroelectric layer 74 and expose the second semiconductor pattern 66B.

[0081] According to the above structure, the ferroelectric memory cell MC may be located in a region where the metal channel layer 75 intersects with the conductive layer 71. The drain select transistor DST may be located in a region where the first semiconductor channel layer 76 intersects with the conductive layer 71. The source select transistor SST may be located in a region where the second semiconductor channel layer 66 intersects with the source select line 64. At least one source select transistor SST, the stacked ferroelectric memory cell MC, and at least one drain select transistor DST stacked along the second semiconductor channel layer 66, the metal channel layer 75, and the first semiconductor channel layer 76 may form a memory string.

[0082] Figures 8A to 8F FIG. is an illustration of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Hereinafter, descriptions overlapping with the above may be omitted.

[0083] Refer to Figure 8A , an insulating layer 81, a source line 82, a buffer layer 83, and a source select line 84 may be formed in the described order above the substrate 80. The insulating layer 81 may be formed on the substrate 80. The insulating layer 81 may cover the top surface of the substrate 80. The source line 82 may include polysilicon, the buffer layer 83 may include an oxide, and the source select line 84 may include polysilicon. The thicknesses of the insulating layer 81, the source line 82, the buffer layer 83, and the source select line 84 may be substantially the same or different. For example, as Figure 8A shown, the insulating layer 81 may be the thinnest of the four layers, the source line may be the thickest of the four layers, and the buffer layer 83 may be thinner than the source select line 84.

[0084] Subsequently, the stack ST may be formed on the source selection line 84. The stack ST may include a first material layer 91 and a second material layer 92 that are alternately stacked. The first material layer 91 may be used to form gate lines such as word lines and drain selection lines. The first material layer 91 may include a sacrificial material such as nitride or may include a conductive material such as polysilicon or metal. The second material layer 92 may insulate the stacked gate lines from each other. The second material layer 92 may include an insulating material such as oxide, nitride, or voids. The lowermost and uppermost layers of the stack ST may be the second material layer 92 and may insulate the stack ST from the source selection line 84 and insulate the stack ST from the structure to be located above the stack ST.

[0085] Subsequently, a first opening OP1 may be formed in the stack ST. The first opening OP1 may extend through the stack ST into the source selection line 84. The first opening OP1 may have a depth that exposes the buffer layer 83.

[0086] Subsequently, an interface layer 93 may be formed in the first opening OP1. The interface layer 93 may be conformally formed along the inner surface of the first opening OP1. The interface layer 93 may be formed on the inner wall and the lower surface of the first opening OP1. The interface layer 93 may include a dielectric material such as tantalum oxide (Ta2O5).

[0087] Subsequently, a ferroelectric layer 94 may be formed in the first opening OP1. The ferroelectric layer 94 may be conformally formed along the profile of the interface layer 93. The ferroelectric layer 94 may be formed on the inner wall and the lower surface of the first opening OP1.

[0088] Subsequently, a first semiconductor pattern 96A may be formed in the first opening OP1. The first semiconductor pattern 96A may be conformally formed along the profile of the ferroelectric layer 94. The first semiconductor pattern 96A may be formed on the inner wall and the lower surface of the first opening OP1.

[0089] Referring Figure 8B , a second opening OP2 may be formed. The buffer layer 83 may be exposed by etching the first semiconductor pattern 96A, the ferroelectric layer 94, and the interface layer 93, and the second opening OP2 may be formed by etching the buffer layer 83. The second opening OP2 may expose the source line 82 and may extend into the source line 82. Thus, an opening that passes through the stack ST, the source selection line 84, and the buffer layer 83 and exposes the source line 82 may be formed.

[0090] Subsequently, a second semiconductor pattern 96B may be formed in the first opening OP1 and the second opening OP2. The second semiconductor pattern 96B may be conformally formed along the contour of the first semiconductor pattern 96A and may be formed on the inner wall and the lower surface of the second opening OP2. The second semiconductor pattern 96B may be connected to the source line 82.

[0091] Referring to Figure 8C , a second insulating core 97 may be formed in the second semiconductor pattern 96B. For example, first, an insulating layer may be formed in the first opening OP1 and the second opening OP2, and then the second insulating core 97 may be formed by etching a part of the insulating layer. The second insulating core 97 may fill the second opening OP2 and only the lower part of the first opening OP1. The upper surface of the second insulating core 97 may correspond to the upper surface of the source select line 84. The upper surface of the second insulating core 97 may be at substantially the same level as the upper surface of the source select line 84.

[0092] Now referring to Figure 8D , the second semiconductor pattern 96B and the first semiconductor pattern 96A exposed by the second insulating core 97 may be etched. Accordingly, portions of the first semiconductor pattern 96A and the second semiconductor pattern 96B corresponding to the stack ST (at the same level as the first material layer 91 and the second material layer 92 of the stack) may be removed by etching. Accordingly, a second semiconductor channel layer 96 including the first semiconductor pattern 96A and the second semiconductor pattern 96B may be formed. The second semiconductor channel layer 96 may extend through the source select line 84 into the source line 82 and may be connected to the source line 82.

[0093] Subsequently, a metal channel layer 95 may be formed. First, a first metal layer 95A may be conformally formed along the contours of the ferroelectric layer 94, the second semiconductor channel layer 96, and the second insulating core 97 exposed through the first opening OP1. Subsequently, a barrier layer 95B may be formed in the first metal layer 95A, and a second metal layer 95C may be formed in the barrier layer 95B. The first metal layer 95A may be in contact with the second semiconductor channel layer 96. The portion of the second semiconductor channel layer 96 in contact with the first metal layer 95A may be silicided, and a metal silicide layer 96C may be formed.

[0094] Referring to Figure 8E , a third opening OP3 may be formed by etching a part of the metal channel layer 95. The portion of the metal channel layer 95 corresponding to the drain select line may be removed, and the upper part of the ferroelectric layer 94 may be exposed.

[0095] Referring to Figure 8F, the first semiconductor channel layer 106 may be formed in the third opening OP3. The first semiconductor channel layer 106 may fill at least a portion of the third opening OP3. As Figure 8F shown in the embodiment of, the first semiconductor channel layer 106 may be conformally formed along the contours of the ferroelectric layer 94 and the metal channel layer 95. The portion of the first semiconductor channel layer 106 that contacts the metal channel layer 95 may be silicided, and a metal silicide layer may be formed at their interface. Subsequently, the first insulating core 107 may be formed in the remaining space of the third opening defined by the first semiconductor channel layer 106. Thus, the third opening OP3 may be filled by the first insulating core 107 and the first semiconductor channel layer 106.

[0096] Subsequently, the first material layer 91 may be replaced with a third material layer 99. For example, in an embodiment, a fourth opening OP4 may be first formed by removing the first material layer 91, and then the fourth opening may be filled with the third material layer 99. After a barrier layer 99A is formed in the fourth opening OP4, a metal layer 99B may be formed in the barrier layer 99A. The barrier layer 99A may include titanium nitride (TiN), and the metal layer 99B may include tungsten (W).

[0097] After the above operations, a gate structure GST including alternately stacked second material layers 92 and third material layers 99 may be formed. A source selection transistor may be formed in a region where the source selection line 84 intersects the second semiconductor channel layer 96. A ferroelectric memory cell may be formed in a region where the third material layer 99 intersects the metal channel layer 95. A drain selection transistor may be formed in a region where the first semiconductor channel layer 106 intersects the third material layer 99. When the first material layer 91 includes a conductive material, the process of replacing the first material layer 91 with the third material layer 99 may be omitted. In this case, the first material layer 91 may be used as a gate line, and the stack ST may be used as the gate structure GST. Additionally, at least one of the insulating layer 81, the source line 82, the buffer layer 83, and the source selection line 84 may be omitted.

[0098] According to the above manufacturing method, a source selection transistor including the second semiconductor channel layer 96, a ferroelectric memory cell including the metal channel layer 95, and a drain selection transistor including the first semiconductor channel layer 106 may be formed.

[0099] Although embodiments in accordance with the technical spirit of the present disclosure have been described with reference to the accompanying drawings, this is only for describing embodiments in accordance with the concept of the present disclosure, and the scope of the present disclosure is not limited to the above embodiments. Within the scope of the technical spirit of the present disclosure, those skilled in the art to which the present disclosure pertains will be able to make various forms of substitution, modification, change, and combination to the embodiments, and these are also included within the scope of the present disclosure.

[0100] Cross - Reference to Related Applications

[0101] This application claims the priority of Korean Patent Application No. 10 - 2024 - 0006842, filed on January 16, 2024, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, the semiconductor device comprising: A gate structure, the gate structure comprising alternately stacked conductive layers and insulating layers; A metal channel layer, the metal channel layer extending through the gate structure; A first semiconductor channel layer, the first semiconductor channel layer being located in the gate structure and connected to the metal channel layer; And A ferroelectric layer, the ferroelectric layer surrounding the metal channel layer and the first semiconductor channel layer.

2. The semiconductor device according to claim 1, wherein, A drain select transistor is located in the region where the first semiconductor channel layer intersects with the conductive layer, and A ferroelectric memory cell is located in the region where the metal channel layer intersects with the conductive layer.

3. The semiconductor device according to claim 1, wherein, The first semiconductor channel layer comprises: A polysilicon layer; and A metal silicide layer, the metal silicide layer being located between the polysilicon layer and the metal channel layer.

4. The semiconductor device according to claim 1, the semiconductor device further comprising: A source line; A source select line, the source select line being located between the source line and the gate structure; And A second semiconductor channel layer, the second semiconductor channel layer extending through the source select line and connected to the metal channel layer and the source line.

5. The semiconductor device according to claim 4, wherein, A drain select transistor is located in the region where the first semiconductor channel layer intersects with the conductive layer, A source select transistor is located in the region where the second semiconductor channel layer intersects with the source select line, and A ferroelectric memory cell is located in the region where the metal channel layer intersects with the conductive layer.

6. The semiconductor device according to claim 4, wherein, The conductive layer comprises a metal, and the source select line comprises polysilicon.

7. The semiconductor device according to claim 1, the semiconductor device further comprising: An interface layer, the interface layer surrounding the ferroelectric layer.

8. The semiconductor device according to claim 7, wherein, The interface layer comprises tantalum oxide Ta2O5.

9. The semiconductor device according to claim 1, the semiconductor device further comprising: An insulating core, the insulating core being located in the first semiconductor channel layer.

10. The semiconductor device according to claim 9, wherein, The first semiconductor channel layer surrounds the sidewall of the insulating core and extends between the metal channel layer and the insulating core.

11. A semiconductor device, the semiconductor device comprising: A bit line; A memory string, the memory string comprising a ferroelectric memory cell and a drain select transistor, the ferroelectric memory cell comprising a metal channel layer, the drain select transistor comprising a first semiconductor channel layer; A word line, the word line being connected to the ferroelectric memory cell; And A drain select line, the drain select line being connected to the drain select transistor and controlling the connection of the memory string to the bit line.

12. The semiconductor device according to claim 11, wherein, During an erase operation, a negative erase voltage is applied to the word line.

13. The semiconductor device according to claim 12, wherein, During the erase operation, a conduction voltage is applied to the drain select line and a ground voltage is applied to the bit line.

14. The semiconductor device according to claim 11, wherein, During a programming operation, a programming voltage is applied to the selected word line among the word lines and a pass voltage is applied to the unselected word lines.

15. The semiconductor device according to claim 14, wherein, During the programming operation, a first bit line voltage is applied to the selected bit line among the bit lines and a second bit line voltage having a higher level than the level of the first bit line voltage is applied to the unselected bit lines.

16. The semiconductor device according to claim 15, wherein, The first bit line voltage is a ground voltage.

17. The semiconductor device according to claim 15, wherein, During the programming operation, a conduction voltage is applied to a selected drain select line among the drain select lines, and a ground voltage is applied to unselected drain select lines.

18. The semiconductor device according to claim 11, wherein the semiconductor device further comprises: a source line; and a source select line that controls connection of the source line to the memory string, wherein each of the memory strings includes a source select transistor, and the source select transistor includes a second semiconductor channel layer.

19. The semiconductor device according to claim 18, wherein, During an erase operation, a conduction voltage is applied to the source select line and a ground voltage is applied to the source line.

20. The semiconductor device according to claim 18, wherein, During a programming operation, a ground voltage is applied to the source select line.

21. A method of manufacturing a semiconductor device, the method comprising the steps of: forming a stack including alternately stacked first and second material layers; forming a first opening in the stack; forming a ferroelectric layer in the first opening; forming a metal channel layer in the ferroelectric layer; forming a second opening by partially etching the metal channel layer; and forming a first semiconductor channel layer in the second opening.

22. The method according to claim 21, wherein, The step of forming the metal channel layer includes the steps of: forming a first metal layer in the ferroelectric layer; forming a barrier layer in the first metal layer; and forming a second metal layer in the barrier layer.

23. The method according to claim 21, wherein the method further comprises the step of: forming an interface layer in the first opening before forming the ferroelectric layer.

24. The method according to claim 23, wherein, The interface layer includes tantalum oxide Ta2O5.

25. The method according to claim 21, wherein the method further comprises the step of: forming a metal silicide layer between the first semiconductor channel layer and the metal channel layer.

26. The method according to claim 21, wherein the method further comprises the step of: replacing the first material layer with a third material layer.

27. A method of manufacturing a semiconductor device, the method comprising the steps of: forming a source line; forming a source select line on the source line; forming a stack including alternately stacked first and second material layers on the source select line; forming an opening that extends through the stack and the source select line to the source line; forming a second semiconductor channel layer in the opening that extends through the source select line and is connected to the source line; forming a metal channel layer in the opening that extends through the stack and is connected to the second semiconductor channel layer; and forming a first semiconductor channel layer in the opening that extends through the stack and is connected to the metal channel layer.

28. The method according to claim 27, wherein, The step of forming the opening includes the steps of: forming a first opening that extends through the stack to the source select line; forming a ferroelectric layer in the first opening; forming a first semiconductor pattern in the ferroelectric layer; and forming a second opening that exposes the source line by etching the ferroelectric layer and the first semiconductor pattern.

29. The method according to claim 28, wherein The step of forming the second semiconductor channel layer includes the steps of: forming a second semiconductor pattern in the first opening and the second opening; and Remove the portions of the first semiconductor pattern and the second semiconductor pattern corresponding to the stack.

30. The method according to claim 28, the method further comprising the steps of: Form an interface layer in the first opening before forming the ferroelectric layer.

31. The method according to claim 30, wherein, The interface layer comprises tantalum oxide Ta2O5.

32. The method according to claim 27, wherein, The step of forming the metal channel layer comprises the steps of: Form a first metal layer in the opening; Form a barrier layer in the first metal layer; and Form a second metal layer in the barrier layer.

33. The method according to claim 27, the method further comprising the steps of: Form a metal silicide layer between the first semiconductor channel layer and the metal channel layer.

34. The method according to claim 27, the method further comprising the steps of: Form a metal silicide layer between the second semiconductor channel layer and the metal channel layer.

35. The method according to claim 27, the method further comprising the steps of: Replace the first material layer with a third material layer.

36. A semiconductor device, the semiconductor device comprising: A gate structure, the gate structure comprising alternating conductive layers and insulating layers stacked; A ferroelectric layer, the ferroelectric layer passing through the gate structure; A metal channel layer, the metal channel layer extending through the lower part of the gate structure; And A first semiconductor channel layer, the first semiconductor channel layer extending through the upper part of the gate structure, the first semiconductor channel layer being located above the metal channel layer, and the lower surface of the first semiconductor channel layer contacting the upper surface of the metal channel layer, Wherein, the ferroelectric layer laterally surrounds the sides of the metal channel layer and the sides of the first semiconductor channel layer.

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