Novel bipolar tunneling field effect transistor

Abstract

The invention discloses a novel bipolar tunneling field effect transistor, and relates to the technical field of semiconductors. The insulating layer is positioned on the upper surface of the substrate; the source region, the channel region, the base region and the emitter region are all located on the upper surface of the insulating layer, and the source region, the channel region, the base region and the emitter region are sequentially arranged on the upper surface of the insulating layer and make contact with one another; wherein the source region, the channel region and the base region form a p-i-n structure of the tunneling field effect transistor, and the channel region, the base region and the emitter region form a PNP structure of the tunneling field effect transistor; the source electrode is located on the upper surface of the source region; the gate oxide layer is located on the upper surface of the channel region, and the gate electrode is located on the upper surface of the gate oxide layer; and the emitter is located on the upper surface of the emitter region. The performance of the tunneling field effect transistor can be improved.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors, and in particular relates to a novel bipolar tunneling field effect transistor. Background Art

[0002] With the continuous development of semiconductor technology, the size of traditional metal-oxide-semiconductor field-effect transistors (MOSFETs) has been continuously reduced. As the size of devices continues to decrease and enter the nanoscale, short channel effects, parasitic effects, and quantum tunneling effects have become increasingly prominent, making power consumption and reliability issues a research hotspot in the field of integrated circuits (ICs), especially power consumption issues. In addition, due to the physical limit of 60mV / Decade of the subthreshold swing of MOSFET, the threshold voltage of traditional MOSFET cannot be further reduced, limiting its performance at low operating voltages.

[0003] Tunneling Field Effect Transistor (TFET) is a new type of semiconductor device. Since its current generation does not rely on thermal electron emission and is not limited by Boltzmann distribution, it has successfully broken through the subthreshold swing limit of 60mV / Dec, making TFET show great potential in low-power and low-operating voltage applications. The working principle of TFET is based on band-to-band tunneling, which uses the tunneling effect to realize the transmission of carriers; in the off state, the leakage current of TFET is extremely low, and in the on state, its switching current ratio (Ion / Ioff) is better than that of traditional MOSFET. Therefore, the low power consumption characteristics of TFET give it a significant advantage in power-sensitive application scenarios such as Internet of Things (IoT) devices and wearable devices.

[0004] Although TFETs have the potential to break through the subthreshold swing limit of traditional MOSFETs, they still face many challenges in practical applications. For example: low on-state current, subthreshold swing degradation, and bipolar effects. These non-ideal effects limit the use of TFETs in high-performance applications. To further optimize the performance, researchers have proposed various structural designs, such as U-gate structures, nanowire structures, and heterostructures. In terms of material selection, in addition to traditional silicon materials, narrow bandgap materials such as III-V materials (e.g., InAs, GaAs) and Ge have also been widely studied to improve the driving ability and switching speed of the devices. However, using structures such as U-gates will undoubtedly increase the process complexity and is not compatible with the current standard CMOS process. Using III-V materials or heterostructures will generate a large number of defects at the interface, deteriorating the subthreshold swing characteristics and current on-off ratio of TFETs.

[0005] Therefore, in view of the above-mentioned many technical problems, it is necessary to provide a TFET structure that is compatible with the current CMOS process and at the same time has a large on-state current, a low off-state current, and a steep subthreshold swing. Summary of the Invention

[0006] To solve the above problems existing in the prior art, the present invention provides a novel bipolar tunneling field effect transistor. The technical problems to be solved by the present invention are realized through the following technical solutions:

[0007] In a first aspect, the present invention provides a novel bipolar tunneling field effect transistor, including:

[0008] A substrate;

[0009] An insulating layer located on the upper surface of the substrate;

[0010] A source region, a channel region, a base region, and an emitter region, all located on the upper surface of the insulating layer. The source region, the channel region, the base region, and the emitter region are arranged in sequence on the upper surface of the insulating layer and are in contact with each other. Among them, the source region, the channel region, and the base region form a p-i-n structure of the tunneling field effect transistor, and the channel region, the base region, and the emitter region form a PNP structure of the tunneling field effect transistor;

[0011] A source electrode located on the upper surface of the source region;

[0012] A gate oxide layer located on the upper surface of the channel region,

[0013] A gate electrode located on the upper surface of the gate oxide layer;

[0014] An emitter electrode located on the upper surface of the emitter region.

[0015] Advantages of the present invention:

[0016] A novel bipolar tunneling field effect transistor provided by the present invention integrates a triode PNP structure on the basis of a traditional tunneling field effect transistor. Through the amplification effect of the built-in PNP structure, a larger on-state current is obtained when the device is in the on state. At the same time, the present invention provides a base region with a low doping concentration, solves the problem of large leakage current in the existing tunneling field effect transistor, ensures the low-power consumption characteristic of the tunneling field effect transistor, ensures that the subthreshold swing characteristic of the device does not deteriorate, and obtains a larger switching current ratio. In addition, the present invention also has the advantage of being compatible with the traditional CMOS process.

[0017] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a schematic diagram of a novel bipolar tunneling field effect transistor provided by an embodiment of the present invention;

[0019] Figure 2 is a schematic diagram of the working principle of a novel bipolar tunneling field effect transistor provided by an embodiment of the present invention;

[0020] Figure 3 is an energy band diagram of the bipolar tunneling field effect transistor provided by an embodiment of the present invention and a traditional tunneling field effect transistor in the off state;

[0021] Figure 4 is a comparison diagram of the tunneling probability of the bipolar tunneling field effect transistor provided by an embodiment of the present invention and a traditional tunneling field effect transistor in the off state;

[0022] Figure 5 is an energy band diagram of the bipolar tunneling field effect transistor provided by an embodiment of the present invention and a traditional tunneling field effect transistor in the on state;

[0023] Figure 6 is a comparison diagram of the transfer characteristic curves of the bipolar tunneling field effect transistor provided by an embodiment of the present invention and a traditional tunneling field effect transistor;

[0024] Figure 7 is a comparison diagram of the subthreshold swing characteristics of the bipolar tunneling field effect transistor provided by an embodiment of the present invention and a traditional tunneling field effect transistor. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] The present invention will be further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0026] Please refer to Figure 1 , Figure 1It is a schematic diagram of a novel bipolar tunneling field-effect transistor provided by an embodiment of the present invention. A novel bipolar tunneling field-effect transistor provided by the present invention includes:

[0027] Substrate 1;

[0028] Insulating layer 2, located on the upper surface of substrate 1;

[0029] Source region 3, channel region 4, base region 5, and emitter region 6 are all located on the upper surface of insulating layer 2. The source region 3, channel region 4, base region 5, and emitter region 6 are arranged in sequence on the upper surface of insulating layer 2 and are in contact with each other. Among them, the source region 3, channel region 4, and base region 5 form the p-i-n structure of the tunneling field-effect transistor, and the channel region 4, base region 5, and emitter region 6 form the PNP structure of the tunneling field-effect transistor;

[0030] Source electrode 7, located on the upper surface of source region 3;

[0031] Gate oxide layer 8, located on the upper surface of channel region 4,

[0032] Gate electrode 9, located on the upper surface of gate oxide layer 8;

[0033] Emitter 10, located on the upper surface of emitter region 6.

[0034] Specifically, please continue to refer to Figure 1, the novel bipolar tunneling field-effect transistor provided in this embodiment includes a substrate 1, an insulating layer 2, a source region 3, a channel region 4, a base region 5, an emitter region 6, a source electrode 7, a gate oxide layer 8, a gate electrode 9, and an emitter electrode 10; wherein, the insulating layer 2 is located on the upper surface of the substrate 1, and the source region 3, the channel region 4, the base region 5, and the emitter region 6 are arranged in sequence on the upper surface of the insulating layer 2. The source region 3 is in contact with the channel region 4, the channel region 4 is in contact with the base region 5, and the emitter region 6 is in contact with the base region 5. The source electrode 7 is located on the upper surface of the source region 3, and the orthographic projection of the source electrode 7 on the substrate 1 is within the orthographic projection of the source region 3 on the substrate 1. The gate oxide layer 8 is located on the upper surface of the channel region 4, the gate electrode 9 is located on the upper surface of the gate oxide layer 8, and the orthographic projections of the gate oxide layer 8 and the gate electrode 9 on the substrate 1 are within the orthographic projection of the channel region 4 on the substrate 1. The emitter electrode 10 is located on the upper surface of the emitter region 6, and the orthographic projection of the emitter electrode 10 on the substrate 1 is within the orthographic projection of the emitter region 6 on the substrate 1; it can be understood that the source region 3, the channel region 4, and the base region 5 constitute the p-i-n structure of the tunneling field-effect transistor, and the channel region 4, the base region 5, and the emitter region 6 constitute the PNP structure of the tunneling field-effect transistor to realize the bipolar tunneling field-effect transistor and improve the performance of the tunneling field-effect transistor; on the one hand, the barrier tunneling width of the device in the off state can be increased, the leakage current of the device in the off state can be effectively reduced, and the subthreshold swing characteristic and the switching current ratio can be improved; on the other hand, through the built-in triode PNP structure, when the tunneling field-effect transistor is in the on state, the tunneling current from the source region 3 to the channel region 4 can be amplified, so as to obtain a larger on-state current and effectively improve the driving ability of the tunneling field-effect transistor; among them, the amplification factor reaches 59.3, significantly improving the on-state current of the device and optimizing the technical problems of the small on-state current and insufficient driving ability of the tunneling field-effect transistor.

[0035] In an alternative embodiment of the present invention, the base region 5 is N-doped with a doping concentration of 1×10 17 ~1×10 18 cm -3 .

[0036] Specifically, in this embodiment, the base region 5 adopts a lower doping concentration, which can increase the barrier tunneling width of the device in the off state, effectively reduce the leakage current of the device in the off state, and further improve the subthreshold swing characteristic and the switching current ratio of the device.

[0037] In an alternative embodiment of the present invention, the source region 3 is P+-doped with a doping concentration of 1×10 20 ~1×10 21 cm -3 .

[0038] In an alternative embodiment of the present invention, the channel region 4 is P-doped with a doping concentration of 1×1016 ~1×10 17 cm -3 。

[0039] In an alternative embodiment of the present invention, the emitter region 6 is P+ doped with a doping concentration of 1×10 20 ~1×10 21 cm -3 , and both electrons and holes participate in conduction.

[0040] Specifically, in this embodiment, the emitter region 6 is P+ doped. Compared with the characteristic that only one type of carrier participates in conduction in a traditional tunneling field-effect transistor, both electrons and holes in the bipolar tunneling field-effect transistor provided in this embodiment participate in conduction, making it a bipolar device.

[0041] In this embodiment, the source region 3, the channel region 4, the base region 5, and the emitter region 6 are made of silicon and together form a top silicon film with a thickness of 70 nm. Optionally, when the thickness of the top silicon film is increased to 100 nm, the on-state current and driving ability of the device can be further improved.

[0042] In an alternative embodiment of the present invention, a PN junction is formed between the emitter region 6 and the base region 5.

[0043] Specifically, in this embodiment, the bipolar tunneling field-effect transistor integrates a p-i-n structure and a triode PNP structure. A PN junction is formed between the emitter region 6 and the base region 5, which can reduce the electric field applied between the channel region 4 and the base region 5 in the off state, thereby effectively suppressing the tunneling current of the device in the off state and improving the subthreshold swing characteristic of the device. This provides a new structure with high performance for the tunneling field-effect transistor without increasing the complexity of the process and is compatible with the traditional CMOS process.

[0044] In an alternative embodiment of the present invention, the substrate 1 is made of silicon and is P- doped with a doping concentration of 1×10 15 ~1×10 16 cm -3 , the insulating layer 2 is made of SiO2, and the top surface of the insulating layer 2 is the top silicon film, which is jointly formed by the source region 3, the channel region 4, the base region 5, and the emitter region 6, and the material of the top silicon film is silicon. Among them, the top silicon film, the insulating layer 2, and the substrate 1 together form a silicon-on-insulator structure.

[0045] Specifically, in this embodiment, the insulating layer 2 is located on the substrate 1 and adopts a silicon-on-insulator (SOI) structure. The SOI structure can effectively reduce the leakage current between the substrate 1 and the base region 5 in the off state of the device, thereby further improving the low-power consumption characteristic of the tunneling field-effect transistor.

[0046] In an alternative embodiment of the present invention, please refer to Figure 2 , Figure 2 which is a schematic diagram of the working principle of the novel bipolar tunneling field-effect transistor provided by the embodiment of the present invention. The bipolar tunneling field-effect transistor (TFET) provided in this embodiment integrates a traditional TFET and a triode PNP structure, and the built-in PNP structure is only triggered after the traditional TFET generates a tunneling current. When the voltage of the emitter 10 is greater than 0 and the voltage of the gate 9 is 0, this state is the off state. In the off state, the bottom of the conduction band EC of the base region 5 is below the top of the valence band EV of the channel region 4, and a tunneling window will be formed between the base region 5 and the channel region 4, enabling electrons in the channel region 4 to tunnel into the base region 5, thereby forming a tunneling current, which is the off-state current of the device.

[0047] In an alternative embodiment of the present invention, the expression for the band-to-band tunneling probability of the tunneling field-effect transistor is:

[0048]

[0049] where W represents the barrier tunneling width, m * represents the effective mass of the carrier, E g represents the bandgap width of the semiconductor material, Δf represents the emerging tunneling window, q represents the electron charge, and h represents the reduced Planck constant.

[0050] Please refer to Figure 3 , Figure 3 which is the energy band diagram of the bipolar tunneling field-effect transistor provided by the embodiment of the present invention and the traditional tunneling field-effect transistor in the off state. The base region 5 corresponds to the drain region of the traditional TFET. Due to the introduction of the low-doped base region 5, the barrier tunneling width of the bipolar TFET in the off state is significantly increased compared to the traditional TFET, which can effectively reduce the electron tunneling probability in the off state and lower the off-state current of the device. As Figure 4 shown, Figure 4 which is the comparison diagram of the tunneling probabilities of the bipolar tunneling field-effect transistor provided by the embodiment of the present invention and the traditional tunneling field-effect transistor in the off state.

[0051] As the voltage of the gate 9 increases, the conduction band and valence band of the channel region 4 will bend downward. When the bottom of the conduction band EC of the channel region 4 drops below the top of the valence band EV of the source region 7, a tunneling window will be formed between the source region 3 and the channel region 4. As Figure 5 shown, Figure 5FIG. 0 is the energy band diagram of the bipolar tunneling field effect transistor provided by the embodiment of the present invention and the traditional tunneling field effect transistor in the on state, enabling electrons in the source region 3 to tunnel to the channel region 4, thereby forming a tunneling current. This state is the on state, and the current in this on state is the on-state current of the device. The tunneling of the traditional TFET in the on state is a typical "point tunneling", and its on-state current is limited, resulting in insufficient driving ability of the device. However, for the bipolar TFET provided in this embodiment, the tunneling electrons entering the channel region 4 will enter the base region 5 under the action of the electric field force of the forward emitter 10, forming a base region 5 current of the built-in PNP structure and triggering the built-in PNP structure, amplifying the tunneling current to obtain a larger on-state current.

[0052] In an alternative embodiment of the present invention, the on-state current of the bipolar tunneling field effect transistor is expressed as:

[0053] I on = β × I tunnel (G BTBT );

[0054] where β represents the amplification factor of the PNP structure, and I tunnel (G BTBT ) represents the tunneling current from the source region 3 to the channel region 4.

[0055] In addition, only one type of tunneling carrier participates in conduction in the traditional TFET. In the on state of the bipolar TFET, the source region 3 provides tunneling electrons to the channel region 4, and the emitter region 6 provides holes to the channel region 4. The simultaneous participation of electrons and holes in conduction makes it a bipolar device with a larger current density and stronger driving ability of the device.

[0056] Please refer to Figure 6 , Figure 6 FIG. 28 is a comparison diagram of the transfer characteristic curves of the bipolar tunneling field effect transistor provided by the embodiment of the present invention and the traditional tunneling field effect transistor. Compared with the traditional TFET, the off-state current of the bipolar TFET has decreased by four orders of magnitude, showing excellent low-power consumption characteristics. In addition, due to the amplification effect of the built-in PNP structure, the on-state current of the bipolar TFET has been significantly increased, and the on-off current ratio exceeds 10 10 , and has a steep subthreshold swing characteristic as shown in Figure 7 . Figure 7 FIG. 34 is a comparison diagram of the subthreshold swing characteristics of the bipolar tunneling field effect transistor provided by the embodiment of the present invention and the traditional tunneling field effect transistor.

[0057] It should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variants are intended to cover non-exclusive inclusion, so that an article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the article or device comprising said element. Similar words such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The orientation or positional relationship indicated by "above", "below", "left", "right", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation of the present invention.

[0058] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. means that the specific features or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.

[0059] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can still be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A novel bipolar tunneling field effect transistor, characterized in that, Comprising: A substrate; An insulating layer located on the upper surface of the substrate; A source region, a channel region, a base region, and an emitter region, all located on the upper surface of the insulating layer. The source region, the channel region, the base region, and the emitter region are arranged in sequence on the upper surface of the insulating layer and are in contact with each other. Among them, the source region, the channel region, and the base region form a p-i-n structure of the tunneling field-effect transistor, and the channel region, the base region, and the emitter region form a PNP structure of the tunneling field-effect transistor; A source electrode located on the upper surface of the source region; A gate oxide layer located on the upper surface of the channel region, A gate electrode located on the upper surface of the gate oxide layer; An emitter electrode located on the upper surface of the emitter region.

2. The novel bipolar tunneling field effect transistor according to claim 1, characterized in that, The base region is N-doped with a doping concentration of 1×10 17 ~1×10 18 cm -3 .

3. The novel bipolar tunneling field effect transistor according to claim 1, characterized in that, The source region is P+ doped with a doping concentration of 1×10 20 ~1×10 21 cm -3 .

4. The novel bipolar tunneling field effect transistor according to claim 1, wherein, The channel region is P-doped with a doping concentration of 1×10 16 ~1×10 17 cm -3 .

5. The novel bipolar tunneling field effect transistor according to claim 1, characterized in that, The emitter region is P+ doped with a doping concentration of 1×10 20 ~1×10 21 cm -3 , and both electrons and holes participate in conduction.

6. The novel bipolar tunneling field effect transistor according to claim 1, characterized in that, A PN junction is formed between the emitter region and the base region.

7. The novel bipolar tunneling field effect transistor according to claim 1, wherein The material of the substrate is silicon, which is P-doped with a doping concentration of 1×10 15 ~1×10 16 cm -3 . The material of the insulating layer is SiO2. The upper surface of the insulating layer is a top silicon film, which is jointly composed of the source region, the channel region, the base region and the emitter region. The material of the top silicon film is silicon. Among them, the top silicon film, the insulating layer and the substrate jointly form a silicon-on-insulator structure.

8. The novel bipolar tunneling field effect transistor according to claim 1, wherein The expression for the band-to-band tunneling probability of the tunneling field-effect transistor is: Among them, W represents the barrier tunneling width, m * represents the effective mass of the carrier, E g represents the bandgap width of the semiconductor material, Δf represents the emerging tunneling window, q represents the electron charge, and h represents the reduced Planck constant.

9. The novel bipolar tunneling field effect transistor according to claim 1, wherein The on-state current of the tunneling field-effect transistor is expressed as: I on = β × I tunnel (G BTBT ) where β represents the amplification factor of the PNP structure, and I tunnel (G BTBT ) represents the tunneling current from the source region to the channel region.

Images