Power device preparation method and power device

Abstract

The invention relates to a power device preparation method and a power device, and belongs to the technical field of semiconductor power devices. Comprising the following steps: respectively etching a plurality of grooves in a first active region and a second active region; wherein the first and second active regions are isolated; growing a field oxide layer in the groove, depositing first polycrystalline silicon, and removing the redundant field oxide layer and the redundant first polycrystalline silicon to form source polycrystalline silicon; according to a preset distance, an isolation oxide layer is deposited above the source polysilicon, and a gate oxide layer is grown; depositing second polycrystalline silicon on the gate oxide layer, and removing the redundant gate oxide layer and the second polycrystalline silicon to form gate polycrystalline silicon; depositing an isolation oxide layer on the grid polycrystalline silicon and the doped region, and penetrating through the isolation oxide layer to the doped region to obtain a contact hole; wherein the doped region is obtained by performing body region and source region injection between each groove in the two active regions. According to the invention, local overheating is avoided, the stability of the device is improved, the warping degree of the wafer is reduced, and the application reliability of the device is enhanced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor power devices, and in particular to a method for manufacturing a power device and a power device. Background Art

[0002] A power device is an electronic component used to control and convert electrical energy, and is widely applied in scenarios with high voltage and high current, such as power management, frequency converters, motor drives, and energy conversion. Compared with ordinary electronic devices, power devices have the ability to handle larger power loads and are an indispensable core component in modern power electronic systems.

[0003] However, there are many problems in the actual application of existing power devices, which limit their performance and reliability. First of all, the zero temperature coefficient point (ZTC) of many power devices (such as MOSFETs and IGBTs) is relatively high. When the temperature changes, the on-resistance and switching characteristics of the device will change significantly, resulting in poor stability. When the device operates near the zero temperature coefficient point, a small temperature change will cause a large fluctuation in the on-resistance, thereby increasing power loss and affecting the stability of the system. At the same time, this also brings complexity to thermal management. Designers need to perform additional calculations and optimizations on the heat dissipation management of the system to cope with possible performance instability at high or low temperatures. This not only increases the design burden but also raises the overall cost of the system.

[0004] Secondly, there is a positive feedback phenomenon during the turn-on process of power devices. At a relatively low gate voltage, if the current is too large when the device conducts, it may trigger a positive feedback effect, causing the current to increase further, thereby causing the device temperature to rise sharply. As the current increases, the heat generated by the device increases, and coupled with the increase in on-resistance, it may cause the temperature in a local area to rise sharply, forming a thermal runaway phenomenon. The continuous action of this positive feedback may lead to device overheating and failure, or even burnout or short circuit, resulting in equipment damage and system downtime. This problem is particularly serious in power electronics and high-power applications.

[0005] In addition, local temperature rise is also one of the important problems faced by power devices. In high-power applications, due to high power density and uneven heat dissipation, some local areas of the device are prone to overheating. The increase in local temperature leads to material fatigue and deterioration, such as a decrease in the conductivity of semiconductor materials or the deterioration of the insulating layer. Continuous local overheating will also cause solder joint detachment, package cracking, and even complete device failure, seriously affecting the reliability and lifespan of the overall system. Summary of the Invention

[0006] To this end, the technical problem to be solved by the present invention is to overcome the poor stability, complexity caused by temperature changes in the prior art, the sharp temperature rise caused by positive feedback, and the material fatigue and deterioration caused by local temperature increase.

[0007] In a first aspect, to solve the above technical problem, the present invention provides a method for manufacturing a power device, including:

[0008] S1. Etch a plurality of trenches in the first active region and the second active region respectively; wherein the first active region and the second active region are isolated.

[0009] S2. Grow a field oxide layer inside the trenches; deposit a first polysilicon on the field oxide layer, and remove the redundant field oxide layer and the first polysilicon to form a source polysilicon.

[0010] S3. Deposit an isolation oxide layer above the source polysilicon according to a preset distance, and grow a gate oxide layer; deposit a second polysilicon on the gate oxide layer, and remove the redundant gate oxide layer and the second polysilicon to form a gate polysilicon.

[0011] S4. Deposit an isolation oxide layer on the gate polysilicon and the doping region, and etch a contact hole through the isolation oxide layer and extending to the doping region; wherein the doping region is obtained by performing a body region implantation and a source region implantation between each trench in the first active region and between each trench in the second active region.

[0012] In an embodiment of the present invention, when etching the trenches in S1, the trench length of the second active region is greater than the trench length of the first active region.

[0013] In an embodiment of the present invention, when etching the trenches in S1, the trench length of the second active region is 1000 - 10000 times the trench length of the first active region.

[0014] In an embodiment of the present invention, in S1, the first active region and the second active region are isolated by an electric field isolation region.

[0015] In an embodiment of the present invention, the material for preparing the electric field isolation region includes bulk silicon material.

[0016] In an embodiment of the present invention, the trenches in the first active region are distributed in a strip shape, and the trenches in the second active region are distributed in a grid pattern.

[0017] In an embodiment of the present invention, in S4, when performing the body region implantation, the body region junction depth of the first active region is greater than the body region junction depth of the second active region.

[0018] In one embodiment of the present invention, in S4, the doped region includes an N-type source region and a P-WELL region, and the contact hole passes through the P-WELL region and the isolation oxide layer and extends to the N-type source region.

[0019] In a second aspect, to solve the above technical problems, the present invention provides a power device, including:

[0020] A first active region and a second active region, both the first active region and the second active region are provided with a plurality of trenches; wherein a source polysilicon is provided inside the trenches, and the source polysilicon includes a field oxide layer and a first polysilicon deposited on the field oxide layer; a gate polysilicon is provided on the source polysilicon; the gate polysilicon includes a gate oxide layer and a second polysilicon deposited on the gate oxide layer;

[0021] A doped region is provided between each trench in the first active region and between each trench in the second active region; an isolation oxide layer and a contact hole passing through the isolation oxide layer are provided on the doped region.

[0022] In one embodiment of the present invention, a gate is further included, and the gate is connected to the first active region and the second active region by a wiring method.

[0023] The above technical solutions of the present invention have the following beneficial effects compared with the prior art:

[0024] (1) For the power device manufacturing method and the power device of the present invention, by etching a plurality of trenches in the first active region and the second active region, and growing a field oxide layer and forming a source polysilicon in the trenches, the current flow path can be optimized, the on-resistance can be reduced, thereby significantly improving the conductivity and overall performance of the device. Further, growing a gate oxide layer and forming a gate polysilicon above the source polysilicon can effectively control the electric field distribution between the gate and the source, optimize the switching characteristics of the device, and improve the switching speed and reliability. Using an electric field isolation region to isolate the first active region and the second active region can effectively reduce the current and thermal influence between the active regions, and significantly improve the reliability and stability of the device. By optimizing the design of the doped region and the isolation oxide layer, the breakdown voltage of the device can be further improved, enabling it to withstand higher voltages.

[0025] (2) By designing different cell structures for the first active region and the second active region, the present invention enables the two regions to have different turn-on voltages under the conditions of the same energy injection, dose, or push junction time in the body region. Therefore, although the second active region is farther from the gate and has a larger gate resistance, its lower turn-on voltage can ensure the same turn-on speed as the first active region. This design effectively reduces the zero temperature coefficient point of the device and avoids the positive feedback phenomenon caused by the first active region turning on first in the conventional design. At a lower gate voltage, the positive feedback effect of current and temperature will cause a local temperature increase, which may lead to device burnout. Through this optimized design, the application reliability of the device has been significantly improved.

[0026] (3) By integrating different cell structures on the same chip, the present invention can achieve stress compensation and cancellation, thereby effectively reducing the degree of wafer warping. The electric field isolation region plays a key role in this process. It can not only achieve the electric field balance and smooth transition of electric field lines between different cell structures but also absorb the generated heat during the frequent switching process of the device. This characteristic further improves the reliability of the device in high-power and high-frequency applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] To make the content of the present invention easier to understand clearly, the following further details the present invention based on the specific embodiments of the present invention in combination with the drawings, where:

[0028] Figure 1 is a flowchart of a method for manufacturing a power device in a preferred embodiment of the present invention;

[0029] Figure 2 is a diagram of the overall structure of a power device in a preferred embodiment of the present invention;

[0030] Figure 3 is a first cross-sectional view of a power device in a preferred embodiment of the present invention;

[0031] Figure 4 is a second cross-sectional view of a power device in a preferred embodiment of the present invention;

[0032] Figure 5 is a third cross-sectional view of a power device in a preferred embodiment of the present invention;

[0033] Figure 6 is in a preferred embodiment of the present invention Figure 3 is a schematic diagram of the overall method for manufacturing a power device from a perspective;

[0034] Figure 7 is in a preferred embodiment of the present invention Figure 4 is a schematic diagram of the overall method for manufacturing a power device from a perspective;

[0035] Figure 8In the preferred embodiment of the present invention, Figure 5 Schematic diagram of the overall method for fabricating a power device at a perspective;

[0036] Figure 9 Figure 2 shows the overall structure of the power device in the preferred embodiment of the present invention.

[0037] Explanation of reference numerals in the drawings: 1, the first active region; 2, the second active region; 3, the trench; 4, the electric field isolation region; 5, the isolation oxide layer; 51, the field oxide layer; 52, the gate oxide layer; 6, the first polysilicon; 7, the second polysilicon; 8, the contact hole; 9, the N-type source region; 10, the P-WELL region; 11, the metal layer; 12, the chip; 13, the gate trace. Detailed implementation manners

[0038] The present invention will be further described below in conjunction with the drawings and specific embodiments, so that those skilled in the art can better understand the present invention and be able to implement it, but the embodiments given are not intended to limit the present invention.

[0039] In the embodiments of the present invention, the key components involved include the active region, the gate, the drain, the source, the electric field isolation region, the contact hole, and the electrode. The following is a detailed description of these components:

[0040] The active region is the core part of the semiconductor device and is responsible for the actual current conduction function. The active region is usually composed of N-type or P-type doped materials, and the specific type depends on the design and application requirements of the device. The gate belongs to the part that controls the switching operation of the device, and the controller controls the conductive state of the active region through the gate voltage. The drain and the source are respectively used for the output and input ends of the device, and the current flows in from the source, passes through the active region, and then flows out from the drain. The electric field isolation region is used to isolate different cells on the chip to prevent current leakage and cross-interference, where a cell refers to the basic repetitive unit that makes up an integrated circuit or a power device in semiconductor device manufacturing. These units are arranged repeatedly on the chip to form a large-scale circuit array. The contact hole is used to connect different layers inside the device, such as the gate, the source, and the drain, as well as the external metal electrode. The electrode is responsible for leading the current from inside the device to the external circuit.

[0041] Embodiment 1

[0042] Referring to Figures 1 to 3 as shown, the present invention provides a method for fabricating a power device, including:

[0043] S1. Etch a plurality of trenches 3 in the first active region 1 and the second active region 2 respectively; wherein the first active region 1 and the second active region 2 are isolated by the electric field isolation region 4;

[0044] S2. Grow a field oxide layer 51 inside the trench 3; deposit a first polysilicon 6 on the field oxide layer 51, and remove the redundant field oxide layer 51 and the first polysilicon 6 to form a source polysilicon;

[0045] S3. Deposit an isolation oxide layer 5 above the source polysilicon according to a preset distance, and grow a gate oxide layer 52; deposit a second polysilicon 7 on the gate oxide layer 52, and remove the redundant gate oxide layer 52 and the second polysilicon 7 to form a gate polysilicon;

[0046] S4. Deposit an isolation oxide layer 5 on the doped region and the gate polysilicon, and etch a contact hole 8 through the isolation oxide layer 5 and extending to the doped region; wherein the doped region is obtained by performing a body region implantation and a source region implantation between each trench of the first active region 1 and between each trench of the second active region 2.

[0047] The embodiment of the present invention provides a method for manufacturing a power device. By etching a plurality of trenches 3 in the first active region 1 and the second active region 2, and growing a field oxide layer 51 and a source polysilicon in the trenches 3, the flow path of the current can be optimized, the on-resistance can be reduced, thereby improving the conduction efficiency and the overall performance of the device. Growing a gate oxide layer 52 above the source polysilicon and forming a gate polysilicon can effectively control the electric field distribution between the gate and the source, optimize the switching characteristics of the device, and improve the switching speed and reliability. Using the electric field isolation region 4 to isolate the first active region 1 and the second active region 2 can effectively reduce the current and thermal influence between the active regions, and improve the reliability and stability of the device. By optimizing the design of the doped region and the isolation oxide layer 5, the breakdown voltage of the device can be increased, enabling it to withstand a higher voltage. This method can make the two regions have different turn-on voltages under the same body region implantation energy or dose or push-junction time conditions by optimizing the cell structure design of the first active region 1 and the second active region 2. In the second active region 2, the gate density of the cell is higher, and its turn-on voltage is 0.5V to 1V lower than that of the active region 1. Therefore, although the second active region 2 is farther from the gate and has a larger gate resistance, its lower turn-on voltage can ensure the same turn-on speed as the first active region 1. This design effectively reduces the zero temperature coefficient point of the device and avoids the positive feedback phenomenon caused by the first active region 1 turning on first in the conventional design. In addition, at a lower gate voltage, the positive feedback effect of the current and temperature will cause a local temperature increase, which may lead to device burnout. And through this optimized design, the local temperature increase is avoided, which causes fatigue and deterioration of the material, and improves the application reliability of the device.

[0048] Specifically, referring to Figure 2, for the first active region 1, a strip-shaped trench 3 distribution design is adopted. These trenches 3 exist in a long strip shape and are arranged continuously along a specific direction (such as the horizontal or vertical direction) of the first active region 1. The design of such strip-shaped trenches 3 helps to construct a continuous current conduction path, thereby providing a low-resistance current flow channel in this direction. Such a design optimizes the current flow pattern, reduces the non-uniformity of the internal current distribution of the device, and thus improves the conductivity of the device. The trenches in the second active region 2 are in a grid-type distribution, and this distribution method helps to achieve a more uniform electric field distribution in the active region, reduces the local electric field concentration, and thus improves the breakdown voltage performance of the device. The trenches in the grid-type distribution can also improve the uniformity of the thermal distribution of the device, contribute to the dispersion of heat, and reduce the risk of local overheating. In addition, when viewed from the X-axis direction, the trench length of the second active region 2 is greater than the trench length of the first active region 1, as Figure 4 shown. In this embodiment, the trench length of the second active region 2 is 1000 - 10000 times that of the trench length of the first active region 1.

[0049] Specifically, in step S1, the first active region 1 and the second active region 2 are isolated by the electric field isolation region 4. The electric field isolation region 4 itself does not contain a cell design and is mainly composed of a bulk silicon part. Among them, the bulk silicon is a single-crystalline silicon material with characteristics such as a high melting point and a large bandgap width. In the embodiment of the present invention, through the structural design of the electric field isolation region 4, it can effectively absorb the heat generated by frequent switching during the operation of the device, thereby significantly improving the reliability of the device in high-power and high-frequency applications. At the same time, the electric field isolation region 4 can also achieve the electric field balance between different cell structures and the smooth transition of electric field lines, further optimizing the electrical performance of the device. Therefore, the electric field isolation region 4 not only plays a key role in electric field management but also performs well in thermal management, providing a strong guarantee for the efficient and stable operation of the device.

[0050] Specifically, due to the advantages of the re-etching process in aspects such as complex structure forming, high integration implementation, etching selectivity optimization, and adaptation to specific material requirements, the re-etching process is preferably used in step S2 to remove the redundant field oxide layer 51 and the first polysilicon 6, thereby forming the source polysilicon. Similarly, in step S3, the re-etching process is used to remove the redundant gate oxide layer 52 and the second polysilicon 7, thereby forming the gate polysilicon. The selection of this process not only ensures the high-precision forming of the device structure but also provides a solid foundation for the smooth implementation of subsequent processes, ensuring the efficiency and stability of the overall manufacturing process.

[0051] Specifically, in steps S2 and S3, both the field oxide layer 51 and the gate oxide layer 52 can be fabricated from a silicon dioxide material. It should be noted that although both the field oxide layer 51 and the gate oxide layer 52 are composed of silicon dioxide, there are differences between them in terms of function, thickness, fabrication method, and the impact on device performance. The gate oxide layer 52 is mainly used to control the switching function of the transistor and is a key structure for realizing the electrical characteristic regulation of the transistor; while the field oxide layer 51 is mainly used to isolate different transistors or active regions, effectively preventing parasitic effects and leakage phenomena, thereby ensuring the isolation performance and overall reliability of the device.

[0052] Furthermore, there are also differences between the first polysilicon 6 and the second polysilicon 7 in terms of function, thickness, fabrication process, doping concentration and type, and the impact on device performance. The first polysilicon 6 is usually used to form the contact of the source or drain, and its thickness and doping concentration may vary according to specific contact requirements; while the second polysilicon 7 is used to form the gate and needs to have higher conductivity and uniformity to ensure the high performance of the transistor. These differences enable them to play different roles in the device to meet different design and performance requirements.

[0053] Specifically, referring to Figures 3 to 5 , in step S4, the doped regions include an N-type source region 9 (also referred to as the N source region) and a P-WELL region 10. Between each trench of the first active region 1, a body region implantation is performed to form the N-type source region 9, where the body region junction depth is precisely set according to actual requirements. Similarly, a body region implantation is also performed between each trench of the second active region 2 to form the N-type source region 9 of this active region. However, there are differences in the body region junction depths of the two active regions. As Figure 6 shown, the body region junction depth d1 of the first active region 1 is greater than the body region junction depth d2 of the second active region 2.

[0054] Furthermore, a source region implantation is performed on the N-type source regions 9 of the two active regions to form the P-WELL region 10. The P-WELL region 10 is a region formed by implanting P-type impurities (such as boron) into the N-type substrate or N-type epitaxial layer through ion implantation technology.

[0055] By etching trenches and forming the N-type source regions 9 in the first active region 1 and the second active region 2, the current flow path is optimized, and the on-resistance is significantly reduced, thereby greatly improving the conductivity and overall performance of the device. At the same time, by designing different body region junction depths and trench lengths, the first active region 1 and the second active region 2 are given unique cell structures. Cross-sectional views from different perspectives (such as Figures 3 to 5)It can be seen that there are obvious structural differences between the two active regions. In addition, by precisely controlling the junction depth of each body region and the distribution of the doped regions, parasitic capacitance and leakage phenomena are effectively suppressed, and the performance of the device is thus further improved.

[0056] Specifically, in step S4, through an etching process, the isolation oxide layer and the P-WELL region 10 are penetrated until reaching the N-type source region 9, thereby forming the contact hole 8. This contact hole 8 is used to achieve the electrical connection of the source, drain, and gate, ensuring the normal conductivity of the device.

[0057] Specifically, a tungsten plug is filled in the contact hole 8 obtained in step S4. This filling process uses advanced tungsten chemical vapor deposition (CVD) technology to ensure that the tungsten plug can uniformly and densely fill the contact hole 8, thereby achieving low resistivity and high conductivity. The filled tungsten plug can not only effectively reduce the contact resistance but also significantly improve the electrical performance and reliability of the device.

[0058] Furthermore, a metal layer 11 is deposited on the surface of the isolation oxide layer 5, and this metal layer 11 is used to form the metal connections of the source, drain, and gate. This process step ensures good electrical connections between the source, drain, and gate by precisely controlling the thickness and uniformity of the metal layer 11, thereby optimizing the electrical performance and overall stability of the device.

[0059] Specifically, referring to Figures 6 to 8 , the specific steps for fabricating the power device are as follows:

[0060] Step 1: In the initial stage of manufacturing the power device, a trench 3 structure needs to be formed through photolithography and etching processes for isolating different cell units. The parameters for etching the trench 3 are as follows:

[0061] The opening size of the trench 3: 0.18μm - 2.0μm. This size range is selected according to the power rating and cell density of the device. A smaller opening size is suitable for high-density designs, while a larger opening size is used for high-power applications. Among them, referring to Figure 7 , the opening size of the trench in the second active region 2 is 2000 - 10000 times that of the trench opening size in the first active region 1.

[0062] The depth of the trench 3: 1.5μm - 10μm. The depth of the trench 3 determines the isolation effect and breakdown voltage capability of the device. The deeper the depth, the better the isolation effect, but at the same time, higher etching precision is required.

[0063] The cell size: 0.65μm - 5.0μm. The cell size refers to the lateral size of each cell unit, which directly affects the area efficiency and current-carrying capacity of the device.

[0064] Step 2: After the etching of the trench 3 is completed, it is necessary to grow a field oxide layer 51 in the trench 3 to achieve electrical isolation. The thickness range of the field oxide layer 51 is 500 Å to 10,000 Å. The thickness of the oxide layer needs to be selected according to the breakdown voltage requirements of the device. A thicker oxide layer can provide higher breakdown voltage capabilities, but it will also increase the parasitic capacitance of the device.

[0065] Step 3: To form the source contact, a layer of first polysilicon 6 needs to be deposited on the field oxide layer 51. The thickness of the first polysilicon 6 needs to be adjusted according to the design requirements to ensure good electrical contact. After the deposition, the excess first polysilicon 6 is removed through a back-etching process to make it flush with the field oxide layer 51, ensuring a flat surface. This process step is crucial for the subsequent formation of the source contact.

[0066] Step 4: After the source polysilicon is formed, the following steps are required:

[0067] Step 4-1: Deposit the isolation oxide layer 5. This step is used to further isolate different cell units and ensure the electrical performance of the device.

[0068] Step 4-2: Grow the gate oxide layer 52. The gate oxide layer 52 is the insulating layer between the gate and the semiconductor substrate, and its thickness range is 350 Å to 1000 Å. The thickness of the gate oxide layer 52 directly affects the switching characteristics of the device. A thinner oxide layer can reduce the gate drive voltage, but it will also increase the leakage current.

[0069] Step 4-3: Deposit the gate polysilicon and perform back-etching. A layer of second polysilicon 7 is deposited on the gate oxide layer 52 to form the gate structure. The excess second polysilicon 7 is removed through a back-etching process to ensure that the size and shape of the gate meet the design requirements.

[0070] Step 5: After the gate structure is formed, a body region implantation and drive-in process need to be performed to form the N-type source region 9. The specific parameters are as follows:

[0071] The depth range of the N-type source region 9 in the first active region 1 (i.e., the body region junction depth d1): 0.4 μm to 1.5 μm.

[0072] The depth range of the N-type source region 9 in the second active region 2 (i.e., the body region junction depth d2): 0.2 μm to 1.3 μm.

[0073] The body region implantation is to implant impurities into the semiconductor substrate through an ion implantation process to form the N-type source region 9. The drive-in process is to make the impurities diffuse through high-temperature annealing to form a source region with a certain depth and concentration distribution. This process step is crucial for the conduction characteristics and breakdown voltage capabilities of the device.

[0074] Step 6: After the implantation in the body region is completed, source region implantation and push - knot process need to be further carried out. This step aims to optimize the doping concentration and distribution in the source region to ensure that the device has good conduction characteristics and low on - resistance. Through ion implantation and high - temperature annealing, the impurity concentration and depth distribution in the source region are further optimized.

[0075] Step 7: After the implantation in the source region is completed, the following steps are also required to complete the fabrication of the device:

[0076] Step 7 - 1: Deposit isolation oxide layer 5 to isolate different electrical regions and ensure the electrical performance of the device.

[0077] Step 7 - 2: Form contact windows for the source, drain, and gate through photolithography and etching processes to ensure that subsequent metal connections can form good electrical contacts with various parts of the device.

[0078] Step 7 - 3: Fill tungsten plugs in contact holes 8 to ensure the stable electrical performance of contact holes 8 and reduce contact resistance.

[0079] Step 7 - 4: Deposit metal layer 11 on the device surface to form metal connections for the source, drain, and gate. The thickness and material selection of metal layer 11 need to be optimized according to the design requirements of the device to ensure the low resistance and high reliability of the device.

[0080] Through the above steps, the fabrication of the power device is finally completed. As Figure 2 or Figure 9 shown, these two figures respectively show the overall structure of the device from different angles. The precise control of these process steps has an important impact on the performance, reliability, and cost of the device. In addition, the power device fabrication method proposed in this embodiment has wide applicability and can cover the design and fabrication of various types of power devices, including but not limited to silicon - based shield - gate MOSFETs, super - junction MOSFETs, trench MOSFETs, IGBTs, and silicon carbide - based MOSFETs, etc.

[0081] An embodiment of the present invention provides a method for manufacturing a power device. By designing different cell structures for the first active region 1 and the second active region 2, it is possible to enable the two regions to have different turn-on voltages under the same conditions of body region implantation energy, dose, or push-junction time. In the second active region 2, the gate density of the cells is higher, so its turn-on voltage is lower than that of the first active region 1. Although the second active region 2 is farther from the gate and has a larger gate resistance, its lower turn-on voltage can ensure the same turn-on speed as the first active region 1. This design effectively reduces the zero temperature coefficient point of the device and avoids the positive feedback phenomenon caused by the first active region 1 turning on first in the conventional design. At a lower gate voltage, the positive feedback effect of current and temperature will cause a local temperature rise, which may lead to device burnout. Through this optimized design, the application reliability of the device is significantly improved. In addition, integrating different cell structures on the same chip 12 can achieve stress compensation and cancellation, thereby effectively reducing the degree of wafer warping. The electric field isolation region 4 plays a key role in this. It can not only achieve the electric field balance and smooth transition of electric field lines between different cell structures, but also absorb the heat generated during the frequent switching of the device. This characteristic further improves the reliability of the device in high-power and high-frequency applications.

[0082] Embodiment 2

[0083] This embodiment provides a power device manufactured by the method for manufacturing a power device described in Embodiment 1, including:

[0084] A first active region 1 and a second active region 2, and a plurality of trenches 3 are provided in both the first active region 1 and the second active region 2; a source polysilicon is provided inside the trench 3, and the source polysilicon includes a field oxide layer 51 and a first polysilicon 6 deposited on the field oxide layer 51; a gate polysilicon is provided on the source polysilicon; the gate polysilicon includes a gate oxide layer 52 and a second polysilicon 7 deposited on the gate oxide layer 52;

[0085] A doping region is provided between each trench in the first active region 1 and between each trench in the second active region 2; an isolation oxide layer 5 and a contact hole 8 passing through the isolation oxide layer 5 are provided on the doping region.

[0086] A power device provided in this embodiment can effectively reduce parasitic capacitance and leakage by setting a field oxide layer 51 and a source polysilicon in the trench 3 and arranging a gate oxide layer 52 and a gate polysilicon above them, thereby improving the switching speed and overall performance of the device. The multiple trench designs of the first active region 1 and the second active region 2, as well as the setting of the doped regions, can optimize the current flow path, reduce the on-resistance, and improve the conduction efficiency of the device. Setting doped regions, isolation oxide layers 5, and contact holes 8 between the active regions can effectively isolate adjacent devices, reduce signal interference and crosstalk, and improve the reliability and stability of the device. At the same time, the above-mentioned structural design can effectively prevent the latch-up effect, especially in high-integration CMOS circuits, which is crucial for improving the anti-interference ability and reliability of the device. Therefore, the power device designed in this embodiment realizes a significant improvement in device performance, effective suppression of parasitic effects, enhanced isolation effect, and increased integration density by optimizing the structure and layout of the active regions, while taking into account the flexibility of the manufacturing process and the reliability of the device.

[0087] Specifically, the power device provided in this embodiment further includes a gate, which is electrically connected to the first active region 1 and the second active region 2 through a specific gate trace 13 method, thereby realizing the control function of the two active regions.

[0088] Obviously, the above embodiments are only examples given for clear illustration and are not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to enumerate all the implementation manners here. And the obvious changes or modifications derived therefrom are still within the protection scope of the present invention.

Claims

1. A method for manufacturing a power device, characterized in that, Including: S1. Etch a plurality of trenches in the first active region and the second active region respectively; wherein the first active region and the second active region are isolated from each other; S2. Grow a field oxide layer inside the trenches; Deposit first polysilicon on the field oxide layer, and remove the redundant field oxide layer and the first polysilicon to form source polysilicon; S3. Deposit an isolation oxide layer above the source polysilicon according to a preset distance, and grow a gate oxide layer; Deposit second polysilicon on the gate oxide layer, and remove the redundant gate oxide layer and the second polysilicon to form gate polysilicon; S4. Deposit an isolation oxide layer on the gate polysilicon and the doping region, and etch through the isolation oxide layer to extend to the doping region to obtain contact holes; wherein the doping region is obtained by performing body region implantation and source region implantation between each trench in the first active region and between each trench in the second active region.

2. The method for manufacturing a power device according to claim 1, wherein, When etching the trenches in S1, the trench length of the second active region is greater than the trench length of the first active region.

3. A method for manufacturing a power device according to claim 2, characterized in that, When etching the trenches in S1, the trench length of the second active region is 1000 - 10000 times the trench length of the first active region.

4. A method for manufacturing a power device according to claim 1, wherein, In S1, the first active region and the second active region are isolated by an electric field isolation region.

5. A method for manufacturing a power device according to claim 4, characterized in that, The material for preparing the electric field isolation region includes bulk silicon material.

6. A method for manufacturing a power device according to claim 1, characterized in that, The trenches in the first active region are distributed in a strip shape, and the trenches in the second active region are distributed in a grid pattern.

7. A method for manufacturing a power device according to claim 1, characterized in that, In S4, when performing body region implantation, the body region junction depth of the first active region is greater than the body region junction depth of the second active region.

8. A method for manufacturing a power device according to claim 1, characterized in that, In S4, the doping region includes an N-type source region and a P-WELL region, and the contact holes pass through the P-WELL region and the isolation oxide layer and extend to the N-type source region.

9. A power device, characterized in that, Including: A first active region and a second active region, both the first active region and the second active region are provided with a plurality of trenches; wherein the inside of the trenches is provided with source polysilicon, and the source polysilicon includes a field oxide layer and first polysilicon deposited on the field oxide layer; Gate polysilicon is provided on the source polysilicon; The gate polysilicon includes a gate oxide layer and second polysilicon deposited on the gate oxide layer; A doping region is provided between each trench in the first active region and between each trench in the second active region; An isolation oxide layer and contact holes passing through the isolation oxide layer are provided on the doping region.

10. A power device according to claim 9, characterized in that, It further includes a gate, and the gate is connected to the first active region and the second active region by a wiring method.

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