Integrated power device with trimming function and manufacturing method thereof

Abstract

The invention relates to the technical field of switching power supplies, and particularly discloses an integrated power device with a trimming function and a manufacturing method thereof.The integrated power device comprises a fuse resistor, an anti-fuse resistor, a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor and a sixth MOS transistor, the fuse resistor, the second MOS transistor and the third MOS transistor form a positive trimming cell of the sixth MOS transistor, and the anti-fuse resistor, the first MOS transistor, the fourth MOS transistor, the fifth MOS transistor and the sixth MOS transistor form a negative trimming cell of the sixth MOS transistor. The anti-fuse resistor, the fourth MOS tube and the fifth MOS tube form a negative trimming cell of the sixth MOS tube, the source electrode of the first MOS tube is connected with the S port, the grid electrode of the second MOS tube and one end of the fuse resistor are connected with the TS1 port, and the grid electrode of the fourth MOS tube and the other end of the anti-fuse resistor are connected with the ATS1 port. According to the integrated power device with the trimming function, the trimming process is added during wafer testing, and the problem that the on-resistance proportion of the power device fluctuates can be solved.

Description

Technical Field

[0001] The present invention relates to the technical field of switching power supplies, and particularly to an integrated power device with a trimming function and a manufacturing method thereof. Background Art

[0002] Currently, in the AC / DC application of switching power supplies, flyback is a commonly used structure. Figures 1A - 1B is a traditional primary circuit topology structure (secondary side omitted) in a flyback AC / DC converter, where Figure 1A is the case of only a rectifier diode, Figure 1B is the case of using an integrated sampling tube and rectifier diode power device. As Figure 1A shown, in order to reduce the loss on the rectifier diode source terminal sampling resistor R CS during sampling, many manufacturers use the Figure 1B shown integrated power device including a sampling tube and a rectifier diode. In this integrated power device, the sampling tube and the rectifier diode have the same layout cell structure, but the on-resistance of the former is only 1 / 500 or 1 / 350 of the latter (the ratio can be designed according to the actual sampling accuracy). In this way, under the same gate voltage, the current flowing through the sampling resistor R CS is only 1 / 500 or 1 / 350 of that on the rectifier diode, greatly reducing the power consumption lost on the sampling resistor R CS during current sampling.

[0003] The integrated power device of the sampling tube and the rectifier diode has the above-mentioned advantages in AC / DC applications. However, in the actual design and production process, due to the influence of device cell conduction uniformity and gate resistance distribution, it is very difficult to accurately control the on-resistance ratio. Summary of the Invention

[0004] An object of the present invention is to overcome the deficiencies existing in the prior art, and provide an integrated power device with a trimming function and a manufacturing method of the integrated power device with a trimming function. By adding a trimming process during wafer testing, the problem of on-resistance ratio fluctuation of the power device can be solved.

[0005] As an aspect of the present invention, a monolithic power device with a trimming function is provided. The monolithic power device with a trimming function includes a fuse resistor TR1, an antifuse resistor ATR1, a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, and a sixth MOS transistor M6. The fuse resistor TR1, the second MOS transistor M2, and the third MOS transistor M3 constitute a positive trimming cell of the sixth MOS transistor M6. The antifuse resistor ATR1, the fourth MOS transistor M4, and the fifth MOS transistor M5 constitute a negative trimming cell of the sixth MOS transistor M6. Wherein, the source of the first MOS transistor M1 is connected to the S port, the gates of the first MOS transistor M1, the third MOS transistor M3, the fifth MOS transistor M5, and the sixth MOS transistor M6 are all connected to the G port, the drains of the first MOS transistor M1, the second MOS transistor M2, the fourth MOS transistor M4, and the sixth MOS transistor M6 are all connected to the D port, the source of the second MOS transistor M2 is connected to the drain of the third MOS transistor M3, the gate of the second MOS transistor M2 and one end of the fuse resistor TR1 are both connected to the TS1 port, the sources of the third MOS transistor M3, the other end of the fuse resistor TR1, the source of the fifth MOS transistor M5, one end of the antifuse resistor ATR1, and the source of the sixth MOS transistor M6 are all connected to the SE port, the gate of the fourth MOS transistor M4 and the other end of the antifuse resistor ATR1 are both connected to the ATS1 port, and the source of the fourth MOS transistor M4 is connected to the drain of the fifth MOS transistor M5.

[0006] Further, the first MOS transistor M1, the third MOS transistor M3, the fifth MOS transistor M5, and the sixth MOS transistor M6 are all enhancement-mode MOS transistors, and the second MOS transistor M2 and the fourth MOS transistor M4 are both depletion-mode MOS transistors.

[0007] As another aspect of the present invention, a flyback AC / DC converter is provided. The flyback AC / DC converter includes an AC / DC primary controller, an EMI filter, a rectifier bridge, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a first resistor R1, a second resistor R2, a sampling resistor R CS, the first diode D1, the second diode D2, the third diode D3, the fourth diode D4, the transformer T1, the seventh MOS transistor M7, the eighth MOS transistor M8, and the integrated power device with trimming function described above. Among them, the positive electrode of the first diode D1 is respectively connected to the drain electrodes of the first MOS transistor M1, the second MOS transistor M2, the fourth MOS transistor M4, and the sixth MOS transistor M6. The source electrode of the first MOS transistor M1 is grounded. The negative electrode of the first diode D1 is connected to the drain electrode of the seventh MOS transistor M7. The source electrode of the seventh MOS transistor M7 is connected to the HV pin of the AC / DC primary controller. The gate electrode of the seventh MOS transistor M7 is respectively connected to the gate electrode of the eighth MOS transistor M8 and the source electrode of the first MOS transistor M1. The source electrode of the eighth MOS transistor M8 is connected to the VDD pin of the AC / DC primary controller. The drain electrode of the eighth MOS transistor M8 is respectively connected to one end of the second resistor R2 and one end of the fourth capacitor C4. The gate electrode of the sixth MOS transistor M6 is connected to the GATE pin of the AC / DC primary controller. The source electrode of the sixth MOS transistor M6 is respectively connected to one end of the sampling resistor R CS and the CS pin of the AC / DC primary controller. The drain electrode of the sixth MOS transistor M6 is respectively connected to the positive electrode of the second diode D2 and the primary winding of the transformer T1.

[0008] Furthermore, both the seventh MOS transistor M7 and the eighth MOS transistor M8 are depletion-mode MOS transistors.

[0009] Furthermore, the AC / DC primary controller includes a high-voltage start-up circuit. The high-voltage start-up circuit includes a MOS control logic circuit, a voltage comparator, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a ninth MOS transistor M9, and a tenth MOS transistor M10. One end of the third resistor R3 and one end of the fourth resistor R4 are both connected to the HV pin of the AC / DC primary controller. The other end of the third resistor R3 is respectively connected to one end of the fifth resistor R5 and the gate electrode of the ninth MOS transistor M9. The other end of the fourth resistor R4 is connected to the drain electrode of the ninth MOS transistor M9. The source electrode of the ninth MOS transistor M9 is respectively connected to the first input terminal of the voltage comparator and the VDD pin of the AC / DC primary controller. The second input terminal of the voltage comparator is connected to the reference voltage Ref. The output terminal of the voltage comparator is connected to the gate electrode of the tenth MOS transistor M10 through the MOS control logic circuit. The drain electrode of the tenth MOS transistor M10 is connected to the other end of the fifth resistor R5. The source electrode of the tenth MOS transistor M10 is grounded.

[0010] Furthermore, the MOS control logic circuit includes a variety of logic gates and an output totem pole.

[0011] As another aspect of the present invention, there is provided a manufacturing method of an integrated power device with a trimming function. Among them, the manufacturing method of the integrated power device with a trimming function includes: Step 1: Provide a substrate, grow a GaN buffer layer, a GaN channel layer, and an AlGaN barrier layer on the substrate in sequence, and form a two-dimensional electron gas at the interface of the GaN channel layer close to the AlGaN barrier layer; Step 2: Form an isolation structure in the GaN channel layer and the AlGaN barrier layer; Step 3: Form a P-type GaN layer above the AlGaN barrier layer; Step 4: Etch the P-type GaN layer, and deposit gate metal on the entire upper surface of the wafer. Among them, a Schottky contact is formed at the contact between the gate metal and the AlGaN barrier layer; Step 5: Etch the gate metal to form the gates of each MOS transistor; Step 6: Deposit drain-source metal on the entire upper surface of the wafer formed in Step 5. Among them, an ohmic contact is formed at the contact between the drain-source metal and the AlGaN barrier layer; Step 7: Etch the drain-source metal to form the source and drain of each MOS transistor; Step 8: Form a first layer of interlayer dielectric on the entire upper surface of the wafer formed in Step 7; Step 9: Etch the first layer of interlayer dielectric to form first-layer vias, and fill the first-layer vias with metal and planarize; Step 10: Deposit and etch first-layer interconnect metal on the entire upper surface of the wafer formed in Step 9; Step 11: Deposit and etch amorphous silicon on the entire upper surface of the wafer formed in Step 10; Step 12: Form a second layer of interlayer dielectric on the entire upper surface of the wafer formed in Step 11, then etch the second layer of interlayer dielectric to form second-layer vias, and then fill the second-layer vias with metal and planarize; Step 13: Deposit and etch second-layer interconnect metal on the entire upper surface of the wafer formed in Step 12 to form the integrated power device with a trimming function.

[0012] Further, the material of the first layer of interlayer dielectric is silicon nitride, the material of the second layer of interlayer dielectric is borophosphosilicate glass or silicon nitride, the material of the first layer of interconnect metal is lead-tin alloy, zinc alloy, silver, or copper-nickel alloy, and the material of the second layer of interconnect metal is aluminum, copper, or gold.

[0013] Further, in the process of filling the first-layer vias with metal, it further includes: Titanium, titanium nitride and tungsten are deposited in sequence in the first-layer through holes.

[0014] Further, in the filling of the second-layer through holes with metal, it further includes: Titanium, titanium nitride and tungsten are deposited in sequence in the second-layer through holes.

[0015] Compared with traditional integrated power devices, the present invention has the following advantages: adding a trimming process during wafer testing can solve the problem of the fluctuation of the on-resistance ratio of power devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present invention, but do not constitute a limitation to the present invention.

[0017] Figure 1A It is a circuit topology diagram of the first traditional primary circuit in a flyback AC / DC converter.

[0018] Figure 1B It is a circuit topology diagram of the second traditional primary circuit in a flyback AC / DC converter.

[0019] Figure 2A It is a circuit schematic diagram of the integrated power device with a trimming function in the embodiment of the present invention.

[0020] Figure 2B It is a structural sectional view of the integrated power device with a trimming function in the embodiment of the present invention.

[0021] Figure 3A It is a circuit schematic diagram of the structure with a trimming function of a sampling tube and integrating a MOS tube as a high-voltage starting device and an auxiliary winding power supply device in the embodiment of the present invention.

[0022] Figure 3B It is for the primary circuit topology diagram of the flyback AC / DC converter using the embodiment Figure 3A of the present invention.

[0023] Figure 3C It is Figure 3B the schematic diagram of the high-voltage starting circuit in

[0024] Figure 4A It is the structural sectional view corresponding to the first manufacturing step in the embodiment of the present invention.

[0025] Figure 4B It is the structural sectional view corresponding to the second manufacturing step in the embodiment of the present invention.

[0026] Figure 4C It is the structural sectional view corresponding to the third manufacturing step in the embodiment of the present invention.

[0027] Figure 4D This is a structural cross-sectional view corresponding to the fourth manufacturing step in the embodiment of the present invention.

[0028] Figure 4E This is a structural cross-sectional view corresponding to the fifth manufacturing step in the embodiment of the present invention.

[0029] Figure 4F This is a structural cross-sectional view corresponding to the sixth manufacturing step in the embodiment of the present invention.

[0030] Figure 4G This is a structural cross-sectional view corresponding to the seventh manufacturing step in the embodiment of the present invention.

[0031] Figure 4H This is a structural cross-sectional view corresponding to the eighth manufacturing step in the embodiment of the present invention.

[0032] Figure 4I This is a structural cross-sectional view corresponding to the ninth manufacturing step in the embodiment of the present invention.

[0033] Figure 4J This is a structural cross-sectional view corresponding to the tenth manufacturing step in the embodiment of the present invention.

[0034] Figure 4K This is a structural cross-sectional view corresponding to the eleventh manufacturing step in the embodiment of the present invention.

[0035] Figure 4L This is a structural cross-sectional view corresponding to the twelfth manufacturing step in the embodiment of the present invention.

[0036] Figure 4M This is a structural top view corresponding to the thirteenth manufacturing step in the embodiment of the present invention.

[0037] In the drawings, the list of components represented by each reference numeral is as follows: 1 - substrate; 2 - GaN buffer layer; 3 - GaN channel layer; 4 - AlGaN barrier layer; 5 - two-dimensional electron gas; 6 - isolation structure; 7 - P-type GaN layer; 8 - gate metal; 9 - drain-source metal; 10 - first interlayer dielectric; 11 - first via; 12 - first interconnect metal; 13 - amorphous silicon; 14 - second interlayer dielectric; 15 - second via; 16 - second interconnect metal. Detailed implementation manners

[0038] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the drawings and in combination with the embodiments.

[0039] To enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0040] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned accompanying drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances for the embodiments of the present invention described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0041] As the manufacturing cost of GaN devices becomes lower and lower, they are becoming more and more popular in the field of switching power supply applications. GaN devices show significant advantages in AC / DC and DC / DC power conversion applications, and their core value is reflected in aspects such as high-frequency characteristics, power density improvement, efficiency optimization, and system integration capabilities.

[0042] Based on the manufacturing process of monolithic integration of enhancement-mode and depletion-mode GaN HEMTs, a power integrated device with a trimming function is provided in the embodiments of the present invention, such as Figures 2A - 2BAs shown, the integrated power device with trimming function includes a fuse resistor TR1, an anti-fuse resistor ATR1, a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, and a sixth MOS transistor M6. The fuse resistor TR1, the second MOS transistor M2, and the third MOS transistor M3 constitute the positive trimming cell of the sixth MOS transistor M6. The anti-fuse resistor ATR1, the fourth MOS transistor M4, and the fifth MOS transistor M5 constitute the negative trimming cell of the sixth MOS transistor M6. Among them, the source of the first MOS transistor M1 is connected to the S port, the gates of the first MOS transistor M1, the third MOS transistor M3, the fifth MOS transistor M5, and the sixth MOS transistor M6 are all connected to the G port, the drains of the first MOS transistor M1, the second MOS transistor M2, the fourth MOS transistor M4, and the sixth MOS transistor M6 are all connected to the D port, the source of the second MOS transistor M2 is connected to the drain of the third MOS transistor M3, the gate of the second MOS transistor M2 and one end of the fuse resistor TR1 are both connected to the TS1 port, the sources of the third MOS transistor M3, the other end of the fuse resistor TR1, the source of the fifth MOS transistor M5, one end of the anti-fuse resistor ATR1, and the source of the sixth MOS transistor M6 are all connected to the SE port, the gate of the fourth MOS transistor M4 and the other end of the anti-fuse resistor ATR1 are both connected to the ATS1 port, and the source of the fourth MOS transistor M4 is connected to the drain of the fifth MOS transistor M5.

[0043] Preferably, the first MOS transistor M1, the third MOS transistor M3, the fifth MOS transistor M5, and the sixth MOS transistor M6 are all enhancement-mode MOS transistors, and the second MOS transistor M2 and the fourth MOS transistor M4 are both depletion-mode MOS transistors.

[0044] It should be noted that Figure 2A the first MOS transistor M1 and the sixth MOS transistor M6 in Figure 1B correspond to the rectifier diode and the sampling diode in Figure 2B This is a simplified diagram of the integrated power device with trimming function of the present invention. The MOS transistors therein can be of a multi-cell structure, and the other electrode leads are not drawn except for the trimming resistors.

[0045] It should be noted that below the rated current and below, the fuse resistor TR1 operates as an ordinary resistor, converting electrical energy into heat and maintaining temperature balance through heat dissipation; when the current exceeds the rated value, the fuse resistor TR1 is heated by Joule heat (Q = I 2Rt) rapidly heats up to the melting point, causing the material to fuse and thus cutting off the circuit. The antifuse is a very important one-time programmable non-volatile programming element. Its structure is a sandwich structure, mainly composed of upper and lower conductive electrodes and an intermediate insulating dielectric layer. When a suitable voltage is applied across the two ends (usually between 5V and 20V), the insulating dielectric breaks down, and the antifuse resistance ATR1 changes from a high resistance to a low resistance.

[0046] Specifically, the fuse resistance TR1, the second MOS transistor M2, and the third MOS transistor M3 constitute the positive trimming cell of the sixth MOS transistor M6. That is, after the trimming of the fuse resistance TR1 takes effect, it is equivalent to increasing the cell area of the sixth MOS transistor M6. For example, the design index of the on-resistance of the first MOS transistor M1 (rectifier) to the on-resistance of the sixth MOS transistor M6 (sampling transistor) is 1:350, but the actual value is deviated to 1:400. At this time, the positive trimming cell can be made to take effect, which is equivalent to increasing the cell area of the sixth MOS transistor M6, and thus equivalent to reducing the on-resistance of the sixth MOS transistor M6, and adjusting the on-resistance ratio back to 1:350.

[0047] Specifically, the antifuse resistance ATR1, the fourth MOS transistor M4, and the fifth MOS transistor M5 constitute the negative trimming cell of the sixth MOS transistor M6. That is, after the trimming of the antifuse resistance ATR1 takes effect, it is equivalent to reducing the cell area of the sixth MOS transistor M6. For example, the design index of the on-resistance of the first MOS transistor M1 (rectifier) to the on-resistance of the sixth MOS transistor M6 (sampling transistor) is 1:350, but the actual value is deviated to 1:300. At this time, the negative trimming cell can be made to take effect, which is equivalent to reducing the cell area of the sixth MOS transistor M6, and thus equivalent to increasing the on-resistance of the sixth MOS transistor M6, and adjusting the on-resistance ratio back to 1:350.

[0048] It should be noted that for the convenience of principle explanation and drawing, Figure 2A only one positive trimming cell and one negative trimming cell are drawn in the figure. In actual design, there can be multiple cells. Trimming only one cell is very likely to not achieve the desired on-resistance ratio, but multiple cells need to be trimmed.

[0049] Next, the working principle of the positive trimming cell and the negative trimming cell will be specifically elaborated.

[0050] The working principle of the positive trimming cell is as follows: Before trimming, the fuse resistor TR1 is in a low-resistance state, the gate potential of the second MOS transistor M2 is pulled down, and the voltage difference between the gate and the drain of the second MOS transistor M2 is negative, generally less than the threshold voltage of the second MOS transistor M2, so the second MOS transistor M2 is turned off. At this time, the branch from the D port to the SE port formed by the second MOS transistor M2 and the third MOS transistor M3 here is disconnected. When a suitable current is applied between the TS1 port and the SE port, the fuse resistor TR1 is disconnected. Without the interference of the gate potential, the two-dimensional electron gas of the second MOS transistor M2 will always exist, and the second MOS transistor M2 is in a normally-on state. At this time, the branch from the D port to the SE port where the third MOS transistor M3 is located can be controlled by the potential of the G port to be turned on or off, which is equivalent to becoming a cell of the sixth MOS transistor M6.

[0051] The working principle of the negative trimming cell is as follows: Before trimming, the anti-fuse resistor ATR1 is in a high-resistance state. Without the interference of the gate potential, the two-dimensional electron gas of the fourth MOS transistor M4 will always exist, and the fourth MOS transistor M4 is in a normally-on state. At this time, the branch from the D port to the SE port where the fifth MOS transistor M5 is located can be controlled by the potential of the G port to be turned on or off, which is equivalent to becoming a cell of the sixth MOS transistor M6. When a suitable voltage is applied between the ATS1 port and the SE port, the anti-fuse resistor ATR1 becomes low-resistance, the gate potential of the fourth MOS transistor M4 is pulled down. When the gate leakage potential difference of the fourth MOS transistor M4 is less than its threshold voltage, the fourth MOS transistor M4 is turned off due to the disconnection of the two-dimensional electron gas, and the branch from the D port to the SE port formed by the fourth MOS transistor M4 and the fifth MOS transistor M5 here is disconnected, which is equivalent to reducing the cells of the sixth MOS transistor M6.

[0052] The integrated power device with a trimming function provided by the present invention adds a trimming process during wafer testing, which can solve the problem of the fluctuation of the on-resistance ratio from the device side.

[0053] In an embodiment of the present invention, a flyback AC / DC converter is further provided, as Figures 3A - 3B shown. The flyback AC / DC converter includes an AC / DC primary controller, an EMI filter, a rectifier bridge, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a first resistor R1, a second resistor R2, and a sampling resistor R CS, the first diode D1, the second diode D2, the third diode D3, the fourth diode D4, the transformer T1, the seventh MOS transistor M7, the eighth MOS transistor M8, and the integrated power device with trimming function described above. Among them, the positive electrode of the first diode D1 is respectively connected to the drain electrodes of the first MOS transistor M1, the second MOS transistor M2, the fourth MOS transistor M4, and the sixth MOS transistor M6. The source electrode of the first MOS transistor M1 is grounded. The negative electrode of the first diode D1 is connected to the drain electrode of the seventh MOS transistor M7. The source electrode of the seventh MOS transistor M7 is connected to the HV pin of the AC / DC primary controller. The gate electrode of the seventh MOS transistor M7 is respectively connected to the gate electrode of the eighth MOS transistor M8 and the source electrode of the first MOS transistor M1. The source electrode of the eighth MOS transistor M8 is connected to the VDD pin of the AC / DC primary controller. The drain electrode of the eighth MOS transistor M8 is respectively connected to one end of the second resistor R2 and one end of the fourth capacitor C4. The gate electrode of the sixth MOS transistor M6 is connected to the GATE pin of the AC / DC primary controller. The source electrode of the sixth MOS transistor M6 is respectively connected to one end of the sampling resistor R CS and the CS pin of the AC / DC primary controller. The drain electrode of the sixth MOS transistor M6 is respectively connected to the positive electrode of the second diode D2 and the primary winding of the transformer T1.

[0054] Preferably, both the seventh MOS transistor M7 and the eighth MOS transistor M8 are depletion-mode MOS transistors.

[0055] Preferably, as Figures 3B - 3C shown, the AC / DC primary controller includes a high-voltage startup circuit. The high-voltage startup circuit includes a MOS control logic circuit, a voltage comparator, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a ninth MOS transistor M9, and a tenth MOS transistor M10. One end of the third resistor R3 and one end of the fourth resistor R4 are both connected to the HV pin of the AC / DC primary controller. The other end of the third resistor R3 is respectively connected to one end of the fifth resistor R5 and the gate electrode of the ninth MOS transistor M9. The other end of the fourth resistor R4 is connected to the drain electrode of the ninth MOS transistor M9. The source electrode of the ninth MOS transistor M9 is respectively connected to the first input terminal of the voltage comparator and the VDD pin of the AC / DC primary controller. The second input terminal of the voltage comparator is connected to the reference voltage Ref. The output terminal of the voltage comparator is connected to the gate electrode of the tenth MOS transistor M10 through the MOS control logic circuit. The drain electrode of the tenth MOS transistor M10 is connected to the other end of the fifth resistor R5. The source electrode of the tenth MOS transistor M10 is grounded.

[0056] Specifically, the MOS control logic circuit includes a variety of logic gates and an output totem pole.

[0057] It should be noted that Figure 3A in [the circuit], the diode D1 is formed by the diode connection method of short-circuiting the gate and drain of the E-mode GaN device, which plays a role in preventing reverse current after the high-voltage startup is completed. The path composed of the diode D1 and the seventh MOS transistor M7 plays a role in supplying power to the high-voltage startup circuit; the MOS transistor M8 provides a path and voltage stabilization for the auxiliary winding power supply circuit.

[0058] Figure 3A For the structure shown, by applying the positive trimming cell and negative trimming cell described above, the problem of the conduction resistance ratio offset between the rectifier diode and the sampling diode can be solved. In addition Figure 3A the first diode D1, the seventh MOS transistor M7 and the eighth MOS transistor M8 in [the circuit], compared with Figure 1B , also have the following advantages: (1) The seventh MOS transistor M7 is monolithically integrated as part of the high-voltage startup circuit, and the controller can adopt a process platform with a lower voltage range, reducing the manufacturing cost of the controller; (2) The eighth MOS transistor M8 is monolithically integrated as part of the auxiliary winding power supply circuit, saving the number of peripheral components of the auxiliary winding power supply circuit and reducing the cost of the entire system.

[0059] It should be noted that the power transistor control logic circuit and overcurrent detection inside the AC / DC primary controller are well-known prior arts to those skilled in the art, and will not be elaborated here.

[0060] The following briefly describes Figure 3B and Figure 3C the working principle of the circuit structure in [the circuit].

[0061] (1) In [the circuit], the mains AC voltage signal is input, passes through the EMI filtering part, and enters the rectifier bridge Rectifier. With the function of the rectifier bridge and the processing of the capacitor C1, the capacitor C1 outputs a signal close to DC; Figure 3B This signal close to DC enters the primary side of the transformer T1. The influence of the transformer T1 can be ignored and it directly enters the integrated power device of the present invention, and then enters the HV pin of the AC / DC primary controller through the forward-biased diode D1 and the seventh MOS transistor M7 in the normally open state; (2) In [the circuit], first, the MOS transistors M9 and M10 are in the off state before being powered on. When this signal close to DC arrives at the HV pin, the gate of the MOS transistor M9 is charged through the resistor R3; (3) In [the circuit], Figure 3C when the gate-source voltage of the MOS transistor M9 is greater than its threshold voltage, the MOS transistor M9 conducts, and the signal from the HV pin charges the capacitor C2 through the MOS transistor M9; (4) When the gate-source voltage of the MOS transistor M9 is greater than its threshold voltage, the MOS transistor M9 conducts, and the signal from the HV pin charges the capacitor C2 through the MOS transistor M9; (5) The voltage comparator collects the voltage on capacitor C2 and compares it with the reference voltage Ref generated inside the AC / DC primary controller. When the voltage on capacitor C2 reaches the reference voltage Ref, the voltage comparator outputs a signal through the MOS control logic circuit to turn on the MOS tube M10. (6) MOS tube M9 is turned off because the gate voltage is pulled down, and the voltage at node A gradually rises until Figure 3B The gate-source voltage V of the MOS tube M7 GS-M7 is less than its threshold voltage V th-M7 MOS tube M7 is turned off, and there is a leakage current from node A to GND. exist:

[0062] The threshold voltage V th-M7 The size of and the resistance values of resistors R3 and R5 further reduce the leakage current and thus reduce the static loss; (7) The power-on process is now complete, and the GATE pin of the AC / DC primary side controller starts to output a control signal, causing the MOS tube M1 to start working, chopping the near-DC signal and transmitting it to the secondary side through the transformer T1; (8) The subsequent capacitor C2 is Figure 3B The auxiliary winding in the power supply circuit is used for power supply. The working principle of the MOS tube M8 in the auxiliary winding power supply circuit is the same as that of the MOS tube M7. Since the MOS tube M8 will be turned off after the voltage on the capacitor C2 reaches the reference voltage Ref, the voltage fluctuation output by the auxiliary winding has little effect on the capacitor C2. The existence of the MOS tube M8 plays a role similar to voltage stabilization, so there is no need to add additional voltage stabilization components or voltage stabilization circuit structure to the auxiliary winding power supply circuit.

[0063] In an embodiment of the present invention, a method for manufacturing an integrated power device with a trimming function is also provided, which is used to manufacture the integrated power device with a trimming function as described above. Figures 4A - 4M FIG. 1 is a schematic diagram of a process for forming an integrated power device with a trimming function according to an embodiment of the present invention. Figures 4A - 4M As shown, the manufacturing method of the integrated power device with trimming function comprises the following steps: Step 1: If Figure 4A As shown, a substrate 1 is provided, a GaN buffer layer 2, a GaN channel layer 3 and an AlGaN barrier layer 4 are sequentially grown on the substrate 1, and a two-dimensional electron gas 5 is formed at the interface of the GaN channel layer 3 near the AlGaN (aluminum gallium nitride) barrier layer 4 according to a polarization mechanism; It should be noted that the substrate 1 may be a silicon substrate or a sapphire substrate.

[0064] Step 2: As shown in Figure 4B , form an isolation structure 6 in the GaN channel layer 3 and the AlGaN barrier layer 4 to avoid mutual influence between devices; wherein, the isolation structure 6 can be deep trench dielectric isolation or isolation formed by high-energy ion implantation.

[0065] Step 3: As shown in Figure 4C , form a P-type GaN layer 7 above the AlGaN barrier layer 4; Step 4: As shown in Figure 4D , etch the P-type GaN layer 7 and deposit gate metal 8 on the entire upper surface of the wafer, wherein a Schottky contact is formed at the contact between the gate metal 8 and the AlGaN barrier layer 4; wherein, the gate metal 8 is generally nickel or gold.

[0066] Step 5: As shown in Figure 4E , etch the gate metal 8 to form the gates of the MOS transistors in the integrated power device with trimming function; Step 6: As shown in Figure 4F , deposit drain-source metal 9 on the entire upper surface of the wafer formed in Step 5, wherein an ohmic contact is formed at the contact between the drain-source metal 9 and the AlGaN barrier layer 4; wherein, the drain-source metal 9 is generally a titanium-aluminum alloy or a titanium-aluminum-nickel-gold multi-layer structure.

[0067] Step 7: As shown in Figure 4G , etch the drain-source metal 9 to form the sources and drains of the MOS transistors in the integrated power device with trimming function; Step 8: As shown in Figure 4H , form a first interlayer dielectric 10 on the entire upper surface of the wafer formed in Step 7; Step 9: As shown in Figure 4I , etch the first interlayer dielectric 10 to form first vias 11, and fill and planarize the first vias 11 with metal; Step 10: As shown in Figure 4J , deposit and etch first interconnect metal 12 on the entire upper surface of the wafer formed in Step 9 (the metal width can be drawn narrow at the fuse resistor TR1 to facilitate thermal fusing of the fuse resistor TR1); Step 11: As shown in Figure 4K , deposit and etch amorphous silicon 13 on the entire upper surface of the wafer formed in Step 10; wherein, the amorphous silicon 13 is usually an insulating material.

[0068] Step 12: As shown in Figure 4LAs shown, a second interlayer dielectric 14 is formed on the entire upper surface of the wafer formed in step eleven, and then the second interlayer dielectric 14 is etched to form second vias 15, and then the second vias 15 are filled with metal and planarized; Step thirteen: As Figure 4M shown, a second interconnect metal 16 is deposited and etched on the entire upper surface of the wafer formed in step twelve to form the integrated power device with trimming function.

[0069] Preferably, the material of the first interlayer dielectric 10 is silicon nitride, the material of the second interlayer dielectric 14 is borophosphosilicate glass or silicon nitride, the material of the first interconnect metal 12 is lead-tin alloy, zinc alloy, silver or copper-nickel alloy, and the material of the second interconnect metal 16 is aluminum, copper or gold.

[0070] Preferably, in the filling of the first via 11 with metal, it further includes: Depositing titanium, titanium nitride and tungsten in the first via 11 in sequence.

[0071] Preferably, in the filling of the second via 15 with metal, it further includes: Depositing titanium, titanium nitride and tungsten in the second via 15 in sequence.

[0072] It can be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principle of the present invention. However, the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also regarded as the protection scope of the present invention.

Claims

1. An integrated power device with a trimming function, characterized in that, The integrated power device with trimming function includes a fuse resistor TR1, an antifuse resistor ATR1, a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, and a sixth MOS transistor M6. The fuse resistor TR1, the second MOS transistor M2, and the third MOS transistor M3 constitute the positive trimming cell of the sixth MOS transistor M6, and the antifuse resistor ATR1, the fourth MOS transistor M4, and the fifth MOS transistor M5 constitute the negative trimming cell of the sixth MOS transistor M6. Among them, the source of the first MOS transistor M1 is connected to the S port, the gates of the first MOS transistor M1, the third MOS transistor M3, the fifth MOS transistor M5, and the sixth MOS transistor M6 are all connected to the G port, the drains of the first MOS transistor M1, the second MOS transistor M2, the fourth MOS transistor M4, and the sixth MOS transistor M6 are all connected to the D port, the source of the second MOS transistor M2 is connected to the drain of the third MOS transistor M3, the gate of the second MOS transistor M2 and one end of the fuse resistor TR1 are both connected to the TS1 port, the sources of the third MOS transistor M3, the other end of the fuse resistor TR1, the source of the fifth MOS transistor M5, one end of the antifuse resistor ATR1, and the source of the sixth MOS transistor M6 are all connected to the SE port, the gate of the fourth MOS transistor M4 and the other end of the antifuse resistor ATR1 are both connected to the ATS1 port, and the source of the fourth MOS transistor M4 is connected to the drain of the fifth MOS transistor M5.

2. The integrated power device with trimming function according to claim 1, characterized in that, The first MOS transistor M1, the third MOS transistor M3, the fifth MOS transistor M5, and the sixth MOS transistor M6 are all enhancement-mode MOS transistors, and the second MOS transistor M2 and the fourth MOS transistor M4 are both depletion-mode MOS transistors.

3. A flyback AC / DC converter, characterized in that, The flyback AC / DC converter includes an AC / DC primary controller, an EMI filter, a rectifier bridge, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a first resistor R1, a second resistor R2, a sampling resistor R CS , a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a transformer T1, a seventh MOS transistor M7, an eighth MOS transistor M8, and the integrated power device with trimming function according to any one of claims 1-2. Wherein, the anode of the first diode D1 is respectively connected to the drains of the first MOS transistor M1, the second MOS transistor M2, the fourth MOS transistor M4, and the sixth MOS transistor M6. The source of the first MOS transistor M1 is grounded. The cathode of the first diode D1 is connected to the drain of the seventh MOS transistor M7. The source of the seventh MOS transistor M7 is connected to the HV pin of the AC / DC primary controller. The gate of the seventh MOS transistor M7 is respectively connected to the gate of the eighth MOS transistor M8 and the source of the first MOS transistor M1. The source of the eighth MOS transistor M8 is connected to the VDD pin of the AC / DC primary controller. The drain of the eighth MOS transistor M8 is respectively connected to one end of the second resistor R2 and one end of the fourth capacitor C4. The gate of the sixth MOS transistor M6 is connected to the GATE pin of the AC / DC primary controller. The source of the sixth MOS transistor M6 is respectively connected to one end of the sampling resistor R CS and the CS pin of the AC / DC primary controller. The drain of the sixth MOS transistor M6 is respectively connected to the anode of the second diode D2 and the primary winding of the transformer T1.

4. The flyback AC / DC converter according to claim 3, characterized in that, The seventh MOS transistor M7 and the eighth MOS transistor M8 are both depletion-mode MOS transistors.

5. The flyback AC / DC converter according to claim 3, characterized in that, The AC / DC primary controller includes a high-voltage start-up circuit. The high-voltage start-up circuit includes a MOS control logic circuit, a voltage comparator, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a ninth MOS transistor M9, and a tenth MOS transistor M10. One end of the third resistor R3 and one end of the fourth resistor R4 are both connected to the HV pin of the AC / DC primary controller. The other end of the third resistor R3 is respectively connected to one end of the fifth resistor R5 and the gate of the ninth MOS transistor M9. The other end of the fourth resistor R4 is connected to the drain of the ninth MOS transistor M9. The source of the ninth MOS transistor M9 is respectively connected to the first input terminal of the voltage comparator and the VDD pin of the AC / DC primary controller. The second input terminal of the voltage comparator is connected to the reference voltage Ref. The output terminal of the voltage comparator is connected to the gate of the tenth MOS transistor M10 through the MOS control logic circuit. The drain of the tenth MOS transistor M10 is connected to the other end of the fifth resistor R5, and the source of the tenth MOS transistor M10 is grounded.

6. The flyback AC / DC converter according to claim 5, wherein The MOS control logic circuit includes a variety of logic gates and an output totem pole.

7. A manufacturing method of an integrated power device with a trimming function, which is used to manufacture the integrated power device with a trimming function as described in any one of claims 1-2, characterized in that, The manufacturing method of the integrated power device with a trimming function includes: Step 1: Provide a substrate (1), and sequentially grow a GaN buffer layer (2), a GaN channel layer (3), and an AlGaN barrier layer (4) on the substrate (1). A two-dimensional electron gas (5) is formed at the interface of the GaN channel layer (3) close to the AlGaN barrier layer (4); Step 2: Form an isolation structure (6) in the GaN channel layer (3) and the AlGaN barrier layer (4); Step 3: Form a P-type GaN layer (7) above the AlGaN barrier layer (4); Step 4: Etch the P-type GaN layer (7), and deposit gate metal (8) on the entire upper surface of the wafer. A Schottky contact is formed at the contact between the gate metal (8) and the AlGaN barrier layer (4); Step 5: Etch the gate metal (8) to form the gates of each MOS transistor; Step 6: Deposit drain-source metal (9) on the entire upper surface of the wafer formed in Step 5. An ohmic contact is formed at the contact between the drain-source metal (9) and the AlGaN barrier layer (4); Step 7: Etch the drain-source metal (9) to form the source and drain of each MOS transistor; Step 8: Form a first interlayer dielectric (10) on the entire upper surface of the wafer formed in Step 7; Step 9: Etch the first interlayer dielectric (10) to form a first via hole (11), and fill the first via hole (11) with metal and planarize; Step 10: Deposit and etch first interconnect metal (12) on the entire upper surface of the wafer formed in Step 9; Step 11: Deposit and etch amorphous silicon (13) on the entire upper surface of the wafer formed in Step 10; Step 12: Form a second interlayer dielectric (14) on the entire upper surface of the wafer formed in Step 11, then etch the second interlayer dielectric (14) to form a second via hole (15), and then fill the second via hole (15) with metal and planarize; Step 13: Deposit and etch second interconnect metal (16) on the entire upper surface of the wafer formed in Step 12 to form the integrated power device with a trimming function.

8. The manufacturing method of the integrated power device with trimming function according to claim 7, characterized in that, The material of the first interlayer dielectric (10) is silicon nitride, the material of the second interlayer dielectric (14) is borophosphosilicate glass or silicon nitride, the material of the first interconnect metal (12) is lead-tin alloy, zinc alloy, silver, or copper-nickel alloy, and the material of the second interconnect metal (16) is aluminum, copper, or gold.

9. The manufacturing method of the integrated power device with trimming function according to claim 7, characterized in that, In the process of filling the first via hole (11) with metal, it further includes: Sequentially deposit titanium, titanium nitride, and tungsten in the first via hole (11).

10. The manufacturing method of the integrated power device with trimming function according to claim 7, characterized in that, In the process of filling the second via hole (15) with metal, it further includes: Sequentially deposit titanium, titanium nitride, and tungsten in the second via hole (15).

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