Semiconductor structure and forming method thereof

Abstract

According to the semiconductor structure and the forming method thereof, in the forming method of the semiconductor structure, transverse intervals between adjacent first core shaft layers are of a first size, the transverse size of each first core shaft layer is of a second size, a first side wall layer is formed on the side wall of each first core shaft layer, and the transverse size of each first side wall layer is of a third size; the sum of the double third size and the second size is equal to the first size, so that the transverse intervals of the adjacent first side wall layers are the same, and in the step of etching the core shaft material layer by taking the first side wall layers as masks, the etching loads borne by the core shaft material layer in each region are the same; according to the manufacturing method, the transverse intervals between the adjacent second side wall layers formed according to the second core shaft layer are easy to be the same, so that in the process of etching the dielectric material layer by taking the second side wall layers as masks, the center line of the formed separation layer is not easy to deviate, the problem of etching load caused by non-uniform mask patterns is solved, and the etching efficiency is improved. The reliability of the semiconductor structure is enhanced, and mass production is facilitated.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] With the continuous improvement of the integration degree of integrated circuits, integrated circuits are rapidly developing towards sub-micron and deep sub-micron directions, and their pattern line widths will become thinner and thinner, which poses higher requirements for semiconductor processes. Therefore, it has become an urgent issue to conduct in-depth research on how to achieve fine line-width patterns to meet the new requirements of semiconductor processes.

[0003] As a technological innovation in the lithography process, Self-Aligned Quadruple Patterning (SAQP for short) aims to greatly improve the performance and capacity of integrated circuits by increasing the pattern density. In the traditional lithography process, we usually coat a photoresist on the surface of a semiconductor wafer, and then irradiate it with light of a specific wavelength to define and form the required micro-patterns through a lithography mask. The introduction of self-aligned quadruple patterning technology marks the birth of a more efficient and finer process method.

[0004] In the field of precision and complex integrated circuit design, Standard Cells play an extremely crucial role. When the technology node develops towards smaller feature sizes, even without the use of extreme ultraviolet (EUV) lithography machines, self-aligned quadruple patterning technology can further reduce the pattern pitch, but the reliability of the current semiconductor structure still needs to be further improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, and to optimize the reliability of the semiconductor structure.

[0006] To solve the above problems, embodiments of the present invention provide a semiconductor structure, including: a dielectric layer, the dielectric layer includes a plurality of spaced-apart first regions and second regions located between the spaced-apart first regions, with the direction perpendicular to the junction of the second region and the first region as the transverse direction, the transverse dimension of the second region is greater than the transverse dimension of the first region; a plurality of spacer layers, located on the dielectric layer, adjacent spacer layers and the dielectric layer form grooves, and the transverse spacing of the grooves in the second region is the same; a first metal layer, located in the grooves of the first region; a second metal layer, located in the grooves of the second region, and the transverse dimension of the first metal layer is an odd multiple of the transverse dimension of the second metal layer.

[0007] Correspondingly, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, where the substrate includes a dielectric material layer and a mandrel material layer located on the dielectric material layer, and on the surface of the dielectric material layer, the lateral direction is perpendicular to the extending direction of the mandrel material layer; forming a plurality of spaced-apart first mandrel layers on the mandrel material layer, the lateral spacing between adjacent first mandrel layers being a first dimension, and the lateral dimension of the first mandrel layer being a second dimension; forming a first spacer layer on the sidewalls of the first mandrel layer, the lateral dimension of the first spacer layer being a third dimension, and the sum of twice the third dimension and the second dimension being equal to the first dimension, such that the lateral spacing between adjacent first spacer layers is equal; etching the mandrel material layer using the first spacer layer as a mask to form a second mandrel layer; forming a second spacer layer on the sidewalls of the second mandrel layer, the lateral spacing between adjacent second spacer layers being the same; etching the dielectric material layer using the second spacer layer as a mask to form a dielectric layer and discrete spacer layers located on the dielectric layer, and adjacent spacer layers and the dielectric layer constituting a groove; and forming a metal material layer in the groove.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] In the method for forming a semiconductor structure provided by the embodiment of the present invention, a plurality of spaced-apart first mandrel layers are formed on the mandrel material layer, the lateral spacing between adjacent first mandrel layers being a first dimension, and the lateral dimension of each first mandrel layer being a second dimension. A first spacer layer is formed on the sidewalls of the first mandrel layer, the lateral dimension of the first spacer layer being a third dimension. Since the sum of twice the third dimension and the second dimension is equal to the first dimension, the lateral spacing between adjacent first spacer layers is equal, that is, the lateral spacing between adjacent first spacer layers is the same. Therefore, in the step of etching the mandrel material layer using the first spacer layer as a mask, the etching load on the mandrel material layer in each region is the same, making it difficult for the center line of the formed second mandrel layer to shift, and enabling the lateral spacing between adjacent second spacer layers formed based on the second mandrel layer to be easily the same. Thus, in the process of etching the dielectric material layer using the second spacer layer as a mask, the etching load on the dielectric material layer in each region is easily the same, making it difficult for the center line of the formed spacer layer to shift, solving the etching load problem caused by non-uniform mask patterns, enhancing the reliability of the semiconductor structure, and being conducive to mass production.

[0010] In an alternative solution, in the embodiment of the present invention, by removing the spacer layer in the first region or removing the second sidewall layer in the first region, the lateral dimension of the groove for forming the first metal layer in the first region is enlarged. Subsequently, the lateral dimension of the first metal layer formed in the first region is greater than that of the second metal layer in the second region, meeting the design requirements of the semiconductor structure. Moreover, since the process window for removing the second sidewall layer or the spacer layer in the first region is large, the process implementation difficulty is also reduced. In addition, since the lateral intervals between the second sidewall layers in the second region are the same, in the step of etching the dielectric material layer using the second sidewall layers in the second region as a mask, the etching load of the dielectric material layer at each location in the second region is likely to be the same, making it difficult for the center line of the spacer layer formed in the second region to shift. In other words, the position of the groove is not likely to shift, and thus the position of the second metal layer formed based on the groove in the second region is not likely to shift. Furthermore, after removing the second sidewall layer or the spacer layer in the first region, there is no spacer layer in the first region, and the position of the groove in the first region is surrounded by the spacer layers at the lateral edges in the second region. This also makes it difficult for the position of the first metal layer in the first region to shift, improving the position accuracy of both the second metal layer and the first metal layer, reducing the etching load problem caused by non-uniform mask patterns during the pattern transfer process, enhancing the reliability of the semiconductor structure, and facilitating mass production. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figures 1 to 5 is a schematic structural diagram of a formation process of a semiconductor structure;

[0012] Figures 6 to 17 is a schematic structural diagram corresponding to each step in the first embodiment of the method for forming a semiconductor structure according to an embodiment of the present invention;

[0013] Figures 18 to 23 is a schematic structural diagram corresponding to each step in the second embodiment of the method for forming a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0014] Currently, the reliability of semiconductor structures still needs to be improved. The reasons for poor reliability are analyzed in combination with a formation process of a semiconductor structure.

[0015] Figures 1 to 5 shows a schematic structural diagram of a formation process of a semiconductor structure.

[0016] As Figure 1 shown, a substrate is provided, the substrate includes a dielectric material layer 1 and a mandrel material layer 2 located on the dielectric material layer 1; a plurality of spaced-apart first mandrel layers 3 are formed on the mandrel material layer 2, and taking the extension direction perpendicular to the first mandrel layer 3 as the lateral direction, the lateral intervals between adjacent first mandrel layers 3 are different.

[0017] AsFigure 2 As shown, a first sidewall layer 4 is formed on the sidewall of the first mandrel layer 3. After the first sidewall layer 4 is formed, the first mandrel layer 3 is removed.

[0018] As Figure 3 shown, the mandrel material layer 2 is etched using the first sidewall layer 4 as a mask to form a second mandrel layer 5. A second sidewall layer (not shown in the figure) is formed on the sidewall of the second mandrel layer 5; after the second sidewall layer is formed, the second mandrel layer 5 is removed.

[0019] As Figure 4 shown, after the second mandrel layer 5 is removed, the dielectric material layer 1 is etched using the second sidewall layer as a mask to form a dielectric layer 6 and discrete spacer layers 7 located on the dielectric layer 6, and the dielectric layer 6 and the spacer layers 7 constitute a groove 8.

[0020] As Figure 5 shown, a metal layer 9 is formed in the groove 8.

[0021] The metal layer 9 includes signal lines (Routing Tracks) for transmitting signals and power lines (Power Rail) for power supply. Considering the usage characteristics of the signal lines and power lines, the lateral dimension of the power line needs to be larger than that of the signal line to obtain a smaller conduction resistance. In order to make the lateral dimensions of the signal lines and power lines formed between the respective spacer layers 7 meet the preset requirements, in the step of providing the substrate, the intervals between adjacent first mandrel layers 3 are not uniform, so that the intervals between the first sidewall layers formed based on the first mandrel layer 3 are not uniform. This results in different etching loads of the mandrel material layer 2 at various locations during the process of etching the mandrel material layer 2 using the first sidewall layer 4 as a mask, leading to a shift in the position of the formed second mandrel layer 5; in addition, because the intervals on both sides of the first sidewall layer are not uniform, during the process of etching the dielectric material layer 1 using the first sidewall layer as a mask, there are differences in the etching loads of the dielectric material layers in different regions, which easily causes a further shift in the position of the formed spacer layer 7, and easily causes the lateral dimension of the metal layer 9 formed in the groove not to meet the design requirements. In addition, in the actual semiconductor process, the formation process of the second sidewall layer needs to be coordinated with other process steps, which also makes the process of etching the dielectric material layer 1 using the second sidewall layer more complex and requires meeting a variety of extremely strict critical process parameters (MTS), which also results in a smaller process window for forming the signal lines and power lines.

[0022] To solve the above technical problems, in the method for forming a semiconductor structure provided by an embodiment of the present invention, a plurality of first mandrel layers spaced apart from each other are formed on the mandrel material layer. The lateral spacing between adjacent first mandrel layers is a first dimension, the lateral dimension of each first mandrel layer is a second dimension, and a first sidewall layer is formed on the sidewalls of the first mandrel layers. The lateral dimension of the first sidewall layer is a third dimension. Since the sum of twice the third dimension and the second dimension is equal to the first dimension, the lateral spacing between adjacent first sidewall layers is equal. In other words, the lateral spacing between adjacent first sidewall layers is the same. Therefore, in the step of etching the mandrel material layer using the first sidewall layer as a mask, the etching load on the mandrel material layer in each region is the same, making it difficult for the center line of the formed second mandrel layer to shift. It is possible to make the lateral spacing between adjacent second sidewall layers formed based on the second mandrel layer easily the same. Thus, in the process of etching the dielectric material layer using the second sidewall layer as a mask, the etching load on the dielectric material layer in each region is easily the same, making it difficult for the center line of the formed separation layer to shift, solving the etching load problem caused by non-uniform mask patterns, enhancing the reliability of the semiconductor structure, and being beneficial for mass production.

[0023] To make the above objects, features, and advantages of the embodiments of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the embodiments of the present invention will be given with reference to the accompanying drawings.

[0024] Figures 6 to 17 It is a schematic structural diagram corresponding to each step in the first embodiment of the method for forming a semiconductor structure according to an embodiment of the present invention.

[0025] Refer to Figure 6 , a substrate is provided. The substrate includes a dielectric material layer 100 and a mandrel material layer 101 located on the dielectric material layer 100. The lateral direction is parallel to the surface of the dielectric material layer 100 and perpendicular to the extension direction of the mandrel material layer 101.

[0026] The substrate provides a process platform for subsequent semiconductor formation methods. In this embodiment, the semiconductor structure is used to form a 6T standard cell structure. The 6T standard cell structure has the advantage of small size and is suitable for low-power scenarios. In other embodiments, the semiconductor structure can also be used to form a 7T standard cell structure. The 7T is higher than the 6T standard cell structure, and the channel is larger during operation, capable of carrying more carriers and having stronger performance.

[0027] The use of standard cells makes the design and manufacturing of integrated circuits modular and standardized, improving design efficiency and repeatability. Different heights of standard cells can be selected according to specific application requirements (such as performance, power consumption, chip area) to optimize the design.

[0028] In this embodiment, the material of the dielectric material layer 100 is a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9), an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative dielectric constant less than 2.6), silicon oxide, silicon nitride, silicon oxynitride, or other dielectric materials.

[0029] In this embodiment, a transistor (not shown in the figure) is formed at the bottom of the dielectric material layer 100. The transistor can be one or both of an NMOS transistor and a PMOS transistor. Specifically, the transistor includes functional structures such as a gate structure, source / drain doping layers located on both sides of the gate structure, and contact hole plugs on the source / drain doping layers.

[0030] In this embodiment, the substrate includes a plurality of spaced-apart first regions I and second regions II located between the spaced-apart first regions I. The lateral dimension of the second region II is greater than that of the first region I.

[0031] It should be noted that the substrate also includes an edge region (not marked in the figure) located at the edges of the first region I and the second region II. During photolithography and pattern transfer, due to the loading effect between the edge and the center during the etching process, the pattern formed in the edge region will have a deviation, resulting in a decrease in pattern accuracy and affecting the reliability of the finally formed semiconductor structure. Therefore, in this embodiment, the pattern formed in the subsequent edge region is not a component of the actual device and does not have an actual function.

[0032] In the subsequent process, the first region I and the second region II are respectively used to form metal layers with different lateral dimensions.

[0033] The mandrel material layer 101 is prepared for the subsequent etching to form the second mandrel layer.

[0034] Specifically, the material of the mandrel material layer 101 includes one or more of silicon oxide, silicon oxynitride, silicon carbonitride, silicon, silicon nitride, amorphous silicon, and metal oxides. As an example, the material of the mandrel material layer 101 is silicon.

[0035] It should be noted that the substrate also includes: a mask material stack 102, located between the dielectric material layer 100 and the mandrel material layer 101. The mask material stack 102 includes: a first mask material layer 1021 and a second mask material layer 1022 located on the first mask material layer 1021.

[0036] In the subsequent formation process of the semiconductor structure, the first mask material layer 1021 and the second mask material layer 1022 are respectively etched to form a first mask layer and a second mask layer.

[0037] In this embodiment, the etching rate of the first mask material layer 1021 is less than that of the second mask material layer 1022. During the subsequent process of etching the second mask material layer 1022 to form the second mask layer, the first mask material layer 1021 serves as an etching stop layer, ensuring that the etching rates of the second mask material layer 1022 at various locations on the first mask material layer 1021 are consistent.

[0038] The materials of the first mask material layer 1021 and the second mask material layer 1022 both include one or more of silicon nitride, silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the first mask material layer 1021 is silicon nitride, and the material of the second mask material layer 1022 is silicon oxynitride.

[0039] Continue to refer to Figure 6 , a plurality of spaced-apart first mandrel layers 103 are formed on the mandrel material layer 101. The lateral dimensions of each of the first mandrel layers 103 are the same, and the lateral intervals between adjacent first mandrel layers 103 are also the same.

[0040] The first mandrel layer 103 prepares for the subsequent formation of the first sidewall layer. In the method for forming the semiconductor structure provided by the embodiment of the present invention, forming a plurality of spaced-apart first mandrel layers 103 on the mandrel material layer 101, where the lateral dimensions of each of the first mandrel layers 103 are the same and the lateral intervals between adjacent first mandrel layers 103 are also the same, is beneficial for making the density on both sides of the first sidewall layer formed based on the first mandrel layer 103 approach consistency.

[0041] In this embodiment, in the step of forming a plurality of spaced-apart first mandrel layers 103 on the mandrel material layer 101, the lateral interval between adjacent first mandrel layers 103 is a first dimension D1 (as shown in Figure 6 ), and the lateral dimension of the first mandrel layer 103 is a second dimension D2 (as shown in Figure 6 ).

[0042] Refer to Figure 7 , a first sidewall layer 104 is formed on the sidewalls of the first mandrel layer 103, and the lateral intervals between adjacent first sidewall layers 104 are equal.

[0043] The first sidewall layer 104 serves as an etching mask for the subsequent etching of the mandrel material layer 101. Since the lateral intervals between adjacent first sidewall layers 104 are equal, in the step of etching the mandrel material layer 101 using the first sidewall layer 104 as a mask, the etching loads on the mandrel material layer 101 in each region are likely to be the same, making the centerline of the formed second mandrel layer less likely to shift, solving the etching load problem caused by the non-uniformly spaced first sidewall layer, enhancing the reliability of the semiconductor structure, and being beneficial for mass production.

[0044] In this embodiment, in the step of forming the first sidewall layer 104 on the sidewall of the first mandrel layer 103, the lateral dimension of the first sidewall layer 104 is the third dimension D3, and the sum of twice the third dimension D3 and the second dimension D2 is equal to the first dimension D1. This makes the intervals between adjacent first sidewall layers 104 equal. Subsequently, in the step of etching the mandrel material layer 101 using the first sidewall layer 104 as a mask, the etching load on the mandrel material layer 101 in each region is likely to be the same, making it less likely for the center line of the formed second mandrel layer to shift, avoiding the etching load problem caused by the first sidewall layers 104 with non-uniform intervals, and improving the reliability of the semiconductor structure forming method.

[0045] In this embodiment, the step of forming the first sidewall layer 104 on the sidewall of the first mandrel layer 103 includes: conformally covering a first sidewall material layer (not shown in the figure) on the first mandrel layer 103 and on the mandrel material layer 101 exposed by the first mandrel layer 103; removing the first sidewall material layer on the top of the first mandrel layer 103 and on the mandrel material layer 101, and the remaining first sidewall material layer on the sidewall of the first mandrel layer 103 serves as the first sidewall layer 104.

[0046] In this embodiment, the first sidewall material layer is formed by chemical vapor deposition (CVD). In other embodiments, it can also be formed by atomic layer deposition (ALD) or physical vapor deposition (PVD).

[0047] The material of the first sidewall layer 104 includes one or more of silicon nitride, silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the first sidewall layer 104 includes silicon nitride.

[0048] The method for forming a semiconductor structure further includes: after forming the first sidewall layer 104 on the sidewall of the first mandrel layer 103, removing the first mandrel layer 103.

[0049] Removing the first mandrel layer 103 prepares for subsequent etching of the mandrel material layer 101 using the first sidewall layer 104 as a mask to form the second mandrel layer.

[0050] Reference Figure 8 , etching the mandrel material layer 101 using the first sidewall layer 104 as a mask to form the second mandrel layer 105.

[0051] In the embodiment of the present invention, the lateral intervals between adjacent first sidewall layers 104 are equal. In other words, the density on both sides of the first sidewall layer 104 is the same. Therefore, in the step of etching the mandrel material layer 101 with the first sidewall layer 104 as a mask, the etching load on the mandrel material layer 101 in each region is the same, making the center line of the formed second mandrel layer 105 not easily deviate, and enabling the lateral intervals between adjacent second sidewall layers formed subsequently based on the second mandrel layer 105 to be easily the same.

[0052] The second mandrel layer 105 provides a process basis for forming the second sidewall layer 106 subsequently.

[0053] In this embodiment, the mandrel material layer 101 is etched with the first sidewall layer 104 as a mask by a dry etching process to form the second mandrel layer 105. The dry etching process is an anisotropic etching process, which has good etching profile controllability and is beneficial to accurately transfer the pattern of the first sidewall layer 104 to the second mandrel layer 105.

[0054] Reference Figure 9 and Figure 10 , a second sidewall layer 106 is formed on the sidewall of the second mandrel layer 105, and the lateral intervals between adjacent second sidewall layers 106 are the same.

[0055] In the method for forming a semiconductor structure provided by the embodiment of the present invention, subsequently, the dielectric material layer 100 is etched with the second sidewall layer 106 as a mask to form a dielectric layer and discrete spacer layers located on the dielectric layer. The adjacent spacer layers and the dielectric layer form grooves. Because the lateral intervals between adjacent second sidewall layers 106 are the same, in the process of etching the dielectric material layer 100 with the second sidewall layer 106 as a mask subsequently, the etching load on the dielectric material layer 100 in each region is easily the same, making the center line of the formed spacer layer not easily deviate, solving the etching load problem caused by non-uniform mask patterns, enhancing the reliability of the semiconductor structure, and being beneficial to mass production.

[0056] In this embodiment, the step of forming the second sidewall layer 106 on the sidewall of the second mandrel layer 105 includes: conformally covering a second sidewall material layer (not shown in the figure) on the second mandrel layer 105 and on the mask material stack 102 exposed by the second mandrel layer 105; removing the second sidewall material layer on the top of the second mandrel layer 105 and on the mask material stack 102, and the remaining second sidewall material layer on the sidewall of the second mandrel layer 105 serves as the second sidewall layer 106.

[0057] In this embodiment, the second sidewall material layer is formed by chemical vapor deposition. In other embodiments, atomic layer deposition or physical vapor deposition can also be used.

[0058] The material of the second sidewall layer 106 includes one or more of silicon nitride, silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the second sidewall layer 106 includes silicon nitride.

[0059] In this embodiment, in the step of forming the second sidewall layer 106, the second sidewall layer 106 includes a plurality of device sidewalls 1061 and a plurality of dummy sidewalls 1062. The second sidewall layer 106 in the first region I is a dummy sidewall 1062, and the second sidewall layer 106 in the second region II is a device sidewall 1061, and the number of device sidewalls 1061 between adjacent dummy sidewalls 1062 is equal.

[0060] It should be noted that in the step of forming the second sidewall layer 106 on the sidewall of the second mandrel layer 105, by controlling the thickness of the second sidewall material layer, the lateral spacing between adjacent second sidewall layers 106 formed can be made the same.

[0061] In the subsequent process, the dielectric material layer 100 is etched using the device sidewall 1061 as a mask, and the dummy sidewall 1062 is etched and removed in the subsequent process. The lateral dimension of the groove in the first region I is larger than that in the second region II, and the number of device sidewalls 1061 between adjacent dummy sidewalls 1062 is equal, such that after the subsequent removal of the dummy sidewall 1062, the grooves in the first region I and the second region II are regularly arranged, which is beneficial to meeting the specific design requirements of the semiconductor structure.

[0062] As an embodiment, in the step of forming the second sidewall layer 106 on the sidewall of the second mandrel layer 105, the lateral dimension of the second sidewall layer 106 is equal to the lateral spacing dimension between the second sidewall layers 106.

[0063] In the subsequent steps of the method for forming the semiconductor structure, it is necessary to remove the dummy sidewall 1062 in the second sidewall layer 106, and then etch the dielectric material layer 100 using the device sidewall 1061 as a mask. The lateral dimension of the second sidewall layer 106 is equal to the lateral spacing dimension between the second sidewall layers 106, such that the size of the groove in the subsequent first region I is an odd multiple of the size of the groove in the second region II, which can better match the resistance and inductance characteristics, help reduce reflection and loss during signal transmission, improve signal integrity and reduce delay. In addition, it can optimize the thermal distribution and heat dissipation path, improve the thermal stability of the semiconductor structure, improve the performance and reliability of the entire circuit, optimize the manufacturing process, and reduce costs.

[0064] As Figure 10 shown, the method for forming the semiconductor structure further includes: after forming the second sidewall layer 106 on the sidewall of the second mandrel layer 105, removing the second mandrel layer 105.

[0065] Remove the second mandrel layer 105 to prepare for subsequent etching of the dielectric material layer 100 using the second sidewall layer 106 as a mask to form a dielectric layer and discrete spacer layers located on the dielectric layer.

[0066] Reference Figures 11 to 14 , Figure 12 For Figure 11 a partial schematic view of region A in

[0067] In the embodiment of the present invention, by removing the second sidewall layer 106 in the first region I, the lateral dimension of the groove for forming the first metal layer in the first region I is enlarged. Subsequently, the lateral dimension of the first metal layer formed in the first region I is greater than the lateral dimension of the second metal layer in the second region II, meeting the design requirements of the semiconductor structure. Moreover, since the process window for removing the second sidewall layer 106 in the first region I is large, the process implementation difficulty is also reduced. Because the lateral spacing between the second sidewall layers 106 in the second region II is the same, in the step of etching the dielectric material layer using the second sidewall layer 106 in the second region II as a mask, the etching load of the dielectric material layer at each location in the second region II is likely to be the same, making it difficult for the center line of the spacer layer formed in the second region II to shift. In other words, the position of the groove is not likely to shift, and thus the position of the second metal layer formed based on the groove in the second region II is not likely to shift. In addition, since no spacer layer is formed in the first region I after removing the second sidewall layer 106 in the first region I, the position of the groove in the first region I is surrounded by the spacer layers at the lateral edges in the second region II, which also makes the position of the first metal layer in the first region I not likely to shift. The position accuracy of both the second metal layer and the first metal layer is improved, reducing the etching load problem caused by non-uniform mask patterns during the pattern transfer process, enhancing the reliability of the semiconductor structure, and being beneficial for mass production.

[0068] Since the second sidewall layer 106 in the first region I is a dummy sidewall 1062, in the step of removing the second sidewall layer 106 in the first region I, the dummy sidewall 1062 is removed to prepare for subsequent etching of the dielectric material layer 100 using the device sidewall 1061 as a mask.

[0069] As an example, the number of dummy sidewalls 1062 is four, and each dummy sidewall 1062 in the first region I is one, and the number of device sidewalls 1061 between adjacent dummy sidewalls 1062 is five. The semiconductor structure is a 6T standard cell structure. The 6T standard cell structure has the advantage of small size and is suitable for low-power scenarios.

[0070] As another example, the number of dummy sidewalls 1062 is three, and there is one dummy sidewall 1062 in each first region I. The number of device sidewalls 1061 between adjacent dummy sidewalls 1062 is six. The semiconductor structure is a 7T standard cell structure, which is higher than the 6T standard cell structure. When working, the channel is larger and can carry more carriers, so the performance is stronger.

[0071] The steps of removing the dummy sidewalls 1062 include: as Figure 11 and Figure 12 shown, an organic material layer 107 is formed on the mask material stack 102 and the second sidewall layer 106, a bottom anti-reflection coating 108 is located on the organic material layer 107, and a photoresist layer 109 is located on the bottom anti-reflection coating 108. The bottom anti-reflection coating 108 in the first region I is exposed by the photoresist layer 109; as Figure 13 and Figure 14 shown, the dummy sidewalls 1062 are removed by etching using the photoresist layer 109 as a mask.

[0072] In this embodiment, the dummy sidewalls 1062 are removed by a dry etching process using the photoresist layer 109 as a mask. The dry etching process is an anisotropic etching process, which is beneficial to reducing the damage to the layers covered by the photoresist layer 109.

[0073] It should be noted that as Figure 13 and Figure 14 shown, in the step of removing the dummy sidewalls 1062, the photoresist layer 109 and the bottom anti-reflection coating 108 are completely removed, and a part of the thickness of the organic material layer 107 is also etched. Correspondingly, the method for forming the semiconductor structure further includes: removing the remaining organic material layer 107 after removing the dummy sidewalls 1062.

[0074] Referring to Figures 15 to 16 , the dielectric material layer 100 is etched using the second sidewall layer 106 as a mask to form a dielectric layer 111 and discrete spacer layers 112 located on the dielectric layer 111. Adjacent spacer layers 112 and the dielectric layer 111 form grooves 113.

[0075] The grooves 113 are prepared for the subsequent formation of the metal material layer.

[0076] Specifically, in the step of etching the dielectric material layer 100 using the second sidewall layer 106 as a mask, the dielectric material layer 100 is etched using the device sidewall 1061 as a mask.

[0077] The step of etching the dielectric material layer 100 using the device sidewall 1061 as a mask includes: etching the mask material stack 102 using the device sidewall 1061 as a mask to form a mask stack 110, where the mask stack 110 includes a first mask layer 1101 and a second mask layer 1102 located on the first mask layer 1101; etching the dielectric material layer 100 using the mask stack 110 as a mask to form a dielectric layer 111 and discrete spacer layers 112 located on the dielectric layer 111.

[0078] In this embodiment, the reason for using the mask stack 110 to etch the dielectric material layer 100 instead of directly etching using the device sidewall 1061 is that by first etching to form the mask stack 110 through the device sidewall 1061 and then etching the dielectric material layer 100 according to the mask stack 110, it is beneficial to improve the selectivity of the etching process, and enhance the accuracy and controllability of the etching process. In other embodiments, the device sidewall can also be directly used as a mask to etch the dielectric material layer.

[0079] In this embodiment, the dielectric material layer 100 is etched using the device sidewall 1061 as a mask by a dry etching process to form a dielectric layer 111 and discrete spacer layers 112 located on the dielectric layer 111. The dry etching process is an anisotropic etching process, which has good etching profile controllability, facilitating the sidewalls of the spacer layers 112 to be relatively vertical, and correspondingly, the sidewalls of the grooves 113 to be relatively vertical.

[0080] Because in the step of forming the second sidewall layer 106 on the sidewalls of the second mandrel layer 105, the lateral dimension of the second sidewall layer 106 is equal to the lateral spacing dimension between the second sidewall layers 106. Therefore, in the step of etching the dielectric material layer 100 using the second sidewall layer 106 as a mask to form the spacer layer 112, the lateral dimension of the groove 113 in the first region I is three times that of the groove 113 in the second region II.

[0081] The method for forming the semiconductor structure further includes: after forming the dielectric layer 111 and the spacer layers 112 located on the dielectric layer 111, removing the mask stack 110.

[0082] Removing the mask stack 110 prepares for forming a metal material layer in the groove 113 later, facilitating the top of the metal material layer to be flush with the top of the spacer layer 112.

[0083] Reference Figure 17 , a metal material layer is formed in the groove 113.

[0084] In this embodiment, the metal material layer in the groove 113 of the second region II serves as the second metal layer 114, and the metal material layer in the groove 113 of the first region I serves as the first metal layer 115.

[0085] In this embodiment, in the step of forming the metal material layer in the groove 213, the first metal layer 115 is connected to the contact hole plug in the bottom of the dielectric layer 111; the second metal layer 114 is connected to the contact hole plug in the bottom of the dielectric layer 111.

[0086] Specifically, the second metal layer 114 includes signal lines (Power Rail), and the first metal layer 115 includes power lines (Routing Tracks).

[0087] The main function of the signal lines is to transmit signals and connect different electronic components, such as processors, memories, and other integrated circuits. The main function of the power lines is to distribute power throughout the semiconductor structure to ensure that power is delivered to different electronic components.

[0088] In this embodiment, the number of second metal layers 114 between adjacent first metal layers 115 is the same, which is beneficial to meeting the specific design requirements of the semiconductor structure. In this embodiment, the number of second metal layers 114 between adjacent first metal layers 115 is four. In other embodiments, the semiconductor structure is a 7T standard cell structure, the number of first metal layers is three, and the number of second metal layers between adjacent first metal layers is five. The semiconductor structure is a 7T standard cell structure.

[0089] In this embodiment, the lateral dimension of the first metal layer 115 is larger than that of the second metal layer 114, so that the resistance of the first metal layer 115 is smaller, which is beneficial to reducing the voltage drop.

[0090] The step of forming the metal material layer in the groove 113 includes: forming a metal material film (not shown in the figure) covering the spacer layer 112 and the dielectric layer 111, and the top of the metal material film is higher than the top of the spacer layer 112; removing the metal material film higher than the spacer layer 112, and the remaining metal material film between the spacer layers 112 is used as the metal material layer.

[0091] In this embodiment, a chemical mechanical planarization (CMP) process is used to remove the metal material film higher than the spacer layer 112.

[0092] Reference Figures 18 to 23 is a schematic structural diagram corresponding to each step in the second embodiment of the method for forming a semiconductor structure according to an embodiment of the present invention.

[0093] The same parts of this embodiment and the first embodiment are not described herein again. The differences are as follows: in the method for forming a semiconductor structure, after forming the second sidewall layer and before forming the spacer layer, the second sidewall layer in the first region is not removed; instead, after forming the spacer layer 212 (such as Figure 20After the (as shown), before forming the metal material layer, the spacer layer 212 in the first region I is removed.

[0094] Reference Figure 18 , a second sidewall layer 206 is formed on the sidewall of the second mandrel layer (not shown in the figure), and the lateral spacing between adjacent second sidewall layers 206 is the same.

[0095] In the method for forming a semiconductor structure provided by the embodiment of the present invention, because the lateral spacing between adjacent second sidewall layers 206 is the same, during the subsequent etching of the dielectric material layer 200 using the second sidewall layer 206 as a mask, the etching load on the dielectric material layer 200 in each region is likely to be the same, making the center line of the subsequent formed spacer layer not prone to shift, solving the etching load problem caused by non-uniform mask patterns, enhancing the reliability of the semiconductor structure, and being beneficial to mass production.

[0096] In this embodiment, the step of forming the second sidewall layer 206 on the sidewall of the second mandrel layer includes: conformally covering a second sidewall material layer (not shown in the figure) on the second mandrel layer and the mask material stack exposed on the second mandrel layer; removing the second sidewall material layer on the top of the second mandrel layer and the mask material stack, and the remaining second sidewall material layer on the sidewall of the second mandrel layer serves as the second sidewall layer 206.

[0097] It should be noted that in the step of forming the second sidewall layer 206 on the sidewall of the second mandrel layer, the lateral dimension of the second sidewall layer 206 is equal to the lateral spacing dimension between the second sidewall layers 206.

[0098] In the subsequent steps of the method for forming a semiconductor structure, the dielectric material layer 200 is etched using the second sidewall layer 206 as a mask to form a dielectric layer and discrete spacer layers on the dielectric layer, and adjacent spacer layers and dielectric layers form grooves. The method for forming a semiconductor structure further includes removing the spacer layer in the first region I. Because the lateral dimension of the second sidewall layer 206 is equal to the lateral spacing dimension between the second sidewall layers 206, the lateral dimension of the subsequent formed spacer layer is equal to the lateral spacing between the spacer layers. After removing the spacer layer in the first region I, the size of the groove in the subsequent first region I is an integer multiple of the size of the groove in the second region II, which can better match the resistance and inductance characteristics, help reduce reflection and loss during signal transmission, improve signal integrity and reduce time delay. In addition, it can optimize the thermal distribution and heat dissipation path, improve the thermal stability of the semiconductor structure, improve the performance and reliability of the entire circuit, optimize the manufacturing process, and reduce costs.

[0099] In the semiconductor structure, a mask material stack 202 is further formed between the dielectric material layer 200 and the second sidewall layer 206. The mask material stack 202 includes: a first mask material layer 2021 and a second mask material layer 2022 located on the first mask material layer 2021.

[0100] Reference Figure 19 and Figure 20 , using the second sidewall layer 206 as a mask to etch the dielectric material layer 200, a dielectric layer 211 (as shown in Figure 20 ) and discrete spacer layers 212 (as shown in Figure 20 ) located on the dielectric layer 211 are formed. Adjacent spacer layers 212 and the dielectric layer 211 form grooves 213 (as shown in Figure 20 ).

[0101] In an embodiment of the present invention, the lateral spacing between adjacent second sidewall layers 206 is the same. In the step of etching the dielectric material layer 200 using the second sidewall layer 206 as a mask, the etching load generated by the dielectric material layer 100 in different regions is the same, so that the centerlines of the formed spacer layers 212 are not prone to shift, that is, the positions of the grooves 213 are not prone to shift, avoiding the etching load problem caused by non-uniform mask patterns during the pattern transfer process, enhancing the reliability of the semiconductor structure, and being beneficial to mass production.

[0102] The step of etching the dielectric material layer 200 using the second sidewall layer 206 as a mask includes: etching the mask material stack 202 (as shown in Figure 18 ) using the second sidewall layer 206 as a mask to form a mask stack 210. The mask stack 210 includes a first mask layer 2101 and a second mask layer 2102 located on the first mask layer 2101; etching the dielectric material layer 200 using the mask stack 210 as a mask to form a dielectric layer 211 and discrete spacer layers 212 located on the dielectric layer 211.

[0103] Because the lateral spacing between each second sidewall layer 206 is the same, in the step of etching the mask material stack using the second sidewall layer 206 as a mask, the etching load received by the mask material stack in each region is easily the same, so that the center of the formed mask stack 210 is not prone to shift, and the position of the spacer layer formed using the mask stack 210 as a mask is not prone to shift, enhancing the reliability of the subsequent formed semiconductor structure and improving the electrical performance of the semiconductor structure.

[0104] In this embodiment, the dielectric material layer 200 is etched using the mask stack 210 instead of directly etching using the second sidewall layer 206. The reason is that by first etching the mask stack 210 through the second sidewall layer 206 and then etching the dielectric material layer 200 according to the mask stack 210, it is beneficial to improve the selectivity of the etching process, and enhance the accuracy and controllability of the etching process. In other embodiments, the dielectric material layer can also be directly etched using the second sidewall layer as a mask.

[0105] In this embodiment, the dielectric material layer 200 is etched using a dry etching process with the second sidewall layer 206 as a mask, forming a dielectric layer 211 and discrete spacer layers 212 located on the dielectric layer 211.

[0106] It should be noted that the lateral dimension of the second sidewall layer 206 is equal to the lateral spacing dimension between the second sidewall layers 206. Therefore, the lateral dimension of the spacer layer 212 is equal to the lateral spacing dimension between the spacer layers 212.

[0107] In this embodiment, the spacer layer 212 includes a plurality of device spacer layers 2121 and a plurality of dummy spacer layers 2122. The spacer layer 212 in the first region I is a dummy spacer layer 2122, and the spacer layer 212 in the second region II is a device spacer layer 2121. Moreover, the number of device spacer layers 2121 between adjacent dummy spacer layers 2122 is equal, such that after removing the dummy spacer layers 2122 subsequently, the grooves in the first region I and the grooves in the second region II are regularly arranged, which is beneficial to meet the specific design requirements of the semiconductor structure.

[0108] In this embodiment, the number of dummy spacer layers 2122 is four, and each first region I has one dummy spacer layer 2122, and the number of device spacer layers 2121 between adjacent dummy spacer layers 2122 is five. Correspondingly, the semiconductor structure is a 6T standard cell structure. In other embodiments, the number of dummy spacer layers is three, and each first region I has one dummy spacer layer, and the number of device spacer layers between adjacent dummy spacer layers is six. Correspondingly, the semiconductor structure is a 7T standard cell structure.

[0109] The method for forming the semiconductor structure further includes: after forming the dielectric layer 211 and the spacer layer 212 located on the dielectric layer 211, removing the remaining mask stack 210.

[0110] In the subsequent step of forming the metal material layer, the top of the metal material layer is flush with the top of the spacer layer 212. Removing the remaining mask stack 210 prepares for the top of the metal material layer formed in the groove 213 to be flush with the top of the spacer layer 212.

[0111] Reference Figure 21 and Figure 22 , Figure 22 is Figure 21Partial schematic view at A. The method for forming a semiconductor structure further includes: after forming the isolation layer 212, removing the isolation layer 212 in the first region I.

[0112] In the embodiment of the present invention, by removing the isolation layer 212 in the first region I, the lateral dimension of the groove 213 for forming the first metal layer in the first region I is enlarged. Subsequently, the lateral dimension of the first metal layer formed in the first region I is larger than that of the second metal layer in the second region II, meeting the design requirements of the semiconductor structure. Moreover, since the process window for removing the isolation layer 212 in the first region I is large, the process implementation difficulty is also reduced. In addition, since the lateral spacing between the second sidewall layers 206 is the same, in the step of etching the dielectric material layer 200 using the second sidewall layer 206 as a mask, the etching load of the dielectric material layer 200 at each location is likely to be the same, making the center line of the formed isolation layer 212 not easily shift. In other words, the positions of the grooves 213 in the first region I and the second region II are not easily shifted. And because there is no isolation layer 212 in the first region I after removing the isolation layer 212 in the first region I, the position of the groove 213 in the first region I is surrounded by the isolation layer 212 at the lateral edge in the second region II. This also makes the positions of the first metal layer formed based on the groove in the first region I and the second metal layer formed based on the groove in the second region II not easily shift, improving the position accuracy of both the second metal layer and the first metal layer, reducing the etching load problem caused by non-uniform mask patterns during the pattern transfer process, enhancing the reliability of the semiconductor structure, and being beneficial for mass production.

[0113] In the step of removing the isolation layer 212 in the first region I, the pseudo-isolation layer 2122 is removed. The step of removing the pseudo-isolation layer 2122 includes: as Figure 21 shown, forming an organic material layer 207 on the dielectric layer 211 and the isolation layer 212, a bottom anti-reflection coating 208 on the organic material layer 207, and a photoresist layer 209 on the bottom anti-reflection coating 208. The photoresist layer 209 exposes the bottom anti-reflection coating 208 in the first region I; etching to remove the pseudo-isolation layer 2122 using the photoresist layer 209 as a mask.

[0114] In this embodiment, the pseudo-isolation layer 2122 is removed using a dry etching process with the photoresist layer 209 as a mask.

[0115] It should be noted that in the step of removing the pseudo-isolation layer 2122, the photoresist layer 209 and the bottom anti-reflection coating 208 are completely removed, and a part of the thickness of the organic material layer 207 is also etched. Correspondingly, the method for forming a semiconductor structure further includes: after removing the pseudo-isolation layer 2122, removing the remaining organic material layer 207.

[0116] Reference Figure 23, a metal material layer is formed in the groove 213.

[0117] In this embodiment, the metal material layer in the groove 213 of the second region II serves as the second metal layer 215, and the metal material layer in the groove 213 of the first region I serves as the first metal layer 214.

[0118] Correspondingly, an embodiment of the present invention further provides a semiconductor structure. Refer to Figure 17 , which shows a schematic structural diagram of an embodiment of the semiconductor structure of the present invention.

[0119] The semiconductor structure includes: a dielectric layer 111, the dielectric layer 111 includes a plurality of spaced-apart first regions I and a second region II located between the spaced-apart first regions I. Taking the direction perpendicular to the junction of the second region II and the first region I as the transverse direction, the transverse dimension of the second region II is greater than the transverse dimension of the first region I; a plurality of spacer layers 112, located on the dielectric layer 111, and the adjacent spacer layer 112 and the dielectric layer 111 form a groove 113 (as Figure 16 shown), and the transverse intervals of the grooves 113 in the second region II are the same; a first metal layer 115, located in the groove 113 of the first region I; a second metal layer 114, located in the groove 113 of the second region II, and the transverse dimension of the first metal layer 115 is an odd multiple of the transverse dimension of the second metal layer 114.

[0120] The semiconductor structure provided by the embodiment of the present invention is formed by using the foregoing method for forming a semiconductor structure. Therefore, the position accuracy of both the second metal layer 114 and the first metal layer 115 is improved, the reliability of the semiconductor structure is enhanced, and it is beneficial for mass production. The transverse dimension of the first metal layer 115 formed in the groove 113 of the first region I is an odd multiple of the transverse dimension of the second metal layer 114 in the groove 113 of the second region II. It can better match the resistance and inductance characteristics, help reduce reflection and loss during signal transmission, improve signal integrity and reduce time delay. In addition, it can optimize the thermal distribution and heat dissipation path, improve the thermal stability of the semiconductor structure, improve the performance and reliability of the entire circuit, optimize the manufacturing process, and reduce costs.

[0121] As an example, the semiconductor structure is used to form a 6T standard cell structure, and the 6T standard cell structure has the advantage of small size and is suitable for low-power scenarios. In other embodiments, the semiconductor structure is used to form a 7T standard cell structure, which is higher than the 6T standard cell structure. When working, the channel is larger and can carry more carriers, and the performance is stronger.

[0122] The use of standard cells makes the design and manufacturing of integrated circuits modular and standardized, improving design efficiency and repeatability. Different-height standard cells can be selected to optimize the design according to specific application requirements (such as performance, power consumption, chip area).

[0123] In this embodiment, the material of the dielectric layer 111 is a low-k dielectric material, an ultra-low-k dielectric material, silicon oxide, silicon nitride, silicon oxynitride or other dielectric materials.

[0124] In this embodiment, transistors (not shown in the figure) are formed at the bottom of the dielectric layer 111. The transistors can be one or both of NMOS transistors and PMOS transistors. Specifically, the transistors include gate structures, source / drain doping layers located on both sides of the gate structures, and contact hole plugs on the source / drain doping layers and other functional structures.

[0125] It should be noted that the dielectric layer 111 also includes an edge region (not marked in the figure) at the edge of the first region I and the second region II. During photolithography and pattern transfer, due to the loading effect between the edge and the center during the etching process, the patterns formed in the edge region will have deviations, resulting in a decrease in pattern accuracy and affecting the reliability of the finally formed semiconductor structure. Therefore, in this embodiment, the patterns formed in the edge region are not part of the actual device and do not have actual functions.

[0126] In this embodiment, the lateral dimension of the first metal layer 115 is larger than that of the second metal layer 114, making the resistance of the first metal layer 115 smaller, which is beneficial to reducing the voltage drop.

[0127] In this embodiment, the first metal layer 115 is connected to the contact hole plugs in the bottom of the dielectric layer 111; the second metal layer 114 is connected to the contact hole plugs in the bottom of the dielectric layer 111. Specifically, the second metal layer 114 includes signal lines (Power Rail), and the first metal layer 115 includes power lines (Routing Tracks).

[0128] The main function of the signal lines is to transmit signals and connect different electronic components, such as processors, memories and other integrated circuits. The main function of the power lines is to distribute power throughout the semiconductor structure to ensure that power is delivered to different electronic components.

[0129] In this embodiment, the lateral dimension of the groove 113 in the first region I is an odd multiple of the lateral dimension of the groove 113 in the second region II. Correspondingly, the lateral dimension of the first metal layer 115 formed in the groove 113 in the first region I is an odd multiple of the lateral dimension of the second metal layer 114 in the groove 113 in the second region II. Specifically, the lateral dimension of the first metal layer 115 is three times that of the second metal layer 114.

[0130] In this embodiment, the tops of the second metal layer 114 and the first metal layer 115 are flush with the top of the spacer layer 112 because the second metal layer 114 and the first metal layer 115 are formed by a planarization process using the top of the spacer layer 112.

[0131] In this embodiment, the number of the second metal layers 114 between adjacent first metal layers 115 is the same, which is beneficial to meeting the specific design requirements of the semiconductor structure. In this embodiment, the number of the second metal layers 114 between adjacent first metal layers 115 is four. In other embodiments, the number of the second metal layers between adjacent first metal layers is five. The semiconductor structure is a 7T standard cell structure.

[0132] The semiconductor structure can be formed by using the formation method of any of the foregoing embodiments, or can be formed by using other formation methods. For the specific description of the semiconductor structure of this embodiment, reference can be made to the corresponding description in the foregoing embodiments, and details are not described herein again.

[0133] Although the embodiments of the present invention are disclosed as above, the embodiments of the present invention are not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present invention. Therefore, the protection scope of the embodiments of the present invention should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A dielectric layer, the dielectric layer comprising a plurality of phase-separated first regions and second regions located between the phase-separated first regions. Taking the direction perpendicular to the junction of the second region and the first region as the lateral direction, the lateral dimension of the second region is greater than the lateral dimension of the first region; A plurality of separation layers, located on the dielectric layer, and the adjacent separation layer and dielectric layer form a groove, and the lateral intervals of the grooves in the second region are the same; A first metal layer, located in the groove of the first region; A second metal layer, located in the groove of the second region, and the lateral dimension of the first metal layer is an odd multiple of the lateral dimension of the second metal layer.

2. The semiconductor structure according to claim 1, wherein The number of the second metal layers between adjacent first metal layers is the same.

3. The semiconductor structure according to claim 1, wherein The second metal layer is a signal line, and the first metal layer is a power line.

4. The semiconductor structure according to claim 1, characterized in that, The lateral dimension of the first metal layer is three times the lateral dimension of the second metal layer.

5. The semiconductor structure according to claim 1, wherein A transistor is provided at the bottom of the dielectric layer, the transistor comprising a gate structure, source-drain doping layers located on both sides of the gate structure, and contact hole plugs on the source-drain doping layers; The first metal layer is connected to the contact hole plug; The second metal layer is connected to the contact hole plug.

6. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate, the substrate comprising a dielectric material layer and a mandrel material layer located on the dielectric material layer. On the surface of the dielectric material layer, taking the direction perpendicular to the extension direction of the mandrel material layer as the lateral direction; forming a plurality of phase-separated first mandrel layers on the mandrel material layer, the lateral interval between adjacent first mandrel layers being a first dimension, and the lateral dimension of the first mandrel layer being a second dimension; Forming a first sidewall layer on the sidewall of the first mandrel layer, the lateral dimension of the first sidewall layer being a third dimension, and the sum of twice the third dimension and the second dimension being equal to the first dimension, so that the lateral intervals between adjacent first sidewall layers are equal; Etching the mandrel material layer using the first sidewall layer as a mask to form a second mandrel layer; forming a second sidewall layer on the sidewall of the second mandrel layer, and the lateral intervals between adjacent second sidewall layers being the same; etching the dielectric material layer using the second sidewall layer as a mask to form a dielectric layer and discrete separation layers located on the dielectric layer, and the adjacent separation layer and the dielectric layer form a groove; Forming a metal material layer in the groove.

7. The method for forming a semiconductor structure according to claim 6, wherein, The substrate comprises a plurality of phase-separated first regions and second regions located between the phase-separated first regions, and the lateral dimension of the second region is greater than the lateral dimension of the first region; The method for forming the semiconductor structure further comprises: after forming the second sidewall layer and before forming the separation layer, removing the second sidewall layer in the first region; or, after forming the separation layer and before forming the metal material layer, removing the separation layer in the first region; In the step of forming the metal material layer in the groove, the metal material layer in the groove of the second region is used as the second metal layer, and the metal material layer in the groove of the first region is used as the first metal layer, and the lateral dimension of the first metal layer is greater than the lateral dimension of the second metal layer.

8. The method for forming a semiconductor structure according to claim 7, wherein, In the step of forming the second sidewall layer, the second sidewall layer includes a plurality of device sidewalls and a plurality of dummy sidewalls. The second sidewall layer in the first region is the dummy sidewall, and the second sidewall layer in the second region is the device sidewall, and the number of device sidewalls between adjacent dummy sidewalls is equal; In the step of removing the second sidewall layer in the first region, the dummy sidewall is removed; In the step of etching the dielectric material layer using the second sidewall layer as a mask, the dielectric material layer is etched using the device sidewall as a mask.

9. The method for forming a semiconductor structure according to claim 8, wherein, The number of dummy sidewalls is four, and there is one dummy sidewall in each first region, and the number of device sidewalls between adjacent dummy sidewalls is five; Alternatively, the number of dummy sidewalls is three, and the number of device sidewalls between adjacent dummy sidewalls is six.

10. The method for forming a semiconductor structure according to claim 7, wherein, In the step of etching the dielectric material layer using the second sidewall layer as a mask to form a partition layer, the partition layer includes a plurality of device partition layers and a plurality of dummy partition layers. The partition layer in the first region is the dummy partition layer, and the partition layer in the second region is the device partition layer, and the number of device partition layers between adjacent dummy partition layers is equal; In the step of removing the partition layer in the first region, the dummy partition layer is removed.

11. The method for forming a semiconductor structure according to claim 10, wherein, The number of dummy partition layers is four, and there is one dummy partition layer in each first region, and the number of device partition layers between adjacent dummy partition layers is five; Alternatively, the number of dummy partition layers is three, and the number of device partition layers between adjacent dummy partition layers is six.

12. The method for forming a semiconductor structure according to claim 7, wherein, The step of forming a metal material layer in the groove includes: forming a metal material film covering the partition layer and the dielectric layer, and the top of the metal material film is higher than the top of the partition layer; Removing the metal material film higher than the partition layer, and the remaining metal material film located between the partition layers serves as the metal material layer.

13. The method for forming a semiconductor structure according to claim 7, wherein The second metal layer includes signal lines, and the first metal layer includes power lines.

14. The method for forming a semiconductor structure according to claim 7, wherein, In the step of forming a second sidewall layer on the sidewall of the second mandrel layer, the lateral interval between adjacent second sidewall layers is equal to the third dimension.

15. The method for forming a semiconductor structure according to claim 7, wherein In the step of forming a second sidewall layer on the sidewall of the second mandrel layer, the lateral dimension of the second sidewall layer is equal to the lateral interval dimension between the second sidewall layers.

16. The method for forming a semiconductor structure according to claim 7, wherein, The lateral dimension of the first metal layer is an odd multiple of the lateral dimension of the second metal layer.

17. The method for forming a semiconductor structure according to claim 16, wherein, The lateral dimension of the first metal layer is three times the lateral dimension of the second metal layer.

18. The method for forming a semiconductor structure according to claim 6, wherein The step of forming a first sidewall layer on the sidewall of the first mandrel layer includes: Conformally covering a first sidewall material layer on the first mandrel layer and the mandrel material layer exposed by the first mandrel layer; Removing the first sidewall material layer on the top of the first mandrel layer and the mandrel material layer, and the remaining first sidewall material layer located on the sidewall of the first mandrel layer serves as the first sidewall layer.

19. The method for forming a semiconductor structure according to claim 6, wherein, In the step of providing a substrate, a transistor is formed at the bottom of the dielectric material layer. The transistor includes a gate structure, source / drain doping layers located on both sides of the gate structure, and contact hole plugs on the source / drain doping layers; In the step of forming a metal material layer in the groove, the metal material layer is connected to the contact hole plug.

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