Write aggregation based on NAND wear levels

Abstract

No programmable block size aggregation is used, but lower multiple pages are used, and even page size aggregation is used. A bad block prediction unit in the controller can predict when the programmable block has a bad page. The bad block prediction unit may reduce the aggregate size of the programmable block by monitoring the life cycle of the programmable block during bad block statistical collection. When the accumulated size exceeds a threshold value, the bad block prediction unit reduces the aggregation size. The bad block prediction unit may also predict when to reduce the aggregation size based on the number of reconstructions. An aggregation size level is set at the page boundary, and the bad block prediction unit reduces the aggregation size to page aggregation once the number of reconstructions reaches the page boundary. The bad block prediction unit can predict both lifecycle threshold variations and reconstruction variations.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of the entire contents of U.S. Non - Provisional Application No. 18 / 447,806, entitled "WRITE AGGREGATION BASED ON NANO WEAR LEVEL", filed on August 10, 2023, with the United States Patent and Trademark Office, and incorporates it herein by reference for all purposes. BACKGROUND OF THE INVENTION Field of the Invention

[0003] Embodiments of the present disclosure generally relate to improved logic for reducing programmable block aggregation size.

[0004] Description of the Related Art

[0005] A NAND die consists of many programmable blocks, and each block consists of pages that include flash memory units (FMUs). Each programmable block has a number of pages of operation that will be considered fully functional. By using NAND, sometimes at least one programmable block has a failed or worn - out page.

[0006] When a programmable block encounters this problem, the programmable block either stops working or continues to try to work normally. In many cases, the controller logic will try to maintain the idea of having all fully functional pages. In this case, the controller works over time to compensate for the missing working pages, which results in a decrease in the performance of the NAND and an insufficient quality of service (QoS).

[0007] In previous methods, the worn - out pages inside the block would cause "floating" pages. Merging the floating pages with fully functional pages to solve the bad - block problem would cause the system to use increased logic to place the floating pages in the programmable block for use by the controller. Previous solutions to this problem have led to a decrease in performance.

[0008] Therefore, there is a need in the art for improved programmable block aggregation. SUMMARY OF THE INVENTION

[0009] Rather than using programmable block size aggregation, lower multiples of pages are used, or even page size aggregation is used. A bad block prediction unit in the controller is capable of predicting when a programmable block has a bad page. The bad block prediction unit can reduce the aggregation size of the programmable block by monitoring the life cycle of the programmable block during bad block statistics collection. When the cumulative size exceeds a threshold, the bad block prediction unit reduces the aggregation size. The bad block prediction unit can also predict when to reduce the aggregation size based on the number of rebuilds. Aggregation size levels are set at page boundaries, and once the number of rebuilds reaches that page boundary, the bad block prediction unit reduces the aggregation size to page aggregation. The bad block prediction unit is capable of predicting both life cycle threshold changes and rebuild changes.

[0010] In one embodiment, a data storage device includes: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: aggregate first data for writing the first data to the memory device, wherein aggregating the first data is for a first aggregation size; change the first aggregation size to a second aggregation size, wherein the first aggregation size is different from the second aggregation size; and aggregate second data for writing the second data to the memory device, wherein aggregating the second data is for the second aggregation size.

[0011] In another embodiment, a data storage device includes: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: aggregate first data for writing the first data to the memory device, wherein aggregating the first data is for a first aggregation size; track the life of the memory device; dynamically change the first aggregation size to a second aggregation size based on the tracked life, wherein the first aggregation size is greater than the second aggregation size; and aggregate second data for writing the second data to the memory device, wherein aggregating the second data is for the second aggregation size.

[0012] In another embodiment, a data storage device includes: means for storing data; and a controller coupled to the means for storing data, wherein the controller is configured to: track the number of rebuilds due to bad blocks in the means for storing data; predict when the number of rebuilds will exceed a predetermined threshold; and switch the aggregation size of the data to be aggregated based on the prediction. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] To understand the above features of the present disclosure in detail, the present disclosure briefly summarized above can be described in more detail by referring to the embodiments, some of which are shown in the drawings. However, it should be noted that the drawings only show typical embodiments of the present disclosure and should not be considered as limiting the scope of the present disclosure, as the present disclosure may allow other equivalent embodiments.

[0014] Figure 1 is a schematic block diagram showing a storage system according to certain embodiments, where a data storage device can be used as a storage device for a host device.

[0015] Figure 2 is a schematic diagram showing a full-function NAND according to certain embodiments.

[0016] Figure 3 is a schematic block diagram showing a storage system according to certain embodiments, where the device has an aggregation function.

[0017] Figure 4 is a flowchart showing a method for aggregation logic according to certain embodiments.

[0018] Figure 5 is a schematic diagram showing a programmable block with worn pages according to certain embodiments.

[0019] Figure 6 is a flowchart showing a method for accumulating size throughout the life cycle according to certain embodiments.

[0020] Figure 7 is a schematic diagram showing a life cycle threshold according to certain embodiments.

[0021] Figure 8 is a schematic diagram showing a storage system according to certain embodiments, where the device has a bad block prediction function.

[0022] Figure 9 is a graph showing a bad block tracker according to certain embodiments.

[0023] Figure 10 is a flowchart showing a method for reducing the aggregation size according to certain embodiments.

[0024] For ease of understanding, wherever possible, the same reference numerals are used to denote the same elements common to the drawings. It is contemplated that the elements disclosed in one embodiment can be beneficially used in other embodiments without specific recitation. Detailed Description

[0025] In the following text, reference is made to embodiments of the present disclosure. However, it should be understood that the present disclosure is not limited to the specifically described embodiments. Instead, any combination of the features and elements below, whether or not they relate to different embodiments, is contemplated for implementing and practicing the present disclosure. Additionally, although embodiments of the present disclosure may achieve advantages over other possible solutions and / or over the prior art, whether a particular advantage is achieved by a given embodiment does not limit the present disclosure. Thus, the aspects, features, embodiments, and advantages below are merely illustrative and are not to be considered elements or limitations of the appended claims unless expressly recited therein. Similarly, references to "the present disclosure" should not be construed as a generalization of any inventive subject matter disclosed herein and are not to be considered elements or limitations of the appended claims unless expressly recited therein.

[0026] Instead of using programmable block size aggregation, lower multiples of pages are used, or even page size aggregation is used. The bad block prediction unit in the controller can predict when a programmable block has a bad page. The bad block prediction unit can reduce the aggregation size of the programmable block by monitoring the life cycle of the programmable block during bad block statistics collection. When the cumulative size exceeds a threshold, the bad block prediction unit reduces the aggregation size. The bad block prediction unit can also predict when to reduce the aggregation size based on the number of reconstructions. Aggregation size levels are set at page boundaries, and once the number of reconstructions reaches that page boundary, the bad block prediction unit reduces the aggregation size to page aggregation. The bad block prediction unit is capable of predicting both life cycle threshold changes and reconstruction changes.

[0027] Figure 1 FIG. 1 is a schematic block diagram of a storage system 100 having a data storage device 106 that can serve as a host device 104 according to certain embodiments. For example, the host device 104 can utilize a non-volatile memory (NVM) 110 included in the data storage device 106 to store and retrieve data. The host device 104 includes a host dynamic random access memory (DRAM) 138. In some examples, the storage system 100 can include multiple storage devices that can operate as a storage array, such as the data storage device 106. For example, the storage system 100 can include multiple data storage devices 106 configured as a redundant array of inexpensive / independent disks (RAID), which together serve as a mass storage device for the host device 104.

[0028] The host device 104 can store data to and / or retrieve data from one or more storage devices such as the data storage device 106. As Figure 1As shown, the host device 104 can communicate with the data storage device 106 via the interface 114. The host device 104 can include any of a wide range of devices, including: computer servers, network-attached storage (NAS) units, desktop computers, notebooks (i.e., laptops) computers, tablets, set-top boxes, telephone handsets (such as so-called "smart" phones, so-called "smart" tablets), televisions, cameras, display devices, digital media players, video game consoles, video streaming devices, or other devices capable of sending or receiving data from the data storage device.

[0029] The host DRAM 138 can optionally include a host memory buffer (HMB) 150. The HMB 150 is a portion of the host DRAM 138 that is allocated to the data storage device 106 for exclusive use by the controller 108 of the data storage device 106. For example, the controller 108 can store mapping data, buffered commands, logical-to-physical (L2P) tables, metadata, etc. in the HMB 150. In other words, the HMB 150 can be used by the controller 108 to store data that would typically be stored in volatile memory 112, buffer 116, the internal memory of the controller 108 such as static random access memory (SRAM), etc. In an example where the data storage device 106 does not include DRAM (i.e., the optional DRAM 118), the controller 108 can utilize the HMB 150 as the DRAM of the data storage device 106.

[0030] The data storage device 106 includes a controller 108, NVM 110, power supply 111, volatile memory 112, interface 114, write buffer 116, and optional DRAM 118. In some examples, the data storage device 106 can include additional components, which are not shown for clarity. Figure 1 For example, the data storage device 106 can include a printed circuit board (PCB) to which the components of the data storage device 106 are mechanically attached, and the printed circuit board includes conductive traces that electrically interconnect the components of the data storage device 106, etc. In some examples, the physical size and connector configuration of the data storage device 106 can conform to one or more standard form factors. Some example standard form factors include but are not limited to 3.5-inch data storage devices (e.g., HDD or SSD), 2.5-inch data storage devices, 1.8-inch data storage devices, peripheral component interconnect (PCI), extended PCI (PCI-X), express PCI (PCIe) (e.g., PCIe x1, x4, x8, x16, PCIe mini card, mini PCI, etc.). In some examples, the data storage device 106 can be directly coupled (e.g., directly soldered or inserted into a connector) to the motherboard of the host device 104.

[0031] Interface 114 may include one or both of a data bus for exchanging data with host device 104 and a control bus for exchanging commands with host device 104. Interface 114 may operate according to any suitable protocol. For example, interface 114 may operate according to one or more of the following protocols: Advanced Technology Attachment (ATA) (e.g., Serial ATA (SATA) and Parallel ATA (PATA)), Fibre Channel Protocol (FCP), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), PCI and PCIe, Non-Volatile Memory Express (NVMe), OpenCAPI, GenZ, Cache Coherent Interface eXtensions (CCIX), Open Channel Solid State Drive (OCSSD), etc. Interface 114 (e.g., the data bus, the control bus, or both) is electrically connected to controller 108, providing an electrical connection between host device 104 and controller 108, enabling data to be exchanged between host device 104 and controller 108. In some examples, the electrical connection of interface 114 may also allow data storage device 106 to receive power from host device 104. For example, as Figure 1 shown, power supply 111 may receive power from host device 104 via interface 114.

[0032] NVM 110 may include a plurality of memory devices or memory cells. NVM 110 may be configured to store and / or retrieve data. For example, the memory cells of NVM 110 may receive data and a message indicating that the memory cell stores the data from controller 108. Similarly, the memory cell may receive a message from controller 108 indicating that the memory cell retrieves data. In some examples, each of the memory cells may be referred to as a die. In some examples, NVM 110 may include a plurality of dies (i.e., a plurality of memory cells). In some examples, each memory cell may be configured to store a relatively large amount of data (e.g., 128 MB, 256 MB, 512 MB, 1 GB, 2 GB, 4 GB, 8 GB, 16 GB, 32 GB, 64 GB, 128 GB, 256 GB, 512 GB, 1 TB, etc.).

[0033] In some examples, each memory cell may include any type of non-volatile memory device such as: flash memory devices, phase change memory (PCM) devices, resistive random access memory (ReRAM) devices, magnetoresistive random access memory (MRAM) devices, ferroelectric random access memory (F-RAM), holographic memory devices, and any other type of non-volatile memory device.

[0034] The NVM 110 may include multiple flash memory devices or memory cells. The NVM flash memory devices may include NAND or NOR based flash memory devices, and may store data based on the charge included in the floating gate of the transistor of each flash memory cell. In the NVM flash memory devices, the flash memory devices may be divided into multiple dies, where each of the multiple dies includes multiple physical blocks or logical blocks, and the multiple physical blocks or logical blocks may be further divided into multiple pages. Each of the multiple blocks within a particular memory device may include multiple NVM cells. The rows of the NVM cells may be electrically connected using word lines to define the pages within the multiple pages. The corresponding cells within each of the multiple pages may be electrically connected to corresponding bit lines. Additionally, the NVM flash memory devices may be 2D or 3D devices, and may be single-level cells (SLC), multi-level cells (MLC), triple-level cells (TLC), or quad-level cells (QLC). The controller 108 may write data to and read data from the NVM flash memory devices at the page level, and erase data from the NVM flash memory devices at the block level.

[0035] The power supply 111 may supply power to one or more components of the data storage device 106. When operating in the standard mode, the power supply 111 may use the power provided by an external device such as the host device 104 to supply power to one or a component. For example, the power supply 111 may use the power received from the host device 104 via the interface 114 to supply power to one or more components. In some examples, the power supply 111 may include one or more power storage components configured to supply power to one or more components when operating in the off mode, such as in the case of stopping receiving power from an external device. In this way, the power supply 111 may be used as an on-vehicle backup power source. Some examples of the one or more power storage components include, but are not limited to, capacitors, supercapacitors, batteries, etc. In some examples, the amount of electric power that may be stored by the one or more power storage components may be a function of the cost and / or size (e.g., area / volume) of the one or more power storage components. In other words, as the amount of electric power stored by the one or more power storage components increases, the cost and / or size of the one or more power storage components also increases.

[0036] The controller 108 may use the volatile memory 112 to store information. The volatile memory 112 may include one or more volatile memory devices. In some examples, the controller 108 may use the volatile memory 112 as a cache. For example, before the information in the cache is written to the NVM 110, the controller 108 may store the information in the cache in the volatile memory 112. As Figure 1As shown, the volatile memory 112 can consume the power received from the power supply 111. Examples of the volatile memory 112 include, but are not limited to, random access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, etc.)). Similarly, the optional DRAM 118 can be used to store mapping data, buffered commands, logical-to-physical (L2P) tables, metadata, cached data, etc. in the optional DRAM 118. In some examples, the data storage device 106 does not include the optional DRAM 118, such that the data storage device 106 is DRAM-less. In other examples, the data storage device 106 includes the optional DRAM 118.

[0037] The controller 108 can manage one or more operations of the data storage device 106. For example, the controller 108 can manage reading data from and / or writing data to the NVM 110. In some embodiments, when the data storage device 106 receives a write command from the host device 104, the controller 108 can initiate a data storage command to store the data in the NVM 110 and monitor the progress of the data storage command. The controller 108 can determine at least one operating characteristic of the storage system 100 and store the at least one operating characteristic in the NVM 110. In some embodiments, when the data storage device 106 receives a write command from the host device 104, the controller 108 temporarily stores the data in an internal memory or a write buffer 116 before sending the data associated with the write command to the NVM 110.

[0038] The controller 108 can include an optional second volatile memory 120. The optional second volatile memory 120 can be similar to the volatile memory 112. For example, the optional second volatile memory 120 can be SRAM. The controller 108 can allocate a portion of the optional second volatile memory to the host device 104 as a controller memory buffer (CMB) 122. The CMB 122 can be directly accessed by the host device 104. For example, the host device 104 can utilize the CMB 122 to store one or more submission queues that are typically maintained in the host device 104 instead of maintaining the one or more submission queues in the host device 104. In other words, the host device 104 can generate commands and store the generated commands with or without associated data in the CMB 122, where the controller 108 accesses the CMB 122 to retrieve the stored generated commands and / or associated data.

[0039] Figure 2is a schematic diagram showing a fully functional NAND 200 according to certain embodiments. The fully functional NAND 200 consists of at least one programmable block. The programmable block consists of four pages. Each of the four pages consists of four flash memory units (FMUs). Each FMU in the FMUs includes 4K of user data. To be able to write to the NAND 200, a controller (such as Figure 1 's controller 108) needs to write the data to the internal cache. Once the data is written to the internal cache, the data must be programmed into the NVM (such as Figure 1 's NVM 110). The programming granularity is done at the programmable block granularity, which is 64K in this example. It should be understood that although the fully functional NAND includes four pages, other fully functional NANDs can have more or fewer pages. Additionally, although five programmable blocks are shown, more or fewer programmable blocks are contemplated.

[0040] Figure 3 is a schematic block diagram showing a storage system 300 according to certain embodiments, where the device has an aggregation function. The storage system 300 includes a device (such as Figure 1 's data storage device 106), host DRAM (such as Figure 1 's host DRAM 138), and NAND 314. The host DRAM 138 includes data 1, data 2, and data 3. Although only three data units are shown in this example, there can be more or fewer units. The device 106 is responsible for transferring the data (data 1, data 2, and data 3) from the host DRAM 138 to the NAND 314. The device 106 includes a PCIe bus 312, a control path 302, and a data path 304. The data path 304 is typically done by hardware (HW) to meet high-performance requirements, while the control path is done by firmware (FW) to allow flexibility. The control path 302 includes a command acquisition unit 306 and a CPU 308, which control the data path 304.

[0041] The data path 304 includes an aggregation control unit 310, a direct memory access (DMA) module 316, a cache memory 318, an error correction unit 320, and a flash memory interface module (FIM) 322. The aggregation control unit 310 is responsible for collecting the data to the programmable block size. The DMA 316 is responsible for the actual data transfer, while the cache memory 318 holds all the accumulated data. The error correction unit 320 is used to allow better data recovery when performing a read operation and is an optional unit. The FIM 322 is responsible for transferring the data to the NAND 314 and triggering the programming operation or programmable granularity, as previously mentioned. The aggregation log of the aggregation control unit 310 is discussed below.

[0042] Figure 4is a flowchart showing method 400 for aggregation logic according to certain embodiments. Once a command arrives, an aggregation controller (such as the aggregation control unit 310 in Figure 3 ) fetches one flash memory unit (FMU) at a time according to the command. Whenever enough data is fetched for a single programming operation, the CPU (such as the CPU 308 in Figure 3 ) triggers error correction and FIM (such as the FIM 322 in Figure 3 ). The controller (such as the controller 108 in Figure 1 ) will continue to process more FMUs for the same or different commands.

[0043] Method 400 begins at block 402. At block 402, the controller identifies that the target size (TS) is equal to 16 FMUs, which will be 4 pages in this example. At block 404, the controller initializes the accumulated size (AS) and TS, where the AS will be 0 and the TS will be 16, as previously mentioned. At block 406, the controller waits for at least one write command to arrive. At block 408, the controller sets the command size (CS) (the number of FMUs). At block 410, the controller fetches at least one FMU from the host DRAM (such as the host DRAM 138 in Figure 1 ). At block 412, the controller increases AS by the following formula: AS is equal to AS plus 1. At block 414, the controller determines whether AS is equal to TS. If the controller determines that AS is not equal to TS, method 400 proceeds to block 420. If the controller determines that AS is equal to TS and the full size has been accumulated, method 400 proceeds to block 416. At block 416, the controller notifies the CPU of the accumulated data. At block 418, the controller sets AS to be equal to 0. At block 420, the controller determines whether CS is greater than 0. If the controller determines that CS is not greater than 0, method 400 returns to block 406. If the controller determines that CS is greater than 0, the controller can move to the next FMU in the command, and method 400 proceeds to block 422. At block 422, the controller sets CS to be equal to CS minus 1. When block 422 is completed, method 400 returns to block 410. Problems with method 400 are seen when the programmable block has at least one bad page.

[0044] Figure 5 is a schematic diagram showing programmable block 500 with worn pages according to certain embodiments. In this example, the CPU / FW (such as CPU 308) cannot use the aggregation size. Since the pages in the programmable block are worn (bad pages), there is a problem with the aggregation size. The controller (such as controller 108) will need to break the block aggregation into page aggregations and reconstruct based on the bad block size. The reconstruction process makes one page "float". When the next block comes from the aggregation unit (such as Figure 3When the floating pages need to be merged with a new programmable block upon arrival of the aggregation control unit 310), the method will then make the next new programmable block have the floating pages. Over time, multiple floating pages will be accumulated to fill the programmable block and written to the NAND (such as Figure 3 NAND 314). In addition, the method introduces FW complexity, and the overhead involved in the destruction and reconstruction of the programmable block may lead to performance degradation. Previously, to solve these problems, accumulation was performed within the page rather than the entire programmable block. Although this method works, it leads to the problem of needing to merge pages into blocks. Even though merging pages is easier than destruction and reconstruction, it still adds FW overhead even on a NAND without bad pages (such as Figure 2 fully functional NAND 200).

[0045] Figure 6 is a flowchart showing a method 600 for accumulating sizes throughout the life cycle according to certain embodiments. At the beginning of the NAND life, the device accumulates data based on the NAND geometry (64KB for the programmable block example). Later, due to bad block statistics collection, it switches to a lower accumulation size (i.e., 32KB) and maintains this lower accumulation size during the mid-life of the NAND. As the programmable block approaches the end of the NAND life, the collected statistical accumulation size may decrease (down to 16k). When collecting statistics on bad blocks and switching from the beginning of the life to the mid-life, the programmable block may cross a threshold. The threshold can be based on the accumulated size of the collected bad blocks.

[0046] Figure 7 is a schematic diagram showing a life cycle threshold 700 according to certain embodiments. The controller (such as Figure 1 controller 108) will accumulate different sizes based on the age of the NAND. The age of the NAND is measured by bad block statistics. The three levels (and two thresholds) are only examples, and there can be more or fewer levels and thresholds. In different embodiments, it can switch directly from 64K to 16K, or from 64K to 48K, then to 32, and then to 16K (any multiplication of the page size starting from the block size). The switch is made because the number of valid pages changes over time and is thus adjusted based on the changing number of valid pages.

[0047] In this embodiment, the life cycle threshold 700 has threshold 1 and threshold 3. For this example, there are three different aging levels, but there can be more or fewer. The three levels are the beginning of life, mid-life, and end of life. At the beginning of life, the maximum accumulation size is 64KB. For mid-life, the intermediate accumulation size is 32KB. At the end of life, the minimum accumulation size is 16KB. Figure 7It is shown that the cumulative size can be dynamic during the device lifetime.

[0048] Figure 8 is a schematic diagram showing a storage system 800 according to some embodiments, where the device has a bad block prediction function. The storage system 800 includes a device (such as Figure 1 data storage device 106), host DRAM (such as Figure 1 host DRAM 138), and NAND 814. The host DRAM 138 includes Data 1, Data 2, and Data 3. Although only three data units are shown in this example, there can be more or fewer units. The device 106 is responsible for transferring data (Data 1, Data 2, and Data 3) from the host DRAM 138 to the NAND 814. The device 106 includes a PCIe bus 812, a control path 802, and a data path 804. The control path 802 includes a command acquisition unit 806 and a CPU 808, which controls the data path 804.

[0049] The data path 804 includes an aggregation control unit 810, a DMA 816, a cache memory 818, an error correction unit 820, a FIM 822, and a bad block prediction unit 824. The aggregation control unit 810 is responsible for collecting data into a programmable block size. The bad block prediction unit 824 tracks the number of "reconstructions" due to bad blocks performed by the CPU 808. The bad block prediction unit 824 predicts when is the best time to switch to page aggregation instead of block aggregation.

[0050] Figure 9 is a graph showing an example 900 of a bad block tracker according to some embodiments. The x-axis is in seconds and the y-axis is the number of reconstructions. The horizontal dashed line (at 13) present in this example is used to indicate the number of reconstructions per second, which aggregates more efficiently at the Figure 7 threshold (such as threshold 1). The solid curve shows the number of reconstructions per second. In this example, at the 11th second, Figure 8 the bad block prediction unit 824 of Figure 1 predicts that the dashed line boundary (at 13) will be crossed in the next second. At this time, the controller (such as Figure 8 controller 108 of

[0051] Figure 10is a flowchart showing a method 1000 for reducing the aggregation size according to certain embodiments. It should be understood that the controller is preset to determine whether to reduce the aggregation size based on the number of reconstructions or the life cycle of the memory device reaching a threshold. Additionally, the controller may decide to check the life cycle of the memory device before checking whether the number of reconstructions has reached the page boundary. Further, in method 1000, block 1016 may be completed before block 1014. When the controller receives a write command at block 1002, once data is read from the memory device at block 1012, the bad block prediction unit 824 will determine whether the life cycle prediction or the reconstruction prediction will be optimal for the performance of the programmable device.

[0052] Method 1000 begins at block 1002. At block 1002, a controller (such as Figure 1 controller 108) receives a write command. At block 1004, the controller obtains data associated with the write command. At block 1006, the controller accumulates data to be written to the memory device. At block 1008, Figure 8 the bad block prediction unit 824 determines whether the amount of data has reached the aggregation size. If the bad block prediction unit 824 determines that the amount of data has not reached the aggregation size, the method returns to block 1004. If the bad block prediction unit 824 determines that the amount of data has reached the aggregation size, the method proceeds to block 1010. At block 1010, the controller writes the data to the memory device. At block 1012, the controller reads data from the memory device. At block 1014, the bad block prediction unit 824 determines whether the life cycle of the memory device has reached a threshold. If the bad block prediction unit 824 determines that the life cycle of the memory device has reached a threshold, the method proceeds to block 1018. If the bad block prediction unit 824 determines that the life cycle of the memory device has not reached a threshold, the method proceeds to block 1016. At block 1016, the bad block prediction unit 824 determines whether the number of reconstructions has reached a threshold. If the bad block prediction unit 824 determines that the number of reconstructions has not reached a threshold, the method returns to block 1002. If the bad block prediction unit 824 determines that the number of reconstructions has reached a threshold, method 1000 proceeds to block 1018. At block 1018, the bad block prediction unit 824 reduces the aggregation size.

[0053] When the NAND has a small number of bad blocks, aggregated block size data is better for performance. When the NAND is worn and includes many bad blocks, aggregated page size data is better for performance. It is advantageous to switch from aggregating by block size to aggregating by page size and to predict when to switch. Bad blocks are discovered during a read operation. It is valuable to track the number of bad blocks and then change the number of aggregated FMUs before writing to a memory device (e.g., NAND), and this can be done on a per-NAND or per-device basis. The main advantage of this new approach is that the optimal aggregation size is based on the NAND wear level. Thus, the device does not need to prepare for the worst case in the worst case. Further, the device can have a more optimized behavior in good cases before reaching the bad case, thus saving performance and power.

[0054] In one embodiment, a data storage device includes: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: aggregate first data for writing the first data to the memory device, wherein aggregating the first data is for a first aggregation size; change the first aggregation size to a second aggregation size, wherein the first aggregation size is different from the second aggregation size; and aggregate second data for writing the second data to the memory device, wherein aggregating the second data is for the second aggregation size. The change is responsive to a bad block determination. The change is responsive to the memory device exceeding a lifetime threshold. The memory device includes at least one die, and wherein the aggregation occurs independently for each die in the at least one die. The aggregation occurs uniformly across the entire memory device. The controller is configured to track the number of rebuilds that occur due to bad blocks in the memory device. The controller is configured to obtain data for one flash memory unit (FMU) at a time from a host device. The controller is configured to accumulate the obtained data until enough data has been accumulated to write the data to the memory device in a single programming operation, and wherein the single programming operation writes an amount of data equal to the first aggregation size. The first aggregation size is a block size aggregation, and wherein the second aggregation size is a lower multiple of a page, down to a page size aggregation.

[0055] In another embodiment, a data storage device includes: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: aggregate first data for writing the first data to the memory device, wherein aggregating the first data is for a first aggregation size; track the lifespan of the memory device; dynamically change the first aggregation size to a second aggregation size based on the tracked lifespan, wherein the first aggregation size is greater than the second aggregation size; and aggregate second data for writing the second data to the memory device, wherein aggregating the second data is for the second aggregation size. The dynamic change occurs when the lifespan exceeds a predetermined threshold. The tracked lifespan is related to an increase in bad blocks in the memory device. The increase in bad blocks is a predicted increase in bad blocks. The increase in bad blocks is a detected increase in bad blocks. The dynamic change includes reducing the aggregation size by at least one page. The controller includes a bad block prediction module. The bad block prediction module is disposed in the data path of the controller and is coupled to a CPU disposed in the control path of the controller.

[0056] In another embodiment, a data storage device includes: means for storing data; and a controller coupled to the means for storing data, wherein the controller is configured to: track the number of reconstructions that occur due to bad blocks in the means for storing data; predict when the number of reconstructions will exceed a predetermined threshold; and switch the aggregation size of the data to be aggregated based on the prediction. The reconstruction is in response to reading data from the means for storing data. The predetermined threshold is related to the number of reconstructions per second, above which it is more efficient to switch the aggregation size.

[0057] Although the foregoing is directed to embodiments of the present disclosure, other and additional embodiments of the present disclosure may be devised without departing from the basic scope thereof, and the scope of the present disclosure is determined by the appended claims.

Claims

1. A data storage device, the data storage device comprising: A memory device; And A controller coupled to the memory device, wherein the controller is configured to: Aggregate first data for writing the first data to the memory device, wherein aggregating the first data is for a first aggregation size; Change the first aggregation size to a second aggregation size, wherein the first aggregation size is different from the second aggregation size; and Aggregate second data for writing the second data to the memory device, wherein aggregating the second data is for the second aggregation size.

2. The data storage device according to claim 1, wherein the change is responsive to a bad block determination.

3. The data storage device according to claim 1, wherein the change is responsive to the memory device exceeding a life threshold.

4. The data storage device according to claim 1, wherein the memory device includes at least one die, and wherein the aggregation occurs independently for each of the at least one die.

5. The data storage device according to claim 1, wherein the aggregation occurs uniformly for the entire memory device.

6. The data storage device according to claim 1, wherein the controller is configured to track the number of reconstructions that occur due to bad blocks in the memory device.

7. The data storage device according to claim 1, wherein the controller is configured to obtain data of one flash memory unit (FMU) from a host device at a time.

8. The data storage device according to claim 7, wherein the controller is configured to accumulate the obtained data until enough data has been accumulated to write the data to the memory device in a single programming operation, and wherein the single programming operation writes a data amount equal to the first aggregation size.

9. The data storage device according to claim 1, wherein the first aggregation size is a block size aggregation, and wherein the second aggregation size is a lower multiple of pages, down to a page size aggregation.

10. A data storage device, the data storage device comprising: A memory device; And A controller coupled to the memory device, wherein the controller is configured to: Aggregate first data for writing the first data to the memory device, wherein aggregating the first data is for a first aggregation size; Track the life of the memory device; Dynamically change the first aggregation size to a second aggregation size based on the tracked life, wherein the first aggregation size is greater than the second aggregation size; And Aggregate second data for writing the second data to the memory device, wherein aggregating the second data is for the second aggregation size.

11. The data storage device according to claim 10, wherein the dynamic change occurs when the life exceeds a predetermined threshold.

12. The data storage device according to claim 11, wherein the tracked life is related to an increase in bad blocks in the memory device.

13. The data storage device according to claim 12, wherein the bad block increase is a predicted bad block increase.

14. The data storage device according to claim 12, wherein the bad block increase is a detected bad block increase.

15. The data storage device according to claim 10, wherein the dynamic change includes reducing the aggregation size by at least one page.

16. The data storage device according to claim 10, wherein the controller includes a bad block prediction module.

17. The data storage device according to claim 16, wherein the bad block prediction module is disposed in a data path of the controller and is coupled to a CPU disposed in a control path of the controller.

18. A data storage device, the data storage device comprising: means for storing data; and a controller coupled to the means for storing data, wherein the controller is configured to: track the number of reconstructions that occur due to bad blocks in the means for storing data; predict when the number of reconstructions will exceed a predetermined threshold; and switch the aggregation size of the data to be aggregated based on the prediction.

19. The data storage device according to claim 18, wherein the reconstruction is in response to reading data from the means for storing data.

20. The data storage device according to claim 18, wherein the predetermined threshold is related to the number of reconstructions per second, above which it is more effective to switch the aggregation size.

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