Low temperature hybrid bond metallization

Abstract

A semiconductor wafer includes a substrate, at least one via formed in the substrate, and a copper plating within the at least one via, where the copper plating includes a first layer of nano-bicrystal copper and a second layer of bulk copper. Further, a method of manufacturing a semiconductor wafer, the method comprising providing a substrate; etching the substrate to form at least one through hole; and depositing a copper plating within the at least one via, wherein the copper plating includes a first layer of nano-bicrystal copper and a second layer of bulk copper.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of U.S. Non - Provisional Application No. 18 / 160,912, filed on January 27, 2023, which is hereby incorporated by reference in its entirety. Background Art

[0003] In today's cost - effective fan - out wafer - level processing, copper redistribution link (RDL), especially multiple RDLs, plays a key role in enhancing the electrical bandwidth between chips. However, cracks may occur in RDLs due to high - temperature annealing and the mismatch of the coefficient of thermal expansion (CTE). Therefore, there is an urgent need for copper with high mechanical properties and high thermal stability. The same is true in the field of hybrid bonding. Compared with other bonding methods, copper - copper bonding has advantages in chip and wafer - level attachment. This bonding currently requires high temperature and high pressure, as well as attention to surface preparation and cleaning. The unique mechanical properties, higher diffusion coefficient, antioxidant ability, and improved electromigration resistance of nanoscale twin - oriented and fine - grained copper make it an ideal choice for RDL, hybrid bonding, and copper pillar applications in the semiconductor industry.

[0004] Since its first introduction in 2004, nanoscale twin - copper (NTCu) has attracted global attention. In the past 15 to 20 years, a large number of researchers from global research institutions / commercial companies have tried to synthesize NTCu efficiently for applications in the semiconductor industry. Despite extensive interest and efforts, the commercial production of efficient NTCu is still not possible.

[0005] In RDL applications, sidewall seeding interferes with the columnar structure. Although several chemical material suppliers provide materials that support the growth of columnar NTCu grains, and NTCu can be used for plating in columns or RDL formation through resist, the interference of sidewall seeding makes the synthesis of efficient NTCu extremely challenging. In addition to the interference of sidewall seeding, NTCu is also ineffective for small damascene features. The conformal plating characteristics of current NTCu electroplating chemistries easily cause pore problems in damascene features, especially when the damascene features have a high aspect ratio. Current research shows that NTCu has good growth in blanket Cu filling or low - aspect - ratio vias, but the challenges for modern high - aspect - ratio vias / trenches remain unsolved.

[0006] When considering the challenges of semiconductor RDL, damascene structures, or hybrid bonding, one of the main problems with NTCu is that sidewall seed growth interferes with the columnar structure. This effect is particularly evident when the aspect ratio is greater than 1. For example, in some cases, the percentage of NTCu on the via interface of a hybrid bond must be reduced from 80 - 90% at an aspect ratio of 0.2 to 0% at an aspect ratio of 1. In the industry, extensive research has been conducted on the paths to solve this challenging problem. For example, chemical suppliers are working hard to produce new additives to inhibit sidewall growth while maintaining the twin structure. Different processes, including electroplating waveform optimization and alternative integrated circuit design methods, have been developed to obtain a high percentage of NTCu on the hybrid bond interface. However, most of this work is still under development and no satisfactory solution has been found.

[0007] Different from NTCu, fine-grained copper can reduce sidewall interference in terms of directional growth and fill RDL or damascene vias. In addition, due to its grain growth, fine-grained copper provides a similar advantage in hybrid bonding, reducing the thermal expansion energy requirement. Therefore, fine-grained copper has received more attention as a candidate for low-temperature hybrid bonding materials. However, it faces its own challenges, namely impurity control and stability. To maintain fine grains, a relatively large amount of organic additives need to be co-deposited into the copper, which may affect the electrical properties of the final product. Some chemistries of fine-grained copper exhibit fine-grain stability problems. After electroplating, the wafer will go through several steps before bonding. If the grain growth occurs during the queueing period, the advantages of fine-grained copper in hybrid bonding will be weakened because of the additional time and expenses.

[0008] In addition, traditionally, when filling small damascene features, the main problem is the mass transfer rate, which can be improved by agitation, bulk solution concentration, and temperature. For example, the mass transfer at the bottom of a damascene feature is different from that at the top of the feature.

[0009] Therefore, there is still a need for low-temperature hybrid bonding materials. In addition, there is still a need for methods and materials that can fill small damascene features. Summary of the Invention

[0010] This summary of the invention is intended to introduce a series of concepts in a simplified form, which are further described in the detailed description below. This summary is not intended to identify the key features of the claimed subject matter, nor is it intended to be a tool for determining the scope of the claimed subject matter.

[0011] The present invention discloses a design and controllable synthesis of copper with different grain structures for low-temperature hybrid bonding applications.

[0012] In one aspect, a semiconductor wafer is disclosed, comprising a substrate, at least one via formed in the substrate, and copper electroplating within the at least one via, wherein the copper electroplating comprises a first layer of nanobipolar copper and a second layer of bulk copper.

[0013] In certain embodiments, the bulk copper is fine-grained copper. In certain embodiments, the first layer is deposited in the via before the second layer is deposited in the via. In certain embodiments, the first layer extends above the top of the via. In certain embodiments, the second layer is deposited in the via before the first layer is deposited in the via. In certain embodiments, the second layer extends above the top of the via. In certain embodiments, the second layer partially fills the via, and the first layer partially fills the via and extends above the top of the via. In certain embodiments, the via is a dual via, including a first and a second via. In certain embodiments, the via is a triple via, including a first via, a second via, and a third via. In certain embodiments, the second layer fills the first via and partially fills the second via, while the first layer partially fills the second via and extends above the top of the second via. In certain embodiments, the second layer fills the first via and the second via, and partially fills the third via, while the second layer partially fills the third via and extends above the top of the third via.

[0014] In certain embodiments, the first layer of nanotwinned copper provides a hybrid bonding interface. In certain embodiments, the hybrid bonding interface comprises more than 50% nanotwinned copper. In certain embodiments, the hybrid bonding interface is 0 - 100% nanotwinned copper. In certain embodiments, the copper electroplating further includes one or more organic additives.

[0015] In certain embodiments, the aspect ratio of at least one via and the substrate is about 0.1.

[0016] In another aspect, a method of manufacturing a semiconductor wafer includes providing a substrate, etching the substrate to form at least one via, depositing a first layer of nanotwinned copper within the at least one via, and depositing a second layer of bulk copper within the at least one via.

[0017] In certain embodiments, the first layer of nanotwinned copper is deposited before the second layer of bulk copper. In certain embodiments, the first layer of nanotwinned copper extends above the top of the via. In certain embodiments, the second layer of bulk copper is deposited before the first layer of nanotwinned copper. In certain embodiments, the second layer of bulk copper extends above the top of the via.

[0018] In certain embodiments, depositing the copper stack may further include an intermediate cleaning step. In certain embodiments, the bulk copper is cleaned using an acid. In certain embodiments, the bulk copper is cleaned using an acid and an oxidizer.

[0019] In certain embodiments, the second layer of bulk copper is fine-grained copper. Description of the Drawings

[0020] The above aspects and many attendant advantages of the present invention will become more readily appreciated when reference is made to the following detailed description, taken in conjunction with the accompanying drawings, in which:

[0021] FIG. 1A is a conventional wafer according to the prior art;

[0022] FIGS. 1B - 1C are conventional vias according to the prior art;

[0023] Figure 2A-2B is an exemplary copper laminate according to the present technology, comprising a layer of massive copper and a layer of nanotwinned copper;

[0024] Figure 2C-2D is an exemplary copper laminate according to the present technology, comprising a layer of nanotwinned copper and a layer of massive copper;

[0025] Figure 3A is an exemplary via according to the present technology, filled with an exemplary copper laminate having a first layer and a second layer;

[0026] Figure 3B is an exemplary double via according to the present technology, filled with an exemplary copper laminate having a first layer and a second layer, wherein the first layer extends through the second via;

[0027] Figure 3C is an exemplary double via according to the present technology, filled with an exemplary copper laminate having a first layer and a second layer, wherein the first layer extends through the second via;

[0028] Figure 3D is an exemplary triple via according to the present technology, filled with an exemplary copper laminate having a first layer and a second layer, wherein the first layer extends through the third via;

[0029] Figure 3E is an exemplary triple via according to the present technology, filled with an exemplary copper laminate having a first layer and a second layer, wherein the first layer extends through the third via;

[0030] Figure 3F is an exemplary triple via according to the present technology, filled with an exemplary copper laminate having a first layer and a second layer, wherein the first layer extends through the third via;

[0031] Figure 4 is a diagram showing a plurality of pulses applied to a semiconductor described herein during electroplating according to the present technology; and

[0032] Figure 5 is an exemplary method of electroplating according to the present technology. DETAILED DESCRIPTION

[0033] Although some specific embodiments have been described and illustrated, it will be understood that various changes can be made without departing from the spirit and scope of the present invention.

[0034] The inventors do not intend to limit this technology to the semiconductor applications listed herein. The disclosed technology is also applicable in many potential applications involving similar research challenges. According to the characteristic structure, the disclosed technology can design controllable Cu or Cu alloys and have a synthesis process with different grain structures for low-temperature hybrid bonding.

[0035] Before explaining in detail at least one embodiment of the presently disclosed and / or claimed inventive concept, it should be understood that the presently disclosed and / or claimed inventive concept is not limited to the construction and arrangement details of the components or steps or methods set forth in the following description. The presently disclosed and / or claimed inventive concept can have other embodiments and can be implemented or executed in various ways. In addition, it should be understood that the terminology used herein is for descriptive purposes only and should not be regarded as limiting.

[0036] Unless otherwise defined, technical terms related to the presently disclosed and / or claimed inventive concept shall have the meanings commonly understood by those of ordinary skill in the art. In addition, unless the context otherwise requires, singular terms shall include plural, and plural terms shall include singular.

[0037] All patents, published patent applications, and non-patent publications mentioned in this specification indicate the technical level of those skilled in the art related to the presently disclosed and / or claimed inventive concept. All patents, published patent applications, and non-patent publications cited in any part of this application are hereby expressly incorporated by reference in their entirety to the same extent as if each individual patent or publication were specifically and individually indicated to be incorporated by reference.

[0038] All the objects and / or methods disclosed herein can be made and executed in accordance with this disclosure without undue experimentation. Although the objects and methods of the presently disclosed and / or claimed inventive concept are described in the form of preferred embodiments, it will be apparent to those skilled in the art that changes can be made to the objects and / or methods and the steps or the order of the steps of the described methods without departing from the essence, spirit, and scope of the presently disclosed and / or claimed inventive concept.

[0039] According to the following terms used in this disclosure, unless otherwise specified, it should be understood to have the following meanings.

[0040] When used in conjunction with the term "comprising", the use of the words "a" or "an" may mean "one", but it also conforms to the meanings of "one or more", "at least one", and "one or more than one". The use of the term "or" means "and / or", unless explicitly stated to refer only to alternative options, and if the alternative options are mutually exclusive, although the disclosure supports the definition of "and / or" referring only to the alternatives. In this application, the term "about" is used to indicate that the value includes the inherent error variation of the measuring device, the method of determining the value, or the variation existing among the research objects. For example, but not limited to, when the term "about" is used, the marked value may vary within a range of plus or minus twelve percent, eleven percent, ten percent, nine percent, eight percent, seven percent, six percent, five percent, four percent, three percent, two percent, or one percent. The use of the term "at least one" will be understood to include one and any quantity more than one, including but not limited to 2, 3, 4, 5, 10, 15, 20, 30, 40, 50, 100, and so on. The term "at least one" can extend up to 100 or 1000 or more, depending on the additional terms; furthermore, the quantities of 100 / 1000 are not considered restrictive, as lower or higher limits may also produce satisfactory results. In addition, the use of the phrase "at least one of X, Y, and Z" will be understood to include only X, only Y, and only Z, as well as any combination of X, Y, and Z. The use of ordinal terms (i.e., "first", "second", "third", "fourth", etc.) is only for distinguishing between two or more items and does not imply any order or importance to an item, or any additional order.

[0041] The terms "comprising", "having", "containing", or "including" used herein are inclusive or open-ended and do not exclude other unrecited elements or method steps. The term "or combinations thereof" used herein refers to all permutations and combinations of the foregoing listed items. For example, "A, B, C, or combinations thereof" is intended to include at least one of the following: A, B, C, AB, AC, BC, or ABC, and if order is important in a particular context, it also includes BA, CA, CB, CBA, BCA, ACB, BAC, or CAB. Continuing with this example, combinations that also explicitly include one or more repetitions of the following items or terms are also included, such as BB, AAA, AB, BBC, AAABCCCC, CBBAAA, CABABB, etc. Those skilled in the art will understand that there is generally no limit to the number of items or terms in any combination, unless it is apparent from the context.

[0042] Turning now to the drawings, FIG. 1A shows a wafer 14 according to the prior art. The wafer 14 can be made of silicon or other semiconductor materials and is designed in the form of a thin disk. In certain applications, the wafer 14 can be used to create electronic integrated circuits (ICs). In these applications, the wafer 14 is regarded as a substrate, as shown in FIGS. 1B - 1C. In certain embodiments, the wafer 14 contains one or more vias, as described herein.

[0043] FIGS. 1B and 1C show vias 10 according to the prior art. In certain embodiments, the wafer 14 (also referred to herein as substrate 14) includes one or more vias 10. In certain embodiments, the vias 10 can be copper interconnects.

[0044] As a non - limiting example, the layer sequence in the via 10 typically includes a dielectric layer in the form of the substrate 14 and a barrier layer 12 (see FIG. 1B). In certain embodiments, the via 10 includes a seed layer 16 (see FIG. 1C) and a copper fill 18. In certain embodiments, the via 10 may also include a copper cap, which is not shown in FIGS. 1B and 1C.

[0045] Conventional fabrication of the via 10 may include the appropriate deposition of the barrier layer 12 on the substrate 14 to prevent the diffusion of copper 18 into the dielectric material of the substrate 14. Suitable barrier layers 12 include, for example, titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), etc. In certain embodiments, the barrier layer 12 may be manganese - based, such as manganese (Mn) and manganese nitride (MnN).

[0046] In certain embodiments, the seed layer 16 can be deposited on the barrier layer 12. In the case of depositing copper, there are several exemplary choices for the seed layer 16. First, the seed layer 16 can be a copper seed layer deposited using physical vapor deposition (PVD) techniques. As another non - limiting example, the seed layer 16 can be a copper alloy, such as a copper - manganese, copper - cobalt, or copper - nickel alloy. The seed layer 16 can also be formed by using other deposition techniques, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0047] Secondly, the seed layer 16 may be a laminated film, such as a liner layer and a PVD seed layer (not shown in FIGS. 1B - 1C). The liner layer is a material used between the barrier layer and the PVD seed layer to reduce discontinuous seed problems and improve the adhesion of the PVD seed. Liners are typically noble metals, such as ruthenium (Ru), platinum (Pt), palladium (Pd), and osmium (Os), but the list may also include cobalt (Co) and nickel (Ni). Currently, CVD Ru and CVD Co are common liners; however, the liner layer can also be formed by using other deposition techniques, such as ALD or PVD.

[0048] Third, the seed layer 16 may be a secondary seed layer. The secondary seed layer is similar to the liner layer in that it is typically composed of noble metals such as Ru, Pt, Pd, and Os, but the list may also include Co and Ni, and most commonly CVD Ru and CVD Co. (Like the seed and liner layers, the secondary seed layer can also be formed by using other deposition techniques, such as ALD or PVD.) The difference is that the secondary seed layer serves as a seed layer, while the liner layer is an intermediate layer between the barrier layer and the PVD Cu seed.

[0049] After depositing the seed layer 16 according to one of the above-described embodiments, the via may include a seed layer enhancement (SLE) layer, which is a thin deposited metal layer (not shown in FIGS. 1B - 1C). As a non-limiting example, the SLE layer may be a copper layer having a thickness of about 2 nm. The SLE layer is also referred to as an electrochemically deposited seed (or ECD seed), and it may be a conformally deposited layer.

[0050] ECD copper seeds are typically deposited using an alkaline chemistry containing a very dilute copper ethylenediamine (EDA) complex. ECD copper seeds can also be deposited using other copper complexes, such as ethylenediamine, glycine, citric acid, tartaric acid, ethylenediaminetetraacetic acid (EDTA), urea, etc., and can be deposited in a pH range of about 2 to about 11, about 3 to about 10, about 4 to about 10, or about 6 to about 10.

[0051] After depositing the seed layer 16 according to one of the examples described above (which layer may also include selective ECD seeds), traditional ECD filling (or copper filling) 18 and capping can be performed in the feature, for example, using acid plating chemistry at a pH below 1.0. Traditional ECD copper acid chemistry may include, for example, copper sulfate, sulfuric acid, methanesulfonic acid, hydrochloric acid, and organic additives (such as accelerators, inhibitors, and concentration regulators). Accelerators are used to increase the copper plating rate within the feature, inhibitors are used to inhibit plating on the substrate, and concentration regulators are used to reduce the thickness variation of the deposited copper on small and dense features and wide features. The combination of these additives enhances the bottom-up plating within the feature relative to the plating on the substrate. Traditional ECD filling is typically a bottom-up gap filling, superfilling, or superconformal plating, with the goal of achieving an almost pore-free fill.

[0052] Electrochemical deposition of copper has been found to be a cost-effective way to deposit copper metallization layers. In addition to being economically viable, the ECD deposition technique provides an almost bottom-up (e.g., non-conformal or superconformal) metal fill that is mechanically and electrically suitable for interconnect structures. However, the metallization layer can also be deposited without using an electrochemical method.

[0053] It should be understood that the technology disclosed herein can be integrated into a wafer, such as wafer 14 having one or more vias 10. For clarity, barrier layers and / or seed layers are not shown in the figures below, but it should be understood that each layer can be included. In addition, the vias disclosed herein may be at least partially fabricated by the processes described above.

[0054] In the present disclosure, a bulk copper and NTCu stack structure is described, aiming to solve the problem of low NTCu ratio in high aspect ratio features, i.e., aspect ratio of 1 or more. By growing a layer of bulk copper bottom layer, the aspect ratio of NTCu growth features can be reduced. For example, an aspect ratio feature of 1:1 can be reduced to 0.1. Therefore, the NTCu ratio on the hybrid bonding interface may increase from 0% to over 50%. In certain embodiments, the method further includes forming a hybrid bonding interface on top of the via. In certain embodiments, the hybrid bonding interface comprises more than 50% of nanobicrystal copper. In certain embodiments, the nanobicrystal copper ratio of the hybrid bonding interface is between 0% and 100%.

[0055] To achieve these results, the present disclosure is directed to a copper stack including bulk Cu having a flat surface to create a reproducible, reduced aspect ratio during NTCu growth.

[0056] Figure 2A and 2B An exemplary copper stack 100 according to the present technology includes a layer of bulk copper 115A and a layer of nanobicrystal copper 110. In certain embodiments, the copper stack 100 is deposited within a via in a substrate (e.g., via 10 in substrate 14). In certain embodiments, the copper stack 100 can be deposited into a small damascene feature.

[0057] In certain embodiments, the copper stack 100 includes the bulk copper 115A and the nanobicrystal copper 110. In certain embodiments, the copper stack 100 includes one or more organic additives. Figure 2A A copper stack 100 is shown having a first layer of NTCu 110 and a second layer of bulk copper 115A. As Figure 2A shown, the bulk copper 115A may have a "normal grain" size, i.e., the grain size exceeds 100 nm.

[0058] In certain embodiments, the second layer of bulk copper 115A is deposited within the via before the first layer of NTCu 110. Due to the first layer of NTCu 110, the resulting copper stack can maintain a high aspect ratio, but due to the bulk copper 115A filling the via, sidewall interference based on potential NTCu growth can be reduced.

[0059] In certain embodiments, as Figure 2BAs shown, the massive copper layer 115 is fine-grained massive copper 115B. Different from NTCu110, the fine-grained Cu 115B can fill the RDL or the embedded vias with less sidewall interference and perform better in terms of the directional growth problem. Due to its grain growth, it can also provide similar advantages in the hybrid bonding, reducing the demand for thermal expansion energy. Based on these advantages, the fine-grained Cu can be used for low-temperature metallization.

[0060] Figure 2C and 2D FIG. 6 is an exemplary copper stack 100 according to the present technology, including a layer of nanobicrystal copper 110 and a layer of massive copper 115.

[0061] In some embodiments, the copper stack 100 simultaneously includes nanobicrystal copper 110 and massive copper 115A. In some embodiments, the first layer of NTCu 110 is deposited in the via before the second layer of massive copper 115A. As Figure 2C shown, the massive copper 115A may have a grain size exceeding 100 nm.

[0062] In some embodiments, the massive copper 115 is fine-grained massive copper 115B. In some embodiments, the fine-grained massive copper 115B can fill the gaps in the small embedded features, as described herein. The grain size of the massive Cu chemistry may also affect the final low-temperature hybrid bonding evaluation. The grain structure in the polycrystalline material can dominate the material properties, so the fine-grained Cu provides additional benefits in the low-temperature hybrid bonding.

[0063] Figure 3A FIG. 18 is an exemplary via 1000 according to the present technology, filled with an exemplary copper stack 200 having a first layer 210 and a second layer 215. In some embodiments, the second layer 210 partially fills the via 1000, while the first layer 215 partially fills the via 1000 and extends over the top 220 of the via 1000.

[0064] In some embodiments, the first layer 210 and the second layer 215 may be copper, as Figure 2A-2D discussed. In some embodiments, the first layer 210 is fine-grained copper. In some embodiments, the first layer 210 is NTCu. In some embodiments, the second layer 215 is fine-grained copper. In some embodiments, the second layer 215 is NTCu. Additionally, in some embodiments, both the first layer 210 and the second layer 215 are fine-grained copper.

[0065] Figure 3BShows an example dual via 1000 according to the present technology, filled with an example copper stack 200 that includes a first layer 210 and a second layer 215, where the first layer 215 extends through the second via 1005B. In certain embodiments, the via 1000 is the dual via 1000. In certain embodiments, the dual via 1000 includes a first via 1005A and a second via 1005B. In certain embodiments, the second layer 215 fills the first via 1005A and partially fills the second via 1005B, while the first layer 210 partially fills the second via 1005B and extends above the top 220 of the second via 1005B. In certain embodiments, the width of the first via 1005A is less than the width of the second via 1005B. In certain embodiments, the depth of the first via 1005A is substantially similar to the depth of the second via 1005B.

[0066] Figure 3C Shows an example dual via 1000 according to the present technology, filled with an example copper stack 200 that includes a first layer 210 and a second layer 215, where the first layer 210 extends through the second via 1005B. In certain embodiments, the width of the first via 1005A is greater than the width of the second via 1005B.

[0067] Figure 3D An example triple via 1000 according to the present technology, filled with an example copper stack 200 that has a first layer 210 and a second layer 215, where the first layer 210 extends beyond the third via 1005C. In certain embodiments, the via 1000 is the triple via 1000, including a first via 1005A, a second via 1005B, and a third via 1005C. In certain embodiments, the second layer 215 fills the first via 1005A and the second via 1005B and partially fills the third via 1005C, while the first layer 210 partially fills the third via 1005C and extends above the top 220 of the third via 1005C. In certain embodiments, the width of the first via 1005A is less than the width of the second via 1005B. In certain embodiments, the width of the third via 1005C is greater than the widths of the first via 1005A and the second via 1005B. In certain embodiments, the sum of the depths of the first via 1005A and the second via 1005B may be substantially equal to the depth of the third via 1005C.

[0068] Figure 3EAn example triple via 1000 according to the present technology is filled with an example copper stack 200 having a first layer 210 and a second layer 215, where the first layer 210 extends beyond the third via 1005C. In some embodiments, the width of the first via 1005A is greater than the width of the second via 1005B, the third via 1005C, or both the second via 1005B and the third via 1005C.

[0069] Figure 3F An example triple via 1000 according to the present technology is filled with an example copper stack 200 having a first layer 210 and a second layer 215, where the first layer 210 extends beyond the third via 1005C. In some embodiments, the width of the second via 1005B is greater than the width of the first via 1005A, the third via 1005C, or both the first via 1005A and the third via 1005C.

[0070] Figure 4 A diagram according to the present technology depicts an example electroplating technique, including multiple pulses applied to a semiconductor as described herein during electroplating. A waveform electroplating process has been developed to obtain fine-grained copper with purity similar to or better than that of copper used in industry applications and with good stability, having a queue time of at least one month. In some embodiments, a copper stack (such as Figure 2A-2D the copper stack 100) is electroplated (i.e., deposited) using pulse electroplating. In some embodiments, the copper stack is electroplated using a combination of pulse and pulse reverse electroplating. In some embodiments, as Figure 4 not shown, the copper stack is electroplated using direct current (DC) electroplating. In some embodiments, the copper stack is electroplated using waveform electroplating. Any electroplating form that allows electroplating of the copper stack should be considered a potential method for electroplating the copper stack.

[0071] Different from DC electroplating, the waveforms of pulse / pulse reverse electroplating are accompanied by high peak currents and start times (i.e., the time for applying multiple pulses). In some embodiments, pulse / pulse reverse electroplating also includes off times (i.e., the time when multiple pulses are not applied). Pulse electroplating increases the density of nucleation sites at a high current density during the start time, while interrupting growth and facilitating re-nucleation during the off time, which helps control the grain size. Regarding the interruption of sidewall seeding of columnar structures, the reverse waveform can effectively and partially remove copper sidewall growth. In some embodiments, using multiple sequential waveforms can better control the stress of grain growth.

[0072] During electroplating, due to the current distribution, the edges and sidewalls will grow preferentially. Conversely, during the reverse process, the edges and sidewalls will be preferentially removed. Therefore, in pulse reverse electroplating, the damage to the sidewalls can be effectively eliminated. In some embodiments, the switching time of the reverse process can also be adjusted / controlled so as not to have an adverse effect on the growth of fine-grained Cu. In some embodiments, multiple / continuous pulses / pulse reverse electroplating are used because this allows for fine adjustment of nucleation and growth at different mass transfer rates. When the damascene features have a small or high aspect ratio, the mass transfer at the bottom is mainly controlled by diffusion, and when the grains grow at the top of the feature and convection plays a role in mass transfer, the required electroplating conditions are different. Therefore, in some embodiments, the electroplating waveform is adjusted to promote the growth of fine-grained Cu in small damascene features.

[0073] In some embodiments, pulse / pulse reverse electroplating contributes to the growth of NTCu in small damascene features. Pulse electroplating allows for the synthesis of a nanoscale twin structure, while reverse pulse electroplating prevents the damage of NTCu to the sidewalls and / or columnar structures.

[0074] Another advantage of the pulse electroplating described herein is the ability to control the synthesis. As described above, in some embodiments, the multiple pulses include a switching time. The on and off times of the switch make it possible to transfer / enhance the stress of grain growth. By appropriately controlling the frequency and duty cycle of the pulse electroplating, the grain growth stress can be controlled to be compression-dominated or tension-dominated. This precise stress control and mass transfer control make single / continuous pulse / pulse reverse electroplating a good choice for handling the complex geometric and structural requirements of semiconductor applications.

[0075] Figure 4 An example of a pulse waveform is shown, and these pulses can be applied to achieve the advantages described herein. The vertical axis represents the charge density of each pulse. The top of the vertical axis is the negative cathode current. The bottom of the vertical axis is the positive anode current. The horizontal axis represents time, in seconds, and divides a state of uncharged current. Therefore, when each pulse, as shown by the bar graph in Figure 4 , is above the horizontal axis, it represents a cathode pulse; when each pulse is below the horizontal axis, it represents an anode pulse.

[0076] In addition, as described herein, when each cathode pulse is applied, it represents the period of time (t 电镀 ) during which the copper stack is being electroplated, i.e., the time during which the copper stack is growing. And each anode pulse represents the period of time (t 去镀 ) during which the copper stack is being stripped, i.e., the time during which the growth of the copper stack in the seed wall is removed.

[0077] As in Figure 4As shown, there is a shaft break in the horizontal axis. It should be understood that the amount of time that this shaft break may represent is proportionally longer than the number of seconds shown.

[0078] It should be understood that the copper laminate can also be plated by direct current (DC). Although not shown, any form of DC plating can be used to plate the copper laminate.

[0079] Figure 5 is an example of a plating method 500 according to the present technology. The method 500 starts at block 510.

[0080] In block 510, a substrate is provided. In some embodiments, the substrate is a wafer, such as wafer 14 in FIG. 1A. In some embodiments, the substrate is a dielectric material, such as silicon.

[0081] In block 520, the substrate is etched to form vias. In some embodiments, multiple vias may be etched. In some embodiments, the vias may be blind vias, buried vias, or through vias.

[0082] In block 530, a copper laminate (such as copper laminate 100 or 200 as described herein) is deposited into the vias. In some embodiments, the copper laminate is deposited into the vias by electroplating as described herein. In some embodiments, the copper laminate has a first layer and a second layer. In some embodiments, the first layer is NTCu and the second layer is bulk copper. In some embodiments, the bulk copper is fine-grained bulk copper. In some embodiments, the first layer is deposited before the second layer. In some embodiments, the second layer is deposited before the first layer. In some embodiments, depositing the copper laminate may include DC electroplating or plating the copper laminate in multiple pulses as described herein. In some embodiments, depositing the copper laminate may further include an intermediate cleaning step. In some embodiments, the bulk copper is cleaned with acid. In some embodiments, the bulk copper is cleaned with acid and an oxidizer. In one example, after depositing the bulk copper into the vias, it is cleaned with sulfuric acid and hydrogen peroxide. This cleaning step may promote better NTCU growth on top of the bulk copper layer.

[0083] This application may refer to quantities and numbers. Unless otherwise specified, these quantities and numbers should not be considered restrictive, but rather represent possible quantities or numbers relevant to this application. Additionally, in this regard, this application may use the term "a plurality of" to refer to a quantity or number. In this regard, the term "a plurality of" means any number greater than one, such as two, three, four, five, etc. Terms such as "about", "approximately", "close to", etc. mean plus or minus 5% of the stated value. For the purposes of this disclosure, the phrase "at least one of A, B, and C" means, for example, (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C), including all further possible permutations when listing more than three elements.

[0084] The foregoing detailed description related to the drawings, where like reference numerals represent like elements, is intended to describe various embodiments of the present disclosure and is not intended to represent the sole embodiment. Each embodiment described in this disclosure is provided only as an example or illustration and should not be construed as being preferred or having an advantage over other embodiments. The exemplary embodiments provided herein are not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Similarly, any step described herein may be interchanged with other steps or combinations of steps to achieve the same or substantially similar results. Generally, the embodiments disclosed herein are non-restrictive, and the inventors contemplate that within the scope of this disclosure there may also be included structures and functions from a plurality of specific embodiments shown in the figures and described in the specification.

[0085] In the foregoing description, specific details are set forth to provide a thorough understanding of the exemplary embodiments of the present disclosure. However, it will be apparent to those skilled in the art that the embodiments disclosed herein may be practiced without embodying all of the specific details. In some instances, well-known process steps have not been described in detail in order not to unnecessarily obscure various aspects of the present disclosure. Additionally, it should be recognized that the embodiments of the present disclosure may employ any combination of the features described herein.

[0086] This application may include references to directions, such as "vertical", "horizontal", "front", "rear", "left", "right", "top", and "bottom", etc. These references and other similar references in this application are intended to assist in describing and understanding specific embodiments (e.g., when the embodiment is positioned for use) and are not intended to limit the present disclosure to these directions or positions.

[0087] This application may also refer to quantities and numbers. Unless otherwise specified, these quantities and numbers should not be considered restrictive, but rather as examples of possible quantities or numbers relevant to this application. Additionally, in this regard, this application may use the term "plurality" to refer to a certain quantity or number. In this context, the term "plurality" means any number greater than one, such as two, three, four, five, etc. The terms "about", "approximately", etc., mean plus or minus 5% of the stated value. The term "based on" means "at least partially based on".

[0088] The principles, representative embodiments, and modes of operation of the present disclosure have been described in the foregoing description. However, certain aspects of the present disclosure intended to be protected should not be construed as limited to the specifically disclosed embodiments. Additionally, the embodiments described herein should be considered illustrative rather than restrictive. It should be understood that others may make variations and changes and use equivalents without departing from the spirit of the present disclosure. Accordingly, it is expressly intended that all such variations, changes, and equivalents be within the spirit and scope of the present disclosure as claimed.

[0089] Although illustrative embodiments have been shown and described, it should be understood that various changes can be made thereto without departing from the spirit and scope of the invention.

Claims

1. A semiconductor wafer, the semiconductor wafer comprising: A substrate; At least one via hole formed in the substrate; And Copper electroplating within the at least one via hole, wherein the copper electroplating includes a first layer of nanobicrystalline copper and a second layer of bulk copper.

2. The semiconductor according to claim 1, wherein the bulk copper is fine-grained copper.

3. The semiconductor according to claim 1, wherein the first layer is deposited in the at least one via hole before the second layer is deposited in the via hole, or wherein the second layer is deposited in the via hole before the first layer is deposited in the at least one via hole.

4. The semiconductor according to claim 3, wherein the first layer extends above the top of the at least one via hole, or wherein the second layer extends above the top of the at least one via hole.

5. The semiconductor wafer according to claim 4, wherein the first layer of nanobicrystalline copper provides a hybrid bonding interface.

6. The semiconductor wafer according to claim 5, wherein the hybrid bonding interface comprises from about 0 to 100% nanobicrystalline copper.

7. The semiconductor according to claim 1, wherein the second layer partially fills the at least one via hole; and the first layer partially fills the at least one via hole and extends above the top of the at least one via hole.

8. The semiconductor wafer according to claim 1, wherein the aspect ratio of the at least one via hole to the substrate is about 0.

1.

9. A method of manufacturing a semiconductor wafer, the method comprising: Providing a substrate; Etching the substrate to form at least one via hole; Depositing a first layer of nanobicrystalline copper within the at least one via hole; And Depositing a second layer of bulk copper within the at least one via hole.

10. The method according to claim 9, wherein the first layer of nanobicrystalline copper is deposited before depositing the second layer of bulk copper, or wherein the second layer of bulk copper is deposited before depositing the first layer of nanobicrystalline copper.

11. The method according to claim 9, wherein the first layer of nanobicrystalline copper extends above the top of the at least one via hole, or wherein the second layer of bulk copper extends above the top of the at least one via hole.

12. The method according to claim 9, wherein the method further comprises: Forming a hybrid bonding interface between the first layer of nanobicrystalline copper and the second layer of bulk copper.

13. The method according to claim 12, wherein the hybrid bonding interface comprises from about 0 to 100% nanobicrystalline copper.

14. The method according to claim 9, wherein the second layer of bulk copper is fine-grained copper.

15. The method according to claim 14, the method further comprising: After depositing the second layer of bulk copper, cleaning the second layer of bulk copper with an acid and then depositing the first layer of nanobicrystalline copper, wherein cleaning the second layer of bulk copper further comprises applying an oxidant.

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