Display device

Abstract

A display device is provided. The display device includes a display panel and an input sensor disposed on the display panel. The input sensor may include an insulating layer, a sensing pattern, and a dummy pattern, the insulating layer being disposed between the sensing pattern and the dummy pattern. The dummy pattern may overlap a cut-off region in the line portions of the sensing pattern or a spacer region between the line portions of the sensing pattern.

Description

Technical Field

[0001] The present invention relates to a display device, and more particularly, to a display device including an input sensor. Background Art

[0002] Various display devices for multimedia devices (such as televisions, mobile phones, tablet computers, navigation systems, and game consoles) have been developed. A keyboard or a mouse may be included as an input device for the display device. In addition, the display device may be provided with an input sensor as an input device. Summary of the Invention

[0003] Technical Problem Embodiments of the present invention provide a display device including an input sensor with reduced visibility.

[0004] Technical Solution According to an embodiment of the present invention, a display device may include: a display panel including a plurality of emission regions and non-emission regions adjacent to the plurality of emission regions; and an input sensor on the display panel. The input sensor may include: an insulating layer; a first sensing electrode; a second sensing electrode including sensing patterns spaced apart from the first sensing electrode in a plan view; and a plurality of dummy patterns spaced apart from the sensing patterns of the first sensing electrode and the second sensing electrode by the insulating layer. Each of the sensing patterns of the first sensing electrode and the second sensing electrode may include a plurality of line portions corresponding to the non-emission regions. The line portions may define a plurality of opening regions overlapping corresponding ones of the plurality of emission regions. A plurality of boundary regions may be defined to indicate an interval region between the line portions of the first sensing electrode and the line portions of the sensing patterns of the second sensing electrode. At least a part of the dummy patterns may overlap the boundary regions.

[0005] Advantageous Effects According to the present invention, the dummy patterns may increase the amount of external light reflected on the cut-off region or the boundary region. The dummy patterns may reduce the difference between the amount of external light reflected on the region where the line portions are provided and the amount of external light reflected on the region corresponding to the cut-off region or the boundary region. Therefore, the input sensor may have reduced visibility. Brief Description of the Drawings

[0006] Figure 1 A perspective view showing a display device according to an exemplary embodiment of the present invention is shown.

[0007] Figure 2 A cross-sectional view showing a display device according to an embodiment of the present invention is shown.

[0008] Figure 3 A plan view showing a display panel according to an embodiment of the present invention is shown.

[0009] Figures 4a to 4c Shows an enlarged plan view of a display area according to an embodiment of the present invention.

[0010] Figure 5 Shows a cross-sectional view taken along line I-I' of Figure 4a .

[0011] Figure 6a Shows a plan view of an input sensor according to an embodiment of the present invention.

[0012] Figure 6b Shows a cross-sectional view of the input sensor taken along line II-II' of Figure 6a .

[0013] Figure 7a Shows an enlarged plan view of a second conductive layer corresponding to a first region of Figure 6a .

[0014] Figure 7b Shows an enlarged plan view of a first conductive layer corresponding to a first region of Figure 6a .

[0015] Figure 7c Shows an enlarged plan view partially showing a first region of Figure 6a .

[0016] Figure 7d Shows a cross-sectional view taken along line III-III' of Figure 7c .

[0017] Figure 7e Shows a perspective view of the reflection of external light generated on a partial region depicted in Figure 7c .

[0018] Figure 8a Shows an enlarged plan view of a second conductive layer corresponding to a second region of Figure 6a .

[0019] Figure 8b Shows an enlarged plan view of a first conductive layer corresponding to a second region of Figure 6a .

[0020] Figures 9a to 9c Shows an enlarged plan view partially showing a first region of an input sensor according to an embodiment of the present invention.

[0021] Figure 9d Shows a cross-sectional view of an input sensor according to an embodiment of the present invention. Detailed Description

[0022] In this description, when a component (or region, layer, part, etc.) is referred to as being "on" another component, "connected to" or "coupled to" another component, the component can be directly on the other component, directly connected to or directly coupled to the other component, or there can be at least one intervening component therebetween.

[0023] Like reference numerals denote like components. Further, in the drawings, the thickness, ratios, and dimensions of components are exaggerated for effective explanation of the technical content. The term "and / or" includes one or more combinations defined by the associated components.

[0024] It will be understood that although the terms first, second, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a second component and vice versa. Unless the context clearly indicates otherwise, the singular forms are also intended to include the plural forms.

[0025] In addition, the terms "beneath", "below", "above", "upper", etc. are used herein to describe the relationship of one component to other components shown in the drawings. Relative terms are intended to include different orientations in addition to the orientation depicted in the drawings.

[0026] It should be understood that the terms "comprises", "comprising", "has", etc. are used to specify the presence of stated features, wholes, steps, operations, components, elements, or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, components, elements, or combinations thereof.

[0027] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. Further, terms defined in a general dictionary should be understood to have the same meaning as defined in the context of the art and should not be understood as idealized or overly formal unless expressly defined herein.

[0028] Some embodiments of the present invention will now be described below with reference to the accompanying drawings.

[0029] Figure 1 A perspective view of a display device DD showing an embodiment according to the present invention is shown. As Figure 1 shown, the display device DD can display an image on a display surface DD-IS. The display surface DD-IS can be parallel to a plane defined by a first direction axis DR1 and a second direction axis DR2. A third direction axis DR3 can indicate a normal direction with respect to the display surface DD-IS or a thickness direction of the display device DD.

[0030] The third direction axis DR3 can distinguish the front surface (or top surface) and the rear surface (or bottom surface) of each component or unit to be discussed below. However, only the first direction axis DR1, the second direction axis DR2, and the third direction axis DR3 are exemplarily shown in this embodiment. In the following description, the first direction, the second direction, and the third direction are the directions indicated by the first direction axis DR1, the second direction axis DR2, and the third direction axis DR3, and are assigned the same reference numerals.

[0031] In an embodiment of the present invention, the display device DD is shown as having a flat display surface, but the present invention is not limited thereto. The display device DD may include a curved display surface or a cubic display surface. The cubic display surface may include a plurality of display regions (such as a curved display surface) representing different directions from each other. A flexible display device may be employed as the display device DD according to this embodiment. The flexible display device DD may be a foldable display device capable of being folded.

[0032] This embodiment describes, by way of example, the display device DD that can be applied to a tablet terminal. The tablet terminal may be configured to include the display device DD in a bracket / case that houses a main board on which an electronic module, a camera module, a power module, etc. are mounted. The display device DD according to the present invention can be applied not only to large-sized electronic devices such as televisions and monitors, but also to small and medium-sized electronic devices such as mobile phones, car navigation systems, game consoles, and smart watches.

[0033] As Figure 1 shown, the display surface DD-IS may include an image region DD-DA for displaying an image and a border region DD-NDA adjacent to the image region DD-DA. The border region DD-NDA may be a region where no image is displayed. Figure 1 An icon image is depicted as an example of the image.

[0034] As Figure 1 shown, the image region DD-DA may have a substantially quadrilateral shape. The expression "substantially quadrilateral shape" may include not only a quadrilateral shape in the mathematical sense, but also a quadrilateral shape whose edges (or corners) are defined as having a curved boundary instead of a vertex.

[0035] The border region DD-NDA may surround the image region DD-DA. However, the present invention is not limited thereto, and the shape of the border region DD-NDA may be changed. For example, the border region DD-NDA may be provided only on one side of the image region DD-DA.

[0036] Figure 2A cross-sectional view showing a display device DD according to an embodiment of the present invention is shown.

[0037] The display device DD may include a display module DM and a window WM disposed on the display module DM. The display module DM and the window WM may be bonded by an adhesive layer PSA. According to an embodiment of the present invention, the window WM may be formed by a coating method and may be in contact with the display module DM without the adhesive layer PSA.

[0038] The display module DM may include a display panel 100, an input sensor 200, and an anti-reflection layer 300. The display panel 100 may include a substrate layer 110, a driving element layer 120, an emitting element layer 130, and a packaging layer 140.

[0039] The driving element layer 120 may be disposed on the top surface of the substrate layer 110. The substrate layer 110 may be a flexible substrate, and the flexible substrate may be bendable, foldable, or rollable. The substrate layer 110 may be a glass substrate, a metal substrate, or a polymer substrate. However, the present invention is not limited thereto, and the substrate layer 110 may be an inorganic layer, an organic layer, or a composite material layer. Basically, the substrate layer 110 may have the same shape as the shape of the display panel 100.

[0040] The substrate layer 110 may have a multilayer structure. For example, the substrate layer 110 may include a first synthetic resin layer, a second synthetic resin layer, and an inorganic layer disposed between the first synthetic resin layer and the second synthetic resin layer. Each of the first synthetic resin layer and the second synthetic resin layer may include a polyimide-based resin, but the present invention is not particularly limited thereto.

[0041] The driving element layer 120 may be disposed on the substrate layer 110. The driving element layer 120 may include a plurality of insulating layers, a plurality of semiconductor patterns, a plurality of conductive patterns, and a plurality of signal lines. The driving element layer 120 may include a pixel driver circuit.

[0042] The emitting element layer 130 may be disposed on the driving element layer 120. The emitting element layer 130 may include light-emitting elements. For example, the light-emitting elements may include organic light-emitting materials, inorganic light-emitting materials, organic-inorganic light-emitting materials, quantum dots, quantum rods, micro LEDs, or nano LEDs.

[0043] The packaging layer 140 may be disposed on the emitting element layer 130. The packaging layer 140 may protect the emitting element layer 130 or the light-emitting elements from moisture, oxygen, and foreign substances such as dust particles. The packaging layer 140 may include at least one packaging inorganic layer. The packaging layer 140 may have a stacked structure of a first packaging inorganic layer, a packaging organic layer, and a second packaging inorganic layer.

[0044] The input sensor 200 may be directly disposed on the display panel 100. The input sensor 200 may detect a user input by using, for example, an electromagnetic induction method and / or a capacitance method. The display panel 100 and the input sensor 200 may be formed through a series of processes. In the present description, the phrase "directly disposed" may mean that no third component is disposed between the input sensor 200 and the display panel 100. For example, an adhesion layer may not be separately disposed between the input sensor 200 and the display panel 100.

[0045] The antireflection layer 300 may reduce the reflectance of external light incident from outside the window WM. In an embodiment of the present invention, the antireflection layer 300 may include a retarder and a polarizer. The retarder may be a film type or a liquid crystal coating type, and may include a λ / 2 retarder and / or a λ / 4 retarder. The polarizer may also be a film type or a liquid crystal coating type. The film type may include a stretchable synthetic resin film, and the liquid crystal coating type may include an array liquid crystal. The retarder and the polarizer may also include their protective films. The retarder and the polarizer or the protective film may be defined as a substrate layer for the antireflection layer 300.

[0046] In an embodiment of the present invention, the antireflection layer 300 may include a color filter. The color filter may be arranged in a specific manner. The arrangement of the color filter may be determined in consideration of the color of light emitted from the pixels included in the display panel 100. The antireflection layer 300 may also include a black matrix adjacent to the color filter. The antireflection layer 300 including the color filter may be directly disposed on the display panel 100.

[0047] In an embodiment of the present invention, the window WM may include a substrate layer and a light-shielding pattern. The substrate layer may include a glass substrate and / or a synthetic resin film. The light-shielding pattern may be partially overlapped with the substrate layer. The light-shielding pattern may be disposed on the bottom surface of the substrate layer, and may substantially define a border region of the display device DD (see Figure 1 DD-NDA). The region where the light-shielding pattern is not disposed may be defined as an image region of the display device DD (see Figure 1 DD-DA).

[0048] Figure 3 A plan view showing the display panel 100 according to an embodiment of the present invention is shown.

[0049] Referring to Figure 3 ,, the display panel 100 may include a plurality of pixels PX, a scan driver circuit SDV, an emission driver circuit EDV, a plurality of signal lines, and a plurality of pads PD (or referred to as "bond pads" or "landing pads"). The plurality of pixels PX may be disposed in the display area 100-DA. The data driver circuit may be included in a driver chip DIC mounted in the non-display area 100-NDA. The display area 100-DA may correspond toFigure 1 The image region DD-DA, and the non-display region 100-NDA may correspond to the border region DD-NDA. In this specification, the phrase "a region or part corresponds to another region or part" may mean that the region or part overlaps with the other region or part, and it is not necessarily limited to the two different regions or parts having the same area. In an embodiment of the present invention, like the scan driver circuit SDV and the emission driver circuit EDV, the data driver circuit may also be integrated in the display panel 100.

[0050] The plurality of signal lines may include a plurality of scan lines SCL1 to SCLm, a plurality of data lines DL1 to DLn, a plurality of emission lines EL1 to ELm, a first control line SL-C1 and a second control line SL-C2, and a first power line PL1 and a second power line PL2. "m" and "n" are natural numbers equal to or greater than 2.

[0051] The scan lines SCL1 to SCLm may extend in the first direction DR1 to be electrically connected to the pixels PX and the scan driver circuit SDV. The data lines DL1 to DLn may extend in the second direction DR2 to be electrically connected to the pixels PX and the driver chip DIC. The emission lines EL1 to ELm may extend in the first direction DR1 to be electrically connected to the pixels PX and the emission driver circuit EDV.

[0052] The first power line PL1 may receive a first power voltage, and the second power line PL2 may receive a second power voltage, and the level of the second power voltage is less than the level of the first power voltage. The second electrode (or cathode) of the light-emitting element may be connected to the second power line PL2.

[0053] The first control line SL-C1 may be connected to the scan driver circuit SDV and may extend toward the lower end of the display panel 100. The second control line SL-C2 may be connected to the emission driver circuit EDV and may extend toward the lower end of the display panel 100. The pad PD may be provided in the non-display region 100-NDA adjacent to the lower end of the display panel 100 and may be closer to the lower end of the display panel 100 than the driver chip DIC. The pad PD may be connected to the driver chip DIC and some signal lines.

[0054] The scan driver circuit SDV can generate a plurality of scan signals, and the scan signals can be applied to the pixels PX through the scan lines SCL1 to SCLm. The driver chip DIC can generate a plurality of data voltages, and the data voltages can be applied to the pixels PX through the data lines DL1 to DLn. The emission driver circuit EDV can generate a plurality of emission signals, and the emission signals can be applied to the pixels PX through the emission lines EL1 to ELm. In response to the scan signal, the pixels PX can be supplied with a data voltage. In response to the emission signal, the pixels PX can emit light corresponding to the data voltage in terms of brightness, thereby displaying an image.

[0055] Figures 4a to 4c An enlarged plan view of a display area 100-DA according to an embodiment of the present invention is shown.

[0056] Referring to Figure 4a , the display area 100-DA can include a plurality of emission areas LA1, LA2, and LA3 and a non-emission area NLA adjacent to the plurality of emission areas LA1, LA2, and LA3. The non-emission area NLA can define the boundaries of the emission areas LA1, LA2, and LA3.

[0057] In Figure 3 there may be a one-to-one correspondence between the pixels PX and the emission areas LA1, LA2, and LA3. Each of the pixels PX can include a light-emitting element, and the emission areas LA1, LA2, and LA3 can be areas through which the light generated in the light-emitting elements is emitted. The layout relationship between the non-emission area NLA and the emission areas LA1, LA2, and LA3 will be discussed with reference to Figure 5 .

[0058] The emission areas LA1, LA2, and LA3 can include a first emission area LA1 (or a first-color emission area) that generates first-color light, a second emission area LA2 (or a second-color emission area) that generates second-color light, and a third emission area LA3 (or a third-color emission area) that generates third-color light. In this embodiment, the first-color light can be red light, the second-color light can be green light, and the third-color light can be blue light.

[0059] The first emission area LA1, the second emission area LA2, and the third emission area LA3 can have different areas from each other, but the present invention is not limited thereto. In this embodiment, among the first emission area LA1, the second emission area LA2, and the third emission area LA3, the first emission area LA1 can have the smallest area, and the third emission area LA3 among the first emission area LA1, the second emission area LA2, and the third emission area LA3 can have the largest area.

[0060] The first emission region LA1, the second emission region LA2, and the third emission region LA3 may define a unit emission region UA. The unit emission region UA may be a repeating arrangement unit of the emission regions provided in the display region 100-DA. In the present embodiment, the unit emission region UA may include a first unit emission region UA1 and a second unit emission region UA2.

[0061] Referring to the first unit emission region UA1 and the second unit emission region UA2, the first emission region LA1 and the second emission region LA2 may be provided on one side of the third emission region LA3 in the first direction DR1 ( Figure 4a the left side as shown in), and may be provided along the second direction DR2. In each of the first unit emission region UA1 and the second unit emission region UA2, the second emission region LA2 may be provided on one side of the first emission region LA1 in the second direction DR2 ( Figure 4a the downward side as shown in).

[0062] In the first unit emission region UA1 and the second unit emission region UA2, the position of the third emission region LA3 relative to the first emission region LA1 and the second emission region LA2 may be different. Referring to the first unit emission region UA1, the third emission region LA3 may be provided at a relatively lower position relative to the first emission region LA1 and the second emission region LA2. Referring to the second unit emission region UA2, the third emission region LA3 may be provided at a relatively higher position relative to the first emission region LA1 and the second emission region LA2. In the first unit emission region UA1 and the second unit emission region UA2, the degree of offset of the third emission region LA3 from the first emission region LA1 and the second emission region LA2 may be different. In the present embodiment, the third emission region LA3 may be offset relatively more in the second unit emission region UA2 than in the first unit emission region UA1. However, the present invention is not limited thereto, and in the first unit emission region UA1 and the second unit emission region UA2, the degree of offset of the third emission region LA3 from the first emission region LA1 and the second emission region LA2 may be the same.

[0063] The first unit emission region UA1 and the second unit emission region UA2 can be alternately arranged along a first direction DR1 in a pixel row PXR. The first unit emission region UA1 and the second unit emission region UA2 can be alternately arranged along a second direction DR2 in a pixel column PXC. The third emission regions LA3 of the first unit emission region UA1 and the third emission regions LA3 of the second unit emission region UA2 can be arranged according to a specific rule based on the arrangement of the first unit emission region UA1 and the second unit emission region UA2. The third emission regions LA3 of two adjacent first unit emission regions UA1 and second unit emission regions UA2 can be set relatively close and spaced apart from each other by a first interval DT1. An emission region pair UP can be defined by the third emission regions LA3 of the first unit emission region UA1 and the third emission regions LA3 of the second unit emission region UA2, in which the third emission regions LA3 are spaced apart from each other by the first interval DT1. The emission region pairs UP can be spaced apart from each other by a second interval DT2 in each pixel column PXC. The second interval DT2 can be greater than the first interval DT1.

[0064] The emission region pair UP can be formed by a mask for deposition. A single emission layer can include light-emitting elements provided in the third emission region LA3 of the first unit emission region UA1 and light-emitting elements provided in the third emission region LA3 of the second unit emission region UA2. For example, a single mask can be used to deposit the emission layer provided in the third emission region LA3 of the first unit emission region UA1 and the emission layer provided in the third emission region LA3 of the second unit emission region UA2. The mask can have an opening corresponding to the emission region pair UP. The region between the openings can correspond to the shielding region of the mask. When the openings are defined to correspond to the emission region pair UP, the number of openings can be reduced to ensure the width of the shielding region of the mask, which is provided between the openings in the second direction DR2. A thin mask may be required to ensure the width of its shielding region in the second direction DR2 to suppress the occurrence of sagging in the deposition process.

[0065] This can be seen by comparing Figure 4b the third interval DT3 between the third emission regions LA3 shown. Referring to Figure 4b , one type of unit emission region UA can be provided in the display area 100-DA. The third interval DT3 between the third emission regions LA3 of adjacent unit emission regions UA in the pixel column PXC can be smaller than Figure 4a the second interval DT2. The mask for forming Figure 4b the third emission region LA3 can have a large number of openings of the mask and a light-shielding region with a relatively small width of the mask. This may be due to the use of Figure 4bThis is caused by the fact that the mask of the emission layer in the third emission region LA3 shown has an opening corresponding to the third emission region LA3.

[0066] Referring to Figure 4c , a type of unit emission region UA0 can be provided in the display region 100 - DA. The unit emission region UA0 can include a second emission region LA2 disposed spaced apart from each other in a first direction DR1, and can also include a first emission region LA1 and a third emission region LA3 disposed spaced apart from each other in a second direction DR2. The four emission regions LA1, LA2, and LA3 of the unit emission region UA0 can be arranged in a rhombus shape. The unit emission regions UA0 in the pixel rows PXR can be arranged along the first direction DR1. The unit emission regions UA0 can be provided staggeredly along the first direction DR1 in adjacent pixel rows PXR. The unit emission regions UA0 can be provided staggeredly along the second direction DR2 in adjacent pixel columns PXC.

[0067] Figure 5 Shows a cross-sectional view of the display device DD taken along the Figure 4a line I - I'. Figure 5 Some components of the display device DD (e.g., Figure 2 antireflection layer 300, adhesion layer PSA, and window WM) are omitted from the illustration.

[0068] A plurality of pixel driving elements can be included in the pixel driver circuit PC for driving the light emitting element LD. The pixel driver circuit PC can include a capacitor Cst and a plurality of transistors S - TFT and O - TFT. Figure 5 Depicts a silicon transistor S - TFT and an oxide transistor O - TFT as examples of transistors. Figure 5 The pixel driver circuit PC of

[0069] Referring to Figure 5 , the substrate layer 110 can have a single - layer structure. The substrate layer 110 can include a synthetic resin such as polyimide. The substrate layer 110 can be formed by coating a synthetic resin layer on a working substrate (or carrier substrate). Subsequent processes can be performed to form the display module DM, and then the working substrate can be removed. In an embodiment of the present invention, the substrate layer 110 can have a multi - layer structure including a first synthetic resin layer, at least one inorganic layer, and a second synthetic resin layer.

[0070] Returning to refer to Figure 5, a barrier layer 10br may be disposed on the substrate layer 110. The barrier layer 10br may prevent the introduction of foreign substances from the outside. The barrier layer 10br may include at least one inorganic layer. The barrier layer 10br may include a silicon oxide layer and a silicon nitride layer. Each of the silicon oxide layer and the silicon nitride layer may be provided in a plurality, and the silicon oxide layer and the silicon nitride layer may be stacked alternately with each other.

[0071] The barrier layer 10br may include a lower barrier layer 10br1 and an upper barrier layer 10br2. A first shielding electrode BMLa may be disposed between the lower barrier layer 10br1 and the upper barrier layer 10br2. The first shielding electrode BMLa may be disposed corresponding to the silicon transistor S-TFT. The first shielding electrode BMLa may include a metal, for example, molybdenum.

[0072] The first shielding electrode BMLa may receive a bias voltage. The first shielding electrode BMLa may receive a first power voltage. The first shielding electrode BMLa may prevent the silicon transistor S-TFT from being affected by a polarization induced potential. The first shielding electrode BMLa may prevent external light from reaching the silicon transistor S-TFT. In an embodiment of the present invention, the first shielding electrode BMLa may be a floating electrode isolated from other electrodes or wiring lines.

[0073] A buffer layer 10bf may be disposed on the barrier layer 10br. The buffer layer 10bf may prevent metal elements or impurities from diffusing from the substrate layer 110 toward the overlying first semiconductor pattern SC1. The buffer layer 10bf may include at least one inorganic layer. The buffer layer 10bf may include a silicon oxide layer and a silicon nitride layer.

[0074] A first semiconductor pattern SC1 may be disposed on the buffer layer 10bf. The first semiconductor pattern SC1 may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon or polycrystalline silicon. For example, the first semiconductor pattern SC1 may include low-temperature polycrystalline silicon.

[0075] The first semiconductor pattern SC1 may have electrical characteristics that change based on whether the first semiconductor pattern SC1 is doped. The first semiconductor pattern SC1 may include a first portion with high conductivity and a second portion with low conductivity. The first portion may be doped with an n-type or p-type impurity. The second portion may be an undoped portion, or may be a doped portion into which an impurity with a concentration less than the concentration of the impurity doped in the first portion is implanted. The silicon transistor S-TFT may include a source portion SE1, a channel portion AC1 (or an active portion), and a drain portion DE1 all formed of the first semiconductor pattern SC1. When observed in a vertical cross-section, the source portion SE1 and the drain portion DE1 may extend from the channel portion AC1 in opposite directions.

[0076] The first insulating layer 10 may be disposed on the buffer layer 10bf. The first insulating layer 10 may cover the first semiconductor pattern SC1. The first insulating layer 10 may be an inorganic layer. The first insulating layer 10 may be a single-layer silicon oxide layer. Similar to the first insulating layer 10, the inorganic layer of the driving element layer 120 to be discussed below may have a single-layer or multi-layer structure and may include at least one of the above materials, but the present invention is not limited thereto.

[0077] The gate GT1 of the silicon transistor S-TFT may be disposed on the first insulating layer 10. The gate GT1 may be part of a metal pattern. The gate GT1 may be stacked with the channel portion AC1. The gate GT1 may be used as a mask in the process of doping the first semiconductor pattern SC1. The first electrode CE10 of the capacitor Cst may be disposed on the first insulating layer 10. Different from that shown in Figure 5 , the first electrode CE10 and the gate GT1 may commonly have a single integral shape.

[0078] The second insulating layer 20 covering the gate GT1 may be disposed on the first insulating layer 10. In an embodiment of the present invention, an upper electrode stacked with the gate GT1 may be disposed on the second insulating layer 20. The second electrode CE20 stacked with the first electrode CE10 may be disposed on the second insulating layer 20. When observed in a plane, the upper electrode and the second electrode CE20 may commonly have a single integral shape.

[0079] The second shielding electrode BMLb may be disposed on the second insulating layer 20. The second shielding electrode BMLb may be disposed corresponding to the oxide transistor O-TFT. In an embodiment of the present invention, the second shielding electrode BMLb may be omitted. According to an embodiment of the present invention, the first shielding electrode BMLa may extend to a position below the oxide transistor O-TFT to replace the second shielding electrode BMLb.

[0080] The third insulating layer 30 may be disposed on the second insulating layer 20. The second semiconductor pattern SC2 may be disposed on the third insulating layer 30. The second semiconductor pattern SC2 may include the channel portion AC2 of the oxide transistor O-TFT. The second semiconductor pattern SC2 may include a metal oxide semiconductor. The second semiconductor pattern SC2 may include a transparent conductive oxide (TCO), such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO x ), or indium oxide (In2O3).

[0081] The metal oxide semiconductor may include a plurality of sections SE2, AC2, and DE2 differentiated according to whether the transparent conductive oxide is reduced. The section where the transparent conductive oxide is reduced (or the reduced section) may have a conductivity greater than that of the section where the transparent conductive oxide is not reduced (or the non-reduced section). The reduced section may basically serve as a signal line or the source / drain of a transistor. The non-reduced section may basically correspond to the semiconductor section (or channel) of the transistor. The fourth insulating layer 40 may be provided on the third insulating layer 30. As Figure 5 shown, the fourth insulating layer 40 may cover the second semiconductor pattern SC2. In an embodiment of the present invention, the fourth insulating layer 40 may be a dielectric pattern that overlaps with the gate GT2 of the oxide transistor O-TFT and exposes the source section SE2 and the drain section DE2 of the oxide transistor O-TFT.

[0082] The gate GT2 of the oxide transistor O-TFT may be provided on the fourth insulating layer 40. The gate GT2 of the oxide transistor O-TFT may be part of a metal pattern. The gate GT2 of the oxide transistor O-TFT may overlap with the channel section AC2 of the oxide transistor O-TFT. A fifth insulating layer 50 covering the gate GT2 may be provided on the fourth insulating layer 40. Each of the first insulating layer 10 to the fifth insulating layer 50 may be an inorganic layer.

[0083] The first connection pattern CNP1 and the second connection pattern CNP2 may be provided on the fifth insulating layer 50. The first connection pattern CNP1 and the second connection pattern CNP2 may be formed by the same process to have the same material and stacking structure. The first connection pattern CNP1 may be coupled to the drain section DE1 of the silicon transistor S-TFT through a first pixel contact hole PCH1 that penetrates the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50. The second connection pattern CNP2 may be coupled to the source section SE2 of the oxide transistor O-TFT through a second pixel contact hole PCH2 that penetrates the fourth insulating layer 40 and the fifth insulating layer 50. The connection relationship of the first connection pattern CNP1 with respect to the silicon transistor S-TFT is not limited to the connection relationship discussed above, and similarly, the connection relationship of the second connection pattern CNP2 with respect to the oxide transistor O-TFT is not limited to the connection relationship discussed above.

[0084] The sixth insulating layer 60 may be disposed on the fifth insulating layer 50. The third connection pattern CNP3 may be disposed on the sixth insulating layer 60. The third connection pattern CNP3 may be coupled to the first connection pattern CNP1 through a third pixel contact hole PCH3 penetrating the sixth insulating layer 60. The data line DL may be disposed on the sixth insulating layer 60. A seventh insulating layer 70 covering the third connection pattern CNP3 and the data line DL may be disposed on the sixth insulating layer 60. The third connection pattern CNP3 and the data line DL may be formed of the same material and have the same stacked structure by the same process. Each of the sixth insulating layer 60 and the seventh insulating layer 70 may be an organic layer.

[0085] The light-emitting element LD may include an anode AE (or a first electrode), an emission layer EL, and a cathode CE (or a second electrode). The anode AE of the light-emitting element LD may be disposed on the seventh insulating layer 70. The anode AE may be a transmissive electrode, a transmissive-reflective electrode, or a reflective electrode. The anode AE may have a stacked structure in which ITO, Ag, and ITO are stacked in this order. The anode AE and the cathode CE may be positioned interchangeably.

[0086] The pixel defining layer PDL may be disposed on the seventh insulating layer 70. The pixel defining layer PDL may be an organic layer. The pixel defining layer PDL may exhibit light absorption properties and may have, for example, a black color. The pixel defining layer PDL may include a black colorant. The black colorant may include a black dye or a black pigment. The black colorant may include carbon black, a metal such as chromium, or an oxide thereof. The pixel defining layer PDL may correspond to a light-shielding pattern having a light-shielding property.

[0087] The pixel defining layer PDL may cover a part of the anode AE. For example, the pixel defining layer PDL may have an opening PDL-OP defined to expose a part of the anode AE. The emission region LA1 may be defined to correspond to the opening PDL-OP. Figure 5 One emission region LA1 corresponding to Figure 4a the first emission region LA1 is depicted. The cross-sections corresponding to the second emission region LA2 and the third emission region LA3 may be substantially the same as Figure 5 that of. However, the second emission region LA2 and the third emission region LA3 may include an emission layer EL having a material different from that of the emission layer EL included in the first emission region LA1. In addition, referring to Figure 4aFor the emission region UP, the pixel defining layer PDL can be disposed between the third emission region LA3 of the first unit emission region UA1 and the third emission region LA3 of the second unit emission region UA2. The emission layer EL in the third emission region LA3 of the first unit emission region UA1 and the third emission region LA3 of the second unit emission region UA2 can be disposed on the pixel defining layer PDL between the third emission region LA3 of the first unit emission region UA1 and the third emission region LA3 of the second unit emission region UA2.

[0088] In an embodiment of the present invention, a hole control layer can be disposed between the anode AE and the emission layer EL. The hole control layer can include a hole transport layer and can further include a hole injection layer. An electron control layer can be disposed between the emission layer EL and the cathode CE. The electron control layer can include an electron transport layer and can further include an electron injection layer.

[0089] The encapsulation layer 140 can cover the light-emitting element LD. The encapsulation layer 140 can include an encapsulation inorganic layer 141, an encapsulation organic layer 142, and an encapsulation inorganic layer 143 stacked in sequence, but the layers included in the encapsulation layer 140 are not necessarily limited thereto. The encapsulation inorganic layers 141 and 143 can include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. Each of the encapsulation inorganic layers 141 and 143 can have a multilayer structure. The encapsulation organic layer 142 can include an acrylate-based organic layer, but the present invention is not limited thereto.

[0090] The input sensor 200 can include at least one conductive layer (or at least one sensor conductive layer) and at least one insulating layer (or at least one sensor insulating layer). In this embodiment, the input sensor 200 can include a first insulating layer 210 (or a first sensor insulating layer), a first conductive layer 220 (or a first sensor conductive layer), a second insulating layer 230 (or a second sensor insulating layer), a second conductive layer 240 (or a second sensor conductive layer), and a third insulating layer 250 (or a third sensor insulating layer). Figure 5 The conductive wires of the first conductive layer 220 and the conductive wires of the second conductive layer 240 are roughly depicted.

[0091] The first insulating layer 210 can be directly disposed on the display panel 100. The first insulating layer 210 can be an inorganic layer including at least one selected from silicon nitride, silicon oxynitride, and silicon oxide. Each of the first conductive layer 220 and the second conductive layer 240 can have a single-layer structure or a multilayer structure in which layers are stacked along the third direction DR3. The first conductive layer 220 and the second conductive layer 240 can include conductive wires defining a mesh-type electrode. Based on the position, the conductive wires of the first conductive layer 220 and the conductive wires of the second conductive layer 240 can be connected or not connected to each other through contact holes penetrating the second insulating layer 230.

[0092] The first conductive layer 220 and the second conductive layer 240 each having a single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or an alloy thereof. The transparent conductive layer may include a transparent conductive oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), or indium zinc tin oxide (IZTO). Additionally or alternatively, the transparent conductive layer may include graphene, metal nanowires, or a conductive polymer (such as poly(3,4-ethylenedioxythiophene) or PEDOT).

[0093] The first conductive layer 220 and the second conductive layer 240 each having a multi-layer structure may include a metal layer. The metal layer may include, for example, a three-layer structure of titanium / aluminum / titanium. The multi-layer conductive layer may include at least one metal layer and at least one transparent conductive layer. The second insulating layer 230 may be disposed between the first conductive layer 220 and the second conductive layer 240. The third insulating layer 250 may cover the second conductive layer 240. In an embodiment of the present invention, the third insulating layer 250 may be omitted. The second insulating layer 230 and the third insulating layer 250 may include an inorganic layer or an organic layer.

[0094] Figure 6a A plan view showing an input sensor 200 according to an embodiment of the present invention is shown. Figure 6b A cross-sectional view showing the input sensor 200 taken along the line II-II' is shown. Figure 6a

[0095] Referring to Figure 6a , the input sensor 200 may include a sensing region 200-DA and a non-sensing region 200-NDA adjacent to the sensing region 200-DA. The sensing region 200-DA and the non-sensing region 200-NDA may respectively correspond to Figure 3 the display region 100-DA and the non-display region 100-NDA depicted in. The input sensor 200 may include first electrodes E1-1 to E1-4 (or first sensing electrodes), second electrodes E2-1 to E2-7 (or second sensing electrodes), a first signal line SL1 (or first sensor signal line), and a second signal line SL2 (or second sensor signal line).

[0096] The first electrodes E1-1 to E1-4 and the second electrodes E2-1 to E2-7 insulated from and crossing the first electrodes E1-1 and E1-4 can be provided in the sensing region 200-DA. The first signal lines SL1 electrically connected to the first electrodes E1-1 to E1-4 and the second signal lines SL2 electrically connected to the second electrodes E2-1 to E2-7 can be provided in the non-sensing region 200-NDA. One of the first signal lines SL1 and the second signal lines SL2 can provide a driving signal for sensing an external input from an external circuit to the corresponding electrodes, and the other of the first signal lines SL1 and the second signal lines SL2 can output a sensing signal. The capacitance change between the first electrodes E1-1 to E1-4 and the second electrodes E2-1 to E2-7 can be measured based on the sensing signal. In this embodiment, an input sensor using mutual capacitance is depicted by way of example, but the present invention is not limited thereto. An input sensor using self-capacitance can be applied. The input sensor using self-capacitance can include one type of sensing electrode.

[0097] The first electrodes E1-1 to E1-4 and the second electrodes E2-1 to E2-7 can have a mesh shape in which a plurality of opening regions are defined. The plurality of opening regions can be superposed corresponding to the plurality of emission regions LA1, LA2, and LA3 shown in Figure 4a . The second electrodes E2-1 to E2-7 can be insulated from and cross the first electrodes E1-1 to E1-4. The first electrodes E1-1 to E1-4 or the second electrodes E2-1 to E2-7 can have a single integral shape. In this embodiment, the second electrodes E2-1 to E2-7 are shown as a single integral shape by way of example.

[0098] The second electrodes E2-1 to E2-7 can include a sensing portion SP2 and an intermediate portion CP2. The sensing portion SP2 can have a rhombus shape and an area larger than that of the intermediate portion CP2. Each of the intermediate portions CP2 can be provided between two adjacent sensing portions SP2 in the sensing portion SP2. The intermediate portion CP2 can have a relatively small length and can be omitted. In this case, the sensing portion SP2 can extend directly from its adjacent sensing portion SP2.

[0099] Each of the first electrodes E1-1 to E1-4 can include a sensing pattern SP1 and a bridging pattern CP1 (or connecting pattern). Two adjacent sensing patterns SP1 can be connected by two bridging patterns CP1, but no limitation is imposed on the number of bridging patterns.

[0100] Referring to Figure 6a and Figure 6b, the bridging pattern CP1 may be formed of the first conductive layer 220, and the plurality of first electrodes E1-1 to E1-4 and the sensing pattern SP1 may be formed of the second conductive layer 240. The bridging pattern CP1 may be connected to the sensing pattern SP1 through a contact hole TH-I formed in the second insulating layer 230. In an embodiment of the present invention, the bridging pattern CP1 may be formed of the second conductive layer 240, and the sensing pattern SP1 and the plurality of first electrodes E1-1 to E1-4 may be formed of the first conductive layer 220.

[0101] In this embodiment, Figure 6a each of the first signal line SL1 and the second signal line SL2 shown in Figure 6b may be formed of the first conductive layer 220 shown in Figure 6a each of the first signal line SL1 and the second signal line SL2 shown in Figure 6b may be provided on the same layer as the bridging pattern CP1 depicted in

[0102] Figure 7a shows an enlarged plan view of the second conductive layer 240 corresponding to the first region A1 of Figure 6a . Figure 7b shows an enlarged plan view of the first conductive layer 220 corresponding to the first region A1 of Figure 6a . Figure 7c shows an enlarged plan view partially showing Figure 6a the first region A1 of Figure 7d shows a cross-sectional view taken along line III-III' of Figure 7c . Figure 7e shows a perspective view showing the reflection of external light generated on a partial region depicted in Figure 7c .

[0103] In Figures 7a to 7d , the second conductive layer 240 may indicate the second conductive layer 240 of Figure 5 , and the first conductive layer 220 may correspond to the first conductive layer 220 of Figure 5 . Figure 7a shows an enlarged view of the sensing pattern SP1 formed of the second conductive layer 240. The sensing pattern SP1 is shown as a representative of the first electrodes E1-1 to E1-4. Figure 7a and Figure 7b also depict Figure 4aThe display region 100-DA shown in []. The sensing part SP2 may have the same structure as that of the sensing pattern SP1.

[0104] Referring to Figure 7a , the sensing pattern SP1 may have a plurality of opening regions EOP1, EOP2, and EOP3 defined therein. The plurality of opening regions EOP1, EOP2, and EOP3 may include a first opening region EOP1 corresponding to (or overlapping) the first emission region LA1, a second opening region EOP2 corresponding to the second emission region LA2, and a third opening region EOP3 corresponding to the emission region pair UP.

[0105] In this embodiment, the first emission region LA1 may be disposed inside the first opening region EOP1, the second emission region LA2 may be disposed inside the second opening region EOP2, and the emission region pair UP may be disposed inside the third opening region EOP3. The third opening region EOP3 may commonly have disposed therein Figure 4a the third emission region LA3 of the first unit emission region UA1 shown in [[]] and Figure 4a the third emission region LA3 of the second unit emission region UA2 shown in [[]]. In an embodiment of the present invention, the third opening region EOP3 may be formed in each of the third emission region LA3 of the first unit emission region UA1 and the third emission region LA3 of the second unit emission region UA2. In this case, the first line portion L1 to be discussed below may be disposed in the region between the third emission region LA3 of the first unit emission region UA1 and the third emission region LA3 of the second unit emission region UA2.

[0106] The sensing pattern SP1 may include a plurality of line portions L1 and L2 that define the plurality of opening regions EOP1, EOP2, and EOP3. The plurality of line portions L1 and L2 may include a first line portion L1 and a second line portion L2 that extend in intersecting directions. In this embodiment, the first line portion L1 may extend in the first direction DR1, and the second line portion L2 may extend in the second direction DR2.

[0107] Each of the first line portions L1 may extend from one second line portion L2 toward another second line portion L2 adjacent to the one second line portion L2. The first line portion L1 may be disposed between two adjacent opening regions among the plurality of opening regions EOP1, EOP2, and EOP3 in the second direction DR2, and may include a plurality of groups of line portions differentiated based on the width in the second direction DR2.

[0108] Multiple line portions L1 and L2 may include a cut-off region DCA defined therein. The cut-off region DCA may be a region where the line portions L1 and L2 are removed. The cut-off region DCA may reduce Figure 6a the visibility of the boundary region between the first electrodes E1-1 to E1-4 and the second electrodes E2-1 to E2-7 depicted in Figure 6a Since the cut-off region DCA is formed in the first electrodes E1-1 to E1-4 and the second electrodes E2-1 to E2-7 depicted in Figure 6a according to a specific rule, in the sensing region 200-DA depicted in

[0109] Visibility level 1 may be defined as indicating a level where only the boundary region is clearly visible because no cut-off region DCA is formed between the first electrodes E1-1 to E1-4 and the second electrodes E2-1 to E2-7. At visibility level 1, the first electrodes E1-1 to E1-4 and the second electrodes E2-1 to E2-7 can be easily identified in terms of position and shape. Visibility level 2 may be defined as indicating a level where the boundary region between the first electrodes E1-1 to E1-4 and the second electrodes E2-1 to E2-7 is less visible because the cut-off region DCA is formed in the first electrodes E1-1 to E1-4 and the second electrodes E2-1 to E2-7. At visibility level 2, the first electrodes E1-1 to E1-4 and the second electrodes E2-1 to E2-7 can be identified in terms of presence, but not precisely in terms of position and shape. This may be caused by the fact that the cut-off region DCA reduces the visibility of the boundary region.

[0110] In this embodiment, the cut-off region DCA may include a first cut-off region C1 to an eighth cut-off region C8. A unit (hereinafter referred to as a cut-off unit) may be composed of the first cut-off region C1 to the eighth cut-off region C8 and may be repeatedly formed in the first electrodes E1-1 to E1-4 and the second electrodes E2-1 to E2-7. Figure 7a Depicts a set of the first cut-off region C1 to the eighth cut-off region C8 included in a single cut-off unit.

[0111] In the following description, the positions of the first cutting region C1 to the eighth cutting region C8 will be discussed based on a region provided with the (m - 1)-th pixel row PXRm-1, the m-th pixel row PXRm, the (m + 1)-th pixel row PXRm+1, the (n - 1)-th pixel column PXCn-1, the n-th pixel column PXCn, and the (n + 1)-th pixel column PXCn+1. m and n may each be a natural number equal to or greater than 2. The first unit emission region UA1 may be provided at each of the intersection points between the (m - 1)-th pixel row PXRm-1 and the (n - 1)-th pixel column PXCn-1, between the (m + 1)-th pixel row PXRm+1 and the (n - 1)-th pixel column PXCn-1, between the m-th pixel row PXRm and the n-th pixel column PXCn, between the (m - 1)-th pixel row PXRm-1 and the (n + 1)-th pixel column PXCn+1, and between the (m + 1)-th pixel row PXRm+1 and the (n + 1)-th pixel column PXCn+1. The second unit emission region UA2 may be provided at each of the intersection points between the m-th pixel row PXRm and the (n - 1)-th pixel column PXCn-1, between the (m - 1)-th pixel row PXRm-1 and the n-th pixel column PXCn, between the (m + 1)-th pixel row PXRm+1 and the n-th pixel column PXCn, and between the m-th pixel row PXRm and the (n + 1)-th pixel column PXCn+1.

[0112] The first cutting region C1 to the eighth cutting region C8 may be divided into four pairs (or cutting region pairs). Each of the four cutting region pairs may include two cutting regions among the first cutting region C1 to the eighth cutting region C8 that are closest to each other. The first cutting region C1 and the second cutting region C2 may form a pair, the third cutting region C3 and the fourth cutting region C4 may form a pair, the fifth cutting region C5 and the sixth cutting region C6 may form a pair, and the seventh cutting region C7 and the eighth cutting region C8 may form a pair. One of the pair of cutting regions may be defined in the first line portion L1, and the other of the pair of cutting regions may be defined in the second line portion L2.

[0113] The first cutting region C1 can be set in the nth pixel column PXCn and can be formed in the first line portion L1 between the first emission region LA1 located in the (m - 1)th pixel row PXRm - 1 and the second emission region LA2 in the (m - 1)th pixel row PXRm - 1. The second cutting region C2 can be set in the (m - 1)th pixel row PXRm - 1 and can be formed in the second line portion L2 between the second emission region LA2 located in the nth pixel column PXCn and the third emission region LA3 in the nth pixel column PXCn. The third cutting region C3 can be set in the nth pixel column PXCn and can be formed in the first line portion L1 between the first emission region LA1 located in the mth pixel row PXRm and the second emission region LA2 in the mth pixel row PXRm. The fourth cutting region C4 can be set in the mth pixel row PXRm and can be formed in the second line portion L2 between the third emission region LA3 located in the (n - 1)th pixel column PXCn - 1 and the second emission region LA2 in the nth pixel column PXCn.

[0114] The fifth cutting region C5 can be set in the (n + 1)th pixel column PXCn + 1 and can be formed in the second line portion L2 between the second emission region LA2 located in the (m - 1)th pixel row PXRm - 1 and the third emission region LA3 in the (m - 1)th pixel row PXRm - 1. The sixth cutting region C6 can be set in the (n + 1)th pixel column PXCn + 1 and can be formed in the first line portion L1 between the second emission region LA2 located in the (m - 1)th pixel row PXRm - 1 and the first emission region LA1 in the mth pixel row PXRm. The seventh cutting region C7 can be set in the mth pixel row PXRm and can be formed in the second line portion L2 between the third emission region LA3 located in the nth pixel column PXCn and the second emission region LA2 in the (n + 1)th pixel column PXCn + 1. The eighth cutting region C8 can be set in the (n + 1)th pixel column PXCn + 1 and can be formed in the first line portion L1 between the second emission region LA2 located in the mth pixel row PXRm and the first emission region LA1 in the (m + 1)th pixel row PXRm + 1.

[0115] The first cutting region C1, the third cutting region C3, the sixth cutting region C6, and the eighth cutting region C8 can be formed in the first line portion L1 and can connect the first opening region EOP1 to the second opening region EOP2. The second cutting region C2, the fourth cutting region C4, the fifth cutting region C5, and the seventh cutting region C7 can be formed in the second line portion L2 and can connect the second opening region EOP2 and the third opening region EOP3.

[0116] Refer to Figure 7b, the first conductive layer 220 may include a plurality of dummy patterns MP. The plurality of dummy patterns MP may be correspondingly stacked with the plurality of cutting regions DCA depicted in Figure 7a . The plurality of dummy patterns MP may include a first dummy pattern MP1, a second dummy pattern MP2, a third dummy pattern MP3, a fourth dummy pattern MP4, a fifth dummy pattern MP5, a sixth dummy pattern MP6, a seventh dummy pattern MP7, and an eighth dummy pattern MP8 corresponding to the first cutting region C1 to the eighth cutting region C8, respectively.

[0117] Figure 7c and Figure 7d show enlarged views of the cutting regions DCA formed in the first line portion L1 and the cutting regions DCA formed in the second line portion L2. The dummy pattern MP may be arranged to correspond to the cutting region DCA.

[0118] The second insulating layer 230 may be disposed between the dummy pattern MP and the cutting region DCA of the first line portion L1 and between the dummy pattern MP and the cutting region DCA of the second line portion L2. In this embodiment, the dummy pattern MP may be disposed below the second insulating layer 230, but the present invention is not limited thereto.

[0119] The first line portion L1 and the second line portion L2 may each have a multi-layer stacked structure. The first line portion L1 and the second line portion L2 may have the same stacked structure. Each of the first line portion L1 and the second line portion L2 may include a first conductive layer CL10 (or a first line conductive layer), a second conductive layer CL20 (or a second line conductive layer) disposed on and in contact with the first conductive layer CL10, and a third conductive layer CL30 (or a third line conductive layer) disposed below and in contact with the first conductive layer CL10. In an embodiment of the present invention, the third conductive layer CL30 may be omitted.

[0120] The first conductive layer CL10 may have a first reflectivity, a first conductivity, and a first thickness. The second conductive layer CL20 may have a second reflectivity less than the first reflectivity, a second conductivity less than the first conductivity, and a second thickness less than the first thickness. The first conductive layer CL10 with low resistance may substantially correspond to the signal transmission path. A plurality of signal lines SL1 and SL2 each having an increased thickness may be disposed in a small planar area. The second conductive layer CL20 with low reflectivity may cover the first conductive layer CL10, thereby reducing the reflectivity of external light.

[0121] medium-sized electronic devices (such as Figure 1 and Figure 6aThe tablet computer and laptop computer depicted therein may have an input sensor whose area is larger than that of the input sensors included in small-sized electronic devices such as mobile phones. As the lengths of the first electrodes E1-1 to E1-4 and the second electrodes E2-1 to E2-7 increase, resulting in an increase in the resistance of the first electrodes E1-1 to E1-4 and the second electrodes E2-1 to E2-7, a low-resistance layer such as the first conductive layer CL10 may have an increased thickness to reduce the resistance.

[0122] Compared with the first conductive layer CL10, the third conductive layer CL30 may have a large bonding force with respect to the first insulating layer 210. The first conductive layer CL10 may include one or more of aluminum, copper, and silver, all of which have low resistance. The second conductive layer CL20 may include titanium. The second conductive layer CL20 may have a thickness of about 100 Å to about 500 Å. Since the second conductive layer CL20 or titanium is used as the topmost conductive layer, the reflectance of external light can be reduced, and the reflected light of the titanium layer can produce a relatively small color shift. The third conductive layer CL30 may include indium zinc oxide (ZIO), indium oxide (In2O3), zinc oxide (ZnO x ), a metal included in the first conductive layer CL10, or an alloy of a metal included in the first conductive layer CL10.

[0123] The dummy pattern MP may have optical properties substantially the same as those of the first line portion L1 and the second line portion L2. For example, the dummy pattern MP may have a reflectance substantially the same as that of the first line portion L1 and the second line portion L2. The dummy pattern MP may have a material substantially the same as that of the first line portion L1 and the second line portion L2.

[0124] The dummy pattern MP may have a stacking structure the same as that of the first line portion L1 and the second line portion L2. The dummy pattern MP and the first line portion L1 may have the same stacking structure. Since the dummy pattern MP is provided to compensate for the cut-off region DCA in terms of optical properties, it may be preferable that the first line portion L1 and the second line portion L2 have the same stacking structure.

[0125] The first conductive layer CL1 (or the first line conductive layer) of the dummy pattern MP may have the same material and thickness as the first conductive layer CL10 of the first line portion L1. The second conductive layer CL2 (or the second line conductive layer) of the dummy pattern MP may have the same material and thickness as the second conductive layer CL20 of the first line portion L1. The third conductive layer CL3 (or the third line conductive layer) of the dummy pattern MP may have the same material and thickness as the third conductive layer CL30 of the first line portion L1.

[0126] Figure 7e depicts the reflection path of external light. Basically, the external light can be reflected from Figure 7d the side surface of the second conductive layer CL20 discussed in. When the dummy pattern MP does not exist, the external light is not reflected on the cut-off area DCA, so the cut-off area DCA will be visible. When the dummy pattern MP is set to correspond to the cut-off area DCA, the external light can be reflected from the dummy pattern MP to correspond to the cut-off area DCA. Therefore, the cut-off area DCA can be less visible.

[0127] Figure 8a shows a magnified plan view of the second conductive layer 240 corresponding to the second region B1 of Figure 6a Figure 8b shows a magnified plan view of the first conductive layer 220 corresponding to the second region B1 of Figure 6a

[0128] Figure 8a depicts the boundary region between the sensing pattern SP1 of the third first electrode E1-3 and the sensing portion SP2 of the fifth second electrode E2-5. Since portions of the first line portion L1 and the second line portion L2 are removed according to a specific rule, a boundary region can be defined between the first electrode E1-3 and the second electrode E2-5, or a boundary region BA can be defined between the first line portion L1 and the second line portion L2 of the sensing pattern SP1 and the first line portion L1 and the second line portion L2 of the sensing portion SP2.

[0129] The boundary line BL is depicted to clearly represent the boundary region between the first electrode E1-3 and the second electrode E2-5. The boundary region between the first electrode E1-3 and the second electrode E2-5 can be defined as a set of boundary regions BA indicating between the first line portion L1 and the second line portion L2 of the sensing pattern SP1 and the first line portion L1 and the second line portion L2 of the sensing portion SP2. Figure 8a Twelve boundary regions BA are depicted by way of example.

[0130] One of the boundary regions BA can be positioned between the first opening region EOP1 and the second opening region EOP2, another one of the boundary regions BA can be positioned between the first opening region EOP1 and the third opening region EOP3, and yet another one of the boundary regions BA can be positioned between the third opening region EOP3 and the second opening region EOP2. One kind in the boundary region BA can be defined in the first line portion L1 or the second line portion L2 each located in the first unit emission region UA1 and the second unit emission region UA2. Another kind in the boundary region BA can be defined in the first line portion L1 or the second line portion L2 located between the first unit emission region UA1 and the second unit emission region UA2 provided in different pixel rows or different pixel columns.

[0131] Referring Figure 8b , the first conductive layer 220 can include a plurality of dummy patterns MP-B in the boundary region BA provided between the first electrode E1-3 and the second electrode E2-5. Although the plurality of dummy patterns MP-B are assigned symbols different from those of the plurality of dummy patterns MP depicted in Figure 7b , the plurality of dummy patterns MP-B can be substantially the same as the plurality of dummy patterns MP depicted in Figure 7b . Figure 7b The plurality of dummy patterns MP depicted in Figure 8b and the plurality of dummy patterns MP-B depicted in

[0132] can be formed in the same process, can have the same structure, and can include the same materials. The plurality of dummy patterns MP-B can correspondingly overlap with the plurality of boundary regions BA. The plurality of dummy patterns MP-B provided on the plurality of boundary regions BA can have functions substantially the same as those of the plurality of dummy patterns MP discussed with reference to Figures 7a to 7e .

[0133] The presence of the plurality of dummy patterns MP-B can reduce the visibility of the boundary region between the first electrode E1-3 and the second electrode E2-5. Visibility level 3 can be defined as the level indicating that the presence of the plurality of dummy patterns MP-B reduces the visibility of the boundary region between the first electrode E1-3 and the second electrode E2-5. Visibility level 4 can be defined as the level indicating that the plurality of boundary regions BA are substantially replaced by the plurality of dummy patterns MP-B so that the boundary region between the first electrode E1-3 and the second electrode E2-5 is substantially not recognized. The plurality of dummy patterns MP-B can cause an optical compensation difference between visibility level 3 and visibility level 4.

[0134] The presence of the plurality of dummy patterns MP-B can reduce Figure 7cThe reflectance difference between the second line portion L2 under discussion and the cut-off region DCA. "Reduction of the reflectance difference" itself can be defined as visibility level 3. Visibility level 4 can be defined as indicating a state where the reflectance difference is in the range of approximately -5% to approximately +5% or from -10% to approximately +10%. For example, compared with the reflectance difference in visibility level 3, the reflectance difference in visibility level 4 can be significantly smaller.

[0135] In Figure 8a , the cut-off region DCA of the sensing pattern SP1 and the sensing portion SP2 is not shown to highlight the boundary region BA, but in this embodiment, the cut-off region DCA according to the rules discussed with reference to Figure 7a can be defined in the first electrode (see E1-1 to E1-4 in Figure 6a ) and the second electrode (see E2-1 to E2-7 in Figure 6a ). In addition, in Figure 8b , the dummy pattern MP is not shown, and the dummy pattern MP can also be set to correspond to the cut-off region DCA according to the rules discussed with reference to Figure 7a . Even in the internal regions of the first electrode E1-3 and the second electrode E2-5, the cut-off region DCA and the dummy pattern MP can provide visibility level 3 or visibility level 4.

[0136] In an embodiment of the present invention, the cut-off region DCA may not be defined in the first electrode E1-3 and the second electrode E2-5. As discussed above, the cut-off region DCA can be formed to reduce visibility level 1 to visibility level 2. However, when visibility level 4 where the boundary region between the first electrode E1-3 and the second electrode E2-5 is substantially invisible can be ensured, it may not matter even if the cut-off region DCA is not formed in the first electrode E1-3 and the second electrode E2-5. When the cut-off region DCA is not formed in the first electrode E1-3 and the second electrode E2-5, the first electrode E1-3 and the second electrode E2-5 can have their reduced resistance to increase sensitivity.

[0137] Figures 9a to 9c A magnified plan view of a first region A1 of the input sensor 200 according to an embodiment of the present invention is shown partially. Figure 9d A cross-sectional view of the input sensor 200 according to an embodiment of the present invention is shown. Figures 9a to 9c can correspond to Figure 7c , and Figure 9d can correspond to Figure 7d . In the following embodiments, Figures 7a to 7c 's description will apply to components identical to those discussed with reference to Figures 7a to 7c .

[0138] As Figures 9a to 9cAs shown, the dummy pattern MP may have various areas and shapes. The area and shape of the dummy pattern MP may be set to conform to the reflection properties of the dummy pattern MP.

[0139] As Figure 9a shown, the dummy pattern MP may have an area smaller than the area of the cut-off region DCA and may have the same line width as the line width of the cut-off region DCA. As Figure 9b shown, the dummy pattern MP may have an area larger than the area of the cut-off region DCA and may have a length and a line width larger than the length and the line width of the cut-off region DCA. As Figure 9c shown, the dummy pattern MP may have a shape different from the shape of the cut-off region DCA. The dummy pattern MP may have a circular shape. The shape of the dummy pattern MP is not particularly limited thereto and may have an elliptical shape or any other suitable shape.

[0140] As Figure 9d shown, the dummy pattern MP may be provided on the second insulating layer 230, and the second line portion L2 may be provided under the second insulating layer 230. In this case, the second conductive layer 240 may be formed as the bridging pattern CP1 discussed with reference to Figure 6a and Figure 6b the discussion.

[0141] Although the embodiments have been described with reference to multiple illustrative examples of the embodiments, those of ordinary skill in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the claims. Accordingly, the technical scope of the invention is not limited by the embodiments and examples described above, but is limited by the claims.

[0142] Industrial Applicability The present invention relates to a display device including an input sensor. Since various input sensors are applied to various display devices, the possibility of applying the present invention to products is high.

Claims

1. A display device, the display device comprising: a display panel including a plurality of emission regions and non-emission regions adjacent to the plurality of emission regions; and an input sensor on the display panel, wherein the input sensor includes: an insulating layer; a first sensing electrode; a second sensing electrode including a sensing pattern spaced apart from the first sensing electrode in a plan view; and a plurality of dummy patterns spaced apart from the sensing pattern of the first sensing electrode and the second sensing electrode, the insulating layer being disposed between the first sensing electrode and the plurality of dummy patterns and between the second sensing electrode and the plurality of dummy patterns, wherein each of the sensing patterns of the first sensing electrode and the second sensing electrode includes a plurality of line portions overlapping with the non-emission regions, wherein the plurality of line portions define a plurality of opening regions overlapping with corresponding emission regions among the plurality of emission regions, wherein a plurality of boundary regions are defined to indicate an interval region between the plurality of line portions of the first sensing electrode and the plurality of line portions of the sensing pattern of the second sensing electrode, and wherein at least a part of the plurality of dummy patterns overlaps with the plurality of boundary regions.

2. The display device according to claim 1, wherein, A plurality of cut-off regions are defined in the plurality of line portions of the first sensing electrode and the plurality of line portions of the sensing pattern of the second sensing electrode, wherein each of the plurality of dummy patterns overlaps with a corresponding cut-off region or boundary region among the plurality of cut-off regions and the plurality of boundary regions.

3. The display device according to claim 2, Among them, wherein the emission regions include: a plurality of first emission regions emitting light of a first color; a plurality of second emission regions emitting light of a second color; and a plurality of third emission regions emitting light of a third color, wherein two first emission regions among the plurality of first emission regions, two second emission regions among the plurality of second emission regions, and two third emission regions among the plurality of third emission regions define a unit emission region, and wherein the unit emission region includes: a first unit emission region in which one of the two first emission regions and one of the two second emission regions are disposed on one side of one of the two third emission regions, and in the first unit emission region, the one third emission region is disposed downward relative to the one first emission region and the one second emission region in a direction along which the one first emission region and the one second emission region are arranged; and The second unit emission region, in which another first emission region of the two first emission regions and another second emission region of the two second emission regions are disposed on one side of another third emission region of the two third emission regions, and in the second unit emission region, the another third emission region is disposed upward relative to the another first emission region and the another second emission region in the direction along which the another first emission region and the another second emission region are arranged.

4. The display device according to claim 3, wherein, The plurality of opening regions include: A first opening region corresponding to the one first emission region; A second opening region corresponding to the one second emission region; and A third opening region commonly corresponding to the one third emission region of the first unit emission region and the another third emission region of the second unit emission region, the one third emission region of the first unit emission region and the another third emission region of the second unit emission region being adjacent to each other in the direction along which the one first emission region and the one second emission region are arranged.

5. The display device according to claim 4, wherein, One of the plurality of boundary regions is disposed between one first emission region and one second emission region, Another one of the plurality of boundary regions is disposed between one first emission region and one third emission region, and Still another one of the plurality of boundary regions is disposed between one second emission region and one third emission region.

6. The display device according to claim 4, wherein, One of the plurality of cutting regions is disposed between one first emission region and one second emission region, and Another one of the plurality of cutting regions is disposed between one second emission region and one third emission region.

7. The display device according to claim 4, Among them, The unit emission regions are provided as a plurality, and the plurality of unit emission regions define a pixel matrix, the pixel matrix including a (m - 1)th pixel row, an mth pixel row, a (m + 1)th pixel row, an (n - 1)th pixel column, an nth pixel column, and an (n + 1)th pixel column, where each of m and n is a natural number equal to or greater than 2, wherein the first unit emission region is disposed at each of intersections between the (m - 1)th pixel row and the (n - 1)th pixel column, between the (m + 1)th pixel row and the (n - 1)th pixel column, between the mth pixel row and the nth pixel column, between the (m - 1)th pixel row and the (n + 1)th pixel column, and between the (m + 1)th pixel row and the (n + 1)th pixel column, and wherein the second unit emission region is disposed at each of intersections between the mth pixel row and the (n - 1)th pixel column, between the (m - 1)th pixel row and the nth pixel column, between the (m + 1)th pixel row and the nth pixel column, and between the mth pixel row and the (n + 1)th pixel column.

8. The display device according to claim 7, Among them, The plurality of line portions include: A first line portion extending in a first direction; and A second line portion extending in a second direction intersecting the first direction, Wherein the plurality of cutting regions define a plurality of cutting units, and each of the plurality of cutting units includes a first cutting region, a second cutting region, a third cutting region, a fourth cutting region, a fifth cutting region, a sixth cutting region, a seventh cutting region, and an eighth cutting region, Wherein the first cutting region is defined in the first line portion between the first emission region and the second emission region of the second unit emission region at the intersection point provided between the (m-1)-th pixel row and the n-th pixel column, Wherein the second cutting region is defined in the second line portion between the second emission region and the third emission region of the second unit emission region at the intersection point provided between the (m-1)-th pixel row and the n-th pixel column, Wherein the third cutting region is defined in the first line portion between the first emission region and the second emission region of the first unit emission region at the intersection point provided between the m-th pixel row and the n-th pixel column, and Wherein the fourth cutting region is defined in the second line portion between the third emission region of the second unit emission region at the intersection point provided between the m-th pixel row and the (n-1)-th pixel column and the second emission region of the first unit emission region at the intersection point provided between the m-th pixel row and the n-th pixel column.

9. The display device according to claim 8, Among them, The fifth cutting region is defined in the second line portion between the second emission region and the third emission region of the first unit emission region at the intersection point provided between the (m-1)-th pixel row and the (n+1)-th pixel column, Wherein the sixth cutting region is defined in the first line portion between the second emission region of the first unit emission region at the intersection point provided between the (m-1)-th pixel row and the (n+1)-th pixel column and the first emission region of the second unit emission region at the intersection point provided between the m-th pixel row and the (n+1)-th pixel column, Wherein the seventh cutting region is defined in the second line portion between the third emission region of the first unit emission region at the intersection point provided between the m-th pixel row and the n-th pixel column and the second emission region of the second unit emission region at the intersection point provided between the m-th pixel row and the (n+1)-th pixel column, and Among them, the eighth cutting region is defined in the first line portion between the second emission region of the second unit emission region located at the intersection point between the m-th pixel row and the (n + 1)-th pixel column and the first emission region of the first unit emission region located at the intersection point between the (m + 1)-th pixel row and the (n + 1)-th pixel column.

10. The display device according to claim 7, Among them, The plurality of line portions include: A first line portion extending in a first direction; and A second line portion extending in a second direction intersecting the first direction, Among them, the plurality of cutting regions define a plurality of cutting units, and each of the plurality of cutting units includes a first cutting region, a second cutting region, a third cutting region, a fourth cutting region, a fifth cutting region, a sixth cutting region, a seventh cutting region, and an eighth cutting region, Among them, the first cutting region to the eighth cutting region are divided into four pairs, and each of the four pairs includes two cutting regions that are closest to each other among the first cutting region to the eighth cutting region, Among them, one of the two cutting regions of each pair is defined in the first line portion, and Among them, the other of the two cutting regions of each pair is defined in the second line portion.

11. The display device according to claim 1, wherein, The plurality of line portions and the plurality of dummy patterns have the same stacking structure.

12. The display device according to claim 11, wherein, Each of the plurality of line portions and the plurality of dummy patterns includes a first conductive layer and a second conductive layer on the first conductive layer, and Among them, the first conductive layer has a conductivity and a reflectivity greater than those of the second conductive layer.

13. The display device according to claim 1, Among them, The sensing patterns are arranged in a plurality along the first direction, Among them, the second sensing electrode further includes bridging patterns, and each of the bridging patterns connects two adjacent sensing patterns among the plurality of sensing patterns, and Among them, the bridging patterns and the plurality of dummy patterns are provided on the same layer.

14. The display device according to claim 13, wherein, The bridging patterns and the plurality of dummy patterns include the same stacking structure.

15. The display device according to claim 14, wherein, The first sensing electrode extends in a second direction and has a single integral shape, and the second direction intersects the first direction.

16. A display device, the display device includes: A display panel including a plurality of emission regions and non-emission regions adjacent to the plurality of emission regions; And An input sensor on the display panel, Among them, the input sensor includes: an insulating layer; a sensing electrode; and a plurality of dummy patterns between the sensing electrode and the insulating layer, Among them, the sensing electrode includes a plurality of line portions stacked with the non-emission regions, and the plurality of line portions define a plurality of opening regions stacked with corresponding emission regions among the plurality of emission regions, Among them, a plurality of cutting regions are defined in the plurality of line portions, and Among them, the plurality of dummy patterns are stacked with the plurality of cutting regions.

17. The display device according to claim 16, Among them, The plurality of line portions include: A first line portion extending in a first direction; and A second line portion extending in a second direction intersecting the first direction, wherein the plurality of cutting regions are divided into a plurality of pairs of cutting regions, each pair of cutting regions including two cutting regions that are closest to each other, wherein one of the two cutting regions in each pair of the plurality of pairs of cutting regions is defined in the first line portion, and wherein the other of the two cutting regions in each pair of the plurality of pairs of cutting regions is defined in the second line portion.

18. The display device according to claim 16, wherein, Each of the plurality of line portions and the plurality of dummy patterns includes a first conductive layer and a second conductive layer on the first conductive layer, and wherein the first conductive layer has a greater conductivity and reflectivity than the second conductive layer.

19. The display device according to claim 16, wherein, The plurality of line portions and the plurality of dummy patterns have the same reflectivity.

20. The display device according to claim 16, wherein, The plurality of line portions and the plurality of dummy patterns include the same material.

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