Method and system for detecting pressure resistance of LCD (Liquid Crystal Display) logic board base material

Abstract

The invention discloses a method and a system for detecting the pressure resistance of an LCD (liquid crystal display) logic board substrate. The method comprises the following steps: preprocessing a substrate sample of an LCD logic circuit board; configuring a multi-stage stepped voltage loading sequence; installing a distributed electrode array; a dynamic voltage withstanding test is executed, test parameters are recorded, and the test parameters comprise an inter-electrode leakage current value and a current fluctuation characteristic parameter, local temperature rise distribution data of a base material sample of the LCD logic circuit board and a surface deformation quantity of the base material sample of the LCD logic circuit board; constructing a composite failure evaluation model based on the test parameters, and outputting a voltage-withstanding stability coefficient; and based on the voltage-withstanding stability coefficient, determining the voltage-withstanding performance grade in a grading manner. The method has the following advantages and effects that multiple electric-thermal-mechanical parameters can be synchronously monitored, a core detection method of a dynamic failure quantification model is established, and finally, the accuracy and reliability of the pressure resistance performance detection result of the LCD logic board base material are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of LCD logic board testing, and particularly relates to a method and system for detecting the withstand voltage performance of the base material of an LCD logic board. Background Art

[0002] As a key component connecting the image processing chip and the panel, the insulation withstand voltage performance of the base material of the LCD logic circuit board directly determines the reliability and safety of the whole machine; under working conditions such as high-voltage drive signal transmission or surge impact, insulation failure of the base material will lead to circuit short-circuit, signal distortion, device burnout or even safety accidents. Therefore, it is crucial to accurately and reliably detect the withstand voltage performance of the base material of the LCD logic board. Currently, the industry generally uses static breakdown voltage testing or single-step voltage application method to detect the withstand voltage performance of the base material of the LCD logic board. These methods have the following fundamental defects: Firstly, the failure mechanism is one-sided, only taking the dielectric breakdown voltage as the sole criterion, ignoring the coupling effect of electro-thermal-mechanical multi-physical fields in actual work; the leakage current fluctuation, local temperature rise gradient and deformation accumulation generated during the dynamic voltage rise process of the base material of the LCD logic board are all key factors inducing the degradation of insulation performance, but the existing methods cannot capture these dynamic parameters.

[0003] Secondly, the lack of risk prediction caused by the one-sided failure mechanism mentioned above leads to the final judgment result often deviating from the true performance under the actual application scenario; moreover, the output result of the traditional method is a binary judgment of pass / fail, which cannot reflect the stability margin and potential risk level of the withstand voltage performance of the material.

[0004] Therefore, there is an urgent need for a core detection method that can synchronously monitor electro-thermal-mechanical multi-parameters and establish a dynamic failure quantification model. Summary of the Invention

[0005] The purpose of the present invention is to provide a method and system for detecting the withstand voltage performance of the base material of an LCD logic board to solve the problems raised in the background art.

[0006] The above technical purpose of the present invention is achieved through the following technical solutions: The present invention provides a method for detecting the withstand voltage performance of the base material of an LCD logic board, including the following steps: S100. Pretreat the base material sample of the LCD logic circuit board; S200. Configure a multi-stage stepped voltage loading sequence; including: Based on the rated working voltage of the base material sample of the LCD logic circuit board, generate a stepped voltage loading sequence including multiple pressurization stages, where the voltage of the first stage is a proportional voltage of the rated voltage, and the voltage of each subsequent stage increases according to a preset ratio, and the duration of each stage is set as a preset holding voltage duration; S300. Install a distributed electrode array, including: Arrange multiple pairs of electrodes on the surface of the substrate sample of the LCD logic circuit board, with the spacing of each pair of electrodes controlled within a preset tolerance range, and the electrodes within each pair of electrodes are coated with an insulating coating of a preset thickness; S400. Perform a dynamic withstand voltage test, including: Apply a test voltage to each pair of electrodes according to the stepped voltage loading sequence through a high-voltage generator, and simultaneously monitor and record the test parameters in real time at a preset sampling frequency; wherein, the test parameters include the leakage current value and current fluctuation characteristic parameters between the electrodes, the local temperature rise distribution data of the substrate sample of the LCD logic circuit board, and the surface deformation amount of the substrate sample of the LCD logic circuit board; S500. Construct a composite failure assessment model based on the test parameters and output a withstand voltage stability coefficient; S600. Classify and determine the withstand voltage performance level based on the withstand voltage stability coefficient.

[0007] By adopting the above technical solutions, through the pretreatment of the substrate sample of the LCD logic circuit board, it is ensured that the substrate sample of the LCD logic circuit board meets the multiple quality control requirements of static electricity, charge, temperature, humidity and surface cleanliness before the test, thereby eliminating the interference of the environment or sample itself defects on the withstand voltage test results and improving the reliability and repeatability of the test data; automatically generate a multi-level stepped voltage loading sequence based on the rated working voltage, so that the loading voltage is accurately matched with the actual bearing capacity of the substrate sample of the LCD logic circuit board, and maintain a constant duration at each stage to fully reflect the transient and steady-state response characteristics of the medium at different voltage levels, so as to more comprehensively evaluate the withstand voltage performance; through the design of the distributed electrode array and the insulating coating, it is possible to achieve multi-point and uniform electric field application and leakage current monitoring on the surface of the substrate sample of the LCD logic circuit board, avoid false breakdown caused by local electric field concentration, accurately capture the leakage current between the electrodes and its fluctuation characteristics, and combine the real-time monitoring of the local temperature rise and deformation distribution to provide multi-dimensional and high-precision test parameters for constructing a composite failure assessment model, and finally give an objective and quantitative determination of the withstand voltage performance level through the withstand voltage stability coefficient, significantly improving the accuracy and comparability of the test results.

[0008] Further, the S100 includes the following steps: S110. Place the substrate sample of the LCD logic circuit board in an anti-static carrier, wherein the surface resistance value of the anti-static carrier is maintained within a preset surface resistance range; at the same time, embed a distributed resistance sensor in the contact area between the anti-static carrier and the substrate sample of the LCD logic circuit board to monitor the static charge accumulation amount in real time; when the monitored static charge accumulation amount exceeds the preset safety threshold, start the charge discharge circuit built in the carrier; S120. Move the anti-static carrier loaded with the substrate sample of the LCD logic circuit board into a constant temperature and humidity environmental chamber, where the temperature of the environmental chamber is controlled within a preset standard temperature range, the relative humidity is maintained within a preset standard humidity range, and the continuous static time reaches a preset equilibrium duration; S130. Use a non-contact laser dust particle counter to scan the surface of the substrate sample of the LCD logic circuit board. When the detected particle size exceeds a preset particle threshold or the particle density per unit area exceeds a preset density threshold, an automatic cleaning instruction is triggered; S140. Use a contact angle measuring instrument to select multiple preset detection sites on the substrate sample of the LCD logic circuit board. When the deionized water contact angle at any detection site exceeds a preset contact angle threshold, plasma surface activation treatment is performed on this site.

[0009] By adopting the above technical solutions, through the real-time monitoring and automatic discharge of the surface resistance and electrostatic charge accumulation amount of the anti-static carrier, the potential damage risk of electrostatic discharge to the substrate sample of the LCD logic circuit board and the test instrument is eliminated to the greatest extent; at the same time, the substrate sample of the LCD logic circuit board is placed in a constant temperature and humidity environmental chamber for replacement and balance treatment to ensure stable and consistent temperature and humidity conditions, and the influence of environmental humidity or temperature difference on the dielectric electrical parameters is excluded; non-contact laser dust particle counting and automatic cleaning are linked and controlled on the surface of the substrate sample of the LCD logic circuit board, which not only ensures that the substrate surface cleanliness meets strict standards, but also avoids local electric field distortion caused by particle contamination; finally, the surface activity state is determined by contact angle measurement, and plasma activation treatment is automatically performed when necessary to make the surface energy reach the optimal level, so as to improve the adhesion of the electrode coating and the electric field uniformity, and further enhance the stability and repeatability of the test process.

[0010] A further setting is that the S200 includes the following steps: S210. Obtain the rated working voltage nominal value from the product specification database of the substrate sample of the LCD logic circuit board, and associate the dielectric layer thickness distribution map of the substrate sample of the LCD logic circuit board; S220. Based on the rated working voltage nominal value and the dielectric layer thickness variation coefficient, generate a basic test voltage through voltage conversion, where the basic test voltage has a negative correlation with the dielectric layer thickness variation coefficient; S230. According to the material type code of the substrate sample of the LCD logic circuit board, retrieve the corresponding voltage increment ratio coefficient and the number threshold of pressurization stages from a preset rule library; among them, the material type code is mapped to a preset material classification matrix; S240. Calculate the voltage safety factor by constructing a medium thickness - material safety matrix based on the medium layer thickness distribution map and the material type code. When the voltage safety factor is less than the preset safety factor threshold, automatically reduce the threshold of the number of pressurization stages; S250. Construct a stepped voltage loading sequence including the threshold of the number of pressurization stages, and verify the sequence continuity through a voltage waveform analyzer.

[0011] By adopting the above technical solutions, the nominal value of the rated working voltage of the base material sample of the LCD logic circuit board is automatically obtained from the product specification database, and the basic test voltage is generated by combining with the medium layer thickness distribution map, which can fully consider the influence of medium thickness variation on the breakdown voltage; by calling the voltage increment ratio coefficient and the threshold of the number of pressurization stages corresponding to the material type from the rule library, the material properties and test parameters are deeply coupled to avoid test deviations caused by blind pressurization or insufficient loading; based on the joint analysis of the thickness distribution and material type, the number of pressurization stages can be dynamically adjusted to ensure that the test process not only fully reveals potential defects but also avoids excessive damage to the base material sample of the LCD logic circuit board, thus improving the test efficiency and the credibility of the results.

[0012] A further setting is that the S240 includes the following steps: S240.1. Map the minimum medium layer thickness of the medium layer thickness distribution map to the preset safety reference curve corresponding to the material type code, and construct a medium thickness - material safety matrix: where the method for obtaining the preset safety reference curve is: Input the material type code into the preset material safety database for matching query, and output the basic safety parameter group corresponding to the material type code, where the basic safety parameter group includes the reference value of the material dielectric strength, the thickness - field strength relationship function identification code, and the material safety correction factor; According to the thickness - field strength relationship function identification code, call the corresponding thickness - field strength relationship function from the physical property function library, and this function defines the mapping rules that satisfy the material classification matrix; Based on the basic test voltage and the material safety correction factor, solve the thickness - field strength relationship function through inverse function operation to obtain the theoretical safety thickness; S240.2. Calculate the voltage safety factor based on the minimum medium layer thickness, the theoretical safety thickness, and the material safety correction factor; S240.3. If the voltage safety factor is less than the preset safety factor threshold, adjust the threshold of the number of pressurization stages to the preset downgrading ratio of the original value.

[0013] By adopting the above technical solutions, the mapping construction of the minimum medium thickness and the preset safety reference curve is introduced in the medium safety assessment stage. The theoretical safety thickness is solved through inverse function operation, ensuring that the calculation of the safety factor has sufficient theoretical basis and experimental data support. When the calculated voltage safety factor is lower than the threshold, the system can automatically reduce the number of pressurization stages, avoiding causing electric field stress higher than the safe bearing limit to the medium, thereby effectively preventing breakdown failure. This not only improves the safety guarantee level of the systematic design, but also realizes the adaptive optimization for different material and thickness distribution conditions, enhancing the versatility and scalability of the test scheme.

[0014] A further setting is that the arrangement rule of the electrode array in the S300 includes: Each pair of electrodes is equally spaced along the diagonal direction of the substrate sample of the LCD logic circuit board; The electrodes of each pair of electrodes are connected to the substrate sample of the LCD logic circuit board through a conductive adhesive material, and the thickness after curing of the conductive adhesive material is controlled within a preset thickness range.

[0015] By adopting the above technical solutions, by arranging multiple pairs of electrodes along the diagonal direction on the surface of the substrate sample of the LCD logic circuit board and strictly controlling the electrode spacing and the thickness after curing of the conductive adhesive material, the electric field distribution in the entire test area is made more uniform and reasonable, avoiding the problems of false breakdown and data deviation caused by local electric field aggregation. The precise control of the curing thickness of the conductive adhesive material ensures the stable and controllable contact impedance between the electrodes and the substrate sample of the LCD logic circuit board, providing a stable transmission channel for subsequent dynamic monitoring.

[0016] A further setting is that the S500 includes the following steps: S510. Obtain the test parameters and perform multi-dimensional feature extraction; including: Based on the leakage current value between the electrodes and the current fluctuation characteristic parameters, obtain the coefficient of variation of current fluctuation; Based on the local temperature rise distribution data of the substrate sample of the LCD logic circuit board, extract the maximum temperature rise value and the temperature rise uniformity index; Based on the surface deformation amount of the substrate sample of the LCD logic circuit board, calculate the deformation gradient and the maximum deformation amount; Confirm the coefficient of variation of current fluctuation, the maximum temperature rise value, the temperature rise uniformity index, the deformation gradient and the maximum deformation amount as the feature vector; S520. Based on the material type code of the substrate sample of the LCD logic circuit board, retrieve the initial weight coefficient from the preset weight rule library; wherein, the initial weight coefficient includes a current weight coefficient, a heat weight coefficient and a mechanical weight coefficient, and the material type code is mapped to the preset material classification matrix in the S230; Adjust and normalize the initial weight coefficients to obtain the final weight coefficients; S530. Calculate the item failure risk indicators, where the item failure risk indicators include current-related failure risk indicators, heat-related failure risk indicators, and mechanical-related failure risk indicators; including: Based on the coefficient of variation of current fluctuations, obtain the current-related failure risk indicator; Based on the maximum temperature rise value and the temperature rise uniformity index, obtain the heat-related failure risk indicator; Based on the deformation gradient and the maximum deformation amount, obtain the mechanical-related failure risk indicator; S540. Input the current-related failure risk indicator, heat-related failure risk indicator, and mechanical-related failure risk indicator into the composite failure assessment model to obtain the composite failure risk score; then, based on the composite failure risk score, generate the voltage withstand stability coefficient.

[0017] By adopting the above technical solution, multi-dimensional feature extraction is introduced in the construction of the composite failure assessment model, and key parameters such as the coefficient of variation of current fluctuations, temperature rise distribution, and surface deformation amount are systematically processed and identified as feature vectors, realizing the comprehensive capture of the three major failure modes of current, heat, and machinery; through the retrieval and normalization of the initial weight coefficients, as well as the precise calculation of the sub-item risks of each failure index, the contribution of each failure mechanism can be reasonably quantified; finally, the sub-item risk indicators are input into the composite assessment model, the composite failure risk score is output and the voltage withstand stability coefficient is generated, providing multi-dimensional and interpretable quantitative results for quality assessment, and greatly improving the accuracy and forward-looking of failure prediction.

[0018] A further setting is that the adjustment and normalization of the initial weight coefficients in S520 to obtain the final weight coefficients includes: Dynamically adjust the initial weight coefficients based on the data quality indicators of the feature vectors; where the data quality indicators include the signal-to-noise ratio of current data, the spatial resolution score of temperature rise data, and the accuracy score of deformation data; Normalize the adjusted initial weight coefficients to obtain the final weight coefficients.

[0019] By adopting the above technical solution, a dynamic correction mechanism for data quality indicators is introduced for the adjustment of the initial weight coefficients. The signal-to-noise ratio of the current data, the spatial resolution score of the temperature rise measurement, and the deformation data accuracy score are evaluated in real time, and the weights are adjusted in combination with these indicators, ensuring that the model still has stable discrimination ability under different sampling conditions; then normalization processing is performed to keep the sum of each weight consistent all the time, thus avoiding model deviation caused by the fluctuation of a single data quality; this not only enhances the robustness of the composite evaluation model, but also makes the weight distribution more in line with the actual test environment, improving the reliability of the evaluation results.

[0020] A further setting is that the S500 further includes the following steps: S550, verifying and outputting the voltage withstand stability coefficient; including: Performing range verification on the voltage withstand stability coefficient. If the voltage withstand stability coefficient is less than 0 or greater than 100, triggering a data re-acquisition instruction; If the verification passes, outputting the voltage withstand stability coefficient to S600.

[0021] By adopting the above technical solution, a range verification link is added before the output of the voltage withstand stability coefficient. When the coefficient exceeds the reasonable range, a data re-acquisition instruction can be automatically triggered, realizing the automatic correction and secondary verification of abnormal test results, avoiding unreasonable judgments caused by accidental errors, and thus ensuring that the finally output voltage withstand stability coefficient is strictly within the preset range, enhancing the credibility of the test results.

[0022] A further setting is that the S600 includes the following steps: S610, receiving the voltage withstand stability coefficient and synchronously retrieving the material type code; S620, according to the material type code, retrieving the corresponding grading threshold table from the preset grading rule library, comparing the voltage withstand stability coefficient with the grading threshold table, and confirming the voltage withstand performance level.

[0023] By adopting the above technical solution, the automatic comparison between the voltage withstand stability coefficient and the preset grading threshold table is realized in the stage of determining the voltage withstand performance level. Combining the material type code, the corresponding grading rules can be quickly obtained, ensuring the objectivity and consistency of the determination results; the entire grading process realizes the standardized and automated grading management of the voltage withstand performance level, providing efficient and reliable decision-making support for quality traceability, batch comparison, and failure analysis in the subsequent production process.

[0024] The present invention also provides a voltage withstand performance detection system for an LCD logic board substrate, including the following modules: Pretreatment module; used to execute S100, including an anti-static carrier unit, an environmental balance unit, a particle cleaning unit, and a surface activation unit; Voltage sequence configuration module; used to execute S200, including a data acquisition unit, a voltage calculation unit, and a sequence verification unit; Electrode array deployment module; used to execute S300, including an electrode arrangement unit and an adhesion control unit; Test execution module: used to execute S400, including an integrated high-voltage generator, a parameter monitoring unit, and a device coordination unit; Composite evaluation module; used to execute S500, including a feature extraction unit, a weight optimization unit, a risk calculation unit, and a coefficient generation unit; Hierarchical determination module: used to execute S600, including a coefficient receiving unit and a grade mapping unit.

[0025] In summary, the present invention has the following beneficial effects: A core detection method that can synchronously monitor multiple electro-thermal-mechanical parameters and establish a dynamic failure quantification model, ultimately improving the accuracy and reliability of the detection results of the withstand voltage performance of the LCD logic board substrate. Brief Description of the Drawings

[0026] Figure 1 Is the main flow block diagram of the embodiment; Figure 2 Is the flow schematic diagram of S500 in the embodiment; Figure 3 Is the system block diagram of the embodiment. Detailed Description of the Embodiment

[0027] The present invention will be further described in detail below with reference to the accompanying drawings.

[0028] As shown in the Figures 1 to 3 accompanying drawings; This embodiment discloses a method for detecting the withstand voltage performance of an LCD logic board substrate, including the following steps: S100. Pretreat the substrate sample of the LCD logic circuit board; S200. Configure a multi-level stepped voltage loading sequence; including: Based on the rated working voltage of the substrate sample of the LCD logic circuit board, generate a stepped voltage loading sequence including multiple pressurization stages, where the voltage of the first stage is a proportional voltage of the rated voltage, and the voltage of each subsequent stage increases according to a preset ratio, and the duration of each stage is set to a preset pressure holding duration; S300. Install a distributed electrode array; including: Arrange multiple pairs of electrodes on the surface of the substrate sample of the LCD logic circuit board, with the spacing between each pair of electrodes controlled within a preset tolerance range, and the electrodes within each pair of electrodes are coated with an insulating coating of a preset thickness; S400. Perform a dynamic withstand voltage test, including: Apply a test voltage to each pair of electrodes in a stepped voltage loading sequence through a high-voltage generator, and simultaneously monitor and record the test parameters in real time at a preset sampling frequency; among them, the test parameters include the leakage current value between the electrodes and the current fluctuation characteristic parameters, the local temperature rise distribution data of the substrate sample of the LCD logic circuit board, and the surface deformation amount of the substrate sample of the LCD logic circuit board; Preferably, a high-precision micro-current measurement device is used to measure the leakage current, and the measurement range covers the preset current range; the temperature rise data is collected by an infrared thermal imaging device, and the spatial resolution is not lower than the preset resolution threshold; an optical deformation detection device is used to detect the deformation amount.

[0029] S500. Construct a composite failure assessment model based on the test parameters and output a withstand voltage stability coefficient; S600. Classify and determine the withstand voltage performance level based on the withstand voltage stability coefficient.

[0030] In a possible implementation manner, S100 includes the following steps: S110. Place the substrate sample of the LCD logic circuit board in an anti-static carrier, where the surface resistance value of the anti-static carrier is maintained within a preset surface resistance range; at the same time, embed a distributed resistance sensor in the contact area between the anti-static carrier and the substrate sample of the LCD logic circuit board to monitor the electrostatic charge accumulation amount in real time; when the monitored electrostatic charge accumulation amount exceeds the preset safety threshold, start the charge discharge circuit built in the carrier; Preferably, the contact surface of the carrier is covered with a cationic anti-static coating; Preferably, measure the surface resistance value of the anti-static carrier, and apply a resistance correction coating if it exceeds the preset surface resistance range; S120. Move the anti-static carrier loaded with the substrate sample of the LCD logic circuit board into a constant temperature and humidity environment chamber, where the temperature of the environment chamber is controlled within a preset standard temperature range, the relative humidity is maintained within a preset standard humidity range, and the continuous static time reaches a preset equilibrium duration; Specifically, the control logic of the environmental parameters is as follows: Adjust the parameters of the environment chamber through a temperature and humidity linkage controller, where the temperature control accuracy reaches the preset temperature accuracy level, and the humidity control accuracy reaches the preset humidity accuracy level; record the hygroscopic expansion coefficient of the substrate sample of the LCD logic circuit board every preset monitoring period during the static process; when the change amount of the hygroscopic expansion coefficient in three consecutive monitoring periods is less than the preset stability threshold, it is determined that the environmental equilibrium state is reached.

[0031] S130. Use a non-contact laser dust particle counter to scan the surface of the substrate sample of the LCD logic circuit board. When it detects that the particle size exceeds the preset particle threshold or the particle density per unit area exceeds the preset density threshold, an automatic cleaning instruction is triggered. Specifically, after the automatic cleaning instruction is triggered, a collaborative cleaning system composed of an electrostatic eliminator and a negative pressure adsorption device is started. The electrostatic eliminator generates an ion wind beam with a preset frequency, and at the same time, the adsorption head of the negative pressure adsorption device maintains a preset working distance from the surface of the substrate sample of the LCD logic circuit board. The operating rules of the collaborative cleaning system therein include: The coverage range of the ion wind beam and the negative pressure adsorption area form an overlapping area with a preset ratio. Dynamically adjust the negative pressure adsorption intensity according to the particle size distribution, and the corresponding relationship between the adsorption intensity and the particle size satisfies a preset adsorption force curve.

[0032] S140. Use a contact angle measuring instrument to select multiple preset detection sites on the substrate sample of the LCD logic circuit board. When the deionized water contact angle at any detection site exceeds the preset contact angle threshold, plasma surface activation treatment is performed on this site.

[0033] Preferably, the process of plasma surface activation treatment includes: Calculate the plasma treatment power according to the exceeded contact angle value, and the treatment power has a preset positive correlation with the contact angle deviation value. Set a thermal sensitive area around the treatment area, and start spraying cooling gas when the area temperature exceeds the preset temperature limit. Re-detect the contact angle after the activation treatment until all detection sites meet the requirements of the preset contact angle threshold.

[0034] Example 1 Place the substrate sample of the LCD logic circuit board in an anti-static carrier with a surface resistance value maintained at . The contact surface of the anti-static carrier is coated with a cationic anti-static coating, and distributed resistance sensors are embedded in the contact area. When the accumulated amount of static charge exceeds , start the built-in charge discharge circuit of the anti-static carrier.

[0035] Then, move the anti-static carrier into a constant temperature and humidity environmental chamber, and control the temperature at , and the relative humidity at . The temperature and humidity linkage controller records the moisture absorption and expansion coefficient of the substrate sample every 5 minutes. When the change amount of the moisture absorption and expansion coefficient is less than for three consecutive times, it is determined that the environment is balanced.

[0036] Then, use a non-contact laser dust particle counter to scan the substrate surface. If it detects that the particle size is greater than 5 μm or the density is greater than 100 particles / cm 2 , trigger the collaborative cleaning system: The static eliminator generates an ion wind beam of 1.2 kHz, and the coverage area overlaps with the negative pressure adsorption area by 70%; the negative pressure adsorption intensity is adjusted dynamically according to the formula where d is the particle diameter in μm; the adsorption head is 10 mm away from the surface; Finally, select 5 detection sites on the substrate sample of the LCD logic circuit board to measure the deionized water contact angle. If the contact angle at any site is greater than 85°: Calculate the plasma treatment power, and monitor the temperature of the heat-sensitive response area during activation. When the temperature exceeds 60°C, start the argon cooling injection; Repeat the treatment until the contact angle is less than or equal to 85°.

[0037] In a possible implementation, S200 includes the following steps: S210. Obtain the rated working voltage nominal value from the product specification database of the substrate sample of the LCD logic circuit board, and associate it with the dielectric layer thickness distribution map of the substrate sample of the LCD logic circuit board; Preferably, the product specification database is a cloud product specification database; Preferably, obtain the dielectric layer thickness distribution map through a laser thickness gauge, and calculate the thickness variation coefficient , where is the thickness variation coefficient; is the standard deviation of the dielectric layer thickness measurement value, is the average thickness of the dielectric layer thickness measurement value.

[0038] S220. Based on the rated working voltage nominal value and the dielectric layer thickness variation coefficient, generate a basic test voltage through voltage conversion, where the basic test voltage has a negative correlation with the dielectric layer thickness variation coefficient; Preferably, the process of generating the basic test voltage through voltage conversion is as follows: ; where is the rated working voltage nominal value; is a preset basic proportional constant; is the thickness sensitivity coefficient; is the thickness variation coefficient; is the basic test voltage; S230. According to the material type code of the substrate sample of the LCD logic circuit board, retrieve the corresponding voltage increment ratio coefficient and the number threshold of pressurization stages from the preset rule library; among them, the material type code is mapped to the preset material classification matrix; specifically, the matrix includes three categories: epoxy resin substrate, polyimide substrate, and ceramic-filled substrate; S240. Calculate the voltage safety factor by constructing a dielectric thickness - material safety matrix based on the dielectric layer thickness distribution map and the material type code. When the voltage safety factor is less than the preset safety factor threshold, automatically reduce the threshold of the number of pressurization stages; S250. Construct a stepped voltage loading sequence including the threshold of the number of pressurization stages, and verify the sequence continuity through a voltage waveform analyzer.

[0039] Specifically, the voltage value of each stage in the stepped voltage loading sequence is calculated as follows: ; Where is the basic test voltage; is the voltage increment ratio coefficient; is the material attenuation factor; is the voltage value of the th pressurization stage; is the pressurization stage serial number.

[0040] In a possible implementation, S240 includes the following steps: S240.1. Map the minimum dielectric layer thickness of the dielectric layer thickness distribution map to the preset safety reference curve corresponding to the material type code, and construct a dielectric thickness - material safety matrix: where the acquisition method of the preset safety reference curve is: Input the material type code into the preset material safety database for matching query, and output the basic safety parameter group corresponding to the material type code, where the basic safety parameter group includes the reference value of the material dielectric strength, the identification code of the thickness - field strength relationship function, and the material safety correction factor; According to the identification code of the thickness - field strength relationship function, call the corresponding thickness - field strength relationship function from the physical property function library , and this function defines the mapping rule that satisfies the material classification matrix; The specific mapping rule is: The epoxy resin substrate corresponds to the first thickness - field strength relationship function; The polyimide substrate corresponds to the second thickness - field strength relationship function; The ceramic - filled substrate corresponds to the third thickness - field strength relationship function; Based on the basic test voltage and the material safety correction factor, solve the thickness - field strength relationship function through inverse function operation to obtain the theoretical safety thickness; The specific process of solving the thickness - field strength relationship function through inverse function operation to obtain the theoretical safety thickness is as follows: ; Where is the basic test voltage; is the material safety correction factor, is the theoretical safety thickness; where the material safety correction factor is obtained as follows: Analyze the coding structure of the material type code and extract the substrate type identifier; Query according to the substrate type identifier in the preset safety correction coefficient table: The epoxy resin substrate corresponds to the first safety correction factor; The polyimide substrate corresponds to the second safety correction factor; The ceramic-filled substrate corresponds to the third safety correction factor; Take the obtained safety correction factor as the material safety correction factor Write it into the basic safety parameter group.

[0041] Specifically, the thickness-field strength relationship function of each material type is specifically defined as: The first thickness-field strength relationship function of the epoxy resin substrate is ; The second thickness-field strength relationship function of the polyimide substrate is ; The third thickness-field strength relationship function of the ceramic-filled substrate is ; where , , , , , , , , are pre-calibrated material characteristic parameters respectively.

[0042] S240.2. Calculate the voltage safety factor based on the minimum dielectric layer thickness, the theoretical safety thickness, and the material safety correction factor; The corresponding formula is as follows: ; where is the minimum dielectric layer thickness; is the voltage safety factor.

[0043] S240.3. If the voltage safety factor is less than the preset safety factor threshold, adjust the number threshold of the pressurization stage to the preset degradation ratio of the original value.

[0044] Example 2 Retrieve the rated working voltage from the cloud product specification database kV; Use a laser thickness gauge to scan and generate a dielectric layer thickness distribution map, and calculate the thickness coefficient of variation ; Calculate the basic test voltage is approximately 2.1 kV, where is set to 0.85, is set to 0.12; The material type code "EP-425" is mapped to an epoxy resin substrate and retrieved from the rule library: Voltage increment ratio coefficient , the number threshold of pressurization stages .

[0045] Then, calculate the voltage safety factor, and the process is as follows: Minimum dielectric layer thickness ; Match the material safety database, epoxy resin substrate, and its thickness-field strength relationship function , material safety correction factor ; Calculate the theoretical safety thickness ; Voltage safety factor , voltage safety factor is greater than the preset safety factor threshold 1, and the number threshold of pressurization stages .

[0046] Finally, construct the voltage sequence, and the process is as follows: The stage voltage value ; where is the epoxy resin attenuation factor.

[0047] An example of the voltage sequence is shown in Table 1; Table 1 Example of voltage sequence

[0048] In a possible implementation, the arrangement rule of the electrode array in S300 includes: Each pair of electrodes is evenly distributed along the diagonal direction of the substrate sample of the LCD logic circuit board; Preferably, the center distance between adjacent electrode pairs satisfies: ; where represents the minimum spacing and satisfies ; represents the maximum spacing and satisfies; where , are the lengths of the short side and the long side of the substrate sample of the LCD logic circuit board respectively; The electrodes of each pair of electrodes are connected to the substrate sample of the LCD logic circuit board through a conductive adhesive material, and the thickness of the conductive adhesive material after curing is controlled within a preset thickness range.

[0049] Example 3 The process of installing the distributed electrode array is as follows: Arrange 8 pairs of electrodes along the diagonal of the substrate sample, where , ; The center distance between adjacent electrode pairs satisfies ; And perform the following processing on the electrodes: Coat the electrodes with a 10-μm alumina insulating coating; connect to the substrate through silver paste conductive bonding, and the curing thickness is 25 ± 2 μm.

[0050] In a possible implementation, S500 includes the following steps: S510, obtain test parameters and perform multi-dimensional feature extraction; including: Based on the leakage current value between electrodes and the current fluctuation characteristic parameters, obtain the coefficient of variation of current fluctuation; specifically: ; Among them, is the coefficient of variation of current fluctuation; is the standard deviation of the leakage current value, is the average value of the leakage current value.

[0051] Based on the local temperature rise distribution data of the substrate sample of the LCD logic circuit board, extract the maximum temperature rise value and the temperature rise uniformity index; specifically: ; Among them, is the temperature rise uniformity index; is the temperature rise value of the th monitoring point; represents the highest temperature rise value among all monitoring points; represents the lowest temperature rise value among all monitoring points.

[0052] Based on the surface deformation amount of the substrate sample of the LCD logic circuit board, calculate the deformation gradient and the maximum deformation amount; specifically: ; Among them, is the deformation gradient; is the deformation amount of the th monitoring point, is the reference length of the substrate sample of the LCD logic circuit board; represents the maximum deformation amount among all monitoring points; Represents the minimum deformation amount among all monitoring points.

[0053] Identify the coefficient of variation of current fluctuation, maximum temperature rise value, temperature rise uniformity index, deformation gradient, and maximum deformation amount as the eigenvector; S520. Based on the material type code of the substrate sample of the LCD logic circuit board, retrieve the initial weight coefficients from the preset weight rule library; among them, the initial weight coefficients include current weight coefficient, heat weight coefficient, and mechanical weight coefficient, and the material type code is mapped to the preset material classification matrix in S230; Adjust and normalize the initial weight coefficients to obtain the final weight coefficients; S530. Calculate the sub-item failure risk indicators, where the sub-item failure risk indicators include current-related failure risk indicators, heat-related failure risk indicators, and mechanical-related failure risk indicators; including: Based on the coefficient of variation of current fluctuation, obtain the current-related failure risk indicator; The generation process of the current-related failure risk indicator is as follows: ; Among them, Is the current-related failure risk indicator; Is the preset threshold of the coefficient of variation of current fluctuation.

[0054] Based on the maximum temperature rise value and the temperature rise uniformity index, obtain the heat-related failure risk indicator; The generation process of the heat-related failure risk indicator is as follows: ; Among them, Is the heat-related failure risk indicator; And Are the preset proportionality coefficients; Is the maximum temperature rise value; Is the preset allowable temperature rise value; Is the temperature rise uniformity index.

[0055] Based on the deformation gradient and the maximum deformation amount, obtain the mechanical-related failure risk indicator; The generation process of the mechanical-related failure risk indicator is as follows: ; Among them, Is the mechanical-related failure risk indicator; Is the deformation gradient; Preset deformation gradient threshold; Is the maximum deformation amount; Is the preset maximum deformation amount threshold; And Are the preset weight factors; Input the current - related failure risk index, heat - related failure risk index, and mechanical - related failure risk index into the composite failure assessment model to obtain a composite failure risk score; then, generate a voltage withstand stability coefficient based on the composite failure risk score.

[0056] The generation process of the composite failure risk score is as follows: ; where, is the composite failure risk score; is a voltage safety correction function, specifically , where is the voltage safety coefficient, is the safety correction gain coefficient, obtained from the material safety database; The generation process of the voltage withstand stability coefficient is as follows: ; where, is the voltage withstand stability coefficient; is the preset maximum composite failure risk score threshold.

[0057] In a possible implementation, the adjustment and normalization of the initial weight coefficient in S520 to obtain the final weight coefficient include: Dynamically adjust the initial weight coefficient based on the data quality index of the eigenvector; among them, the data quality index includes the signal - to - noise ratio of current data, the spatial resolution score of temperature rise data, and the accuracy score of deformation data; Normalize the adjusted initial weight coefficient to obtain the final weight coefficient.

[0058] It should be noted that the acquisition process of the signal - to - noise ratio of current data, the spatial resolution score of temperature rise data, and the accuracy score of deformation data is to obtain the real - time performance parameters of the high - precision micro - current measurement device, infrared thermal imaging device, and optical deformation detection device in S400 through the device self - test protocol; Specifically, perform a zero - drift test on the high - precision micro - current measurement device to calculate the signal - to - noise ratio of current data; analyze the technical specification of the infrared thermal imaging device to extract the spatial resolution score of temperature rise data; obtain the accuracy score of deformation data through the calibration certificate of the optical deformation detection device; Specifically: the process of adjusting the initial weight coefficient is: For the current weight coefficient, ; where is the current weight coefficient; is the adjusted current weight coefficient; is the preset sensitivity coefficient; is the signal - to - noise ratio of current data; For the thermal weight coefficient, ; where is the thermal weight coefficient; is the adjusted thermal weight coefficient; is the preset sensitivity coefficient; is the temperature rise data spatial resolution score; For the mechanical weight coefficient, ; where is the mechanical weight coefficient; is the adjusted mechanical weight coefficient; is the preset sensitivity coefficient; is the deformation data accuracy score; Normalize the adjusted initial weight coefficient to obtain the final weight coefficient , and .

[0059] Example 4 The coefficient of variation of current fluctuation is approximately 6.7%, and the temperature rise uniformity index is approximately 0.77, and the deformation gradient is 0.0135 μm / mm; Retrieve the initial weights of the epoxy resin substrate: The current weight coefficient ; The thermal weight coefficient ; The mechanical weight coefficient .

[0060] An example of adjusting weights based on device performance is shown in Table 2; Table 2 Example of Adjusting Weights Based on Device Performance

[0061] Normalize the adjusted initial weight coefficient to obtain the final weight coefficient is approximately 0.40, is approximately 0.31, and is approximately 0.29.

[0062] Among the sub-item failure risk indicators: The current-related failure risk indicator , where ; The heat-related failure risk indicator , where , , ; The mechanical-related failure risk indicator , where , , , ; Next, generate a composite failure risk score , where , ; Finally, generate a voltage withstand stability coefficient .

[0063] In a possible implementation, S500 further includes the following steps: S550, verify and output the voltage withstand stability coefficient; including: Perform a range check on the voltage withstand stability coefficient. If the voltage withstand stability coefficient is less than 0 or greater than 100, trigger a data re-acquisition instruction; If the check passes, output the voltage withstand stability coefficient to S600.

[0064] Example 5 Voltage withstand stability coefficient , , check passed.

[0065] In a possible implementation, S600 includes the following steps: S610, receive the voltage withstand stability coefficient and synchronously retrieve the material type code; S620, according to the material type code, retrieve the corresponding grading threshold table from the preset grading rule library, and compare the voltage withstand stability coefficient with the grading threshold table to confirm the voltage withstand performance level.

[0066] Specifically, examples of retrieving the corresponding grading threshold table from the grading rule library are shown in Tables 3, 4, and 5; Example of the grading threshold table for epoxy resin substrates in Table 3

[0067] Example of the grading threshold table for polyimide substrates in Table 4

[0068] Example of the grading threshold table for ceramic-filled substrates in Table 5

[0069] Example 6 Output voltage withstand performance level: qualified.

[0070] This embodiment also discloses a voltage withstand performance detection system for an LCD logic board substrate, including the following modules: Pretreatment module; used to execute S100, including an anti-static carrier unit, an environmental balance unit, a particle cleaning unit, and a surface activation unit; Specifically, the anti-static carrier unit integrates a distributed resistance sensor and a charge discharge circuit, which is used to maintain a preset surface resistance range and control the electrostatic charge accumulation; The environmental balance unit adjusts the parameters of the constant temperature and humidity environmental chamber through a temperature and humidity linkage controller, and monitors the hygroscopic expansion coefficient of the substrate sample of the LCD logic circuit board until the environmental balance state is reached; The particle cleaning unit is a collaborative cleaning system that triggers an electrostatic eliminator and a negative pressure adsorption device by a non-contact laser dust particle counter; The surface activation unit detects multiple preset detection sites through a contact angle measuring instrument and performs plasma surface activation treatment.

[0071] Voltage sequence configuration module; used to execute S200, including a data acquisition unit, a voltage calculation unit, and a sequence verification unit; Specifically, the data acquisition unit extracts the rated operating voltage nominal value from the cloud product specification database, and obtains the thickness distribution map of the dielectric layer through a laser thickness gauge; The voltage calculation unit performs the following operations: Based on the rated operating voltage nominal value and the coefficient of variation of the dielectric layer thickness Generate a basic test voltage ; Retrieve the voltage increment ratio coefficient according to the material type code And the number threshold of pressurization stages; Construct a dielectric thickness - material safety matrix to calculate the voltage safety factor λ, and dynamically adjust the number threshold of pressurization stages; The sequence verification unit verifies the continuity of the stepped voltage loading sequence through a voltage waveform analyzer.

[0072] Electrode array deployment module; used to execute S300, including an electrode arrangement unit and an adhesion control unit; Specifically, the electrode arrangement unit arranges multiple pairs of electrodes at equal intervals in the diagonal direction on the surface of the substrate sample of the LCD logic circuit board, and the center distance between adjacent electrode pairs Satisfies ; The adhesion control unit cures and connects the electrodes and the substrate through a conductive adhesive material, and the thickness is controlled within a preset range.

[0073] Test execution module: used to execute S400, including an integrated high-voltage generator, a parameter monitoring unit, and an equipment coordination unit; Specifically, the high-voltage generator outputs a test voltage to each pair of electrodes according to the stepped voltage loading sequence; The parameter monitoring unit includes: A high-precision micro-current measurement device that real-time collects the leakage current value between electrodes and the characteristic parameters of current fluctuation; An infrared thermal imaging device that obtains the local temperature rise distribution data of the substrate sample of the LCD logic circuit board An optical deformation detection device that detects the surface deformation amount of the substrate sample of the LCD logic circuit board; The device cooperation unit synchronously controls the data collection of each device according to a preset sampling frequency.

[0074] A composite evaluation module; used to execute S500, including a feature extraction unit, a weight optimization unit, a risk calculation unit, and a coefficient generation unit; Specifically, the feature extraction unit calculates the coefficient of variation of current fluctuation from the test parameters , the maximum temperature rise value , the temperature rise uniformity index , the deformation gradient and the maximum deformation amount ; The weight optimization unit retrieves the initial weight coefficient according to the material type code, and dynamically adjusts and normalizes it based on the signal-to-noise ratio of the current data, the spatial resolution score of the temperature rise data, and the accuracy score of the deformation data; The risk calculation unit generates a current-related failure risk index , a heat-related failure risk index and a mechanical-related failure risk index ; The coefficient generation unit outputs a withstand voltage stability coefficient through a composite failure evaluation model , and executes range verification and triggers a re-collection instruction.

[0075] A grading determination module: used to execute S600, including a coefficient receiving unit and a grade mapping unit; Specifically, the coefficient receiving unit obtains the withstand voltage stability coefficient and the material type code; The grade mapping unit retrieves the grading threshold table from the grading rule library and outputs the withstand voltage performance grade by matching.

[0076] This specific embodiment is only an explanation of the present invention, and it is not a limitation of the present invention. Those skilled in the art can make modifications without creative contributions to this embodiment after reading this specification, but as long as they are within the scope of the claims of the present invention, they are protected by the patent law.

Claims

1. A method for detecting the voltage withstand performance of an LCD logic board substrate, characterized in that, It includes the following steps: S100. Pretreat the substrate sample of the LCD logic circuit board; S200. Configure a multi-level stepped voltage loading sequence, including: Generate a stepped voltage loading sequence containing multiple pressurization stages based on the rated operating voltage of the substrate sample of the LCD logic circuit board, where the voltage of the first stage is a proportional voltage of the rated voltage, and the voltage of each subsequent stage increases by a preset ratio. The duration of each stage is set to a preset pressure holding duration; S300. Install a distributed electrode array, including: Arrange multiple groups of electrode pairs on the surface of the substrate sample of the LCD logic circuit board, control the spacing of each group of electrode pairs within a preset tolerance range, and coat the electrodes within each group of electrode pairs with an insulating coating of a preset thickness; S400. Perform a dynamic withstand voltage test, including: Apply a test voltage to each electrode pair according to the stepped voltage loading sequence through a high-voltage generator, and simultaneously monitor and record the test parameters in real time at a preset sampling frequency. Among them, the test parameters include the leakage current value and current fluctuation characteristic parameters between the electrodes, the local temperature rise distribution data of the substrate sample of the LCD logic circuit board, and the surface deformation amount of the substrate sample of the LCD logic circuit board; S500. Construct a composite failure assessment model based on the test parameters and output a withstand voltage stability coefficient; S600. Classify and determine the withstand voltage performance level based on the withstand voltage stability coefficient.

2. The pressure resistance performance detection method of an LCD logic board substrate according to claim 1, characterized in that: The S100 includes the following steps: S110. Place the substrate sample of the LCD logic circuit board in an anti-static carrier, where the surface resistance value of the anti-static carrier is maintained within a preset surface resistance range; at the same time, embed a distributed resistance sensor in the contact area between the anti-static carrier and the substrate sample of the LCD logic circuit board to monitor the electrostatic charge accumulation in real time. When the monitored electrostatic charge accumulation exceeds a preset safety threshold, start the charge discharge circuit built in the carrier; S120. Move the anti-static carrier loaded with the substrate sample of the LCD logic circuit board into a constant temperature and humidity environmental chamber, where the temperature of the environmental chamber is controlled within a preset standard temperature range, and the relative humidity is maintained within a preset standard humidity range, and the continuous standing time reaches a preset equilibrium duration; S130. Use a non-contact laser dust particle counter to scan the surface of the substrate sample of the LCD logic circuit board. When it detects that the particle size exceeds a preset particle threshold or the particle density per unit area exceeds a preset density threshold, trigger an automatic cleaning instruction; S140. Use a contact angle measuring instrument to select multiple preset detection sites on the substrate sample of the LCD logic circuit board. When the deionized water contact angle at any detection site exceeds a preset contact angle threshold, perform plasma surface activation treatment on this site.

3. The pressure resistance performance detection method of an LCD logic board substrate according to claim 1, characterized in that: The S200 includes the following steps: S210. Obtain the rated operating voltage nominal value from the product specification database of the substrate sample of the LCD logic circuit board and associate it with the dielectric layer thickness distribution map of the substrate sample of the LCD logic circuit board; S220. Generate a basic test voltage through voltage conversion based on the nominal value of the rated working voltage and the coefficient of variation of the dielectric layer thickness, where the basic test voltage has a negative correlation with the coefficient of variation of the dielectric layer thickness; S230. Retrieve the corresponding voltage increment ratio coefficient and the number threshold of pressurization stages from a preset rule library according to the material type code of the substrate sample of the LCD logic circuit board; where the material type code is mapped to a preset material classification matrix; S240. Calculate the voltage safety factor by constructing a dielectric thickness - material safety matrix based on the dielectric layer thickness distribution map and the material type code. When the voltage safety factor is less than the preset safety factor threshold, automatically reduce the number threshold of pressurization stages; S250. Construct a stepped voltage loading sequence including the number threshold of pressurization stages and verify the sequence continuity through a voltage waveform analyzer.

4. A method for detecting the voltage resistance performance of a substrate of an LCD logic board according to claim 3, characterized in that: The S240 includes the following steps: S240.

1. Map the minimum dielectric layer thickness of the dielectric layer thickness distribution map to a preset safety reference curve corresponding to the material type code to construct a dielectric thickness - material safety matrix: where the acquisition method of the preset safety reference curve is: Input the material type code into a preset material safety database for matching query, and output a basic safety parameter group corresponding to the material type code, where the basic safety parameter group includes a material dielectric strength reference value, a thickness - field strength relationship function identification code, and a material safety correction factor; Call the corresponding thickness - field strength relationship function from the physical property function library according to the thickness - field strength relationship function identification code, and this function definition satisfies the mapping rules of the material classification matrix; Based on the basic test voltage and the material safety correction factor, solve the thickness - field strength relationship function through inverse function operation to obtain the theoretical safety thickness; S240.

2. Calculate the voltage safety factor based on the minimum dielectric layer thickness, the theoretical safety thickness, and the material safety correction factor; S240.

3. If the voltage safety factor is less than the preset safety factor threshold, adjust the number threshold of pressurization stages to a preset downgrading ratio of the original value.

5. A method for detecting the voltage resistance performance of a substrate of an LCD logic board according to claim 3, characterized in that: In the S300, the arrangement rules of the electrode array include: Each pair of electrodes is evenly distributed along the diagonal direction of the substrate sample of the LCD logic circuit board; The electrodes of each pair of electrodes are connected to the substrate sample of the LCD logic circuit board through a conductive adhesive material, and the thickness of the conductive adhesive material after curing is controlled within a preset thickness range.

6. The pressure resistance performance detection method of an LCD logic board substrate according to claim 1, characterized in that: The S500 includes the following steps: S510. Obtain the test parameters and perform multi - dimensional feature extraction; including: Based on the leakage current value between electrodes and the current fluctuation characteristic parameters, obtain the coefficient of variation of current fluctuation; Based on the local temperature rise distribution data of the substrate sample of the LCD logic circuit board, extract the maximum temperature rise value and the temperature rise uniformity index; Based on the surface deformation amount of the substrate sample of the LCD logic circuit board, calculate the deformation gradient and the maximum deformation amount; Confirm the coefficient of variation of current fluctuation, the maximum temperature rise value, the temperature rise uniformity index, the deformation gradient, and the maximum deformation amount as feature vectors; S520. Retrieve the initial weight coefficients from the preset weight rule library based on the material type code of the substrate sample of the LCD logic circuit board. Among them, the initial weight coefficients include a current weight coefficient, a thermal weight coefficient, and a mechanical weight coefficient, and the material type code is mapped to the preset material classification matrix in S230. Adjust and normalize the initial weight coefficients to obtain the final weight coefficients. S530. Calculate the sub-item failure risk indicators, where the sub-item failure risk indicators include current-related failure risk indicators, heat-related failure risk indicators, and mechanical-related failure risk indicators. It includes: Obtain the current-related failure risk indicators based on the coefficient of variation of current fluctuation. Obtain the heat-related failure risk indicators based on the maximum temperature rise value and the temperature rise uniformity index. Obtain the mechanical-related failure risk indicators based on the deformation gradient and the maximum deformation amount. S540. Input the current-related failure risk indicators, heat-related failure risk indicators, and mechanical-related failure risk indicators into the composite failure assessment model to obtain the composite failure risk score. Then, generate the voltage withstand stability coefficient based on the composite failure risk score.

7. The pressure resistance performance detection method of an LCD logic board substrate according to claim 6, characterized in that: The adjustment and normalization process of the initial weight coefficients in S520 to obtain the final weight coefficients includes: Dynamically adjust the initial weight coefficients based on the data quality indicators of the eigenvectors. Among them, the data quality indicators include the signal-to-noise ratio of current data, the spatial resolution score of temperature rise data, and the accuracy score of deformation data. Normalize the adjusted initial weight coefficients to obtain the final weight coefficients.

8. A method for detecting the voltage resistance performance of a substrate of an LCD logic board according to claim 6, characterized in that: S500 further includes the following steps: S550. Verify and output the voltage withstand stability coefficient. It includes: Perform a range check on the voltage withstand stability coefficient. If the voltage withstand stability coefficient is less than 0 or greater than 100, trigger a data re-acquisition instruction. If the check passes, output the voltage withstand stability coefficient to S600.

9. A method for detecting the voltage withstand performance of a substrate of an LCD logic board according to claim 1, characterized in that: S600 includes the following steps: S610. Receive the voltage withstand stability coefficient and synchronously retrieve the material type code. S620. According to the material type code, retrieve the corresponding grading threshold table from the preset grading rule library, compare the voltage withstand stability coefficient with the grading threshold table, and confirm the voltage withstand performance level.

10. A pressure resistance performance detection system for an LCD logic board substrate, which is applied to the pressure resistance performance detection method of the LCD logic board substrate described in any one of claims 1-9, and is characterized in that, It includes the following modules: Pretreatment module; used to execute S100, including an anti-static carrier unit, an environmental balance unit, a particle cleaning unit, and a surface activation unit. Voltage sequence configuration module; used to execute S200, including a data acquisition unit, a voltage calculation unit, and a sequence verification unit. Electrode array deployment module; used to execute S300, including an electrode arrangement unit and an adhesion control unit. Test execution module: used to execute S400, including an integrated high-voltage generator, a parameter monitoring unit, and an equipment coordination unit. Composite evaluation module; Used to execute S500, including a feature extraction unit, a weight optimization unit, a risk calculation unit, and a coefficient generation unit. Grading determination module: used to execute S600, including a coefficient receiving unit and a grade mapping unit.

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