Co-packaged optical switching module and optical engine networking

Abstract

The invention discloses a co-packaged optical switching module and an optical engine network. The co-packaged optical switching module comprises a photonic integrated chip and an optical switching bare core, and the photonic integrated chip is stacked above the optical switching bare core and is electrically connected with the optical switching bare core. The photonic integrated chip is configured to transmit and receive data in an optical signal mode, and an optical signal transmitting and receiving end of the photonic integrated chip is located on one side far away from the optical switching bare core; the optical switching die is configured to process the data. According to the scheme provided by the invention, intermediate substrates such as a silicon dielectric plate and an adapter plate are canceled, the transmission path is further shortened, the data transmission efficiency is improved, in addition, the signal loss can be remarkably reduced by the tight coupling, and the high-speed signal integrity is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of optical modules, and particularly to a co-packaged optical switching module and an optical engine networking. Background Art

[0002] Optical communication is a communication method that uses light waves as carriers and optical fibers or the atmosphere as transmission media to achieve information transmission. The basic principle of optical communication is to convert an electrical signal into an optical signal, transmit it through a transmission medium, and then convert the optical signal back into an electrical signal at the receiving end. Therefore, optical communication has an extremely high transmission bandwidth and can meet the transmission requirements of a large amount of data. However, there is still a large room for improvement in the volume and transmission rate of existing optical modules used to support optical communication. Summary of the Invention

[0003] The main object of the present invention is to provide a co-packaged optical switching module, which includes a photonic integrated chip and an optical switching die. The photonic integrated chip is stacked above the optical switching die and electrically connected to the optical switching die. The photonic integrated chip is configured to receive and transmit data in the form of optical signals, and the optical signal receiving and transmitting ends of the photonic integrated chip are located on the side far from the optical switching die. The optical switching die is configured to process the data.

[0004] In one embodiment, the photonic integrated chip includes a flip-chip optical receiving array and a flip-chip optical transmitting array. The optical receiving array includes a first metal bonding end and an optical receiving end arranged opposite to each other. The optical transmitting array includes a second metal bonding end and an optical transmitting end arranged opposite to each other. The first metal bonding end and the second metal bonding end are respectively bonded to the optical switching die through a solder bump array.

[0005] In one embodiment, the co-packaged optical switching module further includes: electric chips, including a first electric chip and a second electric chip; The first electric chip is disposed between the optical receiving array and the optical switching die; the second electric chip is disposed between the optical transmitting array and the optical switching die.

[0006] In one embodiment, the electric chip is selected from at least any one of a transimpedance amplifier, a clock recovery unit, a high-speed memory, an electrical driver chip, a modulator driver chip, and a digital signal processing chip.

[0007] In one embodiment, the optical transmitting array includes a plurality of VCSEL units distributed in an array, and the optical receiving array includes a plurality of photodetector units distributed in an array.

[0008] In one embodiment, the co-packaged optical switching module further includes: A coupled fiber optic array, including a first coupled fiber optic array and a second coupled fiber optic array, wherein the first coupled fiber optic array is coupled to the light receiving end of the light receiving array, and the second coupled fiber optic array is coupled to the light emitting end of the light emitting array; and / or The coupled fiber optic array is a multi-core fiber optic array.

[0009] In one embodiment, at least any one of an electrically driven unit, an optically driven unit, a transimpedance amplification unit, a clock recovery unit, a memory unit, a microcontroller, a modulator driving unit, and a digital signal processing unit is integrated in the optical switching die; and / or At least any one of an electrically driven unit, an optically driven unit, a transimpedance amplification unit, a clock recovery unit, a memory unit, a microcontroller, a modulator driving unit, and a digital signal processing unit is integrated in the photonic integrated chip; The devices integrated in the optical switching die are different from or complementary to the devices integrated in the photonic integrated chip.

[0010] In one embodiment, the optical switching die is designed based on the Volta architecture or the Ampere architecture or the Hopper architecture.

[0011] In one embodiment, when the optical switching die is designed based on the Hopper architecture, the optical switching die includes at least two SHARP modules, at least two NVLink modules, and at least one XBAR module.

[0012] In a second aspect, the present application further provides an optical engine network, including a plurality of co-packaged optical switching modules as described in any one of the foregoing, and the co-packaged optical switching modules are optically coupled between any two optical engines.

[0013] The present invention has at least the following beneficial effects: For the co-packaged optical switching module and the optical engine network provided by the present invention, by directly packaging the photonic integrated chip above the optical switching die, the optical signal transceiver end of the photonic integrated chip is perpendicular to the upper surface of the optical switching die, for receiving and transmitting high-speed communication data in the form of optical signals, and the optical switching die is responsible for processing (transmitting, interacting) the high-speed communication data received and transmitted by the photonic integrated chip. Since the intermediate substrate between the traditional optical switching die and the photonic integrated chip is eliminated, the transmission path between data processing and data transceiver is further shortened, and the data transmission efficiency is further improved. In addition, this tight coupling can also significantly reduce signal loss and improve the integrity of high-speed signals. Description of the Drawings

[0014] Figure 1 It is a schematic structural diagram of a co-packaged optical switching module in an embodiment of the present application; Figure 2 Schematic diagram of the co-packaged optical switching module according to another embodiment provided for this application; Figure 3 Schematic diagram of the co-packaged optical switching module according to another embodiment provided for the present invention; Figure 4 Schematic diagram of the optical engine networking structure in an embodiment provided for the present invention; Figure 5 Schematic diagram of the optical engine networking structure in another embodiment provided for the present invention; Figure 6 Schematic diagram of the optical engine networking structure in another embodiment provided for the present invention; Figure 7 Schematic diagram of the module framework of the optical switching bare die provided by the present invention.

[0015] The implementation, functional features, and advantages of the present invention will be further described in conjunction with embodiments and with reference to the accompanying drawings. Detailed implementation manners

[0016] In order to make the objectives, technical solutions, and advantages of this application more clearly understood, the following further describes this application in detail in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not used to limit this application.

[0017] It can be understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, the first client may be referred to as the second client, and similarly, the second client may be referred to as the first client.

[0018] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one of such features. The meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically defined. The meaning of "several" is at least one, such as one, two, etc., unless otherwise specifically defined.

[0019] With the development of the AI industry, "cloud data" companies represented by supercomputer companies and data centers have put forward higher requirements for the bandwidth, rate, and lower energy efficiency of the relay module for optical transmission. Inside the traditional pluggable optical module used in data centers, it is gradually developing towards optical transmitters with higher modulation rates and modulation chips with advanced processes. For short-distance transmission scenarios, the optical engine architectures of LPO (Linear-drive Pluggable Optics) and CPO (Co-Packaged Optics) are introduced. Both of them eliminate the DSP or CDR devices traditionally used for long-distance signal recovery, saving approximately 50% of the module power consumption. In the CPO optoelectronic co-packaging solution, the pluggable connection method between the PCB gold fingers and the switch side is eliminated, and the optical engine and the ASIC chip are co-packaged onto the same substrate to achieve the purpose of increasing the bandwidth on the electrical I / O and optical I / O sides and reducing losses.

[0020] However, taking the relatively mainstream CPO packaging as an example, in its main packaging method, multiple dielectric substrates are required for data signal transfer between the electro-optic chips EIC, PIC, and GPU (such as Organic package, TSMC interposer, PCB). Although this has significantly reduced the signal transmission loss compared to the traditional solution, the signal transmission path will still be increased due to the existence of multiple dielectric substrates, resulting in a certain signal transmission loss.

[0021] Based on this, as Figures 1-6 shown, this application provides a co-packaged optical switching module, aiming to solve the above technical problems, with the expectation of further reducing signal transmission loss and improving data transmission efficiency. As Figure 1As shown, the co-packaged optical switching module may include a photonic integrated chip 10 and an optical switching die 20. The photonic integrated chip 10 is stacked above the optical switching die 20 and electrically connected to the optical switching die 20. The photonic integrated chip 10 is configured to transceive data in the form of optical signals, and the optical signal transceiving end of the photonic integrated chip 10 is located on the side away from the optical switching die 20. The optical switching die 20 is configured to process the data. Specifically, the data transceived by the photonic integrated chip 10 is high-speed communication data, which is modulated and transmitted in the form of optical signals. Compared with the traditional copper wire transmission method, optical signals have a larger transmission bandwidth and transmission speed, and are gradually becoming the mainstream communication method in the future. Optical communication is a technology in which light waves are used as signal carriers and transmitted between two nodes via optical fibers. An optical communication system mainly includes an optical transmitter and an optical receiver. Through an optical transceiver, the received optical signal can be converted into an electrical signal that can be processed by an integrated circuit (IC), or the processed electrical signal can be converted into an optical signal to be transmitted via an optical fiber. Therefore, the purpose of communication can be achieved.

[0022] In one example, the photonic integrated chip 10 of the present application can be stacked above the optical switching die 20 by means of flip-chip bonding. At this time, the optical switching die 20 is electrically connected to the photonic integrated chip 10. Specifically, reference can be continued to Figure 1 The photonic integrated chip 10 may include a flip-chip optical receiving array 110 and a flip-chip optical transmitting array 120. The optical receiving array 110 may include a first metal bonding end (not shown in the figure) and an optical receiving end (not shown in the figure) arranged back to back. The optical transmitting array 120 may include a second metal bonding end (not shown in the figure) and an optical transmitting end (not shown in the figure) arranged back to back. The first metal bonding end and the second metal bonding end are respectively bonded to the optical switching die 20 through a solder ball array (132, 134). That is to say, reference can be additionally made to Figure 2, on the upper surface of the optical switching die 20, there is a bonding area with the photonic integrated chip 10. Compared with the traditional photonic integrated chip that needs to be electrically connected to the optical switching die through a silicon dielectric substrate and a TMSC interposer, this application can not only shorten the signal transmission loss but also save the material costs of the silicon dielectric substrate, TMSC interposer, etc. Depending on the size of the photonic integrated chip 10, the ball grid arrays 132, 134 can be selected as a metal ball grid array (BGA Ball), a bump array, or a micro-bump (μbump) array. It can be understood that both the ball grid arrays 132, 134 are used to achieve electrical connection and mechanical fixation, and are key components to ensure the normal operation of the optical interconnection structure, realize signal transmission, and provide physical support. Among them, the diameter range of the metal balls is usually between 0.25 mm and 0.76 mm, the diameter of the bumps is usually between 100 μm and 150 μm, the size of the micro-bumps is the smallest, usually between a few microns and dozens of microns, and in the smallest case, it can be less than 2 μm. Based on different sizes, the difficulty of the preparation processes of the balls, bumps, and micro-bumps gradually increases. In this specific embodiment, the ball grid arrays 132, 134 are selected as micro-bump arrays.

[0023] Furthermore, to enable the optical signal transceiver ends of the photonic integrated chip 10 to be perpendicular to the upper surface of the optical switching bare die 10. The optical receiving array 110 of the present application may adopt a photodiode (PD), and the number of photodiodes is multiple. The multiple photodiodes are arranged in an array. Exemplarily, the multiple photodiodes may be arranged in a regular hexagon, or a regular quadrilateral, or a regular pentagon. The present application does not limit this. The photosensitive surface of the photodiode is flush with the upper surface of the optical switching bare die 20. The optical emission array 120 may adopt a vertical cavity surface emitting laser (VCSEL), and the number of vertical cavity surface emitting lasers is multiple. The multiple vertical cavity surface emitting lasers are arranged in an array. Each laser includes multiple light emitting channels. The multiple light emitting channels may be arranged in a regular hexagon, or a regular quadrilateral, or a regular pentagon. The present application does not limit this. Further, the present application may adopt 4 vertical cavity surface emitting lasers, and the four vertical cavity surface emitting lasers may be configured to emit lasers with at least four wavelengths. These lasers are modulated to convert N electrical data into optical signals in N optical channels. Optionally, the four wavelengths may be selected from the group of 1270 nm, 1280 nm, 1290 nm, and 1300 nm or the group of 1300 nm, 1310 nm, 1320 nm, and 1330 nm with a smaller channel spacing. Optionally, each wavelength is selected in the range from 1270 nm to 1330 nm to serve as a CWDM channel to support optical signal transmission in high-speed (e.g., 100 Gbit / s or higher) data communication. In other embodiments, a photonic integrated chip 10 with a similar configuration may be formed with more than 4 wavelengths. Optionally, 4 or more wavelengths may be selected to have half the spacing compared to the nominal CWDM channels.

[0024] Vertical cavity surface emitting lasers have advantages such as low power consumption, easy integration, low cost, and high reliability, and are widely used in fields such as optical communication, optical interconnection, and optical sensing. Compared with edge-emitting lasers EEL, they have more unique advantages in the field of optical communication or optical interconnection. For example, more vertical cavity surface emitting lasers can be placed under the same area, thus increasing the signal transmission density.

[0025] In one example, reference may be made to Figures 1-3, the co-packaged optical switching module may further include a coupling fiber array (not shown in the figure), and the coupling fiber array may include a first coupling fiber array 510 and a second coupling fiber array 520. The first coupling fiber array 510 is coupled to the light receiving end of the light receiving array 110, and the second coupling fiber array 520 is coupled to the light emitting end of the light emitting array 120. Further, in order to match the foregoing light receiving array 110 and light emitting array 120, the first coupling fiber array 110 and the second coupling fiber array 120 may be selected as multi-core fiber arrays, and the number of fibers in each fiber array matches the number of devices in the light emitting array 120 or the light receiving array 110. For example, one photodiode is coupled to one fiber, and one vertical cavity surface emitting laser is coupled to one fiber. Using a multi-core fiber array can increase the data transmission density.

[0026] In one example, reference may be made to Figure 3, the co-packaged optical switching module may further include an electrical chip (not shown in the figure), and the electrical chip may include a first electrical chip 310 and a second electrical chip 320; the first electrical chip 310 is disposed between the optical receiving array 110 and the optical switching die 20; the second electrical chip 320 is disposed between the optical transmitting array 120 and the optical switching die 20. Taking the first electrical chip 310 and the optical receiving array 110 as an example, the first electrical chip 310 is disposed below the optical receiving array 110, so that the detection light path of the optical transmitting array 110 will not be blocked, thereby improving the light utilization rate of the optical transmitting array 110, reducing losses, and improving the heat dissipation capacity. Specifically, TSV vias may be formed in the first electrical chip 310, and on the side of the first electrical chip 310 welded to the optical switching die 20, the size of the ball grid array used is larger than the size of the ball grid array used between the first electrical chip 310 and the optical receiving array 110; for example, a bump array is used for welding between the first electrical chip 310 and the optical switching die 20, and a micro-bump array is used for welding between the first electrical chip 310 and the optical receiving array 110. The first electrical chip 310 is used to provide a modulation drive signal. Further, the first electrical chip 310 may be selected from at least any one of a transimpedance amplifier TIA, a clock recovery unit, a high-speed memory HBM, an electrical drive chip, a modulator drive chip, and a digital signal processing chip DSP. For example, the first electrical chip 310 is a traditional EIC chip, and some additional components such as a high-speed memory HBM may also be integrated on the basis of the traditional EIC chip. Taking the traditional EIC chip as an example, a photodiode in the optical receiving array 110 individually detects each optical signal and converts it into a current signal that is transmitted to a transimpedance amplifier (TIA) and processed by the transimpedance amplifier module to generate a voltage signal. The digital signal processing DSP chip is configured to provide the module control and power supply required for operating the co-packaged optical switching module. Optionally, the DSP chip includes a gearbox or retimer chip for converting analog signals into digital signals through N-to-N channel electrical data transmission, a digital processor for processing digital signals, one or more interface devices for communicating with an external electrical host, and a current driver for driving four laser chips.

[0027] Optionally, the modulator drive chip may adopt a PAM-N (N is an integer) modulation protocol or an NRZ modulation protocol to modulate the optical signal.

[0028] In one embodiment, reference may be made to Figure 2 , in order to achieve signal transmission between the optical switching die 20 and the photonic integrated chip 10, at least any one of an electrical drive unit, an optical drive unit, a transimpedance amplification unit, a clock recovery unit, a memory unit, a microcontroller, a modulator drive unit, and a digital signal processing unit is integrated in the optical switching die 20. In Figure 2As shown, unit 1, unit 2, unit 3, unit 4... unit N are integrated in the optical switching die 20. Unit 1 can be optionally a transimpedance amplifier unit, and unit 4 can be optionally a modulator driver unit or an electrical driver unit or an optical driver unit; unit 1 can be optionally a modulator driver unit, unit 3 can be optionally a clock recovery unit CDR, and unit N can be selected and adjusted from the remaining units, such as selecting a digital signal processing unit DSP, or selecting a memory unit, or selecting a microcontroller. The main purpose is to integrate the main functional devices of the original EIC chip in the optical switching die 20, thereby eliminating the intermediate EIC chip link. The microcontroller is connected to a corresponding unit or device and is configured to control the operations of the digital signal processing DSP chip, the modulator driver unit, the transimpedance amplifier TIA, and the interfaces therein.

[0029] In one embodiment, in addition to integrating the main functions of the original EIC chip in the optical switching die 20, the main functional devices of the EIC chip can also be integrated in the photonic integrated chip 10, making the photonic integrated chip 10 different from the traditional PIC chip and becoming an EPIC chip. The EPIC chip can be fabricated based on the CMOS process. Similar to the previous embodiment, at least any one of an electrical driver unit, an optical driver unit, a transimpedance amplifier unit, a clock recovery unit, a memory unit, a microcontroller, a modulator driver unit, and a digital signal processing unit can be integrated in the photonic integrated chip 10.

[0030] Furthermore, in order to better allocate devices and achieve the best transmission efficiency, the devices integrated in the optical switching die 20 and the devices integrated in the photonic integrated chip 10 can be set to be different or complementary. For example, the electrical driver unit, the optical driver unit, the transimpedance amplifier unit, the clock recovery unit, and the modulator driver unit are integrated in the photonic integrated chip 10, and the remaining memory unit, microcontroller, and digital signal processing unit are integrated in the optical switching die 20, and the corresponding electrical connections are achieved. Another example is that the electrical driver unit, the optical driver unit, and the modulator driver unit are integrated in the photonic integrated chip 10, and the remaining transimpedance amplifier unit, clock recovery unit, modulator driver unit, memory unit, microcontroller, and digital signal processing unit are integrated in the optical switching die 20.

[0031] In one example, the optical switching die 20 can be designed based on the Volta architecture or the Ampere architecture or the Hopper architecture.

[0032] Specifically, the optical switch die 20 can be designed based on the Volta architecture. Under this architecture, the optical switch die 20 supports 18 interfaces and can also support the full interconnection of up to 16 optical engine modules (GPUs, graphics processors), enabling efficient data sharing and communication. This architecture is fabricated based on the 12nm FinFET FFN process. This advanced process technology enables the optical switch die 20 to operate at a power of 100W while integrating up to 200 million transistors. In terms of circuit IO and packaging, the optical switch die 20 can be packaged in a large BGA chip, giving it 1940 pins, of which 576 are dedicated to supporting 18 NVLinks. The remaining pins are for power and various I / O interfaces, including x4 PCIe management ports, I2C, GPIO, etc., providing the system with flexible management and expansion capabilities.

[0033] More specifically, the optical switch die 20 can be designed based on the Hopper architecture. Under this architecture, the optical switch die 20 can be fabricated using, for example, TSMC's 4N process, maintaining low power consumption even with a large number of transistors and high bandwidth. It provides 64 NVLink link ports, allowing the construction of complex networks containing a large number of optical engine modules while maintaining high-speed communication between each optical engine module. It also supports a full-duplex bandwidth of 3.2TB / s, significantly improving the data transfer rate and making the parallel processing of large-scale data sets more efficient.

[0034] In terms of signal technology, the Hopper architecture adopts 50 Gbaud PAM4 signal technology, with each differential pair providing a bandwidth of 100Gbps, maintaining the high-speed transmission and low-latency characteristics of the signal.

[0035] In one embodiment, as Figure 7 shown, when the optical switch die 20 is based on the Hopper architecture, the optical switch die 20 includes at least two SHARP modules 20a, at least two NVLink modules 20c, and at least one XBAR module 20b. For example, Figure 7 the two SHARP modules 20a, two XBAR modules 20b, and four NVLink modules 20c in

[0036] Specifically, the SHARP module 20a has powerful data processing capabilities, supports a variety of operators, from logical operations to arithmetic operations, and is compatible with multiple data formats, such as FP16 and BF16, providing strong support for AI and machine learning workloads. The SHARP module 20a can include operations such as all_gather, reduce_scatter, and broadcast atomics, providing hardware acceleration for cluster communication and further enhancing performance.

[0037] The XBAR (crossbar) module 20b, as a highly specialized bridging device, enables data packets to flow and be exchanged between multiple GPUs while presenting itself as a single GPU externally. Through the XBAR (crossbar) module 20b, client applications can perceive and utilize the collective performance of multiple GPUs, reducing the complexity of the client for GPU - to - GPU communication management. The XBAR (crossbar) module 20b utilizes static random - access memory (SRAM) - based buffering technology to achieve non - blocking data transfer. This buffering mechanism ensures the continuity and efficiency of data transfer, maintaining high performance even under high - load conditions. It perfectly matches the data transfer requirements of the SHARP module 20a. This collaborative design ensures high efficiency and low latency in data transfer between the optical engine modules, enhancing the overall performance of the system.

[0038] The NVLink module 20c provides additional security protection for data and chips, preventing unauthorized access and potential data leakage, further enhancing the data security of the system. The introduction of the port partitioning function isolates different ports into separate NVLink modules 20c, providing higher flexibility for the system, allowing for logical segmentation of resources between different networks and optimizing the multitasking ability. The NVLink module 20c also has expandable telemetry capabilities, enabling system administrators to more precisely monitor and optimize network performance to ensure the stable operation of the system. The integrated forward error correction (FEC) technology enhances the reliability of data transfer, especially in the face of signal attenuation or interference, ensuring the integrity and accuracy of data.

[0039] Furthermore, the optical switching die 20 may further include a controller module 20d. The controller module 20d is connected to the aforementioned XBAR module 20b, NVLink module 20c, and SHARP module 20a, and provides support for the next-generation Octal SmallFormfactor Pluggable (OSFP) cable, offering a higher data transmission rate and lower signal attenuation, which is suitable for long-distance high-speed communication. When the controller module 20d is connected to the SHARP module 20a, it is designed to be able to manage up to 128 SHARP modules 20a in parallel, handle numerous tasks simultaneously, and significantly improve the efficiency of data parallel processing, thus successfully completing large-scale data processing tasks.

[0040] It can be understood that the specific architecture design of the optical switching die 20 can be understood with reference to the prior art (such as the architecture design of NVDIA), and this application will not be further restricted or elaborated.

[0041] Furthermore, since the computing power of a single optical engine module is gradually approaching the physical limit, in order to meet the growing computing demands, it has become an inevitable trend for multiple optical engine modules to work collaboratively.

[0042] Based on this, as Figures 4-6 This application also provides an optical engine network, which may include several co-packaged optical switching modules 20 as described above; a co-packaged optical switching module 20 is optically coupled between any two optical engine modules 40a and 40b. Furthermore, as Figure 4 shown, optical fiber arrays can be used between the co-packaged optical switching modules 20 to optically couple the photon integration chips 10 of the co-packaged optical switching modules 20 to the photon integration chips 10 of the optical engine modules 40a and 40b respectively. In this specific embodiment, when connecting the optical engine modules 40a and 40b through an optical fiber array, specifically, the optical emission array 120 in the co-packaged optical switching module 40a is optically coupled to the optical reception array 110 of the optical engine module 40b, while the optical reception array 110 of the co-packaged optical switching module 20 is optically coupled to the optical emission array 110 of the previous optical engine module 40a, and the optical emission array 110 of the optical engine module 40b is optically coupled to the optical reception array 110 of the next co-packaged optical switching module (not shown in the figure), thereby realizing the networking of the co-packaged optical modules.

[0043] Further, the optical engine modules 40a and 40b can be selected from any one of a graphics processing unit (GPU), a customized AI accelerator (XPU), or an application-specific integrated circuit (ASIC) chip. Among them, the customized AI accelerator XPU is not a single chip, but a strategic concept of heterogeneous computing, aiming to address complex computing requirements through a diverse hardware combination. Its essence is "Right Tool for the Right Job", that is, using the most suitable hardware to process specific tasks, thereby improving the overall system efficiency. The customized AI accelerator XPU can be, for example, at least any one of a CPU, an NPU, an FPGA, or an AI accelerator. Exemplarily, XPU can be CPU + GPU + NPU to accelerate the training of large-scale models. The ASIC chip includes a SerDes chip for encoding and decoding data through a DSP interface. Further, when the processor die 20 is an application-specific integrated circuit (ASIC) chip, the application-specific integrated circuit (ASIC) chip can include an integrated modulation driver and a microcontroller. The integrated modulation driver is configured to drive optical signal modulation using pulse amplitude modulation (PAM)-4 format, or pulse amplitude modulation (PAM)-6 format, or pulse amplitude modulation (PAM)-8 format. The microcontroller is configured to control the operation of the integrated modulation driver.

[0044] In one example, as Figure 5 shown, the first electrical chip 310 and the second electrical chip 320 are also provided on the optical engine modules 40a and 40b. The first electrical chip 310 and the second electrical chip 320 are packaged on the optical engine modules 40a and 40b in the same manner as the optical switching die 20. The optical engine modules 40a and 40b adopt the same structural design as the optical switching die 20, which can further reduce data transmission loss and improve data transmission efficiency. In this way, data access and interaction between different optical engine modules can be achieved.

[0045] Even further, as Figure 6 shown, this is another example diagram of the optical engine networking of the present application. In this example, different from Figure 5 the embodiment, the first electrical chip 310 and the second electrical chip 320 are also provided on the optical switching die 20 in this embodiment. This method can also reduce data transmission loss and improve data transmission efficiency.

[0046] In this specific embodiment, different optical engine modules are connected through a co-packaged optical switching module, which allows direct data exchange between different optical engine modules and memory data access between the high-speed storage units (HBM) of different optical engine modules. This design not only reduces the latency of data transmission but also significantly improves the throughput of the entire system.

[0047] The foregoing disclosure provides illustrations and descriptions, but is not intended to be exhaustive of the embodiments or to limit the embodiments to the precise forms disclosed. Modifications and variations may be made in light of the above disclosure, or may be acquired from practice of the embodiments. Additionally, any of the embodiments described herein may be combined, unless the foregoing disclosure expressly provides a reason why one or more of the embodiments may not be combined.

[0048] Even though particular combinations of features are recited in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of the various embodiments. In fact, many of these features may be combined in ways not specifically recited in the claims and / or disclosed in the specification. Although each dependent claim listed below may directly depend on only one claim, the disclosure of the various embodiments includes each dependent claim in combination with every other claim in the claim set. As used herein, the phrase referring to “at least one” of a list of items refers to any combination of those items, including a single member. As an example, “at least one of the following: a, b, or c” is intended to cover a, b, c, a-b, a-c, b-c, and a-b-c, as well as any combination having multiple of the same item.

[0049] When a component or one or more components (e.g., a laser emitter or one or more laser emitters) are described or claimed (within a single claim or across multiple claims) as performing multiple operations or being configured to perform multiple operations, such language is intended to broadly cover a variety of architectures and environments. For example, unless otherwise expressly required (e.g., by using “a first component” and “a second component” or other language that differentiates components in the claims), such language is intended to cover a single component that performs or is configured to perform all of the operations, a group of components that jointly perform or are configured to perform all of the operations, a first component that performs or is configured to perform a first operation and a second component that performs or is configured to perform a second operation, or any combination of components that perform or are configured to perform the operations. For example, when a claim is in the form “one or more components are configured to: perform X; perform Y; and perform Z,” the claim should be interpreted to mean “one or more components are configured to perform X; one or more (possibly different) components are configured to perform Y; and one or more (also possibly different) components are configured to perform Z.”

[0050] The components, acts, or instructions used herein should not be construed as critical or essential unless expressly described as such. Additionally, as used herein, the articles "a" and "an" are intended to include one or more items and may be used interchangeably with "one or more." Further, as used herein, the article "the" is intended to include one or more items referenced in conjunction with the article "the" and may be used interchangeably with "the one or more." Additionally, as used herein, the term "set" is intended to include one or more items (e.g., related items, unrelated items, or a combination of related and unrelated items) and may be used interchangeably with "one or more." In instances where only one item is intended, the phrase "only one" or similar language is used. Additionally, as used herein, the terms "having," "including," "carrying," etc. are intended to be open-ended terms. Further, unless expressly stated otherwise, the phrase "based on" is intended to mean "at least partially based on." Additionally, as used herein, unless expressly stated otherwise (e.g., if used in combination with "any" or "only one of"), the term "or" when used in series is intended to be inclusive and may be used interchangeably with "and / or." Further, for ease of description, spatial relative terms such as "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another (one or more) element or (one or more) feature illustrated in the figures. Except for the orientation depicted in the figures, the spatial relative terms are intended to encompass different orientations of the device, apparatus, and / or element in use or operation. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

Claims

1. A co-packaged optical switching module, characterized in that, It includes a photonic integrated chip and an optical switching die. The photonic integrated chip is stacked above the optical switching die and electrically connected to the optical switching die. The photonic integrated chip is configured to transceive data in the form of optical signals, and the optical signal transceiving end of the photonic integrated chip is located on the side away from the optical switching die. The optical switching die is configured to process the data.

2. The co-packaged optical switching module according to claim 1, wherein The photonic integrated chip includes a flip-chip optical receiving array and a flip-chip optical transmitting array. The optical receiving array includes a first metal bonding end and an optical receiving end arranged back to back, and the optical transmitting array includes a second metal bonding end and an optical transmitting end arranged back to back. The first metal bonding end and the second metal bonding end are respectively bonded to the optical switching die through a solder ball array.

3. The co-packaged optical switching module according to claim 2, wherein, It further includes: electric chips, including a first electric chip and a second electric chip; The first electric chip is disposed between the optical receiving array and the optical switching die; the second electric chip is disposed between the optical transmitting array and the optical switching die.

4. The co-packaged optical switching module according to claim 3, wherein The electric chips are selected from at least any one of a transimpedance amplifier, a clock recovery unit, a high-speed memory, an electrical driving chip, a modulator driving chip, and a digital signal processing chip.

5. The co-packaged optical switching module according to claim 2, wherein, The optical transmitting array includes a plurality of VCSEL units distributed in an array, and the optical receiving array includes a plurality of photodetector units distributed in an array.

6. The co-packaged optical switching module according to claim 2, wherein, It further includes: a coupling optical fiber array, including a first coupling optical fiber array and a second coupling optical fiber array. The first coupling optical fiber array is coupled to the optical receiving end of the optical receiving array, and the second coupling optical fiber array is coupled to the optical transmitting end of the optical transmitting array; and / or The coupling optical fiber array is a multi-core optical fiber array.

7. The co-packaged optical switching module according to claim 1, wherein At least any one of an electrical driving unit, an optical driving unit, a transimpedance amplification unit, a clock recovery unit, a memory unit, a microcontroller, a modulator driving unit, and a digital signal processing unit is integrated in the optical switching die; and / or At least any one of an electrical driving unit, an optical driving unit, a transimpedance amplification unit, a clock recovery unit, a memory unit, a microcontroller, a modulator driving unit, and a digital signal processing unit is integrated in the photonic integrated chip; Moreover, the devices integrated in the optical switching die are different or complementary to the devices integrated in the photonic integrated chip.

8. The co-packaged optical switching module according to claim 1, characterized in that The optical switching die is designed based on the Volta architecture or the Ampere architecture or the Hopper architecture.

9. The co-packaged optical switching module according to claim 8, wherein, When the optical switching die is designed based on the Hopper architecture, the optical switching die includes at least two SHARP modules, at least two NVLink modules, and at least one XBARs module.

10. An optical engine networking, characterized in that, It includes a plurality of co-packaged optical switching modules as described in any one of claims 1-9, and the co-packaged optical switching modules are optically coupled between any two optical engines.

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