A high power-supply rejection ratio low-dropout linear voltage regulator based on gate capacitance cancellation
By introducing a gate capacitor cancellation circuit at the output of the error amplifier, the input-to-output gain is reduced, which solves the problem of decreased power supply rejection capability of LDO at high frequencies and achieves a significant improvement in power supply rejection ratio.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NO 24 RES INST OF CETC
- Filing Date
- 2025-04-15
- Publication Date
- 2026-04-21
AI Technical Summary
Existing low dropout linear regulators (LDOs) have input signals VIN directly coupled to the output through the parasitic capacitance of the power transistor MP at high frequencies, resulting in a decrease in power supply rejection capability.
A gate capacitance cancellation circuit is introduced at the output of the error amplifier to reduce the input-to-output gain and improve power supply rejection capability.
By using a gate capacitor cancellation circuit, the power supply rejection ratio (PSR) was improved. Simulation results show that the PSR was improved by -30dB at 1MHz.
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Figure CN120353288B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of power management chip design technology, and in particular relates to a high power supply rejection ratio and low dropout linear regulator based on gate capacitance cancellation. Background Technology
[0002] With the rapid development of technology, portable electronic devices are becoming increasingly important in daily life and work, driving the diversification of power solutions. Low dropout linear regulators (LDOs), as a common step-down chip, are widely used in small electronic devices, especially in System-on-Chips (SoCs), where LDOs are favored for their excellent noise performance and ease of integration.
[0003] A typical LDO structure is as follows: Figure 4 As shown, it includes, in sequence, a bandgap reference, an error amplifier, a power transistor MP, feedback networks R1 and R2, and a load capacitor C. L Among them, C gsp C gdp C oea These are the equivalent capacitances of the power transistor's gate-source, gate-drain, and output capacitances of the error amplifier, respectively.
[0004] As the frequency increases, the input V IN To output V OUT The transfer function can be calculated as follows:
[0005]
[0006] As can be seen from the above formula, the input signal VIN will be directly coupled to the output through the parasitic capacitance of the power transistor MP, which reduces the power supply rejection capability. Summary of the Invention
[0007] To address the problems existing in the background art, the present invention provides a high power supply rejection ratio and low dropout linear regulator based on gate capacitance cancellation, comprising: an error amplifier and a power transistor M. P Feedback networks R1 and R2, load capacitor C L Frequency compensation capacitor C M and gate capacitance cancellation circuit; the output terminal of the error amplifier, the output terminal of the gate capacitance cancellation circuit, and the power transistor M P The gate and frequency compensation capacitor C M One end is connected; frequency compensation capacitor C M The other end, power transistor M P The drain, one end of resistor R1, and load capacitor C L one end and V OUT Terminal connection; power transistor M P The source terminal VIN Terminal; Load capacitor C L The other end of resistor R1, one end of resistor R2, and ground terminal GND are connected; the other end of resistor R1, the other end of resistor R2, and the non-inverting input terminal V of the error amplifier are connected. FB connect.
[0008] The present invention has at least the following beneficial effects
[0009] This invention reduces the input-to-output gain and improves power supply rejection capability by introducing a gate capacitor cancellation circuit at the output of the error amplifier. Attached Figure Description
[0010] Figure 1 This is a schematic diagram of the overall circuit structure of the present invention;
[0011] Figure 2 This is a schematic diagram of the circuit structure of the gate capacitance cancellation circuit of the present invention;
[0012] Figure 3 A schematic diagram showing the simulation comparison of the PSR curves of an LDO with and without a gate capacitor cancellation circuit.
[0013] Figure 4 This is a schematic diagram of the circuit architecture of a traditional LDO;
[0014] Figure 5 This is a schematic diagram of the high PSR architecture of the low dropout linear regulator of the present invention. Detailed Implementation
[0015] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0016] Please see Figure 1 and Figure 2 This invention provides a high power supply rejection ratio and low dropout linear regulator based on gate capacitance cancellation, comprising: an error amplifier and a power transistor M. P Feedback networks R1 and R2, load capacitor C L Frequency compensation capacitor C M and gate capacitance cancellation circuit; the output terminal of the error amplifier, the output terminal of the gate capacitance cancellation circuit, and the power transistor M PThe gate and frequency compensation capacitor C M One end is connected; frequency compensation capacitor C M The other end, power transistor M P The drain, one end of resistor R1, and load capacitor C L one end and V OUT Terminal connection; power transistor M P The source terminal V IN Terminal; Load capacitor C L The other end of resistor R1, one end of resistor R2, and ground terminal GND are connected; the other end of resistor R1, the other end of resistor R2, and the non-inverting input terminal V of the error amplifier are connected. FB connect.
[0017] Preferably, the gate capacitance cancellation circuit includes a current source I. b1 and I b2 Transistor M C1 ~M C6 and capacitor C C The current source I b1 One end, transistor M C3 The source of the transistor M C4 The source and V IN Terminal connection; transistor M C3 Gate, transistor M C4 Gate, transistor M C3 The drain and transistor M C2 The drain connection; the current source I b1 The other end, capacitor C C One end, transistor M C1 The drain of the transistor M C1 Gate and transistor M C2 Gate connection; the current source I b2 One end, transistor M C5 The drain of the transistor M C5 Gate and transistor M C6 The gate connection; the transistor M C4 The drain of the transistor M C6 Drain and capacitor C C The other end is connected to the output of the gate capacitor cancellation circuit; the transistor M C1 The source of the transistor M C2 The source of the transistor M C5 The source of the transistor M C6 The source terminal and ground terminal GND are connected; the current source I b2 The other end is connected to V IN end.
[0018] Preferably, the transistor MC3 and transistor M C4 It is a P-channel MOS transistor; the transistor M C1 Transistor M C2 Transistor M C5 and transistor M C6 It is an N-channel MOS transistor.
[0019] Preferably, the current source I b1 Equal to current source I b2 .
[0020] Preferably, the transistor M C1 and transistor M C2 A current mirror consisting of a 1:N ratio; the transistor M C5 and transistor M C6 A current mirror consisting of a 1:N ratio; the transistor M C3 and transistor M C6 A 1:1 current mirror is formed; where N = 1 + (C oea +C gdp ) / C C C oea C represents the output equivalent capacitance of the error amplifier; gdp Indicates power transistor M P Gate-drain equivalent capacitance
[0021] Preferably, the error amplifier includes: transistors M1 to M2. 20 Among them, the source of transistor M7, the source of transistor M8, the source of transistor M9, and transistor M... 10 The source of the transistor M 11 The source of the transistor M 12 The source of the transistor M 13 The source of the transistor M 14 The source of the transistor M 15 The source of the transistor M 16 The source and V IN Terminal connection; transistor M 17 The source of the transistor M 19 The source of transistor M5, the source of transistor M6, and transistor M 20 The source of the transistor M 18 The source and ground terminal GND are connected; transistor M 19 Gate bias voltage V b1 Transistor M 15 The drain of the transistor M 17 The drain of the transistor M 17 Gate and transistor M 18 Gate connection; transistor M 15Gate, transistor M 13 Gate, transistor M 13 The drain of the transistor M 19 The drain and transistor M 11 Drain connection; transistor M 11 The gate of transistor M1, the gate of transistor M9, the drain of transistor M9, and the drain of transistor M1 are connected; the gate of transistor M7 is connected to the bias voltage V. b2 The drain of transistor M7, the gate of transistor M5, and the drain of transistor M3 are connected; the gate of transistor M3, the gate of transistor M1, and the non-inverting input V of the error amplifier are connected. FB Connections; the source of transistor M3, the drain of transistor M5, and the source of transistor M2 are connected; the source of transistor M1, the source of transistor M4, and the drain of transistor M6 are connected; transistor M... 10 The drain of the transistor M 10 Gate, transistor M 12 The gate of transistor M1 is connected to the drain of transistor M2; the gate of transistor M8 is connected to the bias voltage V. b2 The drain of transistor M8, the drain of transistor M4, and the gate of transistor M6 are connected; the gates of transistor M2 and M4 are connected to the reference voltage VREF; transistor M... 12 The drain of the transistor M 14 The drain of the transistor M 14 Gate, transistor M 16 Gate and transistor M 20 Drain connection; transistor M 20 Gate bias voltage V b1 Transistor M 16 The drain of the transistor M 18 The drain of the amplifier is connected to the output of the error amplifier.
[0022] Preferably, the transistors M7 to M... 16 These are P-channel MOS transistors; transistors M1 to M6, M... 17 ~M 20 It is an N-channel MOS transistor.
[0023] This embodiment provides a gate capacitance canceled PSR LDO, which sequentially includes a bandgap reference, an error amplifier, and a power transistor M. P Feedback networks R1 and R2, load capacitor C L And gate capacitance cancellation circuit. (See attached diagram) Figure 5 As shown. A gate capacitance cancellation circuit is introduced at the output of the error amplifier to reduce the input-to-output gain and improve power supply rejection. The equivalent capacitance of the gate capacitance cancellation circuit is denoted as C. SCThen the input-to-output transfer function can be calculated as:
[0024]
[0025] Design
[0026] C sc =-(C oea +C gdp )
[0027] The input-to-output transfer function can then be recalculated as follows:
[0028]
[0029] By rationally designing the gate capacitance cancellation circuit, the equivalent capacitance C SC This allows the input-to-output gain to be 0, meaning the output voltage is unaffected by the input voltage, thus improving power supply rejection capability.
[0030] To facilitate understanding of the technical means and creative features of this invention, the invention will be further described in conjunction with the accompanying drawings. The specific circuit diagram of the overall circuit of this invention is shown in the attached diagram. Figure 1 As shown. The entire LDO circuit mainly includes an error amplifier and a power transistor M. P Feedback networks R1 and R2, load capacitor C L Frequency compensation capacitor C M And gate capacitance cancellation circuit. The error amplifier consists of transistor M. 1-20 Composition. The gate capacitance cancellation circuit consists of current source I. b1 I b2 and transistor M C1 ~M C6 and capacitor C C Composition, such as Figure 2 As shown. Figure 2 The equivalent capacitance at point G can be calculated as follows:
[0031] C sc =-(N-1)C C
[0032] Therefore, the design is N = 1 + (C) oea +C gdp ) / C C This allows the input-to-output gain to be 0, meaning the output voltage is unaffected by the input voltage, thus improving power supply rejection capability.
[0033] To verify the rationality of this scheme, the following was performed using a 0.18µm process: Figure 1 The circuit was simulated and verified. The PSR curves of the LDO with and without the gate capacitor cancellation circuit are shown in the attached figure. Figure 3As shown in the figure. Simulation results show that the LDO without gate capacitor cancellation circuit has a PSR of -32dB at 1MHz. The LDO with gate capacitor cancellation circuit can achieve a PSR of -62.4dB at 1MHz, an improvement of -30dB.
[0034] In summary, the present invention provides a high power supply rejection ratio and low dropout linear regulator based on gate capacitance cancellation. By introducing a gate capacitance cancellation circuit at the output of the error amplifier, the input-to-output gain is reduced, thereby improving the power supply rejection capability.
[0035] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.
Claims
1. A high power supply rejection ratio low-dropout linear voltage regulator based on gate capacitance cancellation, characterized in that, Comprising: Error amplifier, power transistor M P Feedback networks R1 and R2, load capacitor C L Frequency compensation capacitor C M and gate capacitance cancellation circuit; the output terminal of the error amplifier, the output terminal of the gate capacitance cancellation circuit, and the power transistor M P Gate and frequency compensation capacitor C M One end is connected; frequency compensation capacitor C M The other end, power transistor M P The drain, one end of resistor R1, and load capacitor C L one end and V OUT Terminal connection; power transistor M P The source terminal V IN Terminal; Load capacitor C L The other end of resistor R1, one end of resistor R2, and ground terminal GND are connected; the other end of resistor R1, the other end of resistor R2, and the non-inverting input terminal V of the error amplifier are connected. FB connect; The gate capacitance cancellation circuit includes a current source I. b1 and I b2 Transistor M C1 ~M C6 and capacitor C C The current source I b1 One end, transistor M C3 The source of the transistor M C4 The source and V IN Terminal connection; transistor M C3 Gate, transistor M C4 Gate, transistor M C3 The drain and transistor M C2 The drain connection; the current source I b1 The other end, capacitor C C One end, transistor M C1 The drain of the transistor M C1 Gate and transistor M C2 Gate connection; the current source I b2 One end, transistor M C5 The drain of the transistor M C5 Gate and transistor M C6 The gate connection; the transistor M C4 The drain of the transistor M C6 Drain and capacitor C C The other end is connected to the output of the gate capacitor cancellation circuit; the transistor M C1 The source of the transistor M C2 The source of the transistor M C5 The source of the transistor M C6 The source terminal and ground terminal GND are connected; the current source I b2 The other end is connected to V IN end; The transistor M C1 and transistor M C2 A current mirror consisting of a 1:N ratio; the transistor M C5 and transistor M C6 A current mirror consisting of a 1:N ratio; the transistor M C3 and transistor M C6 A 1:1 current mirror is formed; where N = 1 + (C oea +C gdp ) / C C C oea C represents the output equivalent capacitance of the error amplifier; gdp Indicates power transistor M P The gate-drain equivalent capacitance.
2. The high power supply rejection ratio low-dropout linear voltage regulator based on gate capacitance cancellation of claim 1, wherein, The transistor M C3 and transistor M C4 It is a P-channel MOS transistor; the transistor M C1 Transistor M C2 Transistor M C5 and transistor M C6 It is an N-channel MOS transistor.
3. The high power supply rejection ratio low-dropout linear voltage regulator based on gate capacitance cancellation of claim 1, wherein, The current source I b1 is equal to the current source I b2 .
4. The high power supply rejection ratio low-dropout linear voltage regulator based on gate capacitance cancellation of claim 1, wherein, The error amplifier includes: transistors M1~M 20 Among them, the source of transistor M7, the source of transistor M8, the source of transistor M9, and transistor M... 10 The source of the transistor M 11 The source of the transistor M 12 The source of the transistor M 13 The source of the transistor M 14 The source of the transistor M 15 The source of the transistor M 16 The source and V IN Terminal connection; transistor M 17 The source of the transistor M 19 The source of transistor M5, the source of transistor M6, and transistor M 20 The source of the transistor M 18 The source and ground terminal GND are connected; transistor M 19 Gate bias voltage V b1 Transistor M 15 The drain of the transistor M 17 The drain of the transistor M 17 Gate and transistor M 18 Gate connection; transistor M 15 Gate, transistor M 13 Gate, transistor M 13 The drain of the transistor M 19 The drain and transistor M 11 Drain connection; transistor M 11 The gate of transistor M1, the gate of transistor M9, the drain of transistor M9, and the drain of transistor M1 are connected; the gate of transistor M7 is connected to the bias voltage V. b2 The drain of transistor M7, the gate of transistor M5, and the drain of transistor M3 are connected; the gate of transistor M3, the gate of transistor M1, and the non-inverting input V of the error amplifier are connected. FB Connections; the source of transistor M3, the drain of transistor M5, and the source of transistor M2 are connected; the source of transistor M1, the source of transistor M4, and the drain of transistor M6 are connected; transistor M... 10 The drain of the transistor M 10 Gate, transistor M 12 The gate of transistor M1 is connected to the drain of transistor M2; the gate of transistor M8 is connected to the bias voltage V. b2 The drain of transistor M8, the drain of transistor M4, and the gate of transistor M6 are connected; the gates of transistor M2 and M4 are connected to the reference voltage VREF; transistor M... 12 The drain of the transistor M 14 The drain of the transistor M 14 Gate, transistor M 16 Gate and transistor M 20 Drain connection; transistor M 20 Gate bias voltage V b1 Transistor M 16 The drain of the transistor M 18 The drain of the amplifier is connected to the output of the error amplifier.
5. The high power supply rejection ratio low-dropout linear voltage regulator based on cancellation of gate capacitance of claim 4, wherein, The transistors M7~M 16 are MOS transistors of P channel; the transistors M1~M6, M 17 ~M 20 are MOS transistors of N channel.