Method for realizing synchronous processing of multi-channel ADC data based on FPGA

Abstract

The present invention relates to a method for synchronously processing multi-channel ADC data based on an FPGA, comprising the following steps: the FPGA receives a clock frequency generated by an external clock generator and uses it as the FPGA's operating clock; the FPGA internally generates multiple sets of same-frequency clocks and same-phase clocks, which serve as the operating clocks for each ADC chip; the FPGA receives sampled data from each ADC, sets an enable signal, and when the enable signal is valid, performs digital down-conversion, decimation filtering, and FIR filtering on each sampled data; after the FIR filtering is completed, generates another enable signal EN_end to further store the data or transmit it to a host computer. The method, device, processor, and computer-readable storage medium for synchronously processing multi-channel ADC data based on the present invention are used to control the synchronous start and stop of the processing flow through the enable signals EN_start and EN_end, thereby ensuring synchronous processing of multi-channel ADC data and improving accuracy and effectiveness, thus having a wide range of applications.

Description

Technical Field

[0001] The present invention relates to the field of digital signal processing, in particular to the field of ADC data synchronization processing, and specifically refers to a method, device, processor and computer-readable storage medium thereof for implementing multi-channel ADC data synchronization processing based on FPGA. Background Art

[0002] In a vector network analyzer system, ADC sampling data is crucial. Multi-port vector network analyzers need to process multiple channels of data simultaneously, utilizing multiple ADC chips. To ensure the accuracy and effectiveness of processed data, synchronization of all ADC sampling data is crucial.

[0003] In existing solutions, a clock generator generates multiple clock signals of the same frequency for multiple ADC chips, each serving as the sampling clock for each chip. However, due to hardware limitations and other factors, this solution can cause phase deviations between the sampling clocks at high clock frequencies, affecting the synchronization of all ADC sampled data. Summary of the Invention

[0004] The purpose of the present invention is to overcome the shortcomings of the above-mentioned prior art and provide a method, device, processor and computer-readable storage medium for realizing synchronous processing of multi-channel ADC data based on FPGA, which meet the requirements of high accuracy, high effectiveness and wide application range.

[0005] To achieve the above objectives, the method, device, processor, and computer-readable storage medium for implementing multi-channel ADC data synchronization based on FPGA of the present invention are as follows:

[0006] The method for realizing synchronous processing of multi-channel ADC data based on FPGA is characterized in that the method comprises the following steps:

[0007] (1) FPGA receives the clock frequency generated by the external clock generator and uses it as the working clock of FPGA;

[0008] (2) Multiple sets of same-frequency clocks and same-phase clocks are generated inside the FPGA, which serve as the working clocks of each ADC chip;

[0009] (3) FPGA receives the sampling data from each ADC and sets an enable signal EN_start. When the enable signal EN_start is valid, the sampling data from each channel is processed by digital down-conversion, decimation filtering and FIR filtering.

[0010] (4) After the FIR filtering is completed, the FPGA generates another enable signal EN_end for the single-channel ADC chip to further store the data or transmit it to the host computer.

[0011] Preferably, the step (3) specifically includes the following steps:

[0012] (3.1) The FPGA receives the sampled data from each ADC and sets an enable signal EN_start. When the enable signal EN_start is valid, the FPGA performs digital down-conversion on each sampled data.

[0013] (3.2) After the digital down-conversion process is completed, the data is decimated and filtered;

[0014] (3.3) After the decimation filtering is completed, the data is filtered through an FIR filter.

[0015] Preferably, the step (4) further includes the following steps:

[0016] (4.1) After the FIR filtering is completed, the FPGA generates an enable signal EN_end 1, EN_end 2, ..., EN_end n-1, EN_end n for each ADC chip, where n is an integer greater than 0. The enable signals of all multiple ADC chips are logically ANDed together to generate a new enable signal EN.

[0017] (4.2) If the enable signal EN is valid, the processed data of each ADC chip will be stored or transmitted to the host computer in the set order.

[0018] Preferably, the operating clock frequencies and phases of the ADC chips are the same, and the sampling data of the ADC chips are in a synchronous state.

[0019] Preferably, the working clock of the ADC chip in step (3) is consistent with the working clock of the FPGA that processes the sampled data of the ADC chip.

[0020] The main features of the device for implementing synchronous processing of multi-channel ADC data based on FPGA are as follows:

[0021] a processor configured to execute computer-executable instructions;

[0022] The memory stores one or more computer-executable instructions. When the computer-executable instructions are executed by the processor, the steps of the method for synchronously processing multi-channel ADC data based on FPGA are implemented.

[0023] The main feature of this processor for implementing synchronous processing of multi-channel ADC data based on FPGA is that the processor is configured to execute computer-executable instructions. When the computer-executable instructions are executed by the processor, the various steps of the above-mentioned method for implementing synchronous processing of multi-channel ADC data based on FPGA are implemented.

[0024] The main feature of the computer-readable storage medium is that a computer program is stored thereon, and the computer program can be executed by a processor to implement the various steps of the above-mentioned method for realizing synchronous processing of multi-channel ADC data based on FPGA.

[0025] The method, device, processor, and computer-readable storage medium thereof for implementing synchronous processing of multi-channel ADC data based on FPGA of the present invention are adopted. By controlling the synchronous start and stop of the processing flow through enable signals EN_start and EN_end, the synchronous processing of multi-channel ADC data is ensured, the accuracy and effectiveness are improved, and the application range is wide. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 The figure is a schematic diagram of a commonly used circuit structure of the method for realizing synchronous processing of multi-channel ADC data based on FPGA of the present invention.

[0027] Figure 2 This is a schematic diagram of the main processing flow of FPGA internal signals in the method for realizing synchronous processing of multi-channel ADC data based on FPGA of the present invention. DETAILED DESCRIPTION

[0028] In order to more clearly describe the technical content of the present invention, further description is given below in conjunction with specific embodiments.

[0029] The method for realizing synchronous processing of multi-channel ADC data based on FPGA of the present invention comprises the following steps:

[0030] (1) FPGA receives the clock frequency generated by the external clock generator and uses it as the working clock of FPGA;

[0031] (2) Multiple sets of same-frequency clocks and same-phase clocks are generated inside the FPGA, which serve as the working clocks of each ADC chip;

[0032] (3) FPGA receives the sampling data from each ADC and sets an enable signal EN_start. When the enable signal EN_start is valid, the sampling data from each channel is processed by digital down-conversion, decimation filtering and FIR filtering.

[0033] (4) After the FIR filtering is completed, the FPGA generates another enable signal EN_end for the single-channel ADC chip to further store the data or transmit it to the host computer.

[0034] As a preferred embodiment of the present invention, the step (3) specifically includes the following steps:

[0035] (3.1) The FPGA receives the sampled data from each ADC and sets an enable signal EN_start. When the enable signal EN_start is valid, the FPGA performs digital down-conversion on each sampled data.

[0036] (3.2) After the digital down-conversion process is completed, the data is decimated and filtered;

[0037] (3.3) After the decimation filtering is completed, the data is filtered through an FIR filter.

[0038] As a preferred embodiment of the present invention, the step (4) further includes the following steps:

[0039] (4.1) After the FIR filtering is completed, the FPGA generates an enable signal EN_end 1, EN_end 2, ..., EN_end n-1, EN_end n for each ADC chip, where n is an integer greater than 0. The enable signals of all multiple ADC chips are logically ANDed together to generate a new enable signal EN.

[0040] (4.2) If the enable signal EN is valid, the processed data of each ADC chip will be stored or transmitted to the host computer in the set order.

[0041] As a preferred embodiment of the present invention, the operating clock frequencies and phases of the ADC chips are the same and the phases are consistent, and the sampling data of the ADC chips are in a synchronous state.

[0042] As a preferred embodiment of the present invention, the working clock of the ADC chip in step (3) is consistent with the working clock of the FPGA that processes the sampled data of the ADC chip.

[0043] The device for implementing multi-channel ADC data synchronization processing based on FPGA of the present invention comprises:

[0044] a processor configured to execute computer-executable instructions;

[0045] The memory stores one or more computer-executable instructions. When the computer-executable instructions are executed by the processor, the steps of the method for synchronously processing multi-channel ADC data based on FPGA are implemented.

[0046] The processor for implementing synchronous processing of multi-channel ADC data based on FPGA of the present invention is configured to execute computer-executable instructions. When the computer-executable instructions are executed by the processor, the steps of the above-mentioned method for implementing synchronous processing of multi-channel ADC data based on FPGA are implemented.

[0047] The computer-readable storage medium of the present invention stores a computer program thereon, and the computer program can be executed by a processor to implement the various steps of the above-mentioned method for synchronously processing multi-channel ADC data based on FPGA.

[0048] In view of the limitations and inaccuracies of the above existing solutions, the present invention proposes a multi-channel ADC data synchronization processing method based on FPGA, comprising the following steps:

[0049] Step 1: The external clock generator generates a stable clock frequency that meets the requirements as the FPGA's working clock.

[0050] Step 2: Generate multiple sets of same-frequency and same-phase clocks CLK1, CLK2, ..., CLKn-1, and CLKn within the FPGA, which serve as the working clocks of each ADC chip.

[0051] Step 3: Because the operating clock frequency and phase of each ADC chip are identical, the sampled data from each ADC—DATA 1, DATA 2, ..., DATA n-1, DATA n—is also synchronized. The FPGA receives the sampled data from each ADC and sets an enable signal, EN_start, before processing. When EN_start is active, the FPGA performs digital down-conversion on each sampled data channel. The main purpose of digital down-conversion is to convert high-frequency signals into low-frequency baseband signals, multiply the input signal with the quadrature local oscillator signal generated by the local oscillator (NCO), and filter out high-frequency components generated by the mixing.

[0052] Step 4: After the digital down-conversion process is complete, the data is subjected to decimation filtering. Decimation filtering is widely used in digital down-conversion processing systems. It can not only further filter the digital down-converted signal, but also reduce the amount of data by downsampling through decimation.

[0053] Step 5: After the decimation filter is complete, continue to perform FIR filtering on the data. FIR filtering refers to filtering through an FIR filter. FIR filter is the abbreviation of non-recursive filter, also known as finite length unit impulse response filter. FIR filter with constant coefficients is a LTI (linear time invariant) digital filter. The relationship between the FIR output of length N and the input time series x(n) is given by a finite convolution sum form, as follows:

[0054] ;

[0055] Among them, y(k) is the output signal at the kth moment, N is the filter order, a(n) is the nth coefficient of the filter, there are N coefficients in total, and x(kn) is the input signal at the knth moment, that is, delayed by n sampling points.

[0056] It is important to note that the clock used to perform the above operations on each channel of sampled data must be consistent with the working clock of the ADC chip. The clock used to perform the above operations on each channel of sampled data refers to the multiple groups of same-frequency and same-phase clocks CLK1, CLK2, ..., CLKn-1, CLKn generated by the FPGA in step 2.

[0057] Step 6: After the FIR filter is completed, another enable signal EN_end is generated, indicating that the above series of processing processes are completed. The relevant data can be further stored or transmitted to the host computer. The relevant data here includes the calculated and converted amplitude and phase values.

[0058] Step 7: In the above steps 3 to 6, only the series of operations of sampling data of a single ADC are described. For multi-channel ADCs, an enable signal EN_end will be generated for each channel.

[0059] (7.1) Before further storing or transmitting the relevant data to the host computer, a logical AND operation is performed on the enable signals EN_end 1, EN_end 2, ..., EN_end n-1, EN_end n of all paths to obtain a new enable signal EN, which serves as the enable valid bit for subsequent operations.

[0060] (7.2) When the enable signal EN is valid, the processed data will be stored or transmitted to the host computer in the set order.

[0061] The FPGA of the present invention generates multiple groups of clocks with the same frequency and phase, which serve as the working clocks of each ADC chip respectively. The FPGA needs to constrain each clock to ensure that the delay paths of each clock are consistent, so that each ADC chip can work simultaneously.

[0062] In a specific embodiment of the present invention, Figure 1 As shown, an external clock generator generates a stable, consistent clock frequency, which is connected to the FPGA's clock pins as the FPGA's operating clock. The FPGA internally generates multiple clocks with the same frequency and phase, which are connected to the clock pins of each ADC chip as their operating clocks. Of course, the power supply and driver circuits required for the external clock generator and FPGA operation are also essential, but they are omitted as they are not relevant to this case study. After each ADC chip is operating normally, it outputs sampled data and transmits it to the FPGA.

[0063] like Figure 2 As shown, the FPGA receives sampled data from each ADC and sets an enable signal, EN_start, before processing. When the enable signal is asserted, subsequent processing, including digital down-conversion, decimation filtering, and FIR filtering, is performed on each channel of sampled data. It is important to note that the clock used for performing the relevant operations on each channel of sampled data must be consistent with the operating clock of the corresponding ADC chip. After the FIR filtering is completed, the FPGA generates another enable signal, EN_end, indicating the end of the aforementioned series of processing and that the relevant data can be further stored or transmitted to the host computer. The above steps describe the series of operations on sampled data from a single ADC. For multiple ADCs, each channel generates an enable signal, EN_end. Before the relevant data is further stored or transmitted to the host computer, a logical AND operation is performed on the enable signals, EN_end1, EN_end2, ..., EN_endn-1, EN_endn, generated by all channels, to obtain the final enable signal, EN, which serves as the enable valid bit for subsequent operations. When the enable signal is asserted, the relevant data is stored or transmitted to the host computer in the predefined order.

[0064] FPGAs can generate multiple output clocks simultaneously, each of which can be output simultaneously. By setting each output clock to the same frequency and phase, the operating clocks remain consistent. Before each clock is output to the ADC chips, the FPGA internally constrains each clock to ensure consistent delay paths. This ensures that each ADC chip receives the clock signal simultaneously and operates properly. When each ADC chip starts operating at the same time and at the same frequency, the sampled data it outputs is synchronized.

[0065] In this specification, ADC stands for Analog to Digital Converter (ADC). FIR stands for Finite Impulse Response (FIR). FPGA stands for Field Programmable Gate Array (FPGA).

[0066] The specific implementation scheme of this embodiment can be found in the relevant descriptions in the above embodiments and will not be repeated here.

[0067] It can be understood that the same or similar parts of the above embodiments can be referenced to each other, and the contents not described in detail in some embodiments can refer to the same or similar contents in other embodiments.

[0068] It should be noted that, in the description of the present invention, the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, the meaning of "plurality" is at least two.

[0069] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code comprising one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present invention includes alternative implementations in which functions may be performed out of the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present invention pertain.

[0070] It should be understood that various components of the present invention may be implemented using hardware, software, firmware, or a combination thereof. In the aforementioned embodiments, multiple steps or methods may be implemented using software or firmware stored in a memory and executed by a suitable instruction execution device. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof may be used: a discrete logic circuit having logic gate circuits for implementing logic functions on data signals, an application-specific integrated circuit having suitable combinational logic gate circuits, a programmable gate array (PGA), a field-programmable gate array (FPGA), etc.

[0071] Those skilled in the art will understand that all or part of the steps in the method for implementing the above-mentioned embodiment can be completed by instructing related hardware through a program, and the corresponding program can be stored in a computer-readable storage medium. When the program is executed, it includes one of the steps of the method embodiment or a combination thereof.

[0072] Furthermore, the functional units in the various embodiments of the present invention may be integrated into a single processing module, each unit may exist physically separately, or two or more units may be integrated into a single module. The aforementioned integrated modules may be implemented in the form of hardware or software functional modules. If the integrated modules are implemented in the form of software functional modules and sold or used as independent products, they may also be stored in a computer-readable storage medium.

[0073] The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0074] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0075] The method, device, processor, and computer-readable storage medium thereof for implementing synchronous processing of multi-channel ADC data based on FPGA of the present invention are adopted. By controlling the synchronous start and stop of the processing flow through enable signals EN_start and EN_end, the synchronous processing of multi-channel ADC data is ensured, the accuracy and effectiveness are improved, and the application range is wide.

[0076] In this specification, the present invention has been described with reference to specific embodiments thereof. However, it will be apparent that various modifications and variations may be made without departing from the spirit and scope of the present invention. Accordingly, the specification and drawings are to be regarded as illustrative rather than restrictive.

Claims

1. A method for realizing synchronous processing of multi-channel ADC data based on FPGA, characterized in that: The method comprises the following steps: (1) FPGA receives the clock frequency generated by the external clock generator and uses it as the working clock of FPGA; (2) Multiple sets of same-frequency clocks and same-phase clocks are generated inside the FPGA, which serve as the working clocks of each ADC chip; (3) FPGA receives the sampling data from each ADC and sets an enable signal EN_start. When the enable signal EN_start is valid, the sampling data from each channel is processed by digital down-conversion, decimation filtering and FIR filtering. (4) After the FIR filtering is completed, the FPGA generates another enable signal EN_end for the single-channel ADC chip to further store the data or transmit it to the host computer.

2. The method for realizing multi-channel ADC data synchronization processing based on FPGA according to claim 1, characterized in that: The step (3) specifically includes the following steps: (3.1) The FPGA receives the sampled data from each ADC and sets an enable signal EN_start. When the enable signal EN_start is valid, the FPGA performs digital down-conversion on each sampled data. (3.2) After the digital down-conversion process is completed, the data is decimated and filtered; (3.3) After the decimation filtering is completed, the data is filtered through an FIR filter.

3. The method for realizing multi-channel ADC data synchronization processing based on FPGA according to claim 1, characterized in that: Said step (4) further comprises the following steps: (4.1) After the FIR filtering is completed, the FPGA generates an enable signal EN_end 1, EN_end 2, ..., EN_end n-1, EN_end n for each ADC chip, where n is an integer greater than 0. The enable signals of all multiple ADC chips are logically ANDed together to generate a new enable signal EN. (4.2) If the enable signal EN is valid, the processed data of each ADC chip will be stored or transmitted to the host computer in the set order.

4. The method for realizing multi-channel ADC data synchronization processing based on FPGA according to claim 1, characterized in that: The operating clock frequencies and phases of the ADC chips are the same and consistent, and the sampling data of the ADC chips are in a synchronous state.

5. The method for realizing multi-channel ADC data synchronization processing based on FPGA according to claim 1, characterized in that: The working clock of the ADC chip in step (3) is consistent with the working clock of the FPGA that processes the sampled data of the ADC chip.

6. A device for realizing synchronous processing of multi-channel ADC data based on FPGA, characterized in that: The device comprises: a processor configured to execute computer-executable instructions; A memory storing one or more computer-executable instructions, wherein when the computer-executable instructions are executed by the processor, each step of the method for synchronously processing multi-channel ADC data based on FPGA according to any one of claims 1 to 5 is implemented.

7. A processor for realizing synchronous processing of multi-channel ADC data based on FPGA, characterized in that: The processor is configured to execute computer-executable instructions. When the computer-executable instructions are executed by the processor, the steps of the method for realizing synchronous processing of multi-channel ADC data based on FPGA as described in any one of claims 1 to 5 are implemented.

8. A computer-readable storage medium, characterized in that A computer program is stored thereon, and the computer program can be executed by a processor to implement the various steps of the method for realizing synchronous processing of multi-channel ADC data based on FPGA according to any one of claims 1 to 5.

Images