Memory device and management method thereof
By setting the time length and batch processing operations, the problem of unfixed effective page and invalid page ratio in the memory device is solved, and stable data transfer speed and processing efficiency are achieved.
Patent Information
- Application Number
- CN202410202275.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-01-22
- Filing Date
- 2024-02-23
- Publication Date
- 2025-07-22
AI Technical Summary
During the data transfer process of existing memory devices, the ratio of valid pages and invalid pages is not fixed, resulting in varying processing time and unstable processing speed.
By setting the time length, multiple processing operations are performed in batches, and valid pages in memory blocks are found and moved to the cache database, ensuring that each processing operation takes the same time.
The stable processing speed of memory devices during data transfer is realized, and the efficiency and consistency of data management are improved.
Smart Images
Figure CN120353569A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a memory device and a management method thereof, and particularly to a memory device and a management method thereof regarding the data transfer speed. Background Art
[0002] In common knowledge, a memory device has multiple data pages, and the data pages can be divided into valid pages and invalid pages. A known memory device performs data migration in batches and processes a fixed number of data pages each time. The disadvantage of common knowledge is that although the memory device processes a fixed number of data pages each time, the ratio of valid pages to invalid pages in the data pages processed each time is not fixed, and the time for processing valid pages is much longer than that for processing invalid pages. This results in different lengths of time spent for each migration, and thus the processing speed of the memory device is unstable. Summary of the Invention
[0003] The present invention is directed to a memory device and a management method thereof, which can stabilize the processing speed of the memory device during data migration.
[0004] The management method of the present invention includes: setting a time length; based on the time length, performing a plurality of processing operations on a memory block; in each processing operation, finding valid pages among the plurality of data pages of the memory block; and migrating the data of the valid pages to a cache database.
[0005] The memory device of the present invention includes a memory block and a controller. The memory block includes a plurality of data pages. The controller is coupled to the memory block. And the controller is configured to set a time length, perform a plurality of processing operations on the memory block based on the time length, find valid pages among the plurality of data pages of the memory block in each processing operation, and migrate the data of the valid pages to a cache database.
[0006] Based on the above, the memory device of the present invention batches the migration of valid pages in the storage block by a plurality of processing operations, and uniformly sets the time length required for performing the plurality of processing operations to a fixed value, so that the memory device has a more stable processing speed when detecting whether a data page is a valid page and migrating the valid page to the cache database. To make the above features and advantages of the present invention more obvious and understandable, specific embodiments are given below and are described in detail in conjunction with the accompanying drawings as follows. Brief Description of the Drawings
[0007] The accompanying drawings are included to provide a further understanding of the present invention, and are incorporated into and constitute a part of this specification. The drawings illustrate embodiments of the present invention and, together with the description, are used to explain the principles of the present invention.
[0008] Figure 1 is a circuit schematic diagram of a memory device according to an embodiment of the present invention;
[0009] Figure 2 is Figure 1 a schematic diagram of the data page arrangement of the memory block of
[0010] Figure 3 is a circuit schematic diagram of a memory device according to an embodiment of the present invention;
[0011] Figure 4 is a flowchart of a management method for a memory device according to an embodiment of the present invention. Detailed Embodiments
[0012] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component symbols are used in the drawings and the description to denote the same or similar parts.
[0013] Figure 1 shows a circuit schematic diagram of a memory device according to an embodiment of the present invention. The memory device 100 includes a memory block MB, a controller CTR, and a cache database CDB. In this embodiment, the memory block MB may be a non-volatile memory block, such as a flash memory block.
[0014] In this embodiment, the memory block MB has a plurality of data pages PG1 to PGn, where n is an integer greater than 1. Each of the data pages PG1 to PGn may be a valid page or an invalid page. Among them, the data stored in the so-called valid page is valid data (i.e., data that is still in demand), and the data stored in the so-called invalid page is invalid data (data that is no longer in demand and can be discarded). In the embodiments of the present invention, the valid pages and invalid pages among the data pages PG1 to PGn may be scattered in the memory block MB. That is, the physical address arrangement of the valid pages and invalid pages may not have a specific pattern.
[0015] In this embodiment, the controller CTR is coupled to the memory block MB. When performing data management operations on the memory block MB, the controller CTR may preset a time length TL in advance. The controller CTR may perform a plurality of processing operations on the data pages PG1 to PGn of the memory block MB based on the time length TL. Among them, the time required for the controller CTR to execute each processing operation is a time length TL. When the controller CTR executes each processing operation, within the time length TL, in accordance with the arrangement order of the physical addresses of the data pages PG1 to PGn, it sequentially checks whether a plurality of data pages among the data pages PG1 to PGn are valid pages. After finding one or more valid pages among them, the controller CTR may move the data in the above valid pages to the cache database CDB.
[0016] Regarding the implementation details of the inspection operation for valid pages and invalid pages for each data page PG1 to PGn, during the normal access process of the memory device 100 by the controller CTR, it can record whether each data page PG1 to PGn is a valid page or an invalid page. Taking the data page PG1 as an example, when the controller CTR determines that the data page PG1 is an invalid page, it can write a first indication flag at a specific address of the data page PG1, and use the first indication flag to mark the data page PG1 as an invalid page. In contrast, when the controller CTR determines that the data page PG1 is a valid page, it can write a second indication flag at the same specific address of the data page PG1, and use the second indication flag to mark the data page PG1 as a valid page.
[0017] Therefore, it can be known that when the controller CTR performs the inspection operation to determine whether each data page PG1 to PGn is a valid page or an invalid page, by reading the first indication flag or the second indication flag stored at the specific address of each data page PG1 to PGn, it can quickly know whether each data page PG1 to PGn is a valid page or an invalid page.
[0018] In this embodiment, the first indication flag and the second indication flag can be data of one bit or multiple bits. Taking the first indication flag and the second indication flag as data of one bit as an example, the first indication flag and the second indication flag can have complementary logical values.
[0019] Based on the operation mode of this embodiment, each processing operation can consume the same amount of time, and further make the data management operation of the memory executed by the memory device 100 have a relatively stable processing speed.
[0020] It is worth mentioning that the cache database CDB can be a cache database of a single-level storage unit, or any data storage medium available for data caching, without specific limitations.
[0021] Figure 2 Show Figure 1 A schematic diagram of the data page arrangement in the memory block. In this embodiment, the arrangement of valid pages and invalid pages in the memory block MB has no pattern. The controller CTR can perform multiple processing operations PO_1 to PO_x on the data pages PG1 to PGn in the memory block MB, where x is an integer greater than 1.
[0022] When performing the processing operation PO_1, the controller CTR can detect whether the data page PG1 is a valid page. If the data page PG1 is a valid page, the controller CTR can move the data of the data page PG1 to the cache database CDB and compare whether the time for the controller CTR to process the data page PG1 is greater than the time length TL.
[0023] If the time for the controller CTR to process the data page PG1 is not greater than the time length TL, the controller CTR can continue to detect whether the data page PG2 is a valid page. If the data page PG2 is an invalid page, the controller CTR can refrain from performing any processing on the data page PG2 and compare whether the time for the controller CTR to process the data pages PG1 to PG2 is greater than the time length TL.
[0024] And so on, the controller CTR can sequentially process multiple data pages in the memory block MB one by one and move the data in the valid pages among them to the database CDB. When the time for the controller CTR to cumulatively execute data processing starts to be not less than the time length TL, this processing operation PO_1 can be ended. In this embodiment, in the processing operation PO_1, the controller CTR completes the processing actions for the data pages PG1 to PG7, and the number of data pages processed is 7. Taking the data pages PG1, PG3, PG4, PG5, PG7 as valid pages as an example, the number of valid pages among them is 5.
[0025] In this embodiment, in the processing operation PO_2, the controller CTR completes the processing actions for the data pages PG8 to PG17, and the number of data pages processed is 10. Taking the data pages PG8, PG9, PG13, PG16, PG17 as valid pages as an example, the number of valid pages among them is 5.
[0026] Since the implementation details of the processing operations PO_3 to PO_x are similar to those of the processing operations PO_1 and PO_2, no further elaboration will be provided here. It is worth mentioning that after the processing operation PO_x ends, the controller CTR can complete the processing of the data page PGn. And after the processing operation PO_x ends, the storage device 100 can erase the data of each data page in the data pages PG1 to PGn.
[0027] In Figure 2 each of the processing operations PO_1 to PO_x, the time length is substantially equal to the time length TL. Among them, in each of the processing operations PO_1 to PO_x, there may be a slight time difference due to the number of data transfer operations.
[0028] In addition, in the processing operation PO_1, the number of data pages processed by the memory device 100 is 7, and the number of valid pages among them is 5. In the processing operation PO_2, the number of data pages processed by the memory device 100 is 10, and the number of valid pages among them is 5. In the processing operation PO_3, the number of data pages processed by the memory device 100 is 12, and the number of valid pages among them is 4.
[0029] In this embodiment, the controller CTR can calculate the time length TL. The calculation method of the time length TL is the quotient obtained by dividing the preset total duration by the number x of the processing operations PO_1 to PO_x.
[0030] In this embodiment, the calculation method of the preset total duration is the sum of the product of the preset valid page value and the valid page processing duration plus the product of the preset invalid page value and the invalid page processing duration.
[0031] For example, if the total number of data pages is 3072 pages and the number of valid pages is 1541 pages, then the number of invalid pages is 1531 pages. Also, assuming that the processing duration of a valid page is 1.1377 milliseconds and the processing duration of an invalid page is set to 0.1897 milliseconds, the preset total processing duration can be 2043 milliseconds (1541×1.1376 + 1531×0.1897 = 2043).
[0032] If the number x of processing operations PO_1 to PO_x is 341, the time length TL can be set to 6 milliseconds (2043÷341 = 6), that is, the time for the controller CTR to perform each processing operation is 6 milliseconds.
[0033] Of course, regarding the quantity values of the number of data pages and the related time lengths in the above examples, they are only illustrative examples and are not used to limit the scope of implementation of the present invention. And regarding the quantity values of the number of data pages and the related time lengths in the above examples, they can be set according to the characteristics of the memory device and the actual working requirements, without any specific limitations.
[0034] In this embodiment, the preset valid page value can be the number of valid pages in the data pages PG1 to PGn when the controller CTR executes the previous round of processing operations PO_1 to PO_x. The preset invalid page value can be the difference between the total number of pages n in the data pages PG1 to PGn and the valid pages when the controller CTR executes the previous round of processing operations PO_1 to PO_x. The valid page processing duration is the time consumed by the controller CTR to detect whether a data page is a valid page and move the data page from the memory block MB to the cache database CDB. The invalid page processing duration is the time consumed by the controller CTR to detect whether a data page is an invalid page.
[0035] Figure 3 A circuit schematic diagram of a memory device showing an embodiment of the present invention. The memory device 300 includes a memory block MB, a controller CTR, a cache database CDB, and a mapping table MPT. The circuit characteristics and operation modes of the memory block MB, the controller CTR, and the cache database CDB of the memory device 400 are the same as those of the memory device 100 in Figure 1 、 Figure 2 's embodiment. Different from the foregoing embodiment, the memory device 400 further has a mapping table MPT. The mapping table MPT is coupled to the controller CTR. The mapping table MPT is used to record the mapping relationship between a plurality of logical addresses and a plurality of physical addresses in the memory device.
[0036] When the memory device 400 executes processing operations PO_1 to PO_x, any one of the data pages PG1 to PGn is detected as a valid page by the controller CTR, and the stored data in each of the data pages PG1 to PGn that are valid pages can be moved from the memory device to the cache database CDB. Correspondingly, the content of the mapping table MPT can also be adjusted accordingly. For example, in the original state, the mapping table MPT records a first physical address of the data page PG1 whose first logical address is mapped to the memory block MB. When the data page PG1 is a valid page, the data content of the data page PG1 can be moved to a cache data page with a second physical address in the cache database CDB. Then, the controller CTR can change the first logical address in the mapping table MPT to be mapped to the second physical address.
[0037] Figure 4 A flowchart of a management method for a memory device according to an embodiment of the present invention is shown. In step S402, this embodiment provides a memory device having at least one storage block and sets a time length. In step S404, the memory device can execute a plurality of processing operations on the memory block based on the time length. In step S406, the memory device can detect a plurality of data pages of the memory block and detect whether the plurality of data pages are valid pages. In step S408, the memory device can move the data of the valid pages to a cache database.
[0038] Regarding the implementation details of the above steps, detailed descriptions have been provided in the foregoing multiple embodiments, and thus will not be elaborated herein.
[0039] In summary, the memory device of the present invention batches the movement of valid pages in the storage block by a plurality of processing operations and sets a time length to uniformly execute the time required for the plurality of processing operations, so that the memory device of the present invention has a more stable processing speed when detecting whether the data pages are valid pages and moving the valid pages to the cache database.
[0040] Although the present invention has been disclosed as above with embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope defined by the claims.
[0041] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A management method for a memory device, comprising: Setting a time length; Performing a plurality of processing operations on a memory block based on the time length; Finding at least one valid page among a plurality of data pages of the memory block during the plurality of processing operations; And Moving data of the at least one valid page to a cache database.
2. The management method according to claim 1, further comprising: Providing a preset valid page value and a preset invalid page value; Providing a valid page processing duration and an invalid page processing duration; And Calculating a preset total duration according to the preset valid page value, the preset invalid page value, the valid page processing duration, and the invalid page processing duration.
3. The management method according to claim 2, wherein the time length is a quotient obtained by dividing the preset total duration by the number of executions of the plurality of processing operations.
4. The management method according to claim 1, further comprising: Erasing the plurality of data pages after performing the plurality of processing operations.
5. The management method according to claim 1, wherein moving data of the at least one valid page to the cache database further comprises: Adjusting storage address data of the at least one valid page recorded in a mapping table.
6. A memory device, comprising: A memory block including a plurality of data pages; And A controller coupled to the memory block for: Setting a time length; Performing a plurality of processing operations on the memory block based on the time length; Finding at least one valid page in the memory block during the plurality of processing operations; And Moving data of the at least one valid page to a cache database.
7. The memory device according to claim 6, wherein the controller calculates a preset total duration according to a preset valid page value, a preset invalid page value, a valid page processing duration, and an invalid page processing duration.
8. The memory device according to claim 7, wherein the time length is a quotient obtained by dividing the preset total duration by the number of executions of the plurality of processing operations.
9. The memory device according to claim 6, wherein the controller erases the plurality of data pages after performing the plurality of processing operations.
10. The memory device according to claim 6, further comprising: A mapping table for recording a mapping relationship between a plurality of physical addresses and a plurality of logical addresses of the plurality of data pages.