RISC-based data storage system and method, integrated circuit

Abstract

The present invention provides a RISC-based data storage system, method, and integrated circuit, comprising: a local module generating local data; a user module being a hard-core module of RISC that generates user data; an asynchronous module converting the clock domain of the user data to the clock domain of the local data; an arbitration module receiving local data using an APP interface and receiving user data after clock domain conversion using an AHB interface, and converting the received local data and user data into APP data; a control module converting the APP data into timing signals for DDR particles; and DDR particles receiving and storing data carried by the timing signals. By using DDR particles as storage media, using the AHB interface corresponding to the RISC-based user module as a data transmission interface, and converting the AHB interface into the APP interface of the DDR protocol through the arbitration module, the high-speed, high-performance characteristics of DDR and AHB can be fully utilized, achieving high-speed data interaction between RISC-based and DDR, and solving the problem of how to achieve high-speed data storage based on a RISC-based microcontroller.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits and data storage, and in particular to a data storage system and method based on RISC-V and an integrated circuit. Background Art

[0002] With the rapid growth of the Internet of Things (IoT), an increasing number of devices require microcontrollers. ARM, as a leading microcontroller manufacturer, controls the vast majority of the market. However, since ARM controllers are supplied to the market through IP licensing, high licensing fees are incurred, leading to high controller costs.

[0003] To address the high costs associated with using ARM controllers, the University of California, Berkeley, proposed a reduced instruction set (RISC-V) core. Compared to ARM, RISC-V offers a more compact design, facilitating rapid product iteration in IoT designs and making it suitable for a wider range of small-scale controller applications.

[0004] With the development of RISC-based microcontrollers, the performance and frequency of RISC-based microcontrollers have become increasingly powerful. However, existing technologies generally use Flash memory chips for data storage. Flash memory chips are generally slow and cannot meet the high-speed data exchange requirements of RISC-based microcontrollers, limiting the application of RISC-based microcontrollers in data storage. Summary of the Invention

[0005] The object of the present invention is to provide a data storage system and method based on RISC-V and an integrated circuit to solve the problem of how to achieve high-speed data storage based on a RISC-V microcontroller.

[0006] To solve the above technical problems, the present invention provides a data storage system based on RISC-V, comprising:

[0007] Local module, used to generate local data;

[0008] User module is a hard-core module of RISCV, used to generate user data;

[0009] an asynchronous module, configured to convert a clock domain of the user data to a clock domain of the local data;

[0010] an arbitration module, configured to receive local data generated by the local module using an APP interface, further configured to receive user data after clock domain conversion output by the asynchronous module using an AHB interface, and to convert the received local data and user data into APP data;

[0011] A control module, configured to convert the APP data output by the arbitration module into a timing signal of a DDR particle;

[0012] The DDR particles are used to receive the timing signal output by the control module and store the data carried by the timing signal.

[0013] Optionally, in the RISCV-based data storage system, the arbitration module includes a data pre-judgment unit, a channel state machine, a data conversion unit, and a data selection unit;

[0014] The data pre-judgment unit is used to determine whether the user data contains a user instruction from RISCV according to a preset detection rule, and generate a flag signal and a write enable signal;

[0015] The channel state machine is used to switch to a write state according to a write enable signal, and in the write state, send user data to the data conversion unit;

[0016] The data conversion unit is used to convert user data into APP data;

[0017] The data selection unit is used to switch the connected channel according to the flag signal to transmit user data or local data in APP data format to the control module.

[0018] Optionally, in the RISCV-based data storage system, the user data includes a clock signal, an address signal, a data signal, a burst signal, a data selection signal, a data preparation signal, a transmission status signal, a transmission bit width signal and a data read / write signal; the preset detection rules include: when the data selection signal is valid, the data read / write signal is a write signal, the transmission status signal is in an idle state, and the data preparation signal is valid, it is determined that the user module has generated user data to be cached.

[0019] Optionally, in the RISCV-based data storage system, the channel state machine has a judgment state, a write state, and a read state, and the channel state machine defaults to the judgment state; in the judgment state, the channel state machine determines whether a write enable signal is received, and switches the state to the write state when it determines that a write enable signal is received.

[0020] Optionally, in the RISCV-based data storage system, the data conversion unit includes a command parsing subunit, an address cache subunit and a data cache subunit;

[0021] The command parsing subunit is used to parse user data to extract a write storage address signal, a write data signal, and a write control signal; and is also used to send the write storage address signal, the write data signal, and the write control signal to the data selection unit in an APP data format;

[0022] The address cache subunit is used to cache write storage address signals;

[0023] The data cache subunit is used to cache write data signals.

[0024] Optionally, in the RISCV-based data storage system, the data pre-judgment unit is further configured to generate a read enable signal and a read control signal;

[0025] The channel state machine is further configured to switch to a read state according to a read enable signal, and in the read state, send a read control signal to the data conversion unit;

[0026] The data conversion unit is further configured to receive the interface preparation signal generated by the control module, and parse the read control signal and the interface preparation signal to generate a read instruction;

[0027] The data selection unit is further configured to send a read instruction to the control module to read the corresponding data stored in the DDR particles; and is further configured to switch the connected channel according to the flag signal to transmit the read data to the data conversion unit;

[0028] The data conversion unit is further configured to convert the data read by the data selection unit into AHB data, and output the data to the user module through the channel state machine and the data pre-judgment unit.

[0029] To solve the above technical problems, the present invention further provides a RISC-based data storage method, which is applied to the RISC-based data storage system as described in any one of the above items, and the data storage method includes:

[0030] determining whether a flag signal is generated;

[0031] If the flag signal is generated, the user data generated by the user module is obtained according to the write enable signal, and the user data is converted into APP data; otherwise, the local data generated by the local module is obtained;

[0032] Convert user data or local data in APP data format into timing signals of DDR particles;

[0033] The DDR particles receive the timing signal and store the data carried by the timing signal.

[0034] Optionally, in the RISCV-based data storage method, the data storage method further comprises:

[0035] If the flag signal is generated, the read control signal and the interface preparation signal are parsed according to the read enable signal to generate a read instruction;

[0036] Read the corresponding data stored in the DDR particles according to the read instruction;

[0037] Convert the read data into AHB data and output it to the user module.

[0038] Optionally, in the RISCV-based data storage method, the data storage method further comprises:

[0039] By default, local data generated by the local module is transmitted to DDR particles.

[0040] Optionally, in the RISC-based data storage method, the user data generated by the user module is transmitted in bursts using burst signals; the user data includes a write storage address signal and a write data signal; and the method for converting the user data into APP data includes:

[0041] After receiving the write enable signal, receive and cache the write storage address signal;

[0042] After waiting for one clock cycle, a write data signal corresponding to the write storage address signal is received and cached; wherein, after continuously acquiring all data under the burst signal, all data are spliced ​​into a parallel data, and the parallel data is cached.

[0043] In order to solve the above technical problems, the present invention further provides an integrated circuit, comprising the RISC-based data storage system as described in any one of the above items.

[0044] Optionally, in the integrated circuit, the integrated circuit is implemented based on FPGA.

[0045] The present invention provides a data storage system and method based on RISC-V, and an integrated circuit, comprising: a local module for generating local data; a user module, which is a hard-core module of RISC-V, for generating user data; an asynchronous module for converting the clock domain of the user data to the clock domain of the local data; an arbitration module for receiving the local data generated by the local module using an APP interface, and for receiving the user data output by the asynchronous module after clock domain conversion using an AHB interface, and for converting the received local data and user data into APP data; a control module for converting the APP data output by the arbitration module into a timing signal for a DDR particle; and a DDR particle for receiving the timing signal output by the control module and storing the data carried by the timing signal. By using DDR particles as storage media, using the AHB interface corresponding to the RISC-V user module as a data transmission interface, and converting the AHB interface into the APP interface of the DDR protocol through the arbitration module, the high-speed and high-performance characteristics of DDR and AHB can be fully utilized, realizing high-speed data interaction between RISC-V and DDR. At the same time, the arbitration module can retain the original APP interface, thereby being compatible with different data transmission methods, solving the problem of how to achieve high-speed data storage based on a RISC-V microcontroller. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 A structural block diagram of the RISC-based data storage system provided in this embodiment;

[0047] Figure 2 A schematic diagram of the structure of the arbitration module provided in this embodiment;

[0048] Figure 3 A flowchart of the data storage method based on the write direction of RISC-V provided in this embodiment;

[0049] Figure 4 This is a flowchart of the data storage method based on the read direction of RISC-V provided in this embodiment. DETAILED DESCRIPTION

[0050] The following, in conjunction with the accompanying drawings and specific embodiments, further details the RISC-based data storage system, method, and integrated circuit proposed in the present invention. It should be noted that the drawings are all in a very simplified form and are not accurately scaled, and are only used to conveniently and clearly assist in illustrating the purpose of the embodiments of the present invention. Furthermore, the structures shown in the drawings are often portions of the actual structures. In particular, different drawings may require different emphasis and may sometimes use different scales.

[0051] It should be noted that the terms "first", "second", etc. in the specification, claims, and accompanying drawings of the present invention are used to distinguish similar objects in order to describe the embodiments of the present invention, and are not used to describe a specific order or sequence. It should be understood that the structures used in this way can be interchanged under appropriate circumstances. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or are inherent to these processes, methods, products, or apparatuses.

[0052] To clearly illustrate the implementation of the transceiver delay calibration system and method provided in this embodiment, the technical terms involved in this embodiment are explained as follows:

[0053] FPGA: Field Programmable Gate Array, field programmable gate array;

[0054] DDR SDRAM: Double Data Rate Synchronous Dynamic Random Access Memory, double data rate synchronous dynamic random access memory, referred to as DDR;

[0055] MC: Memory Controller;

[0056] PHY: Physical Layer, physical layer;

[0057] FIFO: First Input First Output, first in first out;

[0058] RAM: Random Access Memory, random access memory;

[0059] CMD:Command, command;

[0060] ARM processor: Advanced RISC Machine, is a low-power, low-cost RISC microprocessor designed by Acorn Ltd. in the UK. The ARM processor itself is a 32-bit design, but it also has a 16-bit instruction set. Generally speaking, it saves up to 35% of the equivalent 32-bit code while retaining all the advantages of a 32-bit system.

[0061] RISC-V: RISC-V instruction set architecture is an open instruction set architecture (ISA) based on the principles of Reduced Instruction Set Computing (RISC). As an open-source standard, RISC-V allows any individual or organization to freely use, modify, and extend it without paying patent fees. Its design goal is to provide a simple, scalable, and flexible instruction set suitable for a wide range of applications, from microcontrollers to high-performance computing.

[0062] AMBA: Advanced Micro-controller Bus Architecture, advanced microcontroller bus architecture;

[0063] AXI: Advanced eXtensible Interface, advanced extensible interface;

[0064] APB: Advanced Peripheral Bus, advanced peripheral bus;

[0065] AHB: Advanced High Performance Bus, advanced high performance bus;

[0066] APP interface: also known as API (Application Programming Interface), application programming interface.

[0067] This embodiment provides a data storage system based on RISC-V. Figure 1 Shown, including:

[0068] Local module, used to generate local data;

[0069] User module is a hard-core module of RISCV, used to generate user data;

[0070] an asynchronous module, configured to convert a clock domain of the user data to a clock domain of the local data;

[0071] an arbitration module, configured to receive local data generated by the local module using an APP interface, further configured to receive user data after clock domain conversion output by the asynchronous module using an AHB interface, and to convert the received local data and user data into APP data;

[0072] A control module, configured to convert the APP data output by the arbitration module into a timing signal of a DDR particle;

[0073] The DDR particles are used to receive the timing signal output by the control module and store the data carried by the timing signal.

[0074] The data storage system based on RISC-V provided in this embodiment uses DDR particles as storage media, uses the AHB interface corresponding to the RISC-V user module as a data transmission interface, and converts the AHB interface and the APP interface of the DDR protocol through an arbitration module. This can fully utilize the high-speed and high-performance characteristics of DDR and AHB, and realize high-speed data interaction between RISC-V and DDR. At the same time, the arbitration module can retain the original APP interface, thereby being compatible with different data transmission methods, and solving the problem of how to achieve high-speed data storage based on the RISC-V microcontroller.

[0075] Specifically, in this embodiment, the local module uses a data source generation module of a NATIVE interface, and the data format of its output is defined as an app name. In actual applications, the local module can be developed based on FPGA.

[0076] Furthermore, in this embodiment, the user module is a hard-core module of RISC-V. In practical applications, user modules can also be developed based on FPGAs. Typically, RISC-V is implemented using registers and wiring resources within the FPGA, but this approach results in a low frequency and slow data transmission speed. Preferably, in this embodiment, the user module can be implemented using an integrated hard-core RISC-V, ensuring that the core frequency and external interface frequency of RISC-V can reach 300 MHz, thereby effectively improving data transmission efficiency.

[0077] In this embodiment, considering that the core frequency and external interface frequency of the user module are relatively high, the AHB module can be used as the data interaction interface, thereby effectively utilizing the high bandwidth and data burst function of the AHB. This is not only more suitable for the DDR storage interface, but also uses fewer resources than the AXI interface.

[0078] In practical applications, since AHB adopts burst data transmission mode, and the data before the control module are all parallel data, the characteristics of the AHB and APP buses can be utilized to use the burst data transmission of AHB to form a group of DDR storage data, thereby achieving efficient data transmission.

[0079] For example, when the bit width of a DDR chip is 16, and the control module uses a 1:4 clock ratio (transmitting 4 data points per rising clock edge), considering DDR's dual-edge sampling capability, one clock can actually transmit 8 data points, or 128 bits. In this case, the AHB can be set to a 16-bit data channel width and a burst size of 8 data points. This ensures that the bandwidth of the two different buses is fully matched, maximizing utilization efficiency.

[0080] Furthermore, in this embodiment, the asynchronous module can also be developed based on an FPGA. Specifically, the asynchronous module's input and output interfaces all use AHB, and the asynchronous module uses a first-in-first-out (FIFO) to convert input and output data into clock domains. This ensures that the frequency of user data matches the frequency of the arbitration module, ensuring the reliability of the data arbitration results.

[0081] Furthermore, in this embodiment, the control module can also be developed based on an FPGA or directly implemented using the internal resources of the FPGA. For example, the control module can be a DDR physical layer (DDR PHY). The main function of the control module is to convert the APP data signal output by the arbitration module into the timing signal of the DDR particle.

[0082] And, in this embodiment, the arbitration module is a key module for realizing data channel switching between the local module and the user module, and interface conversion between local data and user data. Figure 2 As shown, the arbitration module includes a data pre-judgment unit, a channel state machine, a data conversion unit, and a data selection unit. Furthermore, the signals for the user module AHB data write direction include a clock signal HCLK, an address signal HADDR, a data signal HWDATA, a burst signal HBURST, a data selection signal HSEL, a data ready signal HREADY, a transmission status signal HTRANS, a transmission bit width signal HSIZE, and a data read / write signal HWRITE. A high level on the data read / write signal HWRITE indicates writing, while a low level indicates reading.

[0083] The data pre-judgment unit is used to determine whether the user data contains a user instruction from RISCV according to a preset detection rule, and to generate a flag signal and a write enable signal.

[0084] Specifically, in this embodiment, the preset detection rule includes: when the data select signal HSEL is valid, the data read / write signal HWRITE is a write signal (high level), the transmission status signal HTRANS is in the idle state, and the data ready signal HREADY is valid (high level), it is determined that the user module has generated user data to be cached, and a write enable signal wen is generated. A high level for both the data select signal HSEL and the data read / write signal HWRITE indicates a write command, and a high level for the data ready signal HREADY indicates that the storage end allows data writing. If the data ready signal HREADY is low, it is necessary to wait for storage space to become free before continuing to write data. In actual applications, when the write enable signal wen is generated, a write storage address signal waddr and a write data signal wdata are also generated accordingly.

[0085] At the same time, after determining that the user module has generated user data to be cached, the data pre-judgment unit will also generate a flag signal flag, which is used to start the data selection unit so that the data selection unit gives channel priority to the data channel after AHB conversion of the user module.

[0086] Furthermore, the channel state machine is used to switch to a write state according to a write enable signal, and in the write state, send user data to the data conversion unit.

[0087] Specifically, the write enable signal wen, write storage address signal waddr, write data signal wdata and other user data generated by the data pre-judgment unit are input to the channel state machine, and the channel state machine outputs the write storage address signal waddr and write data signal wdata and other user data to the data conversion unit.

[0088] In actual applications, the channel state machine has a judgment state, a write state, and a read state. The channel state machine defaults to the judgment state. In the judgment state, the channel state machine determines whether a write enable signal wen has been received. If it is determined that the write enable signal has been received, the state is switched to the write state, thereby enabling the transmission of user data in the write direction. Similarly, if it is determined that a read enable signal ren has been received, the state is switched to the read state, thereby reading the data in the data conversion unit to the data pre-judgment unit in the read direction.

[0089] Furthermore, the data conversion unit is used to convert user data into APP data.

[0090] Specifically, such as Figure 2 As shown, the data conversion unit includes a command parsing subunit, an address caching subunit, and a data caching subunit. The command parsing subunit is used to parse user data to extract a write memory address signal, a write data signal, and a write control signal; it is also used to send the write memory address signal, the write data signal, and the write control signal to the data selection unit in the APP data format; the address caching subunit is used to cache the write memory address signal; and the data caching subunit is used to cache the write data signal.

[0091] In this embodiment, after the data conversion unit converts the AHB user data, it outputs the command signal cmd, the address signal addr and the data signal data to the data selection unit. Among them, since the AHB adopts the method of delaying the read and write commands and addresses by one beat to transmit burst data, after the data conversion unit receives the user data, it is necessary to write the address information in the write storage address signal into the address cache subunit and wait for one beat, and then obtain the corresponding write data signal. After continuously obtaining 8 data of the burst signal HBURST, the 8 groups of data are spliced ​​into a 128-bit parallel data and written into the data cache subunit, so that the data of the AHB is consistent with the data bit width of the DDR interface and can be directly connected. The command parsing subunit parses the read and write instructions generated by the channel state machine and sends them together to the data selection module. In this way, the complete connection between the AHB interface and the local APP interface is achieved.

[0092] In addition, due to the read and write delay of DDR itself, it is impossible to obtain all the user's read and write data at one time. In this embodiment, a signal app_ready indicating whether the data is idle is also provided in the APP interface of the control module. This signal has the same function as the HREADY signal of AHB and can be directly connected to realize the interconnection of the read and write data idle information.

[0093] Furthermore, the data selection unit is used to switch the connected channel according to the flag signal to transmit the user data or local data in the APP data format to the control module.

[0094] Specifically, when the flag signal is active (high), it indicates that the RISCV user module is ready to read or write DDR data. The data selection unit waits until the previous instruction is executed before switching the channel to the AHB channel to read or write user data. If the flag signal is inactive (low), it indicates that user data reading and writing has stopped. The data selection unit then switches the data channel to the local data module channel.

[0095] The RISC-based data storage system provided in this embodiment can not only write user data of the user module into the DDR particles at high speed, but also read data in the DDR particles to the user module at high speed.

[0096] Specifically, the data pre-judgment unit is also used to generate a read enable signal and a read control signal; the channel state machine is also used to switch to a read state according to the read enable signal, and in the read state, send a read control signal to the data conversion unit; the data conversion unit is also used to receive an interface preparation signal generated by the control module, and parse the read control signal and the interface preparation signal to generate a read instruction; the data selection unit is also used to send a read instruction to the control module to read the corresponding data stored in the DDR particles; it is also used to switch the connected channel according to the flag signal to transmit the read data to the data conversion unit; the data conversion unit is also used to convert the data read by the data selection unit into AHB data, and output it to the user module through the channel state machine and the data pre-judgment unit.

[0097] The RISC-based data storage system provided in this embodiment uses an AHB interface as a DDR storage conversion interface, which not only reduces resource usage and improves performance, but also can utilize the AHB's back pressure function (HREADY) to communicate with the local interface's app_ready signal to implement a read-write wait function and ensure the continuity of data transmission. It can also utilize the AHB's burst function to perform burst storage on data in advance and transmit it after splicing it into a group of DDR data bit widths, thereby effectively utilizing the bit width of the entire transmission channel and improving working bandwidth and efficiency.

[0098] The RISCV-based data storage system provided in this embodiment uses an arbitration module to adapt to external interfaces such as RISCV user modules while retaining the original local direct control interface, thereby achieving switching between different interfaces and being compatible with different data transmission modes.

[0099] This embodiment also provides a RISC-based data storage method, which is applied to the RISC-based data storage system as described above. Figure 3 As shown, the data storage method includes:

[0100] S11, judging whether a flag signal flag is generated.

[0101] Specifically, in this embodiment, the data selection unit in the arbitration module determines whether the data prediction unit generates a flag signal flag.

[0102] S12, if the flag signal is generated, obtaining the user data generated by the user module according to the write enable signal, and converting the user data into APP data; otherwise, obtaining the local data generated by the local module.

[0103] During a write operation, when the flag signal "flag" is generated, it indicates that the user module needs to write data to the DDR chip. Therefore, the user module will send the generated user data to the arbitration module. The data pre-judgment unit in the arbitration module generates a write enable signal "wen" based on the preset detection rules, and inputs the user data, such as the write storage address signal "waddr" and the write data signal "wdata", into the channel state machine. The channel state machine then outputs the user data, such as the write storage address signal "waddr" and the write data signal "wdata", to the data conversion unit, which completes the data conversion and obtains the APP data. At this time, the APP data packet contains the command signal "cmd", the address signal "addr", and the data signal "data".

[0104] Among them, since AHB adopts the method of delaying the read and write commands and addresses by one beat to transmit burst data, after receiving the write enable signal wen, it receives and caches the write storage address signal waddr; after waiting for one clock cycle, it receives the write data signal wdata corresponding to the write storage address signal and caches it. After continuously acquiring all the data under the burst signal HBURST, all the data are spliced ​​into a parallel data, and the parallel data is cached.

[0105] If the flag signal flag is not generated, it indicates that the user module does not need to write data to the DDR particle at this time, and the default channel state is maintained, that is, the local data generated by the local module is transmitted to the DDR particle by default.

[0106] S13, converting the user data or local data in the APP data format into a timing signal of the DDR particle.

[0107] Specifically, after converting the AHB user data, the data conversion unit outputs the command signal cmd, the address signal addr and the data signal data to the data selection unit. The data selection unit sends these signals to the control module via the APP interface, and the control module generates timing signals based on these signals.

[0108] S14, the DDR particle receives the timing signal and stores the data carried by the timing signal.

[0109] The above method is a data storage method when the user module performs a write operation on the DDR particle. The following describes a data storage method when the user module performs a read operation on the DDR particle. Figure 4 As shown, the data storage method further includes:

[0110] S21, judging whether a flag signal is generated.

[0111] Specifically, in this embodiment, the data selection unit in the arbitration module determines whether the data prediction unit generates a flag signal flag.

[0112] S22: If the flag signal is generated, the read control signal and the interface preparation signal are analyzed according to the read enable signal to generate a read instruction.

[0113] During a read operation, when the flag signal "flag" is generated, indicating that the user module needs to read data from the DDR particles, the silt layer user module will send the corresponding read operation instruction in the form of user data to the arbitration module. The data pre-judgment unit in the arbitration module generates a read enable signal "ren" based on preset detection rules and inputs user data such as the read control signal and the interface ready signal into the channel state machine. The channel state machine then outputs the read control signal, the interface ready signal and other user data to the data conversion unit, which completes the data conversion and obtains the APP data, i.e., the read instruction. At this time, the APP data mainly includes the command signal "cmd" and the address signal "addr".

[0114] If the flag signal flag is not generated, it indicates that the user module does not need to read data from the DDR particles at this time, and the default channel state is maintained, that is, the local module reads data from the DDR particles by default.

[0115] S23, reading the corresponding data stored in the DDR particles according to the read instruction.

[0116] Specifically, the data conversion unit outputs the read instruction to the data selection unit, and the data selection unit sends the read instruction to the control module via the APP interface. The control module reads the corresponding data from the DDR particles according to the read instruction.

[0117] S24, converting the read data into AHB data and outputting it to the user module.

[0118] Specifically, the control module sends the read data (APP data) to the data selection unit via the APP interface. The data selection unit further sends the read data (data) to the data conversion unit, which converts the APP data into AHB user data. Because the channel state machine receives the read enable signal (ren), its state switches to the read state, thereby receiving the AHB user data output by the data conversion unit and transmitting the AHB user data to the data pre-determination unit. The data pre-determination unit ultimately outputs the AHB data to the user module.

[0119] The RISC-based data storage method provided in this embodiment uses the AHB interface as the DDR storage conversion interface. This not only reduces resource usage and improves performance, but also utilizes the AHB's back pressure function (HREADY) to communicate with the local interface's app_ready signal to implement a read-write wait function and ensure data transmission continuity. The AHB's burst function can also be used to perform burst storage of data in advance and transmit it after it is spliced ​​into a group of DDR data bit widths, thereby effectively utilizing the bit width of the entire transmission channel and improving working bandwidth and efficiency.

[0120] The RISC-based data storage method provided in this embodiment uses an arbitration module to adapt to external interfaces such as RISC-based user modules while retaining the original local direct control interface, thereby realizing switching between different interfaces and being compatible with different data transmission modes. This allows data to be adapted to different channels and interfaces for both writing and reading, thereby realizing high-speed data storage and reading based on a RISC-based microcontroller.

[0121] Furthermore, this embodiment further provides an integrated circuit, comprising the RISC-based data storage system as described above.

[0122] Specifically, in this embodiment, the integrated circuit is implemented based on FPGA, that is, the local module, user module, asynchronous module, arbitration module, control module and DDR particles can all be implemented based on FPGA, thereby making use of the internal resources of FPGA to realize the flexible design of RISCV-based data storage system.

[0123] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other. In addition, the different parts between the various embodiments can also be used in combination with each other, and the present invention is not limited to this.

[0124] The data storage system, method, and integrated circuit based on RISC-V provided in this embodiment include: a local module for generating local data; a user module, which is a hard-core module of RISC-V, for generating user data; an asynchronous module for converting the clock domain of the user data to the clock domain of the local data; an arbitration module for receiving the local data generated by the local module using an APP interface, and for receiving the user data after clock domain conversion output by the asynchronous module using an AHB interface, and for converting the received local data and user data into APP data; a control module for converting the APP data output by the arbitration module into a timing signal of a DDR particle; and a DDR particle for receiving the timing signal output by the control module and storing the data carried by the timing signal. By using DDR particles as storage media, using the AHB interface corresponding to the RISC-V user module as a data transmission interface, and converting the AHB interface to the APP interface of the DDR protocol through the arbitration module, the high-speed and high-performance characteristics of DDR and AHB can be fully utilized, realizing high-speed data interaction between RISC-V and DDR. At the same time, the arbitration module can retain the original APP interface, thereby being compatible with different data transmission methods, solving the problem of how to achieve high-speed data storage based on a RISC-V microcontroller.

[0125] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A data storage system based on RISC-V, characterized in that: include: Local module, used to generate local data; User module is a hard-core module of RISCV, used to generate user data; an asynchronous module, configured to convert a clock domain of the user data to a clock domain of the local data; an arbitration module, configured to receive local data generated by the local module using an APP interface, further configured to receive user data after clock domain conversion output by the asynchronous module using an AHB interface, and to convert the received local data and user data into APP data; A control module, configured to convert the APP data output by the arbitration module into a timing signal of a DDR particle; The DDR particles are used to receive the timing signal output by the control module and store the data carried by the timing signal.

2. The RISC-based data storage system according to claim 1, characterized in that: The arbitration module includes a data pre-judgment unit, a channel state machine, a data conversion unit and a data selection unit; The data pre-judgment unit is used to determine whether the user data contains a user instruction from RISCV according to a preset detection rule, and generate a flag signal and a write enable signal; The channel state machine is used to switch to a write state according to a write enable signal, and in the write state, send user data to the data conversion unit; The data conversion unit is used to convert user data into APP data; The data selection unit is used to switch the connected channel according to the flag signal to transmit user data or local data in APP data format to the control module.

3. The RISC-based data storage system according to claim 2, characterized in that: The user data includes a clock signal, an address signal, a data signal, a burst signal, a data selection signal, a data ready signal, a transmission status signal, a transmission bit width signal and a data read / write signal; the preset detection rule includes: when the data selection signal is valid, the data read / write signal is a write signal, the transmission status signal is in an idle state, and the data ready signal is valid, it is determined that the user module has generated user data to be cached.

4. The RISC-based data storage system according to claim 2, characterized in that: The channel state machine has a judgment state, a write state and a read state, and the channel state machine defaults to the judgment state; in the judgment state, the channel state machine determines whether a write enable signal is received, and switches the state to the write state when it determines that the write enable signal is received.

5. The RISC-based data storage system according to claim 2, characterized in that: The data conversion unit includes a command parsing subunit, an address cache subunit and a data cache subunit; The command parsing subunit is used to parse user data to extract a write storage address signal, a write data signal, and a write control signal; and is also used to send the write storage address signal, the write data signal, and the write control signal to the data selection unit in an APP data format; The address cache subunit is used to cache write storage address signals; The data cache subunit is used to cache write data signals.

6. The RISC-based data storage system according to claim 2, characterized in that: The data pre-judgment unit is further configured to generate a read enable signal and a read control signal; The channel state machine is further configured to switch to a read state according to a read enable signal, and in the read state, send a read control signal to the data conversion unit; The data conversion unit is further configured to receive the interface preparation signal generated by the control module, and parse the read control signal and the interface preparation signal to generate a read instruction; The data selection unit is further configured to send a read instruction to the control module to read the corresponding data stored in the DDR particles; and is further configured to switch the connected channel according to the flag signal to transmit the read data to the data conversion unit; The data conversion unit is further configured to convert the data read by the data selection unit into AHB data, and output the data to the user module through the channel state machine and the data pre-judgment unit.

7. A RISC-based data storage method, applied to the RISC-based data storage system according to any one of claims 1 to 6, characterized in that: The data storage method includes: determining whether a flag signal is generated; If the flag signal is generated, the user data generated by the user module is obtained according to the write enable signal and the user data is converted into APP data; otherwise, the local data generated by the local module is obtained; Convert user data or local data in APP data format into timing signals of DDR particles; The DDR particles receive the timing signal and store the data carried by the timing signal.

8. The RISC-based data storage method according to claim 7, characterized in that: The data storage method further includes: If the flag signal is generated, the read control signal and the interface preparation signal are parsed according to the read enable signal to generate a read instruction; Read the corresponding data stored in the DDR particles according to the read instruction; Convert the read data into AHB data and output it to the user module.

9. The RISC-based data storage method according to claim 7, characterized in that: The data storage method further includes: By default, local data generated by the local module is transmitted to DDR particles.

10. The RISC-based data storage method according to claim 7, characterized in that: The user data generated by the user module is transmitted in bursts using burst signals; the user data includes a write storage address signal and a write data signal; the method for converting the user data into APP data includes: After receiving the write enable signal, receive and cache the write storage address signal; After waiting for one clock cycle, a write data signal corresponding to the write storage address signal is received and cached; wherein, after continuously acquiring all data under the burst signal, all data are spliced ​​into a parallel data, and the parallel data is cached.

11. An integrated circuit, characterized in that: Comprising the RISC-based data storage system according to any one of claims 1 to 6.

12. The integrated circuit according to claim 11, wherein: The integrated circuit is implemented based on FPGA.

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