Cross-domain overall optimization method, system, equipment and medium for human-machine collaborative function testing

Abstract

The present invention discloses a cross-domain overall optimization method, system, equipment and medium for human-machine collaborative functional testing, which relates to the field of electronic information technology, including: determining the relationship between fault coverage and system inherent reliability by performing reliability analysis on the mainboard functional testing process; establishing a fault tree, extracting component reliability information from a historical maintenance data set, determining the reliability range of all functional test modules, and obtaining the correlation relationship between the modules; based on the fault tree analysis, analyzing the impact of concurrent failures of modules containing the same bottom event on the system inherent reliability, and correcting the system inherent reliability calculation formula; constructing an optimization model for the functional testing process, and proposing a two-stage optimization solution method considering reliability uncertainty; the optimization method, system, equipment and medium enhance the cross-domain overall optimization capability of the model, and provide more reliable decision support for human-machine collaborative testing.

Description

Technical Field

[0001] The present invention relates to the field of electronic information technology, and in particular to a method, system, device and medium for cross-domain overall optimization of human-machine collaborative functional testing. Background Art

[0002] With the continued growth in demand for electronic products, the complexity of circuit board design and manufacturing has increased significantly. As a key step in ensuring product performance and quality, functional testing is becoming increasingly important and facing increasing cost pressures. Existing test strategy methods typically use greedy algorithms, deriving the optimal test strategy based solely on information from the test phase. However, in the flexible manufacturing model of notebook motherboards with multiple varieties and small batches, this single-point optimization approach is prone to overfitting due to the dynamic nature of production line conditions. This makes it difficult to effectively reduce the total cost of testing and often leads to high repair rates, resulting in significant economic losses for manufacturers.

[0003] The above problems arise mainly because in flexible manufacturing systems, the various links of the production process are strongly coupled, and key issues often involve the collaborative optimization of multiple different domains. Yield is only the short-term performance of component reliability in the test link. The existing test strategy design method is based on a single-point optimization model established based on the yield characteristics of the test link, ignoring the fact that the reliability of motherboard components is essentially determined by the upstream manufacturing process. This optimization model constructed based on single-domain information fails to fully consider the correlation of cross-domain information, resulting in a lack of consideration of reliability uncertainty when calculating fault coverage. When faced with dynamic changes in related parameters in other domains, it often performs poorly due to insufficient cross-domain collaborative optimization capabilities. This limitation makes it difficult for the model to adapt to the dynamic needs of multi-domain coupling and rapid response in a flexible manufacturing environment, ultimately affecting the overall optimization effect. Summary of the Invention

[0004] Based on the technical problems existing in the background technology, the present invention proposes a cross-domain overall optimization method, system, equipment and medium for human-computer collaborative functional testing, which improves the optimization effect.

[0005] The cross-domain overall optimization method for human-machine collaborative functional testing proposed in the present invention includes:

[0006] By conducting reliability analysis on the motherboard functional test process, the relationship between fault coverage and system inherent reliability is determined;

[0007] By analyzing the mainboard schematic diagram to establish a fault tree, component reliability information is extracted from the historical maintenance data set. The reliability range of the bottom event in the fault tree is determined by combining the reliability interval estimation method guided by expert knowledge. Based on this, the reliability range of all functional test modules is determined, thereby obtaining the correlation relationship between each functional test module.

[0008] Based on the fault tree analysis, the impact of concurrent failures of functional test modules containing the same bottom event on the system inherent reliability is analyzed, and the calculation formula of the system inherent reliability is modified accordingly;

[0009] An optimization model for the functional testing process is constructed, and a two-stage optimization solution method considering reliability uncertainty is proposed. The goal of the first stage is to maximize the inherent reliability of the system while meeting the test time constraint, and the goal of the second stage is to minimize the average total test cost.

[0010] Furthermore, in the reliability analysis of the motherboard functional test process, the test strategy of the motherboard functional test process divides the test items into two categories: tested items and untested items;

[0011] The unreliability of the motherboard functional test process comes only from the subsystem composed of untested items, and the system inherent reliability The calculation is as follows:

[0012] ;

[0013] in, To test the strategy The total number of functional test modules included in For functional test module index, To test the strategy Middle Functional test modules, Indicates the Functional test modules The test start signal is not active.

[0014] Furthermore, in the fault tree, the mainboard failure is regarded as the top event, the functional test module failure is regarded as the intermediate event, and the bottom cause of the functional test module failure is regarded as the bottom event of the fault tree.

[0015] Furthermore, the reliability interval estimation method guided by expert knowledge determines the reliability range of the bottom event in the fault tree, and accordingly determines the reliability range of all functional test modules, specifically:

[0016] The samples in the historical maintenance dataset are divided into groups, and calculate the reliability of all bottom events in each group;

[0017] Based on the reliability calculation results in each group, the reliability mean and standard deviation of each bottom event are calculated to obtain the reliability range of each bottom event;

[0018] Based on the connection between each intermediate event in the fault tree and the related bottom event through an OR gate, the reliability range of the intermediate event is calculated using the reliability range of the bottom event, thereby obtaining the reliability range of all functional test modules.

[0019] Furthermore, the optimization model is constructed as follows:

[0020] Objective function:

[0021] ;

[0022] Constraints:

[0023] ;

[0024] in, The test strategy for the motherboard functional test, For the Functional test modules The test start signal is activated. To express the inherent reliability of the system, is the total number of functional test modules included in the mainboard functional test process, For functional test module index, Indicates the The average test time of each functional test module, Indicates the test time threshold for each product.

[0025] Furthermore, in the first stage of the two-stage optimization solution method;

[0026] Set the optimization goals for the first phase;

[0027] Randomly generated within the reliability range of all functional test modules The reliability value combination of the group is obtained, and the optimization problem is solved for each combination. a testing strategy;

[0028] Since different rounds of optimization may generate the same test strategy, Round optimization Testing strategies, ;

[0029] A test strategy with a generation frequency greater than a threshold set by the strategy is selected as an alternative test strategy.

[0030] Furthermore, in the two-stage optimization solution method, the second stage optimization solution is specifically as follows:

[0031] A comprehensive evaluation index for test strategy optimization is introduced to select the best test strategy from alternative test strategies :

[0032] ;

[0033] in, Represents the test strategy The average total test cost value on the training set, A set of alternative test strategies.

[0034] The cross-domain overall optimization system for human-machine collaborative functional testing includes a reliability analysis module, a correlation module, a reliability correction module, and a two-stage optimization solution module;

[0035] The reliability analysis module is used to determine the relationship between fault coverage and system inherent reliability by performing reliability analysis on the mainboard function test process;

[0036] The association module is used to establish a fault tree by analyzing the mainboard schematic diagram, extract component reliability information from the historical maintenance data set, and determine the reliability range of the bottom event in the fault tree in combination with the reliability interval estimation method guided by expert knowledge. Based on this, the reliability range of all functional test modules is determined, thereby obtaining the association relationship between the functional test modules;

[0037] The reliability correction module is used to analyze the impact of concurrent failures of functional test modules containing the same bottom event on the inherent reliability of the system based on the fault tree, and to correct the calculation formula of the inherent reliability of the system accordingly;

[0038] The two-stage optimization solution module is used to solve the optimization model for the functional test process. The optimization solution goal of the first stage is to maximize the system inherent reliability while meeting the test time constraint, and the optimization solution goal of the second stage is to minimize the average total test cost.

[0039] A computer device comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the above-mentioned optimization method when executing the computer program.

[0040] A computer-readable storage medium stores a plurality of classification programs, wherein the plurality of classification programs are used to be called by a processor and execute the optimization method described above.

[0041] The advantages of the cross-domain overall optimization method, system, equipment and medium for human-machine collaborative functional testing provided by the present invention are: combining expert experience, from a manufacturing perspective, tracing the root cause of the motherboard failure, and realizing accurate evaluation of the reliability of the motherboard components; then, combining the reliability information of the motherboard components and the reliability analysis of the functional testing process, establishing an optimization model for the functional testing process from the perspective of the system's inherent reliability, and proposing a two-stage optimization solution method considering reliability uncertainty. This model not only improves the accuracy of the system's inherent reliability calculation, but also enhances the model's cross-domain overall optimization capability, providing more reliable decision support for human-machine collaborative testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is a schematic diagram of the process of the present invention;

[0043] Figure 2 This is the mainboard function test flow chart;

[0044] Figure 3 This is the schematic diagram of a typical laptop motherboard;

[0045] Figure 4 for Figure 3 The fault tree diagram of the laptop motherboard is established;

[0046] Figure 5 for Figure 4 Schematic diagram of some branches of the fault tree of a typical laptop motherboard;

[0047] Figure 6 for Figure 4 Schematic diagram of the remaining branches of the fault tree for a typical laptop motherboard;

[0048] Figure 7 Fault tree structure diagram with repeated events for the minimum cut set. DETAILED DESCRIPTION

[0049] The technical solutions of the present invention are described in detail below through specific embodiments. Numerous specific details are set forth in the following description to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways than those described herein, and those skilled in the art may make similar modifications without departing from the scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0050] like Figures 1 to 7 As shown, the cross-domain overall optimization method for human-machine collaborative function testing proposed by the present invention includes steps 1 to 4:

[0051] Step 1: Conduct reliability analysis on the motherboard functional test process to determine the relationship between fault coverage and system inherent reliability;

[0052] Step 2: Build a fault tree by analyzing the motherboard schematic, extract component reliability information from historical maintenance data sets, and use expert knowledge-guided reliability interval estimation methods to determine the reliability range of the bottom event in the fault tree. This is used to determine the reliability range of all functional test modules, thereby obtaining the correlation between the functional test modules.

[0053] Step 3: Analyze the impact of concurrent failures of functional test modules containing the same bottom event on the system inherent reliability based on the fault tree, and modify the system inherent reliability calculation formula accordingly;

[0054] Step 4: Build an optimization model for the functional testing process and set up a two-stage optimization solution method that considers reliability uncertainty. The optimization solution goal of the first stage is to maximize the inherent reliability of the system while meeting the test time constraint, and the optimization solution goal of the second stage is to minimize the average total test cost.

[0055] This example addresses the problem of existing methods lacking consideration of reliability uncertainty, leading to insufficient generalization of the optimal solution of the optimization model. By proposing a cross-domain, holistic optimization method for functional testing, this method integrates expert experience to trace the root causes of product quality issues, laying a key theoretical and data foundation for establishing a cross-domain collaborative optimization model and effectively addressing the limitations of existing single-point optimization methods. Furthermore, based on monitoring the actual operating efficiency of the production and test lines, constraints are set for the model to ensure that the test strategy is optimally matched to the actual operating conditions of the production line.

[0056] That is, first, by conducting reliability analysis on the functional test process, the inherent reliability information of the process is mined, and the traditional fault coverage is replaced by the inherent reliability of the system; then, by additionally considering the situation where modules containing the same basic event fail at the same time, the calculation accuracy of the inherent reliability of the system is improved when there are repeated events in the minimum cut set. Finally, based on the construction of an optimization model for the functional test process, a two-stage optimization solution method considering reliability uncertainty is designed. The case study shows that the proposed method can design a motherboard functional test strategy with cross-domain overall optimization capabilities, thereby reducing the cost of the functional test process.

[0057] In one embodiment, step 1 is to determine the relationship between fault coverage and system inherent reliability by performing reliability analysis on the motherboard function test process, specifically:

[0058] Yield is only a temporary indicator of motherboard component reliability, which is determined by fixed motherboard manufacturing technologies and therefore has a fixed value. Because the reliability of the motherboard functional test process depends on the reliability of the components being tested, the test strategy derived from analyzing the reliability of the motherboard functional test process is deterministic and is more likely to have stronger generalization capabilities than a test strategy derived by maximizing fault coverage.

[0059] Functional testing is divided into two phases: motherboard functional testing and finished product functional testing. The motherboard functional testing phase is conducted according to the test strategy, which determines the test status of each test item. Finished product functional testing tests all functions of the finished product assembled from motherboards that have passed the motherboard functional testing. Therefore, no faulty products are missed during this phase. During the motherboard functional testing phase, the test strategy categorizes test items into two categories: tested items and untested items. A motherboard is considered good only if all tested items pass. If any item fails, it is considered defective and sent to a repair center for additional testing and repair. If a motherboard has an untested faulty item, it is considered a false negative, meaning it was mistakenly classified as good. This motherboard is then assembled into a finished product. During the finished product functional testing process, the finished product will be detected as defective. It will then be disassembled and sent to a repair center. Due to the high cost of reworking false negative motherboards, excessive false negative motherboards can lead to high total testing costs.

[0060] according to Figure 2 From the motherboard flow chart, we know that in the motherboard functional test stage, since each test item is tested serially and the test items are independent of each other, the tested items form a serial subsystem, and the untested items form another serial subsystem. The reliability of the motherboard functional test stage is jointly determined by the two subsystems. According to the above analysis, if the faulty components of a faulty motherboard are tested, the motherboard will definitely be detected as a defective product; therefore, the appearance of a false negative motherboard is caused by the untested items. For the functional test of the finished product, the reliability of the subsystem composed of the tested items in the motherboard functional test process is 100%, and the unreliability of the motherboard functional test process only comes from the subsystem composed of the untested items. Therefore, the inherent reliability of the system is calculated as follows:

[0061] ; (1)

[0062] in, For testing strategies The total number of functional test modules included in For functional test module index, For testing strategies Middle Functional test modules, Indicates the Functional test modules The test start signal is not active.

[0063] In one embodiment, step 2 is to establish a fault tree by analyzing the mainboard schematic, extract component reliability information from the historical maintenance data set, estimate the reliability of the bottom event in the fault tree, and use the reliability interval estimation method guided by expert knowledge to determine the reliability range of the bottom event in the fault tree. The reliability of the estimated bottom event is replaced with the reliability range to obtain the correlation relationship between the modules, specifically:

[0064] The inherent reliability of motherboard components is fundamentally determined by their manufacturing process, and this reliability characteristic is directly reflected in subsequent maintenance data. Based on this, we first construct a historical maintenance dataset by collecting fault diagnosis information recorded by maintenance personnel during testing. We then apply statistical analysis methods to extract component reliability information from this historical maintenance dataset. Finally, we conduct qualitative fault tree analysis and quantitative calculation of test item reliability to achieve reliability assessment from manufacturing to testing.

[0065] First, a typical laptop motherboard was tested for its functionality. The circuit diagram of the motherboard is shown in the figure below. Figure 3 Table 1 lists the functional test items for this motherboard. Motherboards that fail these tests are sent to a repair center for more detailed testing. Based on the test results and the experts' practical experience, the underlying cause of the motherboard failure is determined, the relevant components are repaired, and the information is recorded in the historical repair data set (i.e., the repair log).

[0066] Based on the motherboard functional test results and historical maintenance data sets, we established Figure 4 To simplify the structure of the fault tree, the branches of the intermediate events are drawn in Figure 5 and Figure 6 In the figure, A, B, and C represent fault types, with their specific meanings shown in Table 2. In the fault tree, the mainboard failure is considered the top event; the functional test module failure is considered the intermediate event and listed in Table 3; the underlying cause of the functional test module failure is considered the bottom event of the fault tree and listed in Table 4.

[0067] Table 1 Functional test items of typical notebook computer motherboard

[0068]

[0069] Table 2 Typical laptop motherboard failure types

[0070]

[0071] Table 3 Intermediate events of the fault tree of a typical laptop motherboard

[0072]

[0073] Table 4 Bottom events of the fault tree of a typical laptop motherboard

[0074]

[0075] Table 5. Bottom event set of intermediate events corresponding to test items of typical laptop motherboards

[0076]

[0077] Therefore, the specific step 2 is:

[0078] First, a large amount of historical test results of this motherboard is constructed as a data set ,in Indicates the number of motherboards tested by the motherboard function test process. Then, collect the The corresponding historical maintenance dataset of the motherboard and its finished product contains the diagnosis and repair information of the faulty motherboard in the functional test process of the motherboard and finished product. Then, another dataset is constructed using the historical maintenance dataset and recorded as ,in Representation dataset The number of failed motherboards, Indicates the number of bottom events. In this dataset middle, Indicates the The motherboard is Repair due to the occurrence of a bottom event, . is a sparse matrix, usually Each row of has only one element equal to 1. Use formula (2) to calculate the The number of occurrences of the bottom event :

[0079] ; (2)

[0080] The formula (3) can be used to estimate the bottom event Reliability :

[0081] ; (3)

[0082] Since the number of faulty motherboards is very limited in the high-yield motherboard manufacturing process, in order to improve the accuracy of the bottom event reliability estimation, a large number of tests are required to collect sufficient historical maintenance data sets. Therefore, in general, The value should not be less than .

[0083] Then, the reliability of the intermediate event is derived using the reliability of the bottom event as follows: Figure 5 and Figure 6 As can be seen from Table 5, each intermediate event is connected to its related bottom event through an OR gate. According to the reliability theory, the reliability of the component corresponding to the intermediate event is calculated. as follows:

[0084] ; (4)

[0085] in, To cause the The set of underlying causes (i.e., bottom events) of each functional test module failure, Mainboard functional test process The total number of functional test modules included in For functional test module index, Mainboard functional test process Middle Functional test module.

[0086] In practical applications, the estimated deviation of reliability is difficult to ignore, especially in the motherboard manufacturing process with a high yield rate. To solve this problem, this embodiment proposes an expert knowledge-guided reliability interval estimation method, which uses the reliability range instead of the reliability in formula (3).

[0087] The specific steps are as follows: The samples in the data are divided into several groups, and then the reliability of all the bottom events in each group is calculated using formula (3). Based on the reliability calculation results in each group, the reliability mean and standard deviation of each bottom event are calculated to obtain the reliability range of each bottom event.

[0088] Based on the The reliability mean and standard deviation of the bottom event are recorded as and Then calculate the The reliability range of each event is as follows:

[0089] ; (5)

[0090] in:

[0091] ; (6)

[0092] ; (7)

[0093] According to formulas (4) to (7), the reliability range of the test items can be determined, which is the basis for the subsequent test strategy through optimization modeling.

[0094] In one embodiment, step three is to analyze the impact of concurrent failures of modules containing the same bottom event on the inherent reliability of the system based on the fault tree analysis, and to modify the calculation formula of the inherent reliability of the system accordingly, specifically:

[0095] In step one, by conducting a reliability analysis of the functional test process, it was determined that the use of the system's inherent reliability can more accurately represent the fault coverage rate. Based on reliability theory, the system's inherent reliability is expressed as the product of the reliabilities of the system's components. When calculating the system's inherent reliability, existing analyses fail to fully consider the impact of concurrent failures of modules containing the same underlying event on the system's reliability. Specifically, when performing reliability analysis on the functional test process, existing models ignore the impact of repeated events in the minimum cut set on the calculation results. This simplification leads to significant deviations in the calculated value of the system's inherent reliability, which in turn affects the optimization effect of subsequent test strategies.

[0096] Because the fault tree model constructed in step 2 clearly reveals the relationships between modules, this embodiment, guided by experts, deeply analyzes the fault tree structure, quantitatively analyzes the impact of concurrent module failures involving the same underlying event on system reliability, and modifies the formula for calculating the system's inherent reliability. This improves the accuracy of the system's inherent reliability calculation and provides a more reliable theoretical basis for optimizing testing strategies.

[0097] Considering the existence of repeated events in the minimum cut set, the probability of the top event is Expressed as:

[0098] ; (8)

[0099] ; (9)

[0100]

[0101]

[0102] ; (11)

[0103] ; (12)

[0104] in, This is the first step in the motherboard function test process. Functional test modules, is the total number of functional test modules included in the mainboard functional test process, They are functional test module indexes, The index of the summation term in the formula.

[0105] by Figure 7 Taking the fault tree shown in the figure as an example, the calculation formula for the probability of occurrence of the top event considering repeated events is specifically explained. Figure 7 In the example, events are connected by OR gates. The failure of the top event T may be caused by the failure of events M1, M2, or M3. According to the fault tree structure, events M1 and M2 contain the same event M5, and events M1, M2, and M3 contain the same event M5. The calculation process of the probability of the top event is:

[0106] ; (13)

[0107] The module association information contained in the fault tree is used to solve the probability problem of simultaneous failure of modules containing the same underlying event. For example, if event M1 and event M2 contain a common event M5, the occurrence of event M5 will cause event M1 and event M2 to occur simultaneously. Therefore, the probability of event M5 is used to represent the probability of event M1 and event M2 occurring simultaneously.

[0108] The true value of unreliability is difficult to obtain. Usually, the probability value of the event failure is used as the estimated value of unreliability. According to the reliability analysis in step 1, the unreliability of the motherboard function test process only comes from the subsystem of the untested items. The subsystem composed of the untested items is analyzed as a whole, and the failure of the subsystem is recorded as the top event. , the failure of the intermediate event contained in the subsystem is the bottom event, then the top event The probability of occurrence is:

[0109] ; (14)

[0110]

[0111] in, Indicates the The test start signal of the functional test module is not activated. This is the first step in the motherboard function test process. Functional test module.

[0112] Since the true value of unreliability is difficult to obtain accurately in reality, the present invention uses the probability of occurrence of an event (functional test module failure) as the estimated value of unreliability, and the corrected system inherent reliability is Expressed as:

[0113] ; (16)

[0114] in, is the inherent unreliability of the system.

[0115] In one embodiment, step 4 is to construct an optimization model for the functional testing process and set a two-stage optimization solution method considering reliability uncertainty, specifically:

[0116] The goal of the first phase is to maximize the inherent reliability of the system while meeting the test time constraints.

[0117] The purpose of the motherboard function test is to detect as many defective motherboards as possible, that is, to reduce the reliability of the motherboard function test. Based on the analysis in step 3, the objective function is established as follows:

[0118] ; (17)

[0119] To avoid product accumulation on the test line, the test time for each product should be controlled within a certain range. Therefore, the following constraints are established:

[0120] ; (18)

[0121] in, The test strategy for the motherboard functional test, Indicates the The average test time of each functional test module, Indicates the test time threshold for each product, which is determined based on the multi-dimensional evaluation results of the real-time operating status of the production line.

[0122] To mitigate overfitting, the average test time for each test item is calculated by the historical test time. calculate:

[0123] ; (19)

[0124] in, For the The first motherboard The test time of each functional test module, The number of motherboards tested in the motherboard function test process, The index of the motherboard to be tested during the motherboard function test process.

[0125] Based on the above analysis, the following optimization problem is established:

[0126] ; (20)

[0127] ;(twenty one)

[0128] ;(twenty two)

[0129] For a given set of bottom event reliability values, a certain test strategy can be obtained by solving the optimization problems (20)-(22). However, since only the range of bottom event reliability can be obtained in practice, a random test strategy is generated within the reliability range calculated in step 2. Different reliability value combinations are formed. Then, the optimization problems (20)-(22) are solved for each combination. The optimization result of each combination is a test strategy that ensures the reliability of the motherboard functional test.

[0130] In the first stage of optimization solution, first randomly generate The reliability value combinations of the groups are obtained, and the optimization problems (20)-(22) are solved for each combination. test strategies; since different rounds of optimization may generate the same test strategy, Round optimization Testing strategies, , will Testing strategies exist The frequency of occurrence in round optimization is expressed as ; Select the test strategy with a generation frequency greater than the strategy setting threshold as the alternative test strategy.

[0131] Because a set of reliability is randomly set when solving the optimization problem for each combination, each optimization will get a relatively optimal test strategy. Therefore, the higher the frequency of the test strategy, the more suitable the test strategy is for the reliability of the intermediate event obtained in step 2. Select the test strategy with a generation frequency greater than the strategy setting threshold. The test strategy as an alternative test strategy set :

[0132] ;(twenty three)

[0133] in, The value of is usually determined based on actual production experience. It is recommended to take a value of not less than 0.1 to select the strategies with the highest frequency of occurrence. The value should also be relatively large, and it is recommended to be greater than 200.

[0134] In existing research, fault coverage is often used as the sole criterion for optimizing test strategies, i.e., only test quality is considered in the optimization. Since test time accounts for a high proportion of the total test cost, it is crucial to choose a test strategy that balances test quality and time.

[0135] To this end, this embodiment introduces a comprehensive evaluation index for test strategy optimization in the second stage optimization solution, which is used to select the best test strategy with strong generalization ability from the candidate test strategy set. This comprehensive evaluation index aims to achieve a balance between test quality and test speed. The following formula is used to select the best test strategy with strong generalization ability from the candidate test strategy set. Select the testing strategy with the lowest average total testing cost on the training set The best test strategy obtained as the final optimization is:

[0136] ;(twenty four)

[0137] in Represents the test strategy The average total test cost value on the training set, The calculation process will be described in detail below.

[0138] In this embodiment, in order to verify the effectiveness of the method proposed in this embodiment, three evaluation indicators are set, namely false negative rate (FNR), average motherboard test time, and average motherboard test total cost. The calculation process is as follows:

[0139] First, calculate the actual number of qualified motherboards for:

[0140] ; (25)

[0141] in, Indicates the motherboard index, The number of motherboard batches to be tested. Indicates the The first product The test results of the functional test modules, Indicates the The first motherboard Functional test modules passed the test, The logical AND operation is true.

[0142] The actual number of defective motherboards for:

[0143] ; (26)

[0144] Using a testing strategy The number of defective motherboards detected for:

[0145] ; (27)

[0146] in, Indicates the The first motherboard Functional test modules failed the test;

[0147] In the test strategy The number of undetected defective motherboards for:

[0148] . (28)

[0149] The false negative rate indicates the ratio of the number of undetected defective motherboards to the total number of defective motherboards, and evaluates the detection capability of the test strategy for defective motherboards. The formula for calculating the false negative rate FNR is as follows:

[0150] ; (29)

[0151] in, is the false negative rate under the test strategy S.

[0152] The average test time indicates the average test time for testing a motherboard and is used to evaluate the test efficiency of the test strategy. The formula for the average test time under test strategy S is as follows:

[0153] ; (30)

[0154] in, Indicates the The first product The test time of each functional test module.

[0155] Average total cost of motherboard testing It is the sum of the test time and repair time of a motherboard, which is used to evaluate the overall test effect of the test strategy. The calculation formula is as follows:

[0156] ; (31)

[0157] in, Indicates the average repair time of the motherboard. Indicates the average repair time of finished notebooks, To test strategies during the motherboard functional testing phase The number of faulty motherboards detected.

[0158] This embodiment traces the root causes of product quality by incorporating the expert experience of multiple process domains, and while additionally considering the simultaneous failure of modules containing the same underlying event, it improves the accuracy of calculating the inherent reliability of the system in the presence of repeated events in the minimum cut set. In addition, by further considering the uncertainty of the reliability values ​​of underlying events in actual scenarios, a cross-domain overall optimization method for human-machine collaborative functional testing is designed. This optimization method analyzes component reliability from the perspective of product manufacturing, and then incorporates the reliability characteristics of the manufacturing end into the system reliability analysis of the functional testing process, thereby enhancing the cross-domain optimization capability of the optimization method and solving the problem of insufficient generalization capability of the optimal solution of the optimization model due to the lack of consideration of reliability uncertainty in existing methods.

[0159] In order to verify the effectiveness of this embodiment, the following comparison method is set up:

[0160] (1) A strategy design method based on fault tree analysis. This method is the ablation experiment of this embodiment. Specifically, when the method of this embodiment is used to conduct an experiment, when calculating the inherent reliability of the system, the impact of concurrent failures of functional test modules containing the same bottom event on the inherent reliability of the system is not considered.

[0161] (2) A strategy design method for minimizing the total test cost. This method is the ablation experiment of this embodiment. Specifically, when using the method of this embodiment to conduct an experiment, only one stage of solving the optimization model is set. Specifically, the test strategy with the lowest average total test cost is selected as the optimal test strategy in the solution of the optimization model.

[0162] (3) A strategy design method based on maximum budget coverage. This method is the ablation experiment of this embodiment. Specifically, when using the method of this embodiment to conduct experiments, the reliability information in the motherboard functional test process is not used (that is, the relationship between fault coverage and the inherent reliability of the system is not determined). Maximizing the fault coverage in the training set is used as the objective function of the optimization model. Among them, maximizing the fault coverage in the training set is an existing method. For details, see the literature PAN R, ZHANG Z, LI X, et al. Black-Box Test-Coverage Analysis and Test-Cost Reduction Based on a Bayesian Network Model[C] / / 2019 IEEE 37th VLSI TestSymposium(VTS). 2019: 1-6.

[0163] The evaluation indicators of the method proposed in this embodiment and its comparative method on the test set are shown in Table 6:

[0164] Table 6: Evaluation indicators of the optimization method of this embodiment and its existing methods on the test set

[0165]

[0166] The experimental results in Table 6 demonstrate that the cross-domain holistic optimization method proposed in this embodiment demonstrates significant advantages in key performance indicators: 1) In terms of defect detection, its false negative rate (FNR) is reduced by up to approximately 8.40% compared to existing methods, effectively controlling the missed detection rate of defective motherboards; 2) In terms of economic benefits, it achieves a 7.28% reduction in average total testing costs. This demonstrates that the method proposed in this embodiment, through its innovative integration of a human-machine collaborative decision-making mechanism and cross-domain reliability modeling technology, effectively reduces the cost of the functional testing process and provides an effective cross-domain holistic optimization solution for flexible intelligent manufacturing systems.

[0167] As an embodiment;

[0168] Taking a typical notebook motherboard as the research object, the reliability of the motherboard functional test process was analyzed to determine the relationship between fault coverage and the inherent reliability of the system. Then, the component reliability information contained in the historical maintenance data set was extracted to estimate the reliability of the underlying components, and the module reliability was quantitatively calculated based on the fault tree. Next, the impact of simultaneous failures of multiple modules on the inherent reliability of the system was analyzed based on the fault tree structure, improving the accuracy of the calculation of the inherent reliability of the system when repeated events exist in the minimum cut set. Finally, considering the uncertainty of the reliability value of the underlying event, a two-stage optimization model for reliability uncertainty was established. The specific implementation steps are as follows:

[0169] A1. Analyze the reliability of the functional test process, replacing traditional fault coverage with system inherent reliability. Consider the impact of simultaneous failures of modules containing the same underlying event on the system inherent reliability. Adjust the system inherent reliability calculation formula to establish the optimization problem as follows:

[0170] ; (32)

[0171] ; (33)

[0172] ; (34)

[0173] A2. Based on the current progress of board manufacturing technology and expert experience, the test time threshold of each motherboard is set to Set to 75 seconds.

[0174] A3. According to step 2, the motherboard test information and the corresponding maintenance data of the faulty motherboard are collected to calculate the reliability range of the intermediate event. The results are shown in Table 7:

[0175] Table 7: Reliability range of functional test modules

[0176]

[0177] A4. Solve the optimization problem in A1 (Formulas (32) to (34)) 200 times within the reliability range of the functional test module (i.e., intermediate events) in Table 7, and count the frequency of occurrence of each strategy. Based on expert experience, the number of strategies in Formula (23) is Set it to 95% and use formula (23) to screen alternative test strategies.

[0178] A5. In the training set, calculate the three evaluation indicators of the alternative test strategies in A4 according to formulas (29) to (31), compare the average total test cost indicator values ​​of each alternative strategy, and select the test strategy with the lowest average total test cost indicator value as the best test strategy;

[0179] A6. According to expert experience, replace Set to 0.5h, Set to 4h.

[0180] A7. Based on the evaluation indicators recorded in (29) to (31), the performance indicators of four test strategy design methods were calculated: 1) a test strategy design method based on fault tree analysis (existing method); 2) a test strategy design method based on maximum budget coverage (existing method); 3) a test strategy design method that minimizes total test cost (existing method); and 4) the optimization method based on the optimal test strategy in this embodiment. Table 6 compares the key indicators of each method in terms of fault coverage, average test time, and average total test cost. Through data analysis, it can be clearly seen that the method proposed in this embodiment exhibits stronger generalization ability and provides a more effective technical solution for solving the test strategy optimization problem in flexible manufacturing.

[0181] In this embodiment, a cross-domain overall optimization system for human-machine collaborative functional testing is proposed, including a reliability analysis module, an association relationship module, a reliability correction module, and a two-stage optimization solution module;

[0182] The reliability analysis module is used to determine the relationship between fault coverage and system inherent reliability by performing reliability analysis on the mainboard function test process;

[0183] The association module is used to establish a fault tree by analyzing the mainboard schematic diagram, extract component reliability information from the historical maintenance data set, and determine the reliability range of the bottom event in the fault tree in combination with the reliability interval estimation method guided by expert knowledge. Based on this, the reliability range of all functional test modules is determined, thereby obtaining the association relationship between the functional test modules;

[0184] The reliability correction module is used to analyze the impact of concurrent failures of functional test modules containing the same bottom event on the inherent reliability of the system based on the fault tree, and to correct the calculation formula of the inherent reliability of the system accordingly;

[0185] The two-stage optimization solution module is used to solve the optimization model for the functional test process. The optimization solution goal of the first stage is to maximize the system inherent reliability while meeting the test time constraint, and the optimization solution goal of the second stage is to minimize the average total test cost.

[0186] In this embodiment, a computer device is proposed, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the optimization method described above is implemented. The computer device includes, but is not limited to, digital computers (e.g., desktop computers, server clusters) and mobile terminal devices (e.g., smartphones, wearable smart devices). The device's core architecture comprises a computing unit (including, but not limited to, a CPU, GPU, and AI accelerator chips), a storage system (ROM, RAM, and other non-volatile memory), and a system bus architecture. The device implements human-computer interaction and data communication via an input subsystem (keyboard, touchscreen, and other input devices), an output subsystem (display unit, audio output device), a storage subsystem (storage media such as solid-state drives and mechanical hard drives), and a communication subsystem (wired network interface, wireless communication module). The device exchanges data via a communication network such as the Internet. During operation, the computing unit drives the device by executing program instructions stored in ROM or RAM.

[0187] In this embodiment, a computer-readable storage medium is provided, characterized in that the computer-readable storage medium stores a plurality of classification programs, which are used to be called by a processor to execute the optimization method described above. The programs can be loaded into the device in whole or in part via ROM or a communication subsystem. When the programs are loaded into RAM and executed by a computing unit, one or more processing steps of the aforementioned method can be implemented.

[0188] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0189] The above description is only a preferred specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any technician familiar with the technical field, within the technical scope disclosed by the present invention, who makes equivalent replacements or changes based on the technical solution and inventive concept of the present invention, should be covered by the scope of protection of the present invention.

Claims

1. A cross-domain overall optimization method for human-machine collaborative functional testing, characterized by: include: By conducting reliability analysis on the motherboard functional test process, the relationship between fault coverage and system inherent reliability is determined; By analyzing the mainboard schematic diagram to establish a fault tree, component reliability information is extracted from the historical maintenance data set. The reliability range of the bottom event in the fault tree is determined by combining the reliability interval estimation method guided by expert knowledge. Based on this, the reliability range of all functional test modules is determined, thereby obtaining the correlation relationship between each functional test module. Based on the fault tree analysis, the impact of concurrent failures of functional test modules containing the same bottom event on the system inherent reliability is analyzed, and the calculation formula of the system inherent reliability is modified accordingly; An optimization model for the functional test process is constructed, and a two-stage optimization solution is proposed that takes into account reliability uncertainty. The goal of the first stage is to maximize the inherent reliability of the system while meeting the test time constraint, and the goal of the second stage is to minimize the average total test cost. The process of determining the reliability range of all functional test modules is as follows: The samples in the historical maintenance dataset are divided into groups, and calculate the reliability of all bottom events in each group; Based on the reliability calculation results in each group, the reliability mean and standard deviation of each bottom event are calculated to obtain the reliability range of each bottom event; Based on the connection between each intermediate event in the fault tree and the related bottom event through the OR gate, the reliability range of the intermediate event is calculated using the reliability range of the bottom event, thereby obtaining the reliability range of all functional test modules; In the first stage of the two-stage optimization solution method; Set the optimization goals for the first phase; Randomly generated within the reliability range of all functional test modules The reliability value combination of the group is obtained, and the optimization problem is solved for each combination. a testing strategy; Since different rounds of optimization may generate the same test strategy, Round optimization Testing strategies, ; Select the test strategy with a generation frequency greater than the threshold set by the strategy as the alternative test strategy; In the two-stage optimization solution method, the second stage optimization solution is specifically as follows: A comprehensive evaluation index for test strategy optimization is introduced to select the best test strategy from alternative test strategies : ； in, Represents the test strategy The average total test cost value on the training set, A set of alternative test strategies.

2. The cross-domain overall optimization method for human-machine collaborative function testing according to claim 1 is characterized in that: In the reliability analysis of the motherboard functional test process, the test strategy of the motherboard functional test process divides the test items into two categories: tested items and untested items; The unreliability of the motherboard functional test process comes only from the subsystem composed of untested items, and the system inherent reliability The calculation is as follows: ； in, To test the strategy The total number of functional test modules included in For functional test module index, To test the strategy Middle Functional test modules, Indicates the Functional test modules The test start signal is not active.

3. The cross-domain overall optimization method for human-machine collaborative function testing according to claim 1 is characterized in that: In the fault tree, the mainboard failure is regarded as a top event, the functional test module failure is regarded as an intermediate event, and the underlying cause of the functional test module failure is regarded as a bottom event of the fault tree.

4. The cross-domain overall optimization method for human-machine collaborative function testing according to claim 1 is characterized in that: The optimization model is constructed as: Objective function: ； Constraints: ； in, The test strategy for the motherboard functional test, For the Functional test modules The test start signal is activated. To express the inherent reliability of the system, Mainboard functional test process The total number of functional test modules included in For functional test module index, Indicates the The average test time of each functional test module, Indicates the test time threshold for each product.

5. The cross-domain overall optimization system for human-machine collaborative function testing is characterized by: It includes reliability analysis module, correlation module, reliability correction module and two-stage optimization solution module; The reliability analysis module is used to determine the relationship between fault coverage and system inherent reliability by performing reliability analysis on the mainboard function test process; The association module is used to establish a fault tree by analyzing the mainboard schematic diagram, extract component reliability information from the historical maintenance data set, and determine the reliability range of the bottom event in the fault tree in combination with the reliability interval estimation method guided by expert knowledge. Based on this, the reliability range of all functional test modules is determined, thereby obtaining the association relationship between the functional test modules; The reliability correction module is used to analyze the impact of concurrent failures of functional test modules containing the same bottom event on the inherent reliability of the system based on the fault tree, and to correct the calculation formula of the inherent reliability of the system accordingly; The two-stage optimization solution module is used to solve the optimization model for the functional test process. The optimization solution goal of the first stage is to maximize the inherent reliability of the system while meeting the test time constraint. The optimization solution goal of the second stage is to minimize the average total test cost. The association relationship module is specifically used for: The samples in the historical maintenance dataset are divided into groups, and calculate the reliability of all bottom events in each group; Based on the reliability calculation results in each group, the reliability mean and standard deviation of each bottom event are calculated to obtain the reliability range of each bottom event; Based on the connection between each intermediate event in the fault tree and the related bottom event through the OR gate, the reliability range of the intermediate event is calculated using the reliability range of the bottom event, thereby obtaining the reliability range of all functional test modules; In the first stage of the two-stage optimization solution method; Set the optimization goals for the first phase; Randomly generated within the reliability range of all functional test modules The reliability value combination of the group is obtained, and the optimization problem is solved for each combination. a testing strategy; Since different rounds of optimization may generate the same test strategy, Round optimization Testing strategies, ; Select the test strategy with a generation frequency greater than the strategy setting threshold as the alternative test strategy; In the two-stage optimization solution method, the second stage optimization solution is specifically as follows: A comprehensive evaluation index for test strategy optimization is introduced to select the best test strategy from alternative test strategies : ； in, Represents the test strategy The average total test cost value on the training set, A set of alternative test strategies.

6. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the optimization method according to any one of claims 1 to 4 is implemented.

7. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a plurality of classification programs, which are used to be called by a processor and execute the optimization method according to any one of claims 1 to 4.

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