Automatic wiring method, computer equipment and storage medium

Abstract

The automatic wiring method comprises the steps that a source language of an IP core is obtained, a source language file is generated, and the IP core comprises an IP soft core and a peripheral IP core; analyzing the source language file, and obtaining configuration information of the IP cores and port information of each IP core; the IP soft core randomly selects peripheral IP cores for splicing, the bit width is calculated according to the connecting line between the ports, the peripheral IP cores are randomly connected with the ports of the AXI bus to complete splicing, and a first configuration file is generated; generating a script file based on the first configuration file, and performing automatic wiring based on the script file. The configuration information of the IP core and the port information of each IP core are obtained by analyzing the source language file, splicing between the IP soft core and the peripheral IP core is automatically completed, the script file is generated based on the first configuration file after the first configuration file is generated, automatic wiring is performed based on the script file, the test requirements of testers for different circuits are perfected, and the test efficiency is improved. The test process is accelerated and the test efficiency is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of EDA software design, and particularly relates to an automatic wiring method, a computer device, and a storage medium. Background Art

[0002] FPGA EDA software is an automated tool for designing electronic circuits. It completes the wiring of buses and peripheral IP cores through functions such as calling risc-v soft cores and other necessary peripheral IP cores, wiring, generating HDL_WRAPPER, performing pin constraints, synthesizing and generating bitstream files, and exporting. However, due to the relatively slow manual wiring and configuration information of each soft core, testers need to complete manual wiring according to different configurations and rules, and manual design is usually time-consuming. Especially under the condition of large-scale deployment, how to effectively reduce the configuration time of IP soft cores and peripheral IP cores and improve the test efficiency has become an urgent problem to be solved. Summary of the Invention

[0003] This application obtains the configuration information of IP cores and the port information of each IP core by parsing the source language file, automatically completes the splicing between the IP soft core and the peripheral IP core, generates a first configuration file, then generates a script file based on the first configuration file, and performs automatic wiring based on the script file, improving the test requirements of testers for different circuits, accelerating the test process, and improving the test efficiency.

[0004] Other objects and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0005] To achieve one or part or all of the above objects or other objects, the present invention provides an automatic wiring method, a computer device, and a storage medium.

[0006] An automatic wiring method includes: Obtaining the source language of the IP core to generate a source language file, where the IP core includes an IP soft core and a peripheral IP core; Parsing the source language file to obtain the configuration information of the IP core and the port information of each IP core; The IP soft core randomly selects a peripheral IP core for splicing, calculates the bit width according to the connection between ports, and the peripheral IP core randomly connects to the ports of the AXI bus to complete the splicing, generating a first configuration file; Generating a script file based on the first configuration file and performing automatic wiring based on the script file.

[0007] The source language file includes a circuit file; Converting the circuit program into a circuit file through FPGA EDA and saving it.

[0008] Parse the source language file to obtain the configuration information and input / output port information of the IP soft core, assemble them into structured data, and store them in the first list file.

[0009] Parse the circuit file, loop through all peripheral IP cores, extract the input / output port information of the peripheral IP cores, and store it in the second list file; The specific process of generating the first configuration file includes: Based on the second list file, construct a dictionary storing the port information of the peripheral IP cores, fix the port parameters of the IP soft core, randomly select the clock port and reset key of the peripheral IP core for connection by the IP soft core, calculate the bit width according to the connection between ports, assemble the input / output port information and parameter information, and write them into the first configuration file.

[0010] The specific process of generating the first configuration file further includes: The peripheral IP core randomly connects to the ports of the AXI bus, and calculates the bit width corresponding to the peripheral IP core through the port values of the AXI bus randomly connected by the peripheral IP core; The AXI bus has a total of 16 ports.

[0011] The first configuration file is the bd.v file.

[0012] Based on the first configuration file, obtain the ports of the IP soft core and the peripheral IP cores, and generate a top-level file for verifying the correctness of the process.

[0013] The script file includes: the first configuration file and the top-level file.

[0014] Modify the configuration information of the peripheral IP core by modifying the circuit file.

[0015] The IP soft core is a risc-v soft core.

[0016] A computer device includes a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, it implements the steps of the automatic routing method described in any one of the above.

[0017] A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the steps of the automatic routing method described in any one of the above.

[0018] Compared with the prior art, the beneficial effects of the present invention mainly include: This application obtains the configuration information of the IP cores and the port information of each IP core by parsing the source language file, automatically completes the splicing between the IP soft core and the peripheral IP cores, generates a first configuration file, generates a script file based on the first configuration file, performs automatic routing based on the script file, improves the test requirements of testers for different circuits, speeds up the test process, and improves the test efficiency.

[0019] To make the above and other objects, features, and advantages of the present invention more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, provides a detailed description as follows. Brief Description of the Drawings

[0020] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0021] Figure 1 It is a schematic flowchart of an automatic routing method provided in Embodiment 1 of this application.

[0022] Figure 2 It is the code illustration provided in Embodiment 1 of this application Figure 1 。

[0023] Figure 3 It is the code illustration provided in Embodiment 1 of this application Figure 2 。

[0024] Figure 4 It is the code illustration provided in Embodiment 1 of this application Figure 3 。 Detailed Embodiments

[0025] Regarding the foregoing and other technical contents, features, and effects of the present invention, they will be clearly presented in the following detailed description of a preferred embodiment in conjunction with the reference drawings. The directional terms mentioned in the following embodiments, such as: up, down, left, right, front, or back, etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for illustration and not for limiting the present invention.

[0026] The following will elaborate on each embodiment of this application in conjunction with the accompanying drawings. However, those of ordinary skill in the art can understand that in each embodiment of this application, many technical details are proposed for the convenience of readers to understand this application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in this application can still be implemented.

[0027] Embodiment 1 AsFigure 1 As shown in the figure, an automatic routing method includes: Step S1: Obtain the source language of the IP core and generate a source language file. The IP core includes an IP soft core and a peripheral IP core; Step S2: Parse the source language file to obtain the configuration information of the IP core and the port information of each IP core; Step S3: The IP soft core randomly selects a peripheral IP core for splicing, calculates the bit width according to the connection between the ports, and the peripheral IP core randomly connects to the ports of the AXI bus to complete the splicing, generating a first configuration file; Step S4: Generate a script file based on the first configuration file; Step S5: Perform automatic routing based on the script file.

[0028] Specifically, first obtain the source language of the IP core, generate a source language file (.v / .vhd), and configure the XML file of the IP soft core; Among them, the source language file also includes a circuit file, and the circuit program is converted into a circuit file and saved through FPGA EDA.

[0029] Then parse the.v file and.vhd file to obtain the input and output ports of each IP core, parse the xml file of each soft core to obtain the configuration information of the IP core, and assemble it into structured data, store it in the first list file collectValuesList, generate a format such as: module design.v…endmodule, obtain the configuration information of the parameter parameters of the IP and the port information of input / output, assemble the parameters of the basic core (IP soft core), splice the names of the IP cores, parse the source language ports, organize the routing method, and call the common splicing method after obtaining the port names, such as commonJoin res +='['+ str(n1) + f":" + str(n2) +']'; Among them, the parameter parameter configuration is the configuration information of the xml of the IP, each setting represents the attribute information of 8 IPs, the input port and output port are the routing combinations between any IPs, and the wire parameter part is the maximum value of the bit width obtained after the IPs are directly connected.

[0030] For example Figure 2 As shown in the figure, parse the circuit file, loop through all peripheral IP cores, save the input and output ports of each peripheral IP core to the second list file port_conn, and the risc-v soft core (IP soft core) randomly selects peripheral IP cores for combination to generate a new port name and bit width; Construct a dictionary storing the port information of the peripheral IP core based on the second list file, fix the port parameters of the IP soft core, randomly select the clock port and reset button of the peripheral IP core for the IP soft core to connect, calculate the bit width according to the connections between the ports, assemble the input and output port information and parameter information, and write them into the first configuration file (i.e., the bd.v file).

[0031] Specifically, after routing, calculate the bit width, and save the ports of the peripheral IP core into the dictionary pad_dict in the following format: The basic IP core (IP soft core) randomly selects the clock port and reset button of the peripheral IP core to connect, generates the parameters of the parameter, obtains the configuration information of each soft core in the parsed xml, splices the information of the input / output and wire parts of the ports, and assembles the information of the input and output port parameters and writes it into the first configuration file bd.v by means of writing a file; In this application, the ports and parameters of the port information of 4 basic IP cores and 4 peripheral IP cores are fixed respectively, and are fixed in the bd file by means of writing a file. Fix the port parameters of the fixed IP, randomly splice the peripherals, calculate their bit widths according to the connections between the ports, randomly select the ports of the peripherals to complete the splicing, and generate the bd.v file.

[0032] Figure 2 The parameter, input, output, and wire in it are all parsed from pad_dict in RTL. The parameter is the configuration of the parameter. The input wire port name is the connection combination of the IPs directly. The wire is the maximum bit width of the signal.

[0033] The peripheral IP core randomly connects to the ports of the AXI bus, and calculates the bit width of the corresponding peripheral IP core through the port values of the AXI bus randomly connected by the peripheral IP core; Specifically, as Figure 3 shown, the peripheral IP core randomly connects to the ports of the AXI_Interconnect bus. There are a total of 16 ports of the AXI_Interconnect bus IP. Calculate the bit width of the peripheral IP core through the number of ports of m_count randomly connected by the peripheral IP core, and call the method getRandomNum for calculating the bit width to calculate the bit width according to the randomly connected port values.

[0034] Figure 3The axi_gpio in it is the name of the fixed instantiated IP. The port is the value of the bit width calculated by the serial number of m_count where the S_AXI connects to the axi_interconnect port. The specific calculation method of the bit width of the peripheral IP core in this application is m_rand * 32 + bit width - 1. The bit width calculation methods of other peripheral IP cores are combined in the same way.

[0035] Obtain the IP soft core and the ports of the peripheral IP core based on the first configuration file, and generate a top-level file for verifying the correctness of the process; the script file includes: the first configuration file bd.v file and the top-level file top file. Specifically, as Figure 4 shown, based on the bd.v file, generate the top-level / TOP file. The file format is to generate a new top, obtain the ports of the basic soft core and the peripheral IP, and generate a top-level top to verify the process.

[0036] Figure 4 The port in top is the port name of the debug soft core of the basic IP. clk is the clock port of the basic IP core and the peripheral IP. It is a randomly obtained peripheral port of gpio. In the list of axi_gpio_arr, the display form is [.port name (connected signal)]. In this example, a peripheral IP of gpio is randomly selected. The other three peripheral IPs are also combined and wired in the same way, with the same format but different port names.

[0037] In addition, this application modifies the configuration information of the peripheral IP core by modifying the circuit file RTL file.

[0038] This application parses the RTL file, obtains the port values of the IP and the parameter configuration information of the IP, randomly connects the risc-v soft core and the peripheral IP core. At the same time, the configuration of the parameters of each peripheral IP core can be directly achieved by modifying the RTL, which reduces the operation steps of adding and modifying the configuration of each IP one by one through the interface and connecting the wires one by one. It shortens the waiting time for executing generate to generate bd.v, realizes the steps of manual wiring on the software through the script, greatly improves the test efficiency, reduces the test waiting time, quickly verifies the subsequent process, and obtains the test results in different scenarios.

[0039] Embodiment 2 Embodiment 2 of the present application provides a computer device for implementing the steps of the above-mentioned automatic routing method. The computer device may include: a processor, a communications interface, a memory, and a communication bus. Among them, the processor, the communications interface, and the memory complete communication with each other through the communication bus; the processor can call the logical instructions in the memory, and when the logical instructions in the memory can be implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium.

[0040] Embodiment 3 Embodiment 3 of the present application provides a computer program product. The computer program product includes a computer program stored on a non-transitory computer-readable storage medium. The computer program includes program instructions. When the program instructions are executed by a computer, the computer can execute the steps of the above-mentioned automatic routing method.

[0041] Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods in various embodiments of the present invention. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs that can store program codes.

[0042] Based on such an understanding, the above-mentioned technical solution, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disks, optical discs, etc., and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods of various embodiments or certain parts of the embodiments.

[0043] The present application obtains the configuration information of the IP core and the port information of each IP core by parsing the source language file, automatically completes the splicing between the IP soft core and the peripheral IP core, generates a first configuration file, then generates a script file based on the first configuration file, performs automatic routing based on the script file, improves the test requirements of testers for different circuits, speeds up the test process, and improves the test efficiency.

[0044] Some commonly used English nouns or letters adopted for the sake of clear description in the present invention are only used for exemplary reference rather than limiting interpretation or specific usage, and the protection scope of the present invention should not be limited by their possible Chinese translations or specific letters.

[0045] It should also be noted that in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

Claims

1. An automatic wiring method, characterized in that, Including: Obtain the source language of the IP core, generate a source language file, where the IP core includes an IP soft core and a peripheral IP core; Parse the source language file to obtain the configuration information of the IP core and the port information of each IP core; The IP soft core randomly selects a peripheral IP core for splicing, calculates the bit width according to the connection between ports, and the peripheral IP core randomly connects to the ports of the AXI bus to complete splicing, generating a first configuration file; Generate a script file based on the first configuration file and perform automatic routing based on the script file.

2. The automatic wiring method according to claim 1, characterized in that, The source language file includes a circuit file; Convert the circuit program into a circuit file through FPGA EDA and save it.

3. An automatic wiring method according to claim 2, characterized in that, Parse the source language file to obtain the configuration information and input / output port information of the IP soft core, and assemble them into structured data and store it in a first list file.

4. An automatic wiring method according to claim 2, characterized in that, Parse the circuit file, loop through all peripheral IP cores, extract the input / output port information of the peripheral IP cores and store it in a second list file.

5. An automatic wiring method according to claim 4, characterized in that, The specific process of generating the first configuration file includes: Based on the second list file, construct a dictionary storing the port information of the peripheral IP cores, fix the port parameters of the IP soft core, randomly select the clock port and reset key of the peripheral IP core by the IP soft core for connection, calculate the bit width according to the connection between ports, assemble the input / output port information and parameter information, and write it into the first configuration file.

6. An automatic wiring method according to claim 5, characterized in that, The specific process of generating the first configuration file further includes: The peripheral IP core randomly connects to the ports of the AXI bus, and calculates the bit width corresponding to the peripheral IP core through the port values of the AXI bus randomly connected by the peripheral IP core; The AXI bus has a total of 16 ports.

7. An automatic wiring method according to claim 6, characterized in that The first configuration file is a bd.v file.

8. An automatic wiring method according to claim 7, characterized in that, Based on the first configuration file, obtain the ports of the IP soft core and the peripheral IP core, and generate a top-level file for verifying the correctness of the process; The script file includes: the first configuration file and the top-level file.

9. An automatic wiring method according to claim 1, characterized in that, Modify the configuration information of the peripheral IP core by modifying the circuit file.

10. An automatic wiring method according to claim 1, characterized in that, The IP soft core is a risc-v soft core.

11. A computer device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the automatic routing method described in any one of claims 1 to 10.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the automatic routing method described in any one of claims 1 to 10.

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