Layout layout method and device based on constraint rule functionalization and layer detection

Abstract

The invention relates to a layout method and device based on constraint rule functionalization and layer detection. The method comprises the following steps: acquiring a circuit netlist of a target process; performing device initialization according to the circuit netlist, and generating initial models of all devices; reading a PDK file of a target process, extracting a DRC constraint rule based on the PDK file, and forming a rule function; any device in the circuit netlist is read; entering a parameter modification stage of the device, judging whether the device has a parameter modification requirement or not, if so, performing parameter modification and packaging, and if not, not performing parameter modification; and after the parameter modification stage is completed, carrying out layout through a layer detection layout algorithm. According to the layout method and device based on constraint rule functionalization and layer detection, the layout result which is high in area utilization rate, free of DRC report errors and capable of directly entering the next production process can be generated.

Description

Technical Field

[0001] The present invention relates to the technical field of layout, and in particular, to a layout method and device based on constraint rule functionalization and layer detection. Background Art

[0002] The automatic layout of analog integrated circuit layouts is still in a relatively early stage. Compared with digital integrated circuits where layout design automation and commercialization have already been achieved, there are still many problems in the automatic layout technology of analog integrated circuit layouts. Among them, the more obvious one is that while pursuing area utilization, it is difficult to ensure that the devices meet the DRC constraints in the PDK, and it is easy to generate DRC errors in the hierarchical spacing; in addition, the automatically generated layout results are difficult to meet the layout grid points required for actual chip production, and the automatically generated layout is difficult to be put into actual use. Summary of the Invention

[0003] The purpose of the present invention is to at least solve one of the deficiencies of the prior art, and provide a layout method and device based on constraint rule functionalization and layer detection.

[0004] To achieve the above purpose, the present invention adopts the following technical solutions: Specifically, a layout method based on constraint rule functionalization and layer detection is proposed, including the following: Obtain the circuit netlist of the target process; Perform device initialization according to the circuit netlist to generate initial models of all devices, and the initial models only include the outermost size bounding box of the corresponding devices; Read the PDK file of the target process, extract the DRC constraint rules based on the PDK file and form rule functions, and the rule functions are used to extract the information of all layers in the current device according to the type of the current device to form a device black box, and the device black box includes the outermost size bounding box of the current device and the information of each layer inside the current device; Read any one device in the circuit netlist; Enter the parameter modification stage of the device, determine whether the device has a parameter modification requirement, if so, perform parameter modification and encapsulation, if not, no parameter modification is required; After completing the parameter modification stage, perform layout through the layer detection layout algorithm.

[0005] Further, specifically, determining whether the device has a parameter modification requirement includes, Call the rule function formed by the device, and determine the parameter modification requirement of the device based on the current rule function.

[0006] Further, specifically, the packaging method includes, The packaging is done by the following formula: , Where w and h are the width and height of the device respectively, d0 is the distance for packaging the device, and using twice the d0 ensures that the device is packaged on all sides.

[0007] Further, specifically, the layout is performed by using a layer detection layout algorithm, including: Step 1: extract all layers of the device according to the device black box of the device, determine and extract the layers that need to be tested for interlayer spacing among all the layers, and retain the layer with the largest area, i.e., the outermost layer; Step 2: for the extracted layers that need to be tested for inter-layer spacing and the layer with the largest area, i.e., the outermost layer, the remaining layers are obtained by ignoring the layers other than these layers where devices have been laid out on the layout; Step 3, for the outermost layer of the remaining layers of the device, perform the following operations: place the layer at each position of the layout position list on the layout canvas, detect whether overlap occurs, i.e., outermost layer crossover occurs; if overlap occurs, remove the overlapping position to obtain the remaining positions in the layout position list; Step 4: For other layers in the remaining layers of the device, the operation in step 3 is performed. In addition, other layers that subsequently perform the operation only need to detect the remaining positions in the layout position list. The remaining positions obtained after performing the operation on all positions in the layout position list of the device are recorded as a feasible layout position list. Step 5: According to the list of feasible layout positions, calculate the layout area of each position after the device is placed therein, and select the position with the smallest layout area as the layout position of the device; Step 6: fine-tune the layout position based on the grid point standard required in actual production to complete the layout of the device.

[0008] Furthermore, the method further comprises, in step 5, If there are multiple positions with the smallest layout area at the same time, the position with the smallest area in the lower left corner is selected as the layout position of the device.

[0009] Further, specifically, in step 6, the layout position is fine-tuned based on the grid point standard required in actual production, including: It is determined whether the layout position meets the grid point standard required in actual production, that is, a multiple of 0.05. If it does, no adjustment is made. If it does not, fine-tune it to a multiple of 0.05.

[0010] The present invention also proposes a layout device based on constraint rule functionalization and layer detection, comprising the following: A data acquisition module, configured to acquire a circuit netlist of a target process; An initialization module, configured to perform device initialization according to the circuit netlist to generate initial models of all devices, where the initial model only includes the outermost dimension bounding box of the corresponding device; A rule function generation module, configured to read a PDK file of a target process, extract DRC constraint rules based on the PDK file and form a rule function, where the rule function is used to extract information of all layers in the current device according to the type of the current device to form a device black box, and the device black box includes the outermost dimension bounding box of the current device and information of each layer inside the current device; A data reading module, configured to read any one device in the circuit netlist; A parameter modification module, configured to determine whether there is a parameter modification requirement for the device. If so, perform parameter modification and encapsulation. If not, no parameter modification is required; A layout module, configured to perform layout by a layer detection layout algorithm after completing the parameter modification stage.

[0011] The beneficial effects of the present invention are as follows: The present invention provides a layout method and device for a layout based on constraint rule functionalization and layer detection. Aiming at the problems in the current automatic layout method for analog integrated circuit layouts, such as difficulty in meeting DRC constraint rules, unavoidable error reporting, and insufficient granularity of layout results, a legal constraint rule function is constructed, the DRC constraint rules are parameterized, a black box is applied to the device, layer detection layout is performed, and the layout result of the device is automatically fine-tuned to generate a layout with no DRC errors and high area utilization rate. Description of the Drawings

[0012] By elaborating on the embodiments shown in combination with the drawings, the above and other features of the present disclosure will become more obvious. The same reference numerals in the drawings of the present disclosure represent the same or similar elements. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts. In the drawings: Figure 1 Shows a schematic structural diagram of a layout device for a layout based on constraint rule functionalization and layer detection according to the present invention; Figure 2 Shows a flowchart of a layout method for a layout based on constraint rule functionalization and layer detection according to the present invention; Figure 3 Shows an example diagram of a device black box formed in the present invention. Detailed Embodiments

[0013] The concept, specific structure and technical effects of the present invention will be clearly and completely described below in conjunction with the embodiments and the drawings, so as to fully understand the purpose, solution and effects of the present invention. It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The same reference numerals used throughout the drawings indicate the same or similar parts.

[0014] Example 1, referring to Figure 1 , the present invention proposes a layout method for a layout based on constraint rule functionalization and layer detection, including the following: Step 110, obtain the circuit netlist of the target process; Step 120, perform device initialization according to the circuit netlist to generate initial models of all devices, and the initial models only include the outermost dimensions (bounding box) of the corresponding devices; First, the algorithm reads in the circuit netlist and, according to the device parameters written in the circuit netlist, performs device initialization to generate the initial models of the devices. The initial models only include the outermost dimensions (bounding box) of the devices. Step 130, read the PDK file of the target process, extract the DRC constraint rules based on the PDK file and form a rule function, and the rule function is used to extract the information of all layers in the current device according to the type of the current device to form a device black box. Referring to Figure 3 , the device black box includes the outermost dimensions (bounding box) of the current device and the information of each layer inside the current device; The DRC rules that the present invention focuses on are usually the spacing type and the enclosure type. The spacing type rules are specifically expressed as: the minimum spacing between layer A and layer B is X (A and B can be the same). The generation process of the rule function is to read each DRC spacing type constraint rule in the PDK, save it, and design the input and output interfaces of the function. Then the rule function is actually a model that inputs specific layers A and B and outputs the minimum spacing X, which can be written as spacing X = f(A,B), where A and B can be equal; and the enclosure type DRC constraint rules are met when the device is generated and do not need to be detected again; Taking the metal layers M1, M2, and M3 as an example: the set of layers , the rule function is defined as , then for any , the rule function f represents the minimum spacing between layer A and layer B. Assuming that the rules for these three layers in the PDK are: the minimum spacing between M1 and M1 layers is 0.25u, the minimum spacing between M2 and M2 layers is 0.28u, and the minimum spacing between M3 and M3 layers is 0.30u, then the rule function is constructed as , In practice, the rule functions are often more complex, perhaps up to dozens or hundreds, and the corresponding processing can be carried out according to the above example.

[0015] Step 140: Read any device in the circuit netlist. Step 150: Enter the parameter modification stage of the device, determine whether there is a parameter modification requirement for the device. If there is, perform parameter modification and encapsulation. If not, no parameter modification is required. Step 160: After completing the parameter modification stage, perform layout of the layout by the layer detection layout algorithm.

[0016] In the first embodiment, aiming at the problems in the current automatic layout method of analog integrated circuit layout, such as difficult to meet DRC constraint rules, difficult to avoid error reporting, and insufficient granularity of the layout result, a constraint rule legal function is constructed, the DRC constraint rule is parameterized, a black box is applied to the device, layer detection layout is performed, and the layout result of the device is automatically fine-tuned to generate a layout with no DRC errors and high area utilization rate.

[0017] As a preferred embodiment of the present invention, specifically, determining whether there is a parameter modification requirement for the device includes Calling the rule function formed by the device, and determining the parameter modification requirement of the device based on the current rule function.

[0018] As a preferred embodiment of the present invention, specifically, the encapsulation method includes Encapsulation is performed through the following formula , where w and h are the width and height of the device respectively, and d0 is the distance for encapsulating the device. 2 times of d0 is used to ensure that the device is encapsulated on all sides.

[0019] In this preferred embodiment, taking the nch_ull device as an example, since it needs to be at least 3um away from other devices, the rule function will give the device spacing dm = 3u, and the device is parameter-modified and encapsulated.

[0020] Refer to Figure 2 , as a preferred embodiment of the present invention, specifically, performing layout of the layout by the layer detection layout algorithm includes Step 1: According to the device black box of the device, extract all layers of the device, judge and extract the layers that need to perform layer spacing detection among all layers, and at the same time retain the layer with the largest area, that is, the outermost layer. Step 2: For the layers that have been extracted and need to perform layer spacing detection and the layer with the largest area, that is, the outermost layer, ignore the non-layers of the devices already laid out on the layout to obtain the remaining layers. Step 3: For the outermost layer among the remaining layers of the device, perform the operation: Place this layer at each position in the layout position list on the layout drawing canvas, and detect whether there will be an overlap, that is, whether the outermost layer crosses. If there is an overlap, remove the overlapping positions to obtain the remaining positions in the layout position list. Step 4: For the other layers among the remaining layers of the device, perform the operation in Step 3. Additionally, for the other layers that subsequently perform this operation, only detect the remaining positions in the layout position list. The remaining positions obtained after performing this operation on all positions in the layout position list of the device are denoted as the feasible layout position list. Step 5: According to the feasible layout position list, calculate the layout area of the layout drawing of the device at each position therein, and select the position with the smallest layout area as the layout position of the device. Step 6: Fine-tune the layout position based on the grid point standard required in actual production to complete the layout of the device.

[0021] As a preferred embodiment of the present invention, the method further includes that in Step 5, If there are multiple positions with the smallest layout area at the same time, then select the position with the smallest area in the bottom left corner as the layout position of the device.

[0022] As a preferred embodiment of the present invention, specifically, in Step 6, the fine-tuning of the layout position based on the grid point standard required in actual production includes, Judge whether the layout position meets the grid point standard required in actual production, that is, a multiple of 0.05. If it meets, no adjustment is made. If it does not meet, fine-tune it to a multiple of 0.05.

[0023] Specifically, the layer detection layout algorithm process is as follows: 1) First, according to the black box of the current device, extract all layers of the current device, judge and extract the layers that need to perform layer spacing detection, and at the same time retain the layer with the largest area (that is, the outermost layer). For example, if the minimum spacing required for layer A is 0.28 and the distances between layer A and the four boundaries of the outermost layer of the device are all greater than or equal to 0.28, then it can be considered that layer A does not need to perform layer spacing detection.

[0024] 2) For the layers that have been extracted and need to perform layer spacing detection and the layer with the largest area of the device (that is, the outermost layer), ignore the non - these layers of the devices already laid out on the layout drawing. It should be noted that this operation will not affect the outermost layer of the devices already laid out on the layout drawing. Then, we obtain the layout situation of the layout drawing for each layer layer of the device.

[0025] 3) Next, perform specific layout position screening. First, for the outermost layer of the device, perform the operation: place this layer at each position on the layout canvas and detect whether there will be overlap (i.e., outermost layer crossing). If there is overlap, eliminate these positions. Based on this, a preliminary list of feasible layout positions is obtained.

[0026] 4) Next, for each layer of the current device, perform the operation in step 3). It should be noted that for subsequent layers of the device, only the positions in the already screened layout position list need to be detected, which greatly reduces the hardware consumption.

[0027] 5) According to the list of feasible layout positions, calculate the layout area of the layout of the current device at each position, and select the position with the smallest area as the device layout position. When there are multiple positions with the smallest area, select the position with the smallest area in the bottom left corner.

[0028] 6) Detect the layout result position of the device and determine whether its position meets the grid points required in actual production, that is, a multiple of 0.05. If not, fine-tune the device layout result to reach a multiple of 0.05 to complete the layout of the device.

[0029] 7) After the device layout is completed, detect whether the layout of all devices in the netlist has been completed. If it is completed, the algorithm ends and the layout result is output; if not, repeat step 1).

[0030] The present invention also proposes a layout device for a layout based on constraint rule functionalization and layer detection, including the following: A data acquisition module for acquiring a circuit netlist of a target process; An initialization module for initializing devices according to the circuit netlist to generate initial models of all devices, where the initial models only contain the outermost layer dimensions bounding box of the corresponding devices; A rule function generation module for reading a PDK file of a target process, extracting DRC constraint rules based on the PDK file and forming a rule function, where the rule function is used to extract information of all layers in the current device according to the type of the current device to form a device black box, and the device black box includes the outermost layer dimensions bounding box of the current device and information of each layer inside the current device; A data reading module for reading any device in the circuit netlist; A parameter modification module for determining whether the device has a parameter modification requirement. If so, perform parameter modification and encapsulation. If not, no parameter modification is required; A layout module for performing layout of the layout through a layer detection layout algorithm after completing the parameter modification stage.

[0031] In addition, in each embodiment of the present invention, each functional module can be integrated into a processing module, or each module can exist physically alone, or two or more modules can be integrated into one module. The above-mentioned integrated module can be implemented in the form of hardware or in the form of a software functional module.

[0032] If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, to implement all or part of the processes in the above-mentioned embodiment methods of the present invention, it can also be completed by a computer program instructing relevant hardware. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by a processor, the steps of the above-mentioned various method embodiments can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in the form of source code, object code, executable file or some intermediate form, etc. The computer-readable medium can include: any entity or system, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disc, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal, and software distribution medium, etc., that can carry the computer program code.

[0033] Although the description of the present invention has been quite detailed and several of the described embodiments have been described in particular, it is not intended to be limited to any of these details or embodiments or any particular embodiment, but should be regarded as providing a broad interpretation of these claims in light of the prior art by reference to the appended claims, thereby effectively covering the intended scope of the present invention. In addition, the present invention has been described above with embodiments foreseeable by the inventor for the purpose of providing a useful description, and non-substantive modifications to the present invention that are not currently foreseeable can still represent equivalent modifications of the present invention.

[0034] As mentioned above, these are only the preferred embodiments of the present invention. The present invention is not limited to the above-mentioned implementation manners. As long as it achieves the technical effects of the present invention by the same means, it should fall within the protection scope of the present invention. Within the protection scope of the present invention, various different modifications and variations can be made to its technical solutions and / or implementation manners.

Claims

1. A layout method based on constraint rule functionalization and layer detection, characterized in that The following are included: Obtain the circuit netlist of the target process; Perform device initialization according to the circuit netlist to generate initial models of all devices, where the initial model only contains the outermost dimension bounding box of the corresponding device; Read the PDK file of the target process, extract DRC constraint rules based on the PDK file and form a rule function, where the rule function is used to extract information of all layers in the current device according to the type of the current device to form a device black box, and the device black box includes the outermost dimension bounding box of the current device and information of each layer inside the current device; Read any one device in the circuit netlist; Enter the parameter modification stage of the device, determine whether there is a parameter modification requirement for the device, if so, perform parameter modification and encapsulation, if not, no parameter modification is required; After completing the parameter modification stage, perform layout by the layer detection layout algorithm.

2. A layout method based on constraint rule functionalization and layer detection according to claim 1, characterized in that, Specifically, determine whether there is a parameter modification requirement for the device, including, Call the rule function formed by the device, and determine the parameter modification requirement of the device based on the current rule function.

3. The layout method based on constraint rule functionalization and layer detection according to claim 2, characterized in that Specifically, the encapsulation method includes, Perform encapsulation through the following formula, ， where w and h are the width and height of the device respectively, and d0 is the distance for encapsulating the device.

4. A layout method based on constraint rule functionalization and layer detection according to claim 1, characterized in that Specifically, performing layout by the layer detection layout algorithm includes, Step 1: According to the device black box of the device, extract all layers of the device, judge and extract the layers that need to perform layer spacing detection among all layers, and at the same time retain the layer with the largest area, that is, the outermost layer; Step 2: For the layers that have been extracted and need to perform layer spacing detection and the outermost layer with the largest area, ignore the non - these layers of the devices already laid out on the layout to obtain the remaining layers; Step 3: For the outermost layer among the remaining layers of the device, perform the operation: place this layer at each position in the layout position list on the layout canvas, detect whether there will be an overlap, that is, the outermost layer crossing. If an overlap occurs, remove the overlapping positions to obtain the remaining positions in the layout position list; Step 4: For other layers among the remaining layers of the device, perform the operation in Step 3. In addition, for the other layers that perform the subsequent operation, only need to detect the remaining positions in the layout position list. The remaining positions obtained after performing the operation at all positions in the layout position list of the device are recorded as the feasible layout position list; Step 5: According to the feasible layout position list, calculate the layout area of the device at each position, and select the position with the smallest layout area as the layout position of the device; Step 6: Fine - tune the layout position based on the grid standard required in actual production to complete the layout of the device.

5. A layout method based on constraint rule functionalization and layer detection according to claim 4, characterized in that The method further includes, in Step 5, If there are multiple positions with the smallest layout area at the same time, select the position with the smallest area in the bottom - left corner as the layout position of the device.

6. The layout method based on constraint rule functionalization and layer detection according to claim 4, characterized in that Specifically, in Step 6, fine - tuning the layout position based on the grid standard required in actual production includes, Determine whether the layout position meets the grid standard required in actual production, i.e., a multiple of 0.

05. If it meets, no adjustment is made. If it does not meet, fine-tuning is performed to reach a multiple of 0.

05.

7. An apparatus for layout of a layout based on constraint rule functionalization and layer detection, characterized in that It includes the following: A data acquisition module for acquiring the circuit netlist of the target process; An initialization module for initializing devices according to the circuit netlist to generate initial models of all devices, where the initial model only contains the outermost dimension bounding box of the corresponding device; A rule function generation module for reading the PDK file of the target process, extracting DRC constraint rules based on the PDK file to form a rule function, and the rule function is used to extract information of all layers in the current device according to the type of the current device to form a device black box, and the device black box includes the outermost dimension bounding box of the current device and the information of each layer inside the current device; A data reading module for reading any one device in the circuit netlist; A parameter modification module for determining whether there is a need to modify the parameters of the device. If so, the parameters are modified and encapsulated. If not, no parameter modification is required; A layout module for performing layout through a layer detection layout algorithm after completing the parameter modification stage.

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