Evaluation method of high-speed link system, electronic device and non-transitory storage medium

Abstract

The present application discloses an evaluation method, an electronic device, and a non-transitory storage medium for a high-speed link system, relating to the field of high-speed electronic interconnection technology. The application proposes setting a cutting plane at the geometric height center of an electrical connection structure as the boundary position for sub-link simulation and cascading, so that the impedance discontinuities and parasitic effects that actually exist in the structure can be fully incorporated into the simulation evaluation, thereby making up for the deficiency of the traditional segmented cascade method in reflecting the actual electromagnetic behavior of the interconnection structure. Thus, while improving the simulation accuracy, it also takes into account the modeling efficiency and engineering practicality. The application can be widely used in the performance evaluation and optimization design of various high-speed packaging interconnection systems.

Description

Technical Field

[0001] The present application relates to the field of high-speed electronic interconnection technology, and in particular to an evaluation method, an electronic device, and a non-transitory storage medium for a high-speed link system. Background Art

[0002] In the prior art, those skilled in the art set the cascade boundary at the top / bottom edge of the bump or solder ball, artificially dividing the different structural segments. This prevents the discontinuity of electromagnetic behavior at the connection from being incorporated into the simulation model. This modeling approach ignores the impedance discontinuity, capacitive / inductive coupling, and surface effects caused by the bump and / or solder ball acting as structural mutation points. As a result, the scattering parameters extracted by the simulation do not conform to the actual signal propagation state during cascading. The evaluation results contain systematic errors and cannot accurately reflect the actual signal integrity issues in high-speed links. Furthermore, in the prior art, high-frequency signal transmission faces common challenges such as significant skin effect, increased reflection and loss, and increased difficulty in electromagnetic compatibility (EMC) design. Summary of the Invention

[0003] The present application provides a high-speed link system evaluation method, an electronic device, and a non-transitory storage medium to at least solve the problem in the related art that the true signal integrity in a high-speed link is difficult to accurately evaluate.

[0004] This application provides a high-speed link system evaluation method, including:

[0005] Establish a topology model for a high-speed link system and analyze the link structure in the topology model;

[0006] identifying a location of an electrical connection structure of the link structure and determining parameters of the electrical connection structure;

[0007] A cutting plane is set at the height geometric center of each electrical connection structure to divide the topology model into an upper sub-link and a lower sub-link, and the upper sub-link and the lower sub-link are simulated to obtain a first S parameter matrix of the upper sub-link and a second S parameter matrix of the lower sub-link, wherein the cutting plane is perpendicular to the height direction of the link structure;

[0008] cascading an overall simulated scattering parameter matrix of the link structure based on the first S parameter matrix and the second S parameter matrix, and determining at least one channel characteristic simulation parameter of the link structure based on the overall simulated scattering parameter matrix; and

[0009] Based on at least one channel characteristic simulation parameter, the parameters of the electrical connection structure are iteratively optimized and the simulation is repeated until the link structure meets the link requirements.

[0010] The present application also provides an evaluation device for a high-speed link system, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the above-mentioned evaluation method for the high-speed link system are implemented.

[0011] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of the above-mentioned high-speed link system evaluation method when executing the computer program.

[0012] The present application also provides a non-transitory computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned high-speed link system evaluation method are implemented.

[0013] The present application also provides a computer program product, including a computer program, which implements the steps of the above-mentioned high-speed link system evaluation method when executed by a processor.

[0014] This application innovatively proposes setting a cutting plane at the geometric height center of electrical connection structures such as bumps and / or solder balls as the boundary position between sub-link simulation and cascade, so that the impedance discontinuities and parasitic effects that actually exist in the structure can be fully incorporated into the simulation evaluation, making up for the deficiency of the traditional segmented cascade method in reflecting the actual electromagnetic behavior of the interconnection structure. While improving the simulation accuracy, it also takes into account modeling efficiency and engineering practicality, and can be widely used in the performance evaluation and optimization design of various high-speed packaging interconnection systems. Furthermore, the actual measured data verification shows that the evaluation method of this application is not only highly close to the physical measured curve in the frequency domain evaluation results, but also has the advantages of simple modeling, high simulation efficiency, and strong versatility of the evaluation process, effectively improving the prediction ability and reliability of structural-level signal integrity in the design stage of high-speed link systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0016] Figure 1 It is an interconnection structure of high-speed links in the existing technology;

[0017] Figure 2 A flowchart of a high-speed link system evaluation method provided in an embodiment of the present application;

[0018] Figure 3A diagram illustrating the discontinuity of waves at the top / bottom edges of differential signal solder balls in electric field simulation, which is involved in the evaluation method for a high-speed link system provided by an embodiment of the present application;

[0019] Figure 4 A diagram illustrating the discontinuity of waves at the top / bottom edges of differential signal solder balls in a magnetic field simulation involved in the evaluation method for a high-speed link system provided by an embodiment of the present application;

[0020] Figure 5 A diagram illustrating a method for cutting bumps / solder balls in a high-speed link system evaluation method provided by an embodiment of the present application;

[0021] Figure 6 A diagram comparing the insertion loss evaluation results and test results in the high-speed link system evaluation method provided in an embodiment of the present application;

[0022] Figure 7 This is a diagram comparing the return loss evaluation results and test results in the high-speed link system evaluation method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0023] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0024] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0025] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0026] In the current design process for high-speed link systems, the chip, package substrate, and printed circuit board are typically designed, verified, and delivered separately by different suppliers. Therefore, when evaluating the performance of the entire high-speed link, system designers often treat the chip, package, and PCB layers as independent modules and cascade and stitch together simulation models of each sub-link to estimate overall signal integrity. However, this traditional cascaded evaluation approach has significant limitations when dealing with the interface between bumps and solder balls.

[0027] In modern high-speed communication systems, the electrical interconnects between the chip (silicon), package substrate (package substrate), and printed circuit board (PCB) are crucial for achieving stable, high-speed signal transmission. Bumps are typically used to connect the chip to the package substrate, while solder balls are used to connect the package substrate to the PCB. This type of interconnect is widely used in packaging solutions such as BGA (Ball Grid Array), FCBGA (Flip Chip BGA), and WLCSP (Wafer-Level Chip Scale Package). In these high-speed link systems, bumps and solder balls are typical electrical connection structures, and their geometry, material properties, and layout all affect signal transmission characteristics. In multilayer interconnect structures, particularly where bumps and solder balls are located at the interface between upper and lower layers of the system, their electromagnetic properties can lead to complex changes in the transmission performance of the entire link.

[0028] In the prior art, those skilled in the art set the cascade boundary at the top / bottom edge of the bump or solder ball, that is, artificially dividing the different structural segments, so that the discontinuity of the electromagnetic behavior at the connection point is not incorporated into the simulation model. This modeling method ignores the impedance discontinuity, capacitance / inductance coupling and surface effects caused by the bump and / or solder ball as a structural mutation point, resulting in the scattering parameters extracted by the simulation not being consistent with the actual signal propagation state during cascading. The evaluation results have systematic errors and are difficult to accurately reflect the actual signal integrity issues in high-speed links.

[0029] The following combination Figure 1 The interconnection structure of high-speed links in the prior art is described.

[0030] Figure 1 It is an interconnection structure of high-speed links in the existing technology.

[0031] like Figure 1As shown, in the prior art, bumps are typically used to interconnect the chip and the package substrate, while solder balls are used to connect the package substrate and the PCB. Bumps / solder balls are discontinuities in signal transmission, significantly impacting the signal. First, they increase signal transmission loss. Furthermore, as the medium connecting electronic components to the circuit board, the material and connection quality of the bumps / solder balls can affect signal transmission. If the connection between the bumps / solder balls and the pins or pads is cold or loose, the contact resistance increases. According to Ohm's law, when current flows, a voltage drop is generated across the contact resistance, causing signal amplitude attenuation and increased signal transmission loss. Furthermore, during high-frequency signal transmission, the skin effect causes the current to concentrate on the surface of the conductor. High-frequency signal transmission faces common challenges such as significant skin effect, increased reflections and losses, and increased difficulty in electromagnetic compatibility (EMC) design.

[0032] To this end, the present invention proposes a method for evaluating a high-speed link system, an evaluation device for a high-speed link system, an electronic device, a non-transitory computer-readable storage medium, and a computer-readable product. The method for evaluating a high-speed link system is based on cascade modeling of plane cutting at the geometric height of bumps / solder balls, with the middle of the bumps and / or solder balls set as the sub-link cutting interface. Since the impedance at both ends of the cutting surface tends to be continuous, and the electric and magnetic field changes are in the transmission state, it can better meet the scattering parameter cascade principle, thereby fully incorporating signal discontinuities into the evaluation model at the structural level, improving simulation accuracy. Based on the upper and lower sub-link S parameter matrices extracted by this method, the overall link simulation results formed after cascade combination can more realistically reflect key indicators such as insertion loss, return loss, and impedance disturbance caused by bumps and / or solder balls. Due to the systematic modeling of the link topology of the chip, package substrate, and PCB layer, combined with key connection nodes such as bumps and solder balls, and setting a cutting surface at their height geometric center, it is physically divided into upper and lower sub-links, more accurately reflecting the boundary conditions and discontinuities of electromagnetic behavior. Furthermore, high-frequency electromagnetic simulations are performed on the upper and lower sub-links respectively to extract scattering parameters. The parameters are cascaded using the two-port network cascade principle to obtain the transmission characteristics of the entire link, thereby avoiding problems such as high simulation complexity and inaccurate boundaries caused by one-time modeling of the entire link.

[0033] Furthermore, verification of measured data shows that the mid-plane cutting cascade method is not only highly close to the physically measured curve in frequency domain evaluation results, but also has the advantages of simple modeling, high simulation efficiency, and strong versatility of evaluation process, effectively improving the prediction ability and reliability of structural-level signal integrity in the design stage of high-speed link systems.

[0034] In conjunction with the specific application environment architecture or specific hardware architecture on which the execution of the evaluation method for the high-speed link system depends, the specific application environment architecture or specific hardware architecture is described herein.

[0035] The evaluation method of this high-speed link system is applicable to at least high-speed electronic systems with the following typical structures, for example, a system on chip (SoC) or a high-performance processor chip that outputs high-speed differential signals; the packaging substrate may be a multi-layer BT resin board or ABF board with internal integrated vias, traces, ground layers, etc.; the bottom of the packaging substrate is connected to a multi-layer PCB via solder balls or solder ball arrays; a transceiver controller, a storage unit, or a connector is connected to the PCB, but the high-speed electronic systems to which the embodiments of the evaluation method of this high-speed link system are applicable are not limited to these.

[0036] In addition, the evaluation method of the high-speed link system can utilize at least the following platforms or databases, such as 3D electromagnetic simulation software, protocol specification database, S-parameter matrix processing tool, vector network analyzer (VNA), test fixture and fixture board, precision probe station or package socket, and automated comparison and analysis system, but the platforms or databases utilized in the embodiments of the evaluation method of the high-speed link system are not limited to these.

[0037] To this end, an embodiment of the present application provides a method for evaluating a high-speed link system. The method is described in detail in conjunction with the execution flow of the method for evaluating a high-speed link system.

[0038] The following combination Figure 2 The evaluation method of the high-speed link system provided in the embodiment of the present application is described.

[0039] Figure 2 This is a flowchart of a high-speed link system evaluation method provided in an embodiment of the present application.

[0040] like Figure 2 As shown, in some embodiments, it should be noted that the evaluation method of the high-speed link system may include the following steps:

[0041] S1: Establish a topology model for the high-speed link system and analyze the link structure in the topology model;

[0042] S2: Identify the location of the electrical connection structure and determine the parameters of the electrical connection structure;

[0043] S3: Set a cutting plane at the height geometric center of each electrical connection structure to split the topology model into an upper sub-link and a lower sub-link, and simulate the upper sub-link and the lower sub-link to obtain the first S parameter matrix of the upper sub-link and the second S parameter matrix of the lower sub-link. The cutting plane is perpendicular to the height direction of the link structure.

[0044] S4: cascading an overall simulated scattering parameter matrix of the link structure based on the first S parameter matrix and the second S parameter matrix, and determining at least one channel characteristic simulation parameter of the link structure based on the overall simulated scattering parameter matrix; and

[0045] S5: Based on at least one channel characteristic simulation parameter, iteratively optimize the parameters of the electrical connection structure and traverse the simulation until the link structure meets the link requirements.

[0046] Specifically, with respect to S1, in some embodiments, it should be noted that the evaluation method of the high-speed link system may also include: the topological model may include at least a chip layer, a packaging substrate layer, and a printed circuit board layer, and the electrical connection structure includes at least one of a bump and a solder ball, but the topological model of the present application is not limited to this.

[0047] More specifically, with respect to S1, for the link structure in the topology model, the planes of the chip layer, the package substrate layer, and the printed circuit board layer can be parallel. Furthermore, the height direction of the link structure can be described as a direction perpendicular to the planes of the chip layer, the package substrate layer, and the printed circuit board layer.

[0048] More specifically, with respect to S1, in some embodiments, it should be noted that the evaluation method of the high-speed link system may also include: the chip layer and the packaging substrate layer may be interconnected through bumps, and the packaging substrate layer and the printed circuit board layer may be interconnected through solder balls, but the interconnection relationship of the present application is not limited to this.

[0049] Specifically, for S2, in some embodiments, it should be noted that the evaluation method of the high-speed link system may also include: the parameters of the electrical connection structure may include at least one of the contact cross-sectional area, vertical height, conductivity, magnetic permeability, relative dielectric constant, and surface roughness, but the parameters of the electrical connection structure of the present application are not limited to this.

[0050] More specifically, it should be noted that the parameters of the electrical connection structure include, but are not limited to, its dimensions and material. The dimensions can be determined based on IPC specifications, BGA package pin size, and the board manufacturer's processing capabilities. In simulations, in addition to the dimensions of the electrical connection structure, another influencing factor is the metal material of the electrical connection structure, such as its electrical conductivity, magnetic permeability, relative permittivity, and surface roughness.

[0051] More specifically, it should be noted that in order to standardize terminology, the so-called dimensions may include but are not limited to concepts such as diameter and height, among which the diameter may be standardized in this application as the contact cross-sectional area, and the height may be standardized in this application as the vertical height, that is, the geometric vertical height perpendicular to the planes of each layer.

[0052] More specifically, it should be noted that factors such as surface roughness and irregular shapes of electrical connection structures can increase high-frequency signal transmission losses. This is because surface irregularities lengthen the current path and reduce the effective conductive area, which in turn increases high-frequency resistance, exacerbates signal attenuation, and can lead to impedance mismatch. Improper size, shape, or soldering positions of electrical connection structures can cause changes in the characteristic impedance of the signal transmission line, resulting in impedance mismatch.

[0053] More specifically, when a signal encounters an impedance discontinuity during transmission, part of the signal is reflected back, forming a reflected wave. This reflected wave, superimposed on the original signal, can produce overshoot, undershoot, and ringing in the time domain, affecting signal integrity and disrupting normal transmission and reception. It can also cause electromagnetic interference, as current flowing through electrical connections generates a magnetic field.

[0054] More specifically, it's important to note that improper electrical connection layouts or the interaction of currents between multiple electrical connections can generate strong electromagnetic radiation. High-speed signals, with their high frequency of change, generate relatively high levels of electromagnetic radiation, potentially causing electromagnetic interference to surrounding electronic components or signal lines, impacting the system's electromagnetic compatibility.

[0055] More specifically, it should be noted that electromagnetic coupling may occur between adjacent electrical connection structures. When the signal current in one electrical connection structure changes, it generates a changing magnetic field in the surrounding area. This magnetic field may induce an electromotive force in adjacent electrical connection structures, thereby generating interference signals. This electromagnetic coupling is particularly pronounced in high-density packaged electronic devices, and may cause crosstalk between signals, reducing signal quality and reliability.

[0056] Specifically, with respect to S3, in some embodiments, it should be noted that the evaluation method of the high-speed link system may further include: setting a cutting plane at the height geometric center along each electrical connection structure.

[0057] The following combination Figure 3 and Figure 4 The present invention describes the discontinuity of waves at the top / bottom edges of differential signal solder balls in electric field / magnetic field simulation involved in the evaluation method of a high-speed link system provided by an embodiment of the present application.

[0058] Figure 3 This is a diagram illustrating the discontinuity of waves at the top / bottom edges of differential signal solder balls in electric field simulation, which is involved in the evaluation method for a high-speed link system provided by an embodiment of the present application.

[0059] Figure 4This is a diagram illustrating the discontinuity of waves at the top / bottom edges of differential signal solder balls in a magnetic field simulation involved in the evaluation method for a high-speed link system provided by an embodiment of the present application.

[0060] In some embodiments, it should be noted that the discontinuity of the electrical connection structure only occurs at the connection interface between the solder ball and the pad of the package substrate / printed circuit board PCB, while the transmission of the signal wave is continuous along the actual solder ball surface. Figure 3 and Figure 4 , simulating the transmission of waves at the top / bottom edges of the differential signal solder balls, the simulated electric field (E-field) and magnetic field (H-field) clearly show that regardless of whether the pad and solder ball are the same size, there is a waveform discontinuity at the solder ball-pad interface. In the full-wave channel simulation, such discontinuities will be fully included in the entire module to ensure consistency with the actual results. However, when a cutting plane is selected at the solder ball-pad interface, the port impedance on both sides is different, which will lead to waveform discontinuity.

[0061] Furthermore, the following Figure 5 The present invention describes a method for cutting bumps / solder balls in a high-speed link system evaluation method provided by an embodiment of the present application.

[0062] Figure 5 This is a diagram illustrating a method for cutting bumps / solder balls in a high-speed link system evaluation method according to an embodiment of the present application.

[0063] Reference Figure 5 In some embodiments, it should be noted that a cutting plane is first used to divide the link into a package substrate and an upper half of the solder ball, and a PCB board and a lower half of the solder ball, and then the two parts after cutting are cascaded. This cutting method can fully evaluate the discontinuous characteristics of the solder ball contact points, making the cascade method more accurate.

[0064] Specifically, for S3, in some embodiments, it should be noted that the evaluation method of the high-speed link system may also include: using high-frequency electromagnetic simulation software to set the port type, port impedance, frequency domain scanning range, and step size to simulate the upper sub-link and the lower sub-link.

[0065] More specifically, in some embodiments, the port type can be set to a wave port or a lumped port, the port impedance can be set to 50Ω, the frequency domain scanning range can be set to 0GHz to 60GHz, and the step size can be set to 10MHz to simulate the upper sub-link and the lower sub-link, but the embodiments of the present application are not limited to this.

[0066] In addition, it should be noted that the modeling and simulation parameters can be confirmed with the board manufacturer based on the BGA pin size, pin pitch, and IPC specifications. The pad pich spacing is very small, for example, it can be 0.6-0.8mm, and the solder ball size is even smaller, and its tolerance requirement is within the order of 0.05, so it will not have a significant impact on the accuracy.

[0067] Specifically, with respect to S4, in some embodiments, it should be noted that the evaluation method of the high-speed link system may also include: converting the first S parameter matrix and the second S parameter matrix into a simulation mixed parameter matrix based on the two-port network cascade principle, and performing matrix multiplication and inverse transformation on the simulation mixed parameter matrix to obtain an overall simulation scattering parameter matrix.

[0068] Specifically, with respect to S4, in some embodiments, it should be noted that the evaluation method of the high-speed link system may further include: at least one channel characteristic simulation parameter may at least include characteristic impedance, insertion loss or return loss.

[0069] More specifically, regarding S4, in some embodiments, it should be noted that impedance mismatch can cause time-domain distortions such as signal reflections, overshoot, and ringing, impacting signal integrity. Excessive insertion loss indicates severe link power attenuation, potentially preventing the minimum signal level at the receiving end, and reducing bit error rate performance. Furthermore, low return loss indicates severe reflections, leading to multiple reflections, crosstalk, and signal distortion. Therefore, quantitative calculation of impedance and loss can ensure that the link meets both signal attenuation thresholds and reflection indicators within a specific frequency range, ensuring reliable system operation.

[0070] More specifically, in some embodiments, it should be noted that the at least one channel characteristic simulation parameter may also include link crosstalk and input impedance.

[0071] Specifically, with respect to S5, in some embodiments, it should be noted that the evaluation method of the high-speed link system may further include: determining whether at least one channel characteristic simulation parameter meets the threshold requirements of various channel characteristic parameters in the high-speed protocol or design specification.

[0072] Specifically, for S5, based on the limit requirements for IL, RL, and impedance deviation in the corresponding high-speed protocol or design specification, the threshold requirements can be set to IL ≤3dB within 0~20 GHz; RL ≥15dB within 0~20 GHz; and impedance deviation ≤±5%, but obviously, the embodiments of the present application are not limited to this.

[0073] More specifically, with respect to S5, in some embodiments, it should be noted that the evaluation method of the high-speed link system may further include: when the insertion loss exceeds the threshold requirement, reducing the routing length of the link structure, or changing the laminate material.

[0074] For example, when the insertion loss exceeds the threshold requirement, high-speed circuit materials with lower dielectric loss tangent, more stable dielectric constant (εr), and low surface roughness (low Ra) can be selected to reduce the insertion loss IL caused by the dielectric, thereby improving the high-frequency transmission performance of the link.

[0075] More specifically, with respect to S5, in some embodiments, it should be noted that the evaluation method of the high-speed link system may further include: when the characteristic impedance is lower than the threshold requirement, reducing the contact cross-sectional area of ​​the electrical connection structure such as a bump or a solder ball in steps of 0.1 mm, or increasing the vertical height of the electrical connection structure such as a bump or a solder ball.

[0076] More specifically, with respect to S5, in some embodiments, it should be noted that the evaluation method of the high-speed link system may further include: when the return loss is lower than the threshold requirement, judging the local reflection source based on the resonant frequency and reflection peak position of the return loss curve in the frequency domain.

[0077] More specifically, with respect to S5, in some embodiments, it should be noted that the evaluation method of the high-speed link system may further include: in the case where the electrical connection structure has reflections dominated by parasitic capacitance effects, reducing the contact cross-sectional area of ​​the electrical connection structure such as a bump or a solder ball, or increasing the vertical height of the electrical connection structure such as a bump or a solder ball; or in the case where the electrical connection structure has reflections dominated by inductive coupling effects, increasing the contact cross-sectional area of ​​the electrical connection structure such as a bump or a solder ball, or reducing the vertical height of the electrical connection structure such as a bump or a solder ball.

[0078] The following combination Figure 6 and Figure 7 The following describes a process for further verifying the reliability of the high-speed link system evaluation method provided in an embodiment of the present application.

[0079] Figure 6 This is a diagram comparing the insertion loss evaluation results and test results in the high-speed link system evaluation method provided in an embodiment of the present application.

[0080] Figure 7 This is a diagram comparing the return loss evaluation results and test results in the high-speed link system evaluation method provided in an embodiment of the present application.

[0081] Furthermore, in some embodiments, it should be noted that the evaluation method of the high-speed link system may also include: using a vector network analyzer to test the upper sub-link and the lower sub-link to obtain a third S parameter matrix of the upper sub-link and a fourth S parameter matrix of the lower sub-link; according to the two-port network cascade principle, cascading the third S parameter matrix and the fourth S parameter matrix to obtain the overall measured scattering parameter matrix of the link structure, and based on the overall measured scattering parameter matrix, determining at least one channel characteristic measured parameter of the link structure; respectively comparing the characteristic impedance, insertion loss or return loss among at least one channel characteristic measured parameter with the characteristic impedance, insertion loss or return loss among at least one channel characteristic simulation parameter to determine whether the errors between each simulation curve and each measured curve are within the error range.

[0082] Specifically, to simulate and extract the link S parameters, it is necessary to build a link environment and input the parameters of various components such as stackup, line width, spacing, vias, connectors, cables, etc. The software simulates and extracts the simulated S parameter model of the link, where the simulated insertion loss and return loss can be obtained through the simulated S parameter model; the link is measured using a vector network analyzer (VNA) to obtain the measured S parameter model, where the measured insertion loss and return loss can be obtained through the measured S parameter model.

[0083] For example, the final simulation results are compared with the actual measured results of the link system. If the fit between the two meets the preset accuracy, the evaluation method of the high-speed link system is determined to be accurate and reliable, where the preset accuracy can be set to IL error <0.5dB and RL error <1dB, but the embodiments of the present application are not limited to this.

[0084] Reference Figure 6 and Figure 7 , it can be seen that, in some embodiments, it should be noted that the insertion loss and return loss curves of the cascaded evaluation method of the high-speed link system have a good match with the test results in the frequency range up to 85 GHz, thereby accurately verifying the system signal integrity.

[0085] In some embodiments, the process of the evaluation method of the high-speed link system can also be described as: 1) establishing a high-speed link topology, evaluating the links in the topology, sorting out the cutting positions of the electrical connection structure surfaces in the link topology, and determining the initial values ​​of the electrical connection structure dimensions; 2) adjusting the electrical connection structure dimension parameters, system link stacks and panels, in order to adjust the system parameter values ​​according to the high-speed signal protocol regulations; 3) cutting the electrical connection structure in the middle and cascading it to simulate the link impedance, loss and crosstalk to see if the link requirements are met. If not, return to 2) for adjustment; 4) handing over the electrical connection structure parameters to the manufacturer for processing and production.

[0086] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0087] An embodiment of the present application also provides an evaluation device for a high-speed link system, including: a topology model construction module, which establishes a topology model of the high-speed link system and analyzes the link structure in the topology model; an electrical connection structure identification module, which identifies the position of the electrical connection structure and determines the parameters of the electrical connection structure; a sub-link segmentation module, which sets a cutting plane at the height geometric center of each electrical connection structure to segment the topology model into an upper sub-link and a lower sub-link, and simulates the upper sub-link and the lower sub-link to obtain a first S parameter matrix of the upper sub-link and a second S parameter matrix of the lower sub-link; an S parameter matrix acquisition module, which cascades the overall simulation scattering parameter matrix of the link structure based on the first S parameter matrix and the second S parameter matrix, and determines at least one channel characteristic simulation parameter of the link structure based on the overall simulation scattering parameter matrix; and a link structure optimization module, which iteratively optimizes the parameters of the electrical connection structure based on at least one channel characteristic simulation parameter and traverses the simulation until the link structure meets the link requirements.

[0088] For the description of the features in the embodiment corresponding to the evaluation device of the high-speed link system, reference can be made to the relevant description of the embodiment corresponding to the evaluation method of the high-speed link system, which will not be repeated here.

[0089] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any of the above-mentioned high-speed link system evaluation method embodiments.

[0090] An embodiment of the present application also provides a non-transitory computer-readable storage medium, which stores a computer program, wherein the computer program is configured to execute the steps of any of the above-mentioned high-speed link system evaluation method embodiments when running, including but not limited to, establishing a topological model of the high-speed link system and analyzing the link structure in the topological model; identifying the position of the electrical connection structure and determining the parameters of the electrical connection structure; setting a cutting plane at the height geometric center along each electrical connection structure to divide the topological model into an upper sub-link and a lower sub-link, and simulating the upper sub-link and the lower sub-link to obtain a first S parameter matrix of the upper sub-link and a second S parameter matrix of the lower sub-link; based on the first S parameter matrix and the second S parameter matrix, cascading the overall simulation scattering parameter matrix of the link structure, and determining at least one channel characteristic simulation parameter of the link structure based on the overall simulation scattering parameter matrix; and based on the at least one channel characteristic simulation parameter, iteratively optimizing the parameters of the electrical connection structure and traversing the simulation until the link structure meets the link requirements.

[0091] In some embodiments, the above-mentioned non-transitory computer-readable storage medium may include but is not limited to: a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and other media that can store computer programs.

[0092] An embodiment of the present application also provides a computer program product, which includes a computer program. When the computer program is executed by a processor, it implements the steps in any of the above-mentioned high-speed link system evaluation method embodiments, including but not limited to establishing a topological model of the high-speed link system and analyzing the link structure in the topological model; identifying the position of the electrical connection structure and determining the parameters of the electrical connection structure; setting a cutting plane at the height geometric center of each electrical connection structure to divide the topological model into an upper sub-link and a lower sub-link, and simulating the upper sub-link and the lower sub-link to obtain a first S parameter matrix of the upper sub-link and a second S parameter matrix of the lower sub-link; based on the first S parameter matrix and the second S parameter matrix, cascading the overall simulation scattering parameter matrix of the link structure, and determining at least one channel characteristic simulation parameter of the link structure based on the overall simulation scattering parameter matrix; and based on the at least one channel characteristic simulation parameter, iteratively optimizing the parameters of the electrical connection structure and traversing the simulation until the link structure meets the link requirements.

[0093] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the steps in any of the above-mentioned high-speed link system evaluation method embodiments, including but not limited to establishing a topological model of the high-speed link system and analyzing the link structure in the topological model; identifying the position of the electrical connection structure and determining the parameters of the electrical connection structure; setting a cutting plane at the height geometric center of each electrical connection structure to divide the topological model into an upper sub-link and a lower sub-link, and simulating the upper sub-link and the lower sub-link to obtain a first S parameter matrix of the upper sub-link and a second S parameter matrix of the lower sub-link; based on the first S parameter matrix and the second S parameter matrix, cascading the overall simulation scattering parameter matrix of the link structure, and determining at least one channel characteristic simulation parameter of the link structure based on the overall simulation scattering parameter matrix; and based on the at least one channel characteristic simulation parameter, iteratively optimizing the parameters of the electrical connection structure and traversing the simulation until the link structure meets the link requirements.

[0094] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0095] The above is a detailed introduction to the evaluation method of a high-speed link system provided by the present application. This article uses specific examples to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core ideas of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A method for evaluating a high-speed link system, characterized in that: include: Establishing a topology model of the high-speed link system and analyzing a link structure in the topology model, wherein the topology model includes at least a chip layer, a packaging substrate layer, and a printed circuit board layer, wherein the chip layer and the packaging substrate layer are interconnected via an electrical connection structure, and the packaging substrate layer and the printed circuit board layer are interconnected via an electrical connection structure; identifying an electrical connection structure of the link structure and determining parameters of the electrical connection structure; Setting a cutting plane at a height geometric center along each of the electrical connection structures to divide the topology model into an upper sub-link and a lower sub-link, and simulating the upper sub-link and the lower sub-link to obtain a first S parameter matrix of the upper sub-link and a second S parameter matrix of the lower sub-link, wherein the cutting plane is perpendicular to a height direction of the link structure; Based on the first S parameter matrix and the second S parameter matrix, the overall simulated scattering parameter matrix of the link structure is cascaded, and at least one channel characteristic simulation parameter of the link structure is determined based on the overall simulated scattering parameter matrix. The cascading of the overall simulated scattering parameter matrix of the link structure based on the first S parameter matrix and the second S parameter matrix includes: according to the two-port network cascade principle, the first S parameter matrix and the second S parameter matrix are converted into a simulation mixing parameter matrix, and the simulation mixing parameter matrix is ​​matrix multiplied and inversely transformed to obtain the overall simulated scattering parameter matrix; and based on the at least one channel characteristic simulation parameter, the parameters of the electrical connection structure are iteratively optimized and the simulation is traversed until the link structure meets the link requirements.

2. The evaluation method according to claim 1, wherein: The electrical connection structure includes at least one of a bump and a solder ball.

3. The evaluation method according to claim 2, characterized in that The chip layer and the packaging substrate layer are interconnected through the bumps, and the packaging substrate layer and the printed circuit board layer are interconnected through the solder balls.

4. The evaluation method according to any one of claims 1 to 3, characterized in that: The parameters of the electrical connection structure include at least one of a contact cross-sectional area, a vertical height, electrical conductivity, magnetic permeability, relative dielectric constant, and surface roughness.

5. The evaluation method according to claim 4, characterized in that The simulating the upper sub-link and the lower sub-link includes: High-frequency electromagnetic simulation software is used to set the port type, port impedance, frequency domain scanning range, and step size to simulate the upper sub-link and the lower sub-link.

6. The evaluation method according to claim 1, wherein: The at least one channel characteristic simulation parameter includes characteristic impedance, insertion loss or return loss.

7. The evaluation method according to claim 6, characterized in that The iteratively optimizing the parameters of the electrical connection structure based on the at least one channel characteristic simulation parameter and traversing the simulation until the link structure meets the link requirements includes: Determine whether the at least one channel characteristic simulation parameter meets the threshold requirements of various channel characteristic parameters in the high-speed protocol or design specification.

8. The evaluation method according to claim 7, characterized in that The iteratively optimizing the parameters of the electrical connection structure based on the at least one channel characteristic simulation parameter and traversing the simulation until the link structure meets the link requirements further includes: When the insertion loss exceeds the threshold requirement, the routing length of the link structure is reduced or the stacking material is changed.

9. The evaluation method according to claim 7, wherein: The iterative optimization of the parameters of the electrical connection structure based on the at least one channel characteristic simulation parameter and traversing the simulation until the link structure meets the link requirements further includes: When the characteristic impedance is lower than the threshold requirement, the contact cross-sectional area of ​​the electrical connection structure is reduced, or the vertical height of the electrical connection structure is increased.

10. The evaluation method according to claim 7, wherein: The iterative optimization of the parameters of the electrical connection structure based on the at least one channel characteristic simulation parameter and traversing the simulation until the link structure meets the link requirements further includes: When the return loss is lower than the threshold requirement, the local reflection source is determined according to the resonance frequency and the reflection peak position of the return loss curve in the frequency domain.

11. The evaluation method according to claim 10, characterized in that: The determining of the local reflection source according to the resonant frequency and the reflection peak position of the return loss curve in the frequency domain further includes: In the case where the electrical connection structure has reflection dominated by parasitic capacitance effect, reducing the contact cross-sectional area of ​​the electrical connection structure, or increasing the vertical height of the electrical connection structure; or In the case where the electrical connection structure has reflection dominated by the inductive coupling effect, the contact cross-sectional area of ​​the electrical connection structure is increased, or the vertical height of the electrical connection structure is reduced.

12. The evaluation method according to claim 1, wherein: The evaluation method further comprises: Using a vector network analyzer, testing the upper sub-link and the lower sub-link to obtain a third S-parameter matrix of the upper sub-link and a fourth S-parameter matrix of the lower sub-link; cascading the third S parameter matrix and the fourth S parameter matrix according to a two-port network cascade principle to obtain an overall measured scattering parameter matrix of the link structure, and determining at least one measured channel characteristic parameter of the link structure based on the overall measured scattering parameter matrix; The characteristic impedance, insertion loss or return loss among the at least one channel characteristic measured parameter are compared with the characteristic impedance, insertion loss or return loss among the at least one channel characteristic simulated parameter to determine whether the errors between each simulation curve and each measured curve are within the error range.

13. An evaluation device for a high-speed link system, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the steps of the high-speed link system evaluation method according to any one of claims 1 to 12 are implemented.

14. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the high-speed link system evaluation method according to any one of claims 1 to 12 when executing the computer program.

15. A non-transitory computer-readable storage medium, characterized in that The non-transitory computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the high-speed link system evaluation method according to any one of claims 1 to 12 are implemented.

16. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the high-speed link system evaluation method according to any one of claims 1 to 12 are implemented.

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