Text-based object generation

Abstract

The invention relates to text-based object generation. Apparatuses, systems, and techniques for generating 3D models. In at least one embodiment, the 3D model generated by the second neural network is refined by the first neural network. In at least one embodiment, a first neural network is adjusted based on a determination made by the first neural network.

Description

Technical Field

[0001] At least one embodiment relates to processing resources for performing and facilitating artificial intelligence. For example, at least one embodiment relates to a processor or computing system for generating 3D models according to various novel techniques. Background Art

[0002] Generating 3D models using neural networks may produce inaccurate results. Techniques for generating 3D models using neural networks can be improved. Brief Description of the Drawings

[0003] Figure 1 An example of a system for text-based object generation according to at least one embodiment is shown;

[0004] Figure 2 A flowchart of a process for text-based object generation according to at least one embodiment is shown;

[0005] Figure 3 A flowchart of a process for adjusting a 3D image to match an input string according to at least one embodiment is shown;

[0006] Figure 4 A system for refining a 3D image according to at least one embodiment is shown;

[0007] Figure 5 A flowchart of a process for 3D image refinement according to at least one embodiment is shown;

[0008] Figure 6 An example of a processor according to at least one embodiment is shown;

[0009] Figure 7 is a block diagram showing a driver and / or runtime including one or more libraries for providing one or more application programming interfaces (APIs) according to at least one embodiment;

[0010] Figure 8A Logic according to at least one embodiment is shown;

[0011] Figure 8B Logic according to at least one embodiment is shown;

[0012] Figure 9 Training and deployment of a neural network according to at least one embodiment is shown;

[0013] Figure 10 An example data center system according to at least one embodiment is shown;

[0014] Figure 11AShows an example of an autonomous vehicle according to at least one embodiment;

[0015] Figure 11B Shows an example of an autonomous vehicle according to at least one embodiment Figure 11A of the camera positions and fields of view;

[0016] Figure 11C Is a block diagram showing an example system architecture of an autonomous vehicle according to at least one embodiment Figure 11A ;

[0017] Figure 11D Is a diagram showing a system for communication between one or more cloud-based servers and an autonomous vehicle according to at least one embodiment Figure 11A ;

[0018] Figure 12 Is a block diagram showing a computer system according to at least one embodiment;

[0019] Figure 13 Is a block diagram showing a computer system according to at least one embodiment;

[0020] Figure 14 Shows a computer system according to at least one embodiment;

[0021] Figure 15 Shows a computer system according to at least one embodiment;

[0022] Figure 16A Shows a computer system according to at least one embodiment;

[0023] Figure 16B Shows a computer system according to at least one embodiment;

[0024] Figure 16C Shows a computer system according to at least one embodiment;

[0025] Figure 16D Shows a computer system according to at least one embodiment;

[0026] Figure 16E And Figure 16F Shows a shared programming model according to at least one embodiment;

[0027] Figure 17 Shows an exemplary integrated circuit and associated graphics processor according to at least one embodiment;

[0028] Figures 18A - 18B Shows an exemplary integrated circuit and associated graphics processor according to at least one embodiment;

[0029] Figures 19A - 19BShows additional exemplary graphics processor logic in accordance with at least one embodiment;

[0030] Figure 20 Shows a computer system in accordance with at least one embodiment;

[0031] Figure 21A Shows a parallel processor in accordance with at least one embodiment;

[0032] Figure 21B Shows a partitioning unit in accordance with at least one embodiment;

[0033] Figure 21C Shows a processing cluster in accordance with at least one embodiment;

[0034] Figure 21D Shows a graphics multiprocessor in accordance with at least one embodiment;

[0035] Figure 22 Shows a multi-graphics processing unit (GPU) system in accordance with at least one embodiment;

[0036] Figure 23 Shows a graphics processor in accordance with at least one embodiment;

[0037] Figure 24 Is a block diagram showing a processor microarchitecture for a processor in accordance with at least one embodiment;

[0038] Figure 25 Shows a deep learning application processor in accordance with at least one embodiment;

[0039] Figure 26 Is a block diagram showing an example neuromorphic processor in accordance with at least one embodiment;

[0040] Figure 27 Shows at least a portion of a graphics processor in accordance with one or more embodiments;

[0041] Figure 28 Shows at least a portion of a graphics processor in accordance with one or more embodiments;

[0042] Figure 29 Shows at least a portion of a graphics processor in accordance with one or more embodiments;

[0043] Figure 30 Is a block diagram of a graphics processing engine of a graphics processor in accordance with at least one embodiment;

[0044] Figure 31 Is a block diagram of at least a portion of a graphics processor core in accordance with at least one embodiment;

[0045] Figures 32A - 32B Illustrates thread execution logic according to at least one embodiment, which includes an array of processing elements of a graphics processor core.

[0046] Figure 33 Illustrates a parallel processing unit (“PPU”) according to at least one embodiment;

[0047] Figure 34 Illustrates a general processing cluster (“GPC”) according to at least one embodiment;

[0048] Figure 35 Illustrates a memory partition unit of a parallel processing unit (“PPU”) according to at least one embodiment;

[0049] Figure 36 Illustrates a streaming multiprocessor according to at least one embodiment;

[0050] Figure 37 Is an example data flow diagram of an advanced computing pipeline according to at least one embodiment;

[0051] Figure 38 Is a system diagram of an example system for training, adapting, instantiating, and deploying a machine learning model in an advanced computing pipeline according to at least one embodiment;

[0052] Figure 39 Includes an example illustration of an advanced computing pipeline for processing imaging data according to at least one embodiment;

[0053] Figure 40A Includes an example data flow diagram of a virtual instrument supporting an ultrasound device according to at least one embodiment;

[0054] Figure 40B Includes an example data flow diagram of a virtual instrument supporting a CT scanner according to at least one embodiment;

[0055] Figure 41A Illustrates a data flow diagram of a process for training a machine learning model according to at least one embodiment; and

[0056] Figure 41B Is an example illustration of a client - server architecture for enhancing an annotation tool using a pre - trained annotation model according to at least one embodiment. Detailed Description

[0057] In at least one embodiment, one or more first neural networks adjust one or more three-dimensional (3D) models of one or more objects to be adjusted using text, at least in part based on one or more second neural networks. In at least one embodiment, the one or more first neural networks are trained at least in part based on an indication generated by the one or more second neural networks, the indication indicating whether the adjusted 3D model matches the text. In at least one embodiment, the one or more first neural networks include convolutional neural networks. In at least one embodiment, the one or more second neural networks include diffusion models. In at least one embodiment, the one or more first neural networks are trained to identify features of the one or more 3D models that can be adjusted such that the adjusted 3D model matches the text. In at least one embodiment, the one or more first neural networks are used to adjust one or more textures of the one or more 3D models. In at least one embodiment, the one or more first neural networks are used to adjust one or more meshes of the one or more 3D models.

[0058] Figure 1 An example of a system 100 for text-based object generation according to at least one embodiment is shown. In at least one embodiment, a processor 102 generates a 3D model 104 and a texture map 106. In at least one embodiment, the processor 102 is a CPU, a GPU, a combination of processors, or any other suitable processor.

[0059] In at least one embodiment, the 3D model 104 is a mesh, such as a Skinned Multi-Person Linear (SMPL) model, or any other suitable type of model. In at least one embodiment, the 3D model 104 represents the shape of a human body. In at least one embodiment, the 3D model 104 represents the shape of an object other than a human body. In at least one embodiment, the 3D model 104 is initialized by the processor 102 using random values, zeros, predetermined initial values, or in any other suitable manner. In at least one embodiment, the texture map 106 represents the appearance (e.g., color, texture, etc.) to be applied to the 3D model 104.

[0060] In at least one embodiment, the 3D model 104 and the texture map 106 are combined to render a 3D image 108. In at least one embodiment, the rendering is performed by the processor 102. In at least one embodiment, the rendering is performed by a different processor.

[0061] In at least one embodiment, a first neural network 110 receives a text input 112. In at least one embodiment, the text input 112 describes the desired appearance of the 3D image 108, such as Figure 1The "soccer player" shown. In at least one embodiment, the first neural network 110 is a diffusion model, or any other suitable neural network. In at least one embodiment, the neural network 110 receives the 3D image 108 and determines whether the 3D image 108 depicts the content described by the text input 112.

[0062] In at least one embodiment, the neural network 110 outputs an indication to the processor 102 as to whether the 3D image 108 is similar to the content described by the text input 112. In at least one embodiment, if the neural network 110 indicates that the 3D image 108 is not similar to the content described by the text input 112, the processor 102 adjusts the 3D model 104 and / or the texture map 106 and causes the 3D image 108 to be re-rendered and evaluated by the neural network 110. In at least one embodiment, the process repeats until the neural network 110 determines that the 3D image 108 sufficiently matches the content described by the text input 112. In at least one embodiment, as described in more detail below (e.g., with reference to Figure 4 and Figure 5 ), a refinement process 114 is performed on the 3D image 108. In at least one embodiment, the refinement process 114 is performed after the neural network 110 determines that the 3D image 108 sufficiently matches the content described by the text input 112. In at least one embodiment, the refinement process 114 causes an increase in the resolution of the 3D image 108, an increase in realism, or any other improvement.

[0063] In at least one embodiment, the refinement neural network 114 performs a refinement process on the 3D image 108 to produce a refined 3D image 116. In at least one embodiment, the refined 3D image 116 has a higher resolution, is more realistic, or is otherwise improved compared to the 3D image 108.

[0064] Figure 2A flowchart of a process 200 for text-based object generation according to at least one embodiment is shown. In at least one embodiment, a neural network (e.g., neural network 110) receives 202 an input string (e.g., text string 112). In at least one embodiment, a processor (e.g., processor 102) initializes 204 a 3D model (e.g., 3D model 104). In at least one embodiment, a processor (e.g., processor 102) initializes 206 a texture map (e.g., texture map 106). In at least one embodiment, initializing the 3D model 204 and / or initializing the texture map 206 may include setting the 3D model values and / or texture map values to zero, random values, pseudo-random values, noise, predetermined values, or any other suitable initial values. In at least one embodiment, receiving the input string 202, initializing the 3D model 204, and initializing the texture map may occur simultaneously, sequentially, partially simultaneously or sequentially, or in any other order.

[0065] In at least one embodiment, a processor (e.g., processor 102) renders 3D image (e.g., 3D image 108) based on the 3D model and the texture map. In at least one embodiment, as discussed in more detail below, a neural network (e.g., neural network 110) causes 210 the 3D image to match the input string (e.g., the string received in step 202). In at least one embodiment, causing the 3D image to match the input string includes causing the processor (e.g., processor 102) to adjust the 3D model (e.g., 3D model 104) and / or the texture map (e.g., texture map 106) to render the 3D image.

[0066] In at least one embodiment, once the 3D image has been rendered to sufficiently match the input string, the 3D image can be refined 212, for example, as discussed in refinement 114 in Figure 1

[0067] Figure 3 A flowchart of a process 300 for adjusting a 3D image to match an input string according to at least one embodiment (e.g., as described in step 210 in reference Figure 2 ) is shown. In at least one embodiment, a neural network (e.g., neural network 110) receives 302 an input string and a 3D image. In at least one embodiment, flowchart 300 can be used to implement Figure 2 step 210 shown in Figure 1 . In at least one embodiment, the 3D image and the input string may be similar to the 3D image 108 and the text string 112 described in reference

[0068] In at least one embodiment, if the 3D image matches what is described by the input string, the 3D image is returned 310 for refinement. In at least one embodiment, if the 3D image does not match what is described by the text string, the processor (e.g., processor 102) adjusts the texture map and / or the 3D model. In at least one embodiment, the adjustment is random, pseudo-random, incremental, follows any suitable pattern, or is based on an indication (e.g., generated by a neural network) of how the adjustment should be made to match the 3D model to what is described by the input string.

[0069] In at least one embodiment, after the adjustment 308, the processor (e.g., processor 102) renders 309 a 3D image based on the adjusted texture map and 3D model. In at least one embodiment, after this rendering 309, the comparison 304 is performed again using this newly rendered 3D image. In at least one embodiment, the comparison 304, adjustment 308, and rendering 309 are repeated until it is determined 306 that the 3D image matches the input string.

[0070] Figure 4 A system 400 for refining a 3D image according to at least one embodiment is shown.

[0071] In at least one embodiment, a 3D image 408 is generated by a processor (e.g., processor 110) and determined by a neural network 410 to represent what is described by a text string 412, such as reference Figures 1 - 3 as described; however, the 3D image 408 may be blurry, low resolution, or otherwise in need of improvement. In at least one embodiment, this improvement to the 3D image 408 will maintain the appearance of the 3D image 408 as representing what is described by the text string 412.

[0072] In at least one embodiment, a portion 413 of the 3D image 408 is selected for refinement. In at least one embodiment, the portion 413 is a facial portion of the body represented by the 3D image 408. In at least one embodiment, the portion 413 is the entire 3D image 408, or any other portion of the 3D image 408.

[0073] In at least one embodiment, portion 413 is provided to neural network 414 to produce a refined portion 416. In at least one embodiment, the refined portion 416 depicts portion 413 from a perspective different from that of the 3D image 408. In at least one embodiment, the refined portion 416 depicts portion 413 from the same perspective as the 3D image 408. In at least one embodiment, neural network 414 modifies a portion of the 3D model (e.g., 3D model 104) corresponding to portion 413. In at least one embodiment, neural network 414 modifies a portion of the texture map (e.g., texture map 106) corresponding to portion 413. In at least one embodiment, neural network 414 includes an encoder 414a, a convolutional layer 414b, and a decoder 414c. In at least one embodiment, neural network 414 includes any other suitable neural network. In at least one embodiment, neural network 414 and neural network 410 are included as parts of a single neural network.

[0074] In at least one embodiment, neural network 410 evaluates the refined portion 416 to determine whether the refined portion 416 represents what is described by the text string 412 (e.g., by comparing the embedding of the text string 412 with the embedding of the refined portion 416). In at least one embodiment, neural network 414 is a general image refinement neural network that is not specifically trained to generate an image of what is described by the text string 412 (e.g., as shown, "soccer player"), so the refined portion 416 may initially have a higher quality (e.g., higher resolution) than portion 413, but does not necessarily resemble what is described by the text string 412.

[0075] In at least one embodiment, if neural network 410 determines that the refined 3D image 416 does not resemble what is described by the text input 412, then neural network 414 is adjusted. In at least one embodiment, the adjustment of neural network 414 includes adjusting one or more of the encoder 414a, the convolutional layer 414b, the decoder 414c, or any other part of neural network 414 (e.g., adjusting its parameters). In at least one embodiment, this process of refinement, evaluation, and adjustment is repeated until neural network 410 determines that the refined portion 416 sufficiently matches what is described by the text input 412.

[0076] Figure 5 A flowchart of a process 500 for 3D image refinement according to at least one embodiment is shown. In at least one embodiment, the process shown by flowchart 500 can be used to implement Figure 2 step 212 as shown.

[0077] In at least one embodiment, a portion of the 3D image (e.g., portion 413) is received 502 by a neural network (e.g., neural network 414). In at least one embodiment, the portion is all of the 3D image, a portion of the 3D image, or multiple portions of the 3D image.

[0078] In at least one embodiment, an input string, such as text input 112 or text input 412, is received 504 by the neural network. In at least one embodiment, step 506 can be performed before, after, or in parallel with step 502 and / or step 506. In at least one embodiment, the input string describes what is represented in the 3D image, obtaining the content obtained in step 502 from the 3D image.

[0079] In at least one embodiment, the neural network causes the received portion of the 3D image to be refined 506. In at least one embodiment, the refinement includes improving resolution, realism, clarity, lighting, or any other improvement. In at least one embodiment, the refinement 506 can be Figure 1 the refinement 114 shown in Figure 2 step 212 shown in Figure 4 the refinement performed by system 400 shown in or any other refinement.

[0080] In at least one embodiment, a second neural network (e.g., neural network 110) determines 510 whether the refined portion of the 3D image generated in step 504 matches the content described by the input string. In at least one embodiment, the neural network is the same as the neural network used to generate the 3D image, obtaining the portion of the 3D image received in step 502 from the 3D image.

[0081] In at least one embodiment, in step 512, if the second neural network determines that the refined portion of the 3D image does not match the input string received in step 504, the parameters of the first neural network used to generate the refined portion of the 3D image in step 506 are adjusted 514, and process 500 returns to step 506. In at least one embodiment, adjusting 514 these parameters causes the refined portion of the 3D image generated in step 506 to more closely resemble the content described by the input string received in step 504. In at least one embodiment, adjusting 514 includes adjusting one or more of encoder 414a, convolutional layer 414b, and / or decoder 414c.

[0082] In at least one embodiment, if the second neural network determines that the refined portion of the 3D image does indeed match the input string received in step 504, the refined portion is returned 516 and process 500 ends.

[0083] Figure 6 Shows an example of a processor 600 according to at least one embodiment. In at least one embodiment, the processor 600 executes one or more processes, such as the processes described with reference to Figures 1 - 5 to cause one or more first neural networks (e.g., neural network 414) to generate one or more 3D models (e.g., 3D image 408) to be adjusted based at least in part on one or more second neural networks (e.g., neural network 410) using text (e.g., text input 412), and to adjust these one or more 3D models.

[0084] In at least one embodiment, the processor 600 includes one or more processors, such as the processors described in connection with Figures 8A - 41B In at least one embodiment, the processor 600 is any suitable processing unit or combination of processing units, such as one or more CPUs, GPUs, GPGPUs, or PPUs. In at least one embodiment, the processor 600 includes a neural network training module 602, a 3D model module 604, a texture map module 606, a rendering module 608, a text input module 610, a neural network module 612, and a refinement module 614. In at least one embodiment, the neural network training module 602, the 3D model module 604, the texture map module 606, the rendering module 608, the text input module 610, the neural network module 612, and the refinement module 614 are part of the processor 600, as shown in the example of Figure 6 or may be part of one or more other processors. In at least one embodiment, the neural network training module 602, the 3D model module 604, the texture map module 606, the rendering module 608, the text input module 610, the neural network module 612, and the refinement module 614 are distributed among multiple processors that communicate via a bus, a network, by writing to shared memory, or any suitable communication process (e.g., the communication processes described with reference to Figures 8A - 41B ).

[0085] In at least one embodiment, the neural network training module 602 includes circuitry that causes all or part of a neural network (e.g., any of the neural networks 110, 414, and 414 shown in Figure 1 and Figure 4 ) to be trained to perform text-based object generation, such as as shown in Figure 2 , Figure 3 and Figure 5 .

[0086] In at least one embodiment, the 3D model module 604 includes circuitry that causes a 3D model (e.g., Figure 1a circuit in which the 3D model 104) shown in is generated or adjusted. In at least one embodiment, for example, the 3D model module 604 may perform operations to implement Figure 2 and Figure 3 the steps 204, 210, and 308 shown in.

[0087] In at least one embodiment, the texture map module 606 includes a circuit that causes a texture map (e.g., Figure 1 the texture map 106 shown in) to be generated or adjusted. In at least one embodiment, for example, the texture map module 606 may perform operations to implement Figure 2 and Figure 3 the steps 206, 210, and 308 shown in.

[0088] In at least one embodiment, the rendering module 608 includes a circuit that causes a 3D image (e.g., Figure 1 the 3D image 108 shown in) to be rendered. In at least one embodiment, for example, the rendering module 608 may perform operations to implement Figure 2 and Figure 3 the steps 208 and 309 shown in.

[0089] In at least one embodiment, the text input module 610 includes a circuit that causes text input (e.g., Figure 1 the text input 112 shown in) to be received. In at least one embodiment, for example, the text input module 610 may perform operations to implement Figure 2 , Figure 3 and Figure 5 the steps 202, 302, and 504 shown in.

[0090] In at least one embodiment, the neural network module 612 includes a circuit that causes a neural network (e.g., neural networks 110, 410, and / or 414) to evaluate whether a 3D image matches the text input and / or refine a portion of the 3D image. In at least one embodiment, for example, the neural network module 612 may perform operations to implement Figure 2 , Figure 3 and Figure 5 the steps 210, 302 - 310, and 502 - 516 shown in.

[0091] In at least one embodiment, the refinement module 614 includes a circuit that causes a 3D image or a portion of the 3D image to be refined, such as as Figure 4 shown. In at least one embodiment, for example, the refinement module 614 may perform operations to implement Figure 2 and Figure 5 the steps 212 and 502 - 516 shown in.

[0092] Figure 7 FIG. 700 is a block diagram showing a driver and / or runtime including one or more libraries for providing one or more application programming interfaces (APIs) according to at least one embodiment. In at least one embodiment, software program 702 is a software module, such as modules 602, 604, 606, 608, 610, 612, and 614. In at least one embodiment, a software container is a group of software programs. In at least one embodiment, software program 702 includes one or more software modules. In at least one embodiment, software modules are further shown non-exclusively as Figure 6 described herein. In at least one embodiment, one or more APIs 708 are software instruction sets that, if executed, cause one or more processors (e.g., processor 600) to perform one or more computing operations. In at least one embodiment, one or more APIs 708 are distributed or otherwise provided as part of one or more libraries 706, runtime 704, driver 704, and / or any other grouping of software and / or executable code further described herein. In at least one embodiment, one or more APIs 708 perform one or more computing operations in response to being invoked by software program 702. In at least one embodiment, software program 702 is a collection of software code, commands, instructions, or other sequences of text for instructing a computing device to perform one or more computing operations and / or to invoke one or more other instruction sets (e.g., API 708 or API function 710) to be executed. In at least one embodiment, the functionality provided by one or more APIs 708 includes software functions 710, such as software functions that can be used to accelerate one or more portions of software program 702 using one or more parallel processing units (PPUs) (e.g., graphics processing units (GPUs)).

[0093] In at least one embodiment, API 708 is a hardware interface to one or more circuits for performing one or more computing operations. In at least one embodiment, one or more of the software APIs 708 described herein are implemented as one or more circuits for performing one or more of the techniques described in conjunction with Figures 1 - 6 described below. In at least one embodiment, one or more software programs 702 include instructions that, if executed, cause one or more hardware devices and / or circuits to adjust one or more 3D models using one or more first neural networks to generate one or more objects to be adjusted based at least in part on one or more second neural networks using text, as further described in conjunction with Figures 1 - 6 below.

[0094] In at least one embodiment, a software program 702 (e.g., a user-implemented software program) uses one or more application programming interfaces (APIs) 708 to perform various computational operations, such as memory reservation, matrix multiplication, arithmetic operations, or any computational operation performed by a parallel processing unit (PPU) (e.g., a graphics processing unit (GPU)), as further described herein. In at least one embodiment, one or more APIs 708 provide a set of callable functions 710 (referred to herein as APIs, API functions, and / or functions), which respectively perform one or more computational operations, such as computational operations related to parallel computing. In at least one embodiment, for example, one or more APIs 708 provide functions 710 for causing information to be stored in one or more storage locations that are at least partially accessible by a second software container based on control information generated by one or more first software containers, and / or for otherwise performing the operations described herein.

[0095] In at least one embodiment, one or more software programs 702 interact with or otherwise communicate with one or more APIs 708 to perform one or more computational operations using one or more PPUs (e.g., GPUs). In at least one embodiment, one or more computational operations using one or more PPUs include at least one set or more of computational operations that are accelerated by being at least partially performed by the one or more PPUs. In at least one embodiment, one or more software programs 702 interact with one or more APIs 708 to cause one or more hardware devices and / or circuits to adjust one or more 3D models using one or more first neural networks based at least in part on one or more 3D models of one or more objects to be adjusted generated using text by one or more second neural networks, and / or for otherwise performing the operations described herein.

[0096] In at least one embodiment, the interface is software instructions that, if executed, provide access to one or more functions 710 provided by one or more APIs 708. In at least one embodiment, when a software developer compiles one or more software programs 702 in conjunction with one or more libraries 706 that include one or more APIs 708 or otherwise provide access to one or more APIs 708, the software programs 702 use a native interface. In at least one embodiment, one or more software programs 702 are statically compiled in conjunction with a pre-compiled library 706 that includes instructions for executing one or more APIs 708 or uncompiled source code. In at least one embodiment, one or more software programs 702 are dynamically compiled and the one or more software programs are linked using a linker to one or more pre-compiled libraries 706 that include one or more APIs 708.

[0097] In at least one embodiment, when a software developer executes a software program that uses a library 706 that includes one or more APIs 708 or otherwise communicates with a library 706 that includes one or more APIs 708 over a network or other remote communication medium, the software program 702 uses a remote interface. In at least one embodiment, one or more libraries 706 that include one or more APIs 708 are executed by a remote computing service (e.g., a computing resource service provider). In another embodiment, one or more libraries 706 that include one or more APIs 708 are executed by any other computing host that provides the one or more APIs 708 to one or more software programs 702 (e.g., a software container that includes a software program).

[0098] In at least one embodiment, a processor (e.g., processor 600) that executes or uses one or more software programs 702 invokes, uses, executes, or otherwise implements one or more APIs 708 to allocate and otherwise manage the memory 712 to be used by the software program 702. In at least one embodiment, one or more software programs 702 use one or more APIs 708 to allocate and otherwise manage the memory 712 to be used by one or more portions of the software program 702 to be accelerated using one or more PPUs (e.g., GPUs) or any other accelerator or processor further described herein. In one embodiment, these software programs 702 request that a neural network perform signal processing using functions 710 provided by one or more APIs 608.

[0099] In at least one embodiment, API 708 is an API for facilitating parallel computing. In at least one embodiment, API 708 is any other API further described herein. In at least one embodiment, API 708 is provided by driver and / or runtime 704. In at least one embodiment, API 708 is provided by the CUDA user-mode driver. In at least one embodiment, API 708 is provided by the CUDA runtime. In at least one embodiment, driver 704 is data values and software instructions that, if executed, perform or otherwise facilitate the operation of one or more functions 710 of API 708 during the loading and execution of one or more portions of software program 702. In at least one embodiment, runtime 704 is data values and software instructions that, if executed, perform or otherwise facilitate the operation of one or more functions 710 of API 708 during the execution of software program 702. In at least one embodiment, one or more software programs 702 use one or more APIs 708 implemented or otherwise provided by driver and / or runtime 704 to cause one or more hardware devices and / or circuits to adjust one or more 3D models of one or more objects to be adjusted, at least in part based on one or more second neural networks using text to generate the one or more 3D models, and / or to otherwise perform the operations described herein.

[0100] In at least one embodiment, one or more software programs 702 use one or more APIs 708 provided by driver and / or runtime 704 to perform combined arithmetic operations on one or more PPUs (e.g., GPUs). In at least one embodiment, one or more APIs 708 provide combined arithmetic operations via driver and / or runtime 704, as described above. In at least one embodiment, one or more software programs 702 utilize one or more APIs 708 provided by driver and / or runtime 704 to allocate or otherwise reserve one or more blocks of memory 712 of one or more PPUs (e.g., GPUs). In at least one embodiment, one or more software programs 702 utilize one or more APIs 708 provided by driver and / or runtime 704 to allocate or otherwise reserve blocks of memory 712. In at least one embodiment, one or more APIs 708 invoke neural networks to cause one or more first neural networks to adjust one or more 3D models of one or more objects to be adjusted, at least in part based on one or more second neural networks using text to generate the one or more 3D models, and / or to otherwise perform the operations described herein.

[0101] In at least one embodiment, the processor includes one or more circuits for executing API 708 to cause one or more hardware devices and / or circuits to use one or more first neural networks to adjust one or more 3D models of one or more objects to be adjusted, at least in part based on one or more second neural networks using text to generate the one or more 3D models, and / or to otherwise perform the operations described herein. In at least one embodiment, block diagram 700 illustrates a processor that includes one or more circuits for executing API 708 to cause one or more software programs indicated by API 708 to cause one or more hardware devices and / or circuits to use one or more first neural networks to adjust one or more 3D models of one or more objects to be adjusted, at least in part based on one or more second neural networks using text to generate the one or more 3D models, and / or to otherwise perform the operations described herein. In at least one embodiment, block diagram 700 illustrates a processor that executes one or more functions 710, such as the processor described in conjunction with Figures 1 - 6 as described. In at least one embodiment, block diagram 700 illustrates API 708, such as being executed by the hardware described in conjunction with Figures 8A - 41B as described.

[0102] In at least one embodiment, the system includes a processor that includes one or more circuits for causing information to be stored in one or more storage locations and / or to otherwise perform the operations described herein, at least in part based on control information generated by one or more first software containers indicating one or more storage locations accessible to a second software container. In at least one embodiment, the system performs process 200 as shown in Figure 2 as shown, process 300 as shown in Figure 3 as shown, process 500 as shown in Figure 5 as shown, or portions thereof. In at least one embodiment, Figures 1 - 6 further illustrates a system using API 708. In at least one embodiment, the system includes one or more hardware as shown in Figures 8A - 41B as shown, for example, for causing one or more hardware devices and / or circuits to use one or more first neural networks to adjust one or more 3D models of one or more objects to be adjusted, at least in part based on one or more second neural networks using text to generate the one or more 3D models, and / or to otherwise perform the operations described herein.

[0103] Logic

[0104] Figure 8ALogic 815 is shown, as described elsewhere herein, which may be used in one or more devices to perform operations such as those discussed herein according to at least one embodiment. In at least one embodiment, logic 815 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, logic 815 is inference and / or training logic. The following is combined with Figure 8A and / or Figure 8B provides details regarding logic 815. In at least one embodiment, logic refers to any combination of software logic, hardware logic, and / or firmware logic to provide the functions or operations described herein, where the logic may be embodied collectively or individually as circuitry forming part of a larger system, such as an integrated circuit (IC), a system on a chip (SoC), or one or more processors (e.g., CPU, GPU).

[0105] In at least one embodiment, logic 815 may include, but is not limited to, code and / or data storage 801, which is used to store forward and / or output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network that is trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, logic 815 may include or be coupled to code and / or data storage 801 for storing graph code or other software to control timing and / or sequence, where weights and / or other parameter information are loaded to configure the logic, which includes integer and / or floating-point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, the code (such as graph code) loads weight or other parameter information into the processor ALU based on the architecture of the neural network corresponding to the code. In at least one embodiment, code and / or data storage 801 stores the weight parameters and / or input / output data of each layer of the neural network used or trained in combination with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 801 may be included within other on-chip or off-chip data storage, including the L1, L2, or L3 cache of the processor or system memory.

[0106] In at least one embodiment, any part of the code and / or data storage 801 can be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 801 can be cache memory, dynamic random access memory (“DRAM”), static random access memory (“SRAM”), non-volatile memory (such as flash memory), or other storage. In at least one embodiment, the choice of whether the code and / or data storage 801 is internal or external to the processor, e.g., or includes DRAM, SRAM, flash memory, or some other storage type, can depend on the on-chip versus off-chip available storage, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0107] In at least one embodiment, the logic 815 can include, but is not limited to, the code and / or data storage 805 for storing the backward and / or output weights and / or input / output data corresponding to the neurons or layers of the neural network that are trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, during training and / or inference using aspects of one or more embodiments, the code and / or data storage 805 stores the weight parameters and / or input / output data of each layer of the neural network that are combined with one or more embodiments during the backpropagation of the input / output data and / or weight parameters. In at least one embodiment, the logic 815 can include or be coupled to the code and / or data storage 805 for storing the graph code or other software to control the timing and / or sequence, where the weights and / or other parameter information are loaded to configure the logic, which includes integer and / or floating-point units (collectively referred to as arithmetic logic units (ALUs)).

[0108] In at least one embodiment, code (such as a graph code) causes weight or other parameter information to be loaded into the processor ALU based on the architecture of the neural network corresponding to the code. In at least one embodiment, any portion of the code and / or data storage 805 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of the code and / or data storage 805 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 805 may be cache memory, DRAM, SRAM, non-volatile memory (such as flash memory), or other storage. In at least one embodiment, the choice of whether the code and / or data storage 805 is internal or external to the processor, e.g., including DRAM, SRAM, flash memory, or some other storage type, may depend on the available on-chip versus off-chip storage, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0109] In at least one embodiment, the code and / or data storage 801 and the code and / or data storage 805 may be separate storage structures. In at least one embodiment, the code and / or data storage 801 and the code and / or data storage 805 may be the same storage structure. In at least one embodiment, the code and / or data storage 801 and the code and / or data storage 805 may be partially combined and partially separated. In at least one embodiment, any portion of the code and / or data storage 801 and the code and / or data storage 805 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0110] In at least one embodiment, logic 815 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 810 (including integer and / or floating point units) for performing logical and / or mathematical operations at least in part based on and / or as directed by training and / or inference code (e.g., graph code), the result of which may produce activations (e.g., output values from layers or neurons within a neural network) stored in activation store 820, which are a function of input / output and / or weight parameter data stored in code and / or data store 801 and / or code and / or data store 805. In at least one embodiment, the activations stored in activation store 820 are generated according to linear algebra and / or matrix-based mathematics performed by ALU 810 in response to executing instructions or other code, where the weight values stored in code and / or data store 805 and / or code and / or data store 801 are used as operands along with other values such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data store 805 or code and / or data store 801 or other on-chip or off-chip storage.

[0111] In at least one embodiment, one or more ALUs 810 are included in one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 810 may be external to the processors or other hardware logic devices or circuits that use them (e.g., coprocessors). In at least one embodiment, ALU 810 may be included within the execution units of a processor or otherwise included in an ALU bank accessible by the execution units of a processor, which execution units may be within the same processor or distributed among different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, code and / or data store 801, code and / or data store 805, and activation store 820 may share a processor or other hardware logic device or circuit, while in another embodiment, they may be in different processors or other hardware logic devices or circuits or some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation store 820 may be included with other on-chip or off-chip data stores, including the L1, L2, or L3 cache of a processor or system memory. Additionally, inference and / or training code may be stored with other code accessible to the processor or other hardware logic or circuits and may be extracted and / or processed using the fetch, decode, schedule, execute, retire, and / or other logic circuits of the processor.

[0112] In at least one embodiment, activation store 820 can be a cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, activation store 820 can be wholly or partially within or external to one or more processors or other logic circuits. In at least one embodiment, the choice of whether activation store 820 is internal or external to the processor, e.g., or includes DRAM, SRAM, flash memory, or some other storage type, can depend on on-chip versus off-chip available storage, latency requirements for performing training and / or inference functions, the batch size of data used in inferring and / or training a neural network, or some combination of these factors.

[0113] In at least one embodiment, Figure 8A the logic 815 shown in can be used in conjunction with an application specific integrated circuit (“ASIC”), such as the processing unit from Google, the TM inference processing unit (IPU) from Graphcore, or the (e.g., “Lake Crest”) processor from Intel Corporation. In at least one embodiment, Figure 8A the logic 815 shown can be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware, or other hardware (e.g., field programmable gate array (“FPGA”)).

[0114] Figure 8B Logic 815 is shown in accordance with at least one embodiment. In at least one embodiment, logic 815 is inference and / or training logic. In at least one embodiment, logic 815 can include, but is not limited to, hardware logic where computing resources are dedicated or otherwise exclusively used with weight values or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, Figure 8B the logic 815 shown in can be used in conjunction with an application specific integrated circuit (“ASIC”), such as the processing unit from Google, the TM inference processing unit (IPU) from Graphcore, or the (e.g., “Lake Crest”) processor from Intel Corporation. In at least one embodiment, Figure 8BThe logic 815 shown in FIG. may be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware (such as a field programmable gate array (FPGA)). In at least one embodiment, the logic 815 includes, but is not limited to, code and / or data storage 801 and code and / or data storage 805, which may be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. In Figure 8B In at least one embodiment shown in FIG., each of code and / or data storage 801 and code and / or data storage 805 is respectively associated with dedicated computing resources (such as computing hardware 802 and computing hardware 806). In at least one embodiment, each of computing hardware 802 and computing hardware 806 includes one or more ALUs that perform only mathematical functions (such as linear algebra functions) on the information stored in code and / or data storage 801 and code and / or data storage 805, and the results are stored in activation storage 820.

[0115] In at least one embodiment, each of code and / or data storage 801 and 805 and the corresponding computing hardware 802 and 806 respectively corresponds to a different layer of a neural network, such that the activation obtained from one storage / computation pair 801 / 802 of code and / or data storage 801 and computing hardware 802 is provided as the input to the next storage / computation pair 805 / 806 of code and / or data storage 805 and computing hardware 806, in order to reflect the conceptual organization of the neural network. In at least one embodiment, each storage / computation pair 801 / 802 and 805 / 806 may correspond to more than one layer of a neural network. In at least one embodiment, additional storage / computation pairs (not shown) may be included in the logic 815 after or in parallel with the storage / computation pairs 801 / 802 and 805 / 806.

[0116] Neural network training and deployment

[0117] Figure 9Illustrates the training and deployment of a deep neural network according to at least one embodiment. In at least one embodiment, a training dataset 902 is used to train an untrained neural network 906. In at least one embodiment, the training framework 904 is the PyTorch framework, while in other embodiments, the training framework 904 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training frameworks. In at least one embodiment, the training framework 904 trains the untrained neural network 906 and enables it to be trained using the processing resources described herein to generate a trained neural network 908. In at least one embodiment, the weights can be randomly selected or pre-trained using a deep belief network. In at least one embodiment, the training can be performed in a supervised, partially supervised, or unsupervised manner.

[0118] In at least one embodiment, supervised learning is used to train the untrained neural network 906, where the training dataset 902 includes inputs paired with desired outputs for the inputs, or where the training dataset 902 includes inputs with known outputs and the outputs of the neural network 906 are manually graded. In at least one embodiment, the untrained neural network 906 is trained in a supervised manner, processes the inputs from the training dataset 902, and compares the resulting outputs with a set of expected or desired outputs. In at least one embodiment, the error is then backpropagated through the untrained neural network 906. In at least one embodiment, the training framework 904 adjusts the weights controlling the untrained neural network 906. In at least one embodiment, the training framework 904 includes tools for monitoring the degree to which the untrained neural network 906 converges to a model (such as the trained neural network 908) suitable for generating correct answers (such as result 914) based on input data (such as new dataset 912). In at least one embodiment, the training framework 904 repeatedly trains the untrained neural network 906 while adjusting the weights to refine the output of the untrained neural network 906 using a loss function and an adjustment algorithm (such as stochastic gradient descent). In at least one embodiment, the training framework 904 trains the untrained neural network 906 until the untrained neural network 906 reaches a desired accuracy. In at least one embodiment, the trained neural network 908 can then be deployed to perform any number of machine learning operations.

[0119] In at least one embodiment, unsupervised learning is used to train an untrained neural network 906, where the untrained neural network 906 attempts to train itself using unlabeled data. In at least one embodiment, the unsupervised learning training dataset 902 will include input data without any associated output data or "ground truth" data. In at least one embodiment, the untrained neural network 906 can learn groupings within the training dataset 902 and can determine how individual inputs relate to the untrained dataset 902. In at least one embodiment, unsupervised training can be used to generate a self-organizing map in the trained neural network 908, which can perform operations useful for reducing the dimensionality of a new dataset 912. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows identifying data points in the new dataset 912 that deviate from the normal pattern of the new dataset 912.

[0120] In at least one embodiment, semi-supervised learning can be used, which is a technique where a mixture of labeled and unlabeled data is included in the training dataset 902. In at least one embodiment, the training framework 904 can be used to perform incremental learning, such as through transfer learning techniques. In at least one embodiment, incremental learning enables the trained neural network 908 to adapt to a new dataset 912 without forgetting the knowledge injected into the trained neural network 908 during initial training.

[0121] In at least one embodiment, the training framework 904 is a framework that is processed in conjunction with a software development kit such as the OpenVINO (Open Visual Inference and Neural Network Optimization) toolkit. In at least one embodiment, the OpenVINO toolkit is a toolkit developed, for example, by Intel Corporation of Santa Clara, California. In at least one embodiment, OpenVINO includes logic 815 or uses logic 815 to perform the operations described herein. In at least one embodiment, a SoC, integrated circuit, or processor uses OpenVINO to perform the operations described herein.

[0122] In at least one embodiment, OpenVINO is a toolkit for facilitating the development of applications (particularly neural network applications) for various tasks and operations such as human vision simulation, speech recognition, natural language processing, recommendation systems, and / or variations thereof. In at least one embodiment, OpenVINO supports neural networks such as convolutional neural networks (CNNs), recurrent neural networks, and / or attention-based neural networks, and / or various other neural network models. In at least one embodiment, OpenVINO supports various software libraries, such as OpenCV, OpenCL, and / or variations thereof.

[0123] In at least one embodiment, OpenVINO supports neural network models for various tasks and operations such as classification, segmentation, object detection, face recognition, speech recognition, pose estimation (e.g., of a person and / or an object), monocular depth estimation, inpainting, style transfer, action recognition, coloring, and / or variations thereof.

[0124] In at least one embodiment, OpenVINO includes one or more software tools and / or modules for model optimization, also referred to as the Model Optimizer. In at least one embodiment, the Model Optimizer is a command-line tool that facilitates the conversion between the training and deployment of neural network models. In at least one embodiment, the Model Optimizer optimizes neural network models to execute on various devices and / or processing units such as GPUs, CPUs, PPUs, GPGPUs, and / or variations thereof. In at least one embodiment, the Model Optimizer generates an internal representation of the model and optimizes the model to generate an intermediate representation. In at least one embodiment, the Model Optimizer reduces the number of layers of the model. In at least one embodiment, the Model Optimizer removes layers of the model used for training. In at least one embodiment, the Model Optimizer performs various neural network operations such as modifying the input of the model (e.g., resizing the input of the model), modifying the size of the input of the model (e.g., modifying the batch size of the model), modifying the model structure (e.g., modifying the layers of the model), normalization, standardization, quantization (e.g., converting the weights of the model from a first representation such as floating point to a second representation such as integer), and / or variations thereof.

[0125] In at least one embodiment, OpenVINO includes one or more software libraries for inference, also referred to as the Inference Engine. In at least one embodiment, the Inference Engine is a C++ library or a library in any suitable programming language. In at least one embodiment, the Inference Engine is used to infer input data. In at least one embodiment, the Inference Engine implements various classes to infer input data and generate one or more results. In at least one embodiment, the Inference Engine implements one or more API functions to process the intermediate representation, set the input and / or output format, and / or execute the model on one or more devices.

[0126] In at least one embodiment, OpenVINO provides various capabilities for the heterogeneous execution of one or more neural network models. In at least one embodiment, heterogeneous execution or heterogeneous computing refers to one or more computing processes and / or systems that utilize one or more types of processors and / or cores. In at least one embodiment, OpenVINO provides various software functions to execute programs on one or more devices. In at least one embodiment, OpenVINO provides various software functions to execute programs and / or parts of programs on different devices. In at least one embodiment, OpenVINO provides various software functions, for example, to run a first code portion on a CPU and a second code portion on a GPU and / or FPGA. In at least one embodiment, OpenVINO provides various software functions to execute one or more layers of a neural network on one or more devices (e.g., execute a first set of layers on a first device (e.g., GPU) and a second set of layers on a second device (e.g., CPU)).

[0127] In at least one embodiment, OpenVINO includes various functions similar to those associated with the CUDA programming model, such as various neural network model operations associated with frameworks such as TensorFlow, PyTorch, and / or variations thereof. In at least one embodiment, one or more CUDA programming model operations are executed using OpenVINO. In at least one embodiment, the various systems, methods, and / or techniques described herein are implemented using OpenVINO.

[0128] Data center

[0129] Figure 10 An example data center 1000 that can use at least one embodiment is shown. In at least one embodiment, the data center 1000 includes a data center infrastructure layer 1010, a framework layer 1020, a software layer 1030, and an application layer 1040.

[0130] In at least one embodiment, as Figure 10As shown, the data center infrastructure layer 1010 may include a resource coordinator 1012, grouped computing resources 1014, and node computing resources ("node C.R.") 1016(1)-1016(N), where "N" represents a positive integer (which may be a different integer "N" from the integers used in other figures). In at least one embodiment, the node C.R. 1016(1)-1016(N) may include, but is not limited to, any number of central processing units ("CPU") or other processors (including accelerators, field programmable gate arrays (FPGA), graphics processors, etc.), memory storage devices 1018(1)-1018(N) (such as dynamic read-only memory, solid-state storage, or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VM"), power modules, and cooling modules, etc. In at least one embodiment, one or more of the node C.R. 1016(1)-1016(N) may be servers having one or more of the above computing resources.

[0131] In at least one embodiment, the grouped computing resources 1014 may include separate groupings of node C.R. housed within one or more racks (not shown), or numerous racks housed within data centers (also not shown) at various geographical locations. In at least one embodiment, the separate groupings of node C.R. within the grouped computing resources 1014 may include grouped computing, network, memory, or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, several node C.R. including CPUs or processors may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0132] In at least one embodiment, the resource coordinator 1012 may configure or otherwise control one or more of the node C.R. 1016(1)-1016(N) and / or the grouped computing resources 1014. In at least one embodiment, the resource coordinator 1012 may include a software design infrastructure ("SDI") management entity for the data center 1000. In at least one embodiment, the resource coordinator 1012 may include hardware, software, or some combination thereof.

[0133] In at least one embodiment, as Figure 10As shown, the framework layer 1020 includes a job scheduler 1022, a configuration manager 1024, a resource manager 1026, and a distributed file system 1028. In at least one embodiment, the framework layer 1020 may include a framework for supporting software 1032 of the software layer 1030 and / or one or more applications 1042 of the application layer 1040. In at least one embodiment, the software 1032 or the application 1042 may respectively include web-based service software or applications, such as service software or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 1020 may be, but is not limited to, a type of free and open-source software web application framework, such as Apache SparkTM (hereinafter referred to as "Spark") that can utilize the distributed file system 1028 for large-scale data processing (e.g., "big data"). In at least one embodiment, the job scheduler 1022 may include a Spark driver for facilitating the scheduling of workloads supported by the various layers of the data center 1000. In at least one embodiment, the configuration manager 1024 may be capable of configuring different layers, such as the software layer 1030 and the framework layer 1020 including Spark and the distributed file system 1028 for supporting large-scale data processing. In at least one embodiment, the resource manager 1026 may be capable of managing clustered or grouped computing resources mapped to or allocated for supporting the distributed file system 1028 and the job scheduler 1022. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 1014 at the data center infrastructure layer 1010. In at least one embodiment, the resource manager 1026 may coordinate with the resource coordinator 1012 to manage these mapped or allocated computing resources.

[0134] In at least one embodiment, the software 1032 included in the software layer 1030 may include software used by at least respective portions of the nodes C.R. 1016(1)-1016(N), the grouped computing resources 1014, and / or the distributed file system 1028 of the framework layer 1020. In at least one embodiment, one or more types of software may include, but are not limited to, Internet web search software, email virus scanning software, database software, and streaming video content software.

[0135] In at least one embodiment, one or more applications 1042 included in the application layer 1040 may include one or more types of applications used by at least respective portions of nodes C.R. 1016(1)-1016(N), grouped computing resources 1014, and / or the distributed file system 1028 of the framework layer 1020. In at least one embodiment, one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, applications, and machine learning applications, including training or inference software, machine learning framework software (such as PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0136] In at least one embodiment, any one of the configuration manager 1024, the resource manager 1026, and the resource coordinator 1012 may implement any number and type of self-modifying actions based on any amount and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modifying actions may relieve the data center operator of the data center 1000 from making potentially bad configuration decisions and may avoid underutilization and / or poorly performing portions of the data center.

[0137] In at least one embodiment, the data center 1000 may include tools, services, software, or other resources for training one or more machine learning models or using one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weight parameters according to a neural network architecture by using the software and computing resources described above with respect to the data center 1000. In at least one embodiment, by using the weight parameters calculated by one or more training techniques described herein, the resources described above with respect to the data center 1000 may be used to infer or predict information using the trained machine learning model corresponding to one or more neural networks.

[0138] In at least one embodiment, the data center may use a CPU, an application specific integrated circuit (ASIC), a GPU, an FPGA, or other hardware to perform training and / or inference using the above resources. In addition, one or more of the above software and / or hardware resources may be configured as a service for allowing a user to train or perform information inference, such as image recognition, speech recognition, or other artificial intelligence services.

[0139] Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. This is described in conjunction with Figure 8A and / or Figure 8BProvide details regarding logic 815. In at least one embodiment, logic 815 may be used in data center 1000 for performing inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0140] In at least one embodiment, data center 1000 is used to at least partially implement text-based object generation as shown in Figures 1 - 6 the text.

[0141] Autonomous vehicle

[0142] Figure 11A An example of an autonomous vehicle 1100 according to at least one embodiment is shown. In at least one embodiment, autonomous vehicle 1100 (alternatively referred to herein as “vehicle 1100”) may be, but is not limited to, a passenger vehicle such as a car, truck, bus, and / or another type of vehicle that accommodates one or more passengers. In at least one embodiment, vehicle 1100 may be a semi-trailer truck for hauling cargo. In at least one embodiment, vehicle 1100 may be an airplane, a robotic vehicle, or another type of vehicle.

[0143] Autonomous vehicles may be described according to automation levels defined by the National Highway Traffic Safety Administration (“NHTSA”) under the United States Department of Transportation and the Society of Automotive Engineers (“SAE”) in “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., Standard No. J3016-201806 issued on June 15, 2018, Standard No. J3016-201609 issued on September 30, 2016, and previous and future versions of this standard). In at least one embodiment, vehicle 1100 may be capable of having functionality according to one or more of levels 1 to 5 of the autonomous driving levels. For example, in at least one embodiment, vehicle 1100 may be capable of having conditional automation (level 3), highly automated (level 4), and / or fully automated (level 5), depending on the embodiment.

[0144] In at least one embodiment, vehicle 1100 may include, but is not limited to, components such as a chassis, a body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of the vehicle. In at least one embodiment, vehicle 1100 may include, but is not limited to, a propulsion system 1150, such as an internal combustion engine, a hybrid arrangement, a fully electric motor, and / or another type of propulsion system. In at least one embodiment, propulsion system 1150 may be connected to a driveline of vehicle 1100, which may include, but is not limited to, a transmission for enabling propulsion of vehicle 1100. In at least one embodiment, propulsion system 1150 may be controlled in response to receiving a signal from a throttle / accelerator 1152.

[0145] In at least one embodiment, when propulsion system 1150 is operating (e.g., when vehicle 1100 is in motion), a steering system 1154 (which may include, but is not limited to, a steering wheel) is used to steer vehicle 1100 (e.g., along a desired path or route). In at least one embodiment, steering system 1154 may receive a signal from a steering actuator 1156. In at least one embodiment, for fully automated (level 5) functionality, the steering wheel may be optional. In at least one embodiment, a brake sensor system 1146 may be used to operate vehicle brakes in response to receiving a signal from a brake actuator 1148 and / or a brake sensor.

[0146] In at least one embodiment, one or more controllers 1136, which may include, but is not limited to, one or more system-on-chips (“SoC”) ( Figure 11A(not shown) and / or a graphics processing unit (“GPU”) to provide signals (e.g., representative of commands) to one or more components and / or systems of the vehicle 1100. For example, in at least one embodiment, one or more controllers 1136 may send signals to operate vehicle brakes via a brake actuator 1148, operate a steering system 1154 via one or more steering actuators 1156, and operate a propulsion system 1150 via one or more throttles / accelerators 1152. In at least one embodiment, one or more controllers 1136 may include one or more in-vehicle (e.g., integrated) computing devices that process sensor signals and output operation commands (e.g., signals representative of commands) to effect autonomous driving and / or assist a human driver in driving the vehicle 1100. In at least one embodiment, one or more controllers 1136 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functions (e.g., computer vision), a fourth controller for infotainment functions, a fifth controller for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the above functions, and two or more controllers may handle a single function and / or any combination thereof.

[0147] In at least one embodiment, one or more controllers 1136 provide signals for controlling one or more components and / or systems of the vehicle 1100 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, sensor data may be received from, for example but not limited to, the following sensors: one or more Global Navigation Satellite System (“GNSS”) sensors 1158 (e.g., one or more Global Positioning System sensors), one or more RADAR sensors 1160, one or more ultrasonic sensors 1162, one or more LIDAR sensors 1164, one or more Inertial Measurement Unit (IMU) sensors 1166 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 1196, one or more stereo cameras 1168, one or more wide-angle cameras 1170 (e.g., fisheye cameras), one or more infrared cameras 1172, one or more surround cameras 1174 (e.g., 360-degree cameras), remote cameras ( Figure 11A (not shown), mid-range cameras ( Figure 11Anot shown), one or more speed sensors 1144 (e.g., for measuring the speed of vehicle 1100), one or more vibration sensors 1142, one or more steering sensors 1140, one or more braking sensors (e.g., as part of a braking sensor system 1146), and / or other sensor types.

[0148] In at least one embodiment, one or more controllers 1136 may receive inputs (e.g., represented by input data) from the instrument panel 1132 of vehicle 1100 and provide outputs (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 1134, a sound annunciator, a speaker, and / or via other components of vehicle 1100. In at least one embodiment, the output may include information such as vehicle speed, speed, time, map data (e.g., a high-definition map ( Figure 11A not shown), location data (e.g., the location of vehicle 1100, e.g., on a map), direction, the locations of other vehicles (e.g., occupancy grids), information about objects, and the status of objects sensed by one or more controllers 1136, etc. For example, in at least one embodiment, the HMI display 1134 may display information about the presence of one or more objects (e.g., road signs, warning signs, traffic signal changes, etc.) and / or information about driving maneuvers the vehicle has made, is making, or will make (e.g., changing lanes now, reaching exit 34B in two miles, etc.).

[0149] In at least one embodiment, vehicle 1100 further includes a network interface 1124, which may communicate via one or more networks using one or more wireless antennas 1126 and / or one or more modems. For example, in at least one embodiment, the network interface 1124 may be capable of communicating via Long-Term Evolution (“LTE”), Wideband Code Division Multiple Access (“WCDMA”), Universal Mobile Telecommunications System (“UMTS”), Global System for Mobile Communications (“GSM”), IMT-CDMA Multi-Carrier (“CDMA2000”) networks, etc. In at least one embodiment, one or more wireless antennas 1126 may also enable communication between objects in the environment (e.g., vehicles, mobile devices, etc.) using one or more local area networks (such as Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, etc.) and / or one or more low-power wide area networks (“LPWAN”) (such as LoRaWAN, SigFox, etc. protocols).

[0150] Logic 815 for performing inference and / or training operations associated with one or more embodiments. As described herein in connection with Figure 8A and / or Figure 8BDetails regarding logic 815 are provided. In at least one embodiment, logic 815 can be used in vehicle 1000 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0151] In at least one embodiment, vehicle 1100 is used to at least partially implement text-based object generation as shown in Figures 1 - 6 the following.

[0152] Figure 11B An example of the camera positions and fields of view of autonomous vehicle 1100 according to at least one embodiment is shown. In at least one embodiment, the cameras and respective fields of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located at different positions on vehicle 1100. Figure 11A

[0153] In at least one embodiment, the camera type for the cameras can include, but is not limited to, digital cameras that may be adapted to work with the components and / or systems of vehicle 1100. In at least one embodiment, one or more cameras can operate at an automotive safety integrity level (“ASIL”) B and / or other ASIL. In at least one embodiment, the camera type may be capable of having any image capture rate, such as 60 frames per second (fps), 120 fps, 240 fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, other types of shutters, or a combination thereof. In at least one embodiment, the color filter array can include a red clear clear clear (“RCCC”) color filter array, a red clear clear blue (“RCCB”) color filter array, a red blue green clear (“RBGC”) color filter array, a Foveon X3 color filter array, a Bayer (RGGB) sensor color filter array, a monochrome sensor color filter array, and / or other types of color filter arrays. In at least one embodiment, transparent pixel cameras, such as cameras having RCCC, RCCB, and / or RBGC color filter arrays, can be used to attempt to improve photosensitivity.

[0154] In at least one embodiment, one or more cameras can be used to perform advanced driver assistance system (“ADAS”) functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-functional monocular camera can be installed to provide functions including lane departure warning, traffic sign assistance, and smart headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) can record and provide image data (e.g., video) simultaneously.​

[0155] In at least one embodiment, one or more cameras can be mounted in a mounting assembly, such as a custom-designed (three-dimensional (“3D”) printed) assembly, to remove stray light and reflected light from within the vehicle 1100 (e.g., reflected light from the dashboard reflected in the windshield mirror) that may interfere with the camera's image data capture capabilities. Regarding the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly can be 3D printed custom such that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras can be integrated into the rearview mirror. In at least one embodiment, for side cameras, one or more cameras can also be integrated within the four pillars at each corner of the cabin.

[0156] In at least one embodiment, a camera having a field of view of portions of the environment in front of the vehicle 1100 (e.g., a forward camera) can be used for surround view to help identify the forward path and obstacles and to assist in providing information crucial for generating an occupancy grid and / or determining a preferred vehicle path with the help of one or more controllers 1136 and / or a control SoC. In at least one embodiment, the forward camera can be used to perform many ADAS functions similar to LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward camera can also be used for ADAS functions and systems, including but not limited to lane departure warning (“LDW”), adaptive cruise control (“ACC”), and / or other functions (such as traffic sign recognition).

[0157] In at least one embodiment, a variety of cameras can be used in a forward configuration, including for example a monocular camera platform including a CMOS (“complementary metal oxide semiconductor”) color imager. In at least one embodiment, a wide-angle camera 1170 can be used to sense objects entering the view from the periphery (e.g., pedestrians, intersection traffic, or bicycles). Although only one wide-angle camera 1170 is shown Figure 11B in, in other embodiments, there can be any number (including zero) of wide-angle cameras on the vehicle 1100. In at least one embodiment, any number of long-range cameras 1198 (e.g., a long-range stereo camera pair) can be used for depth-based object detection, especially for objects for which a neural network has not been trained. In at least one embodiment, one or more long-range cameras 1198 can also be used for object detection and classification and basic object tracking.

[0158] In at least one embodiment, any number of stereo cameras 1168 may also be included in a forward configuration. In at least one embodiment, one or more stereo cameras 1168 may include an integrated control unit that includes a scalable processing unit that may provide programmable logic (“FPGA”) and a multi-core microprocessor with a controller area network (“CAN”) or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the environment of vehicle 1100, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 1168 may include, but are not limited to, compact stereo vision sensors that may include, but are not limited to, two camera lenses (one each for left and right) and an image processing chip that may measure the distance from vehicle 1100 to a target object and use the information generated (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 1168 may be used in addition to or in place of those described herein.

[0159] In at least one embodiment, cameras having a field of view of portions of the environment including the sides of vehicle 1100 (e.g., side cameras) may be used for surround view, which provides information for creating and updating an occupancy grid, as well as generating side impact collision warnings. For example, in at least one embodiment, surround cameras 1174 (e.g., four surround cameras as Figure 11B shown) may be positioned on vehicle 1100. In at least one embodiment, one or more surround cameras 1174 may include, but are not limited to, any number and combination of wide-angle cameras, one or more fisheye cameras, one or more 360-degree cameras, and / or similar cameras. For example, in at least one embodiment, four fisheye cameras may be located at the front, rear, and sides of vehicle 1100. In at least one embodiment, vehicle 1100 may use three surround cameras 1174 (e.g., left, right, and rear), and may utilize one or more other cameras (e.g., a forward camera) as the fourth surround camera.

[0160] In at least one embodiment, cameras having a field of view of portions of the environment including the rear of vehicle 1100 (e.g., rear cameras) may be used for parking assistance, surround view, rear collision warning, and creating and updating an occupancy grid. In at least one embodiment, a variety of cameras may be used, including but not limited to cameras that are also suitable as one or more forward cameras (e.g., long-range camera 1198 and / or one or more mid-range cameras 1176, one or more stereo cameras 1168, one or more infrared cameras 1172, etc.) as described herein.

[0161] Figure 11Cis a block diagram showing an example system architecture of an autonomous vehicle 1100 in accordance with at least one embodiment. In at least one embodiment, Figure 11A each of the components, features, and systems of the vehicle 1100 in Figure 11C is shown as being connected via a bus 1102. In at least one embodiment, the bus 1102 may include, but is not limited to, a CAN data interface (alternatively referred to herein as the "CAN bus"). In at least one embodiment, CAN may be a network inside the vehicle 1100 for assisting in controlling various features and functions of the vehicle 1100, such as actuation of brakes, acceleration, braking, steering, windshield wipers, etc. In at least one embodiment, the bus 1102 may be configured to have dozens or even hundreds of nodes, each having its own unique identifier (e.g., CAN ID). In at least one embodiment, the bus 1102 can be read to find the steering wheel angle, ground speed, engine revolutions per minute ("RPM"), button positions, and / or other vehicle state indicators. In at least one embodiment, the bus 1102 may be a CAN bus compliant with ASIL B.

[0162] In at least one embodiment, in addition to or instead of CAN, FlexRay and / or Ethernet protocols may also be used. In at least one embodiment, there may be any number of buses forming the bus 1102, which may include, but are not limited to, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using different protocols. In at least one embodiment, two or more buses may be used to perform different functions, and / or may be used for redundancy. For example, a first bus may be used for collision avoidance functions, and a second bus may be used for actuation control. In at least one embodiment, each bus in the bus 1102 may communicate with any component of the vehicle 1100, and two or more buses in the bus 1102 may communicate with corresponding components. In at least one embodiment, each of any number of system-on-chips ("SoC") 1104 (e.g., SoC 1104(A) and SoC 1104(B)), each of one or more controllers 1136, and / or each computer in the vehicle may access the same input data (e.g., input from sensors of the vehicle 1100), and may be connected to a common bus, such as a CAN bus.

[0163] In at least one embodiment, the vehicle 1100 may include one or more controllers 1136, such as those described herein with respect to Figure 11AThose described. In at least one embodiment, the controller 1136 can be used for a variety of functions. In at least one embodiment, the controller 1136 can be coupled to any one of a variety of other components and systems of the vehicle 1100 and can be used to control the vehicle 1100, the artificial intelligence of the vehicle 1100, the infotainment of the vehicle 1100, and / or other functions.

[0164] In at least one embodiment, the vehicle 1100 can include any number of SoCs 1104. In at least one embodiment, each of the SoCs 1104 can include, but is not limited to, a central processing unit (“one or more CPUs”) 1106, a graphics processing unit (“one or more GPUs”) 1108, one or more processors 1110, one or more caches 1112, one or more accelerators 1114, one or more data stores 1116, and / or other components and features not shown. In at least one embodiment, one or more of the SoCs 1104 can be used to control the vehicle 1100 in a variety of platforms and systems. For example, in at least one embodiment, one or more of the SoCs 1104 can be combined with a high-definition (“HD”) map 1122 in a system (e.g., a system of the vehicle 1100), and the HD map 1122 can obtain map refreshes and / or updates from one or more servers ( Figure 11C not shown in the figure).

[0165] In at least one embodiment, one or more of the CPUs 1106 can include a CPU cluster or a CPU complex (alternatively referred to herein as “CCPLEX”). In at least one embodiment, one or more of the CPUs 1106 can include multiple cores and / or a secondary (“L2”) cache. For example, in at least one embodiment, one or more of the CPUs 1106 can include eight cores in a coherent multi-processor configuration. In at least one embodiment, one or more of the CPUs 1106 can include four dual-core clusters, each of which has a dedicated L2 cache (e.g., a 2-megabyte (MB) L2 cache). In at least one embodiment, one or more of the CPUs 1106 (e.g., CCPLEX) can be configured to support simultaneous cluster operations, which enables any combination of the clusters of one or more of the CPUs 1106 to be active at any given time.

[0166] In at least one embodiment, one or more CPUs 1106 may implement power management functions, which include but are not limited to one or more of the following features: automatically clock-gating individual hardware blocks during idle to save dynamic power; gating each core clock when the core is not actively executing instructions due to executing a wait-for-interrupt ("WFI") / wait-for-event ("WFE") instruction; each core can be independently power-gated; when all cores are clock-gated or power-gated, each core cluster can be independently clock-gated; and / or when all cores are power-gated, each core cluster can be independently power-gated. In at least one embodiment, one or more CPUs 1106 may further implement an enhanced algorithm for managing power states, where allowed power states and expected wake-up times are specified, and the hardware / microcode determines the optimal power states to enter for cores, clusters, and CCPLEX. In at least one embodiment, the processing core may support a simplified power state entry sequence in software, where the work is offloaded to the microcode.

[0167] In at least one embodiment, one or more GPUs 1108 may include an integrated GPU (alternatively referred to herein as "iGPU"). In at least one embodiment, one or more GPUs 1108 may be programmable and efficient for parallel workloads. In at least one embodiment, one or more GPUs 1108 may use an enhanced tensor instruction set. In at least one embodiment, one or more GPUs 1108 may include one or more streaming microprocessors, where each streaming microprocessor may include a level-1 ("L1") cache (e.g., an L1 cache with a storage capacity of at least 96 KB), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with a storage capacity of 512 KB). In at least one embodiment, one or more GPUs 1108 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 1108 may use one or more computing application programming interfaces (APIs). In at least one embodiment, one or more GPUs 1108 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).

[0168] In at least one embodiment, one or more GPUs 1108 may be power optimized to achieve optimal performance in automotive and embedded use cases. For example, in at least one embodiment, one or more GPUs 1108 may be fabricated on fin field-effect transistor (“FinFET”) circuitry. In at least one embodiment, each streaming microprocessor may include multiple mixed-precision processing cores partitioned into multiple blocks. By way of example and not limitation, 64 FP32 cores and 32 FP64 cores may be partitioned into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA tensor cores for deep learning matrix arithmetic, a level zero (“L0”) instruction cache, a scheduler (e.g., a warp scheduler) or an orderer, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor may include separate parallel integer and floating-point data paths for efficient execution of workloads with a mix of computational and addressing operations. In at least one embodiment, the streaming microprocessor may include separate thread scheduling capabilities to enable more fine-grained synchronization and cooperation between parallel threads. In at least one embodiment, the streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0169] In at least one embodiment, one or more GPUs 1108 may include high bandwidth memory (“HBM”) and / or a 16GB HBM2 memory subsystem, which in some examples is used to provide a peak memory bandwidth of approximately 900GB / second. In at least one embodiment, synchronous graphics random access memory (“SGRAM”), such as fifth generation graphics double data rate type synchronous random access memory (“GDDR5”), may be used in addition to or in place of HBM memory.

[0170] In at least one embodiment, one or more GPUs 1108 may include unified memory technology. In at least one embodiment, address translation service (“ATS”) support may be used to allow one or more GPUs 1108 to directly access the page tables of one or more CPUs 1106. In at least one embodiment, when a memory management unit (“MMU”) of a GPU in one or more GPUs 1108 experiences a miss, an address translation request may be sent to one or more CPUs 1106. In response, in at least one embodiment, two CPUs in one or more CPUs 1106 may look up the virtual-physical mapping of the address in their page tables and send the translation back to one or more GPUs 1108. In at least one embodiment, unified memory technology may allow a single unified virtual address space for the memories of both one or more CPUs 1106 and one or more GPUs 1108, thus simplifying the programming of one or more GPUs 1108 and porting applications to one or more GPUs 1108.

[0171] In at least one embodiment, one or more GPUs 1108 may include any number of access counters, which may track the access frequency of one or more GPUs 1108 to the memories of other processors. In at least one embodiment, one or more access counters may help ensure that memory pages are moved to the physical memory of the processor that most frequently accesses the pages, thereby improving the efficiency of sharing memory ranges among processors.

[0172] In at least one embodiment, one or more SoCs 1104 may include any number of caches 1112, including those described herein. For example, in at least one embodiment, one or more caches 1112 may include a level-three (“L3”) cache that may be available to both one or more CPUs 1106 and one or more GPUs 1108 (e.g., connected to one or more CPUs 1106 and one or more GPUs 1108). In at least one embodiment, one or more caches 1112 may include a write-back cache that may track the state of each line, such as by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, depending on the embodiment, the L3 cache may include 4MB of memory or more, although smaller cache sizes may be used.

[0173] In at least one embodiment, one or more SoCs 1104 may include one or more accelerators 1114 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, one or more SoCs 1104 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memories. In at least one embodiment, a large on-chip memory (e.g., 4MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 1108 and offload some tasks of one or more GPUs 1108 (e.g., to free up more cycles of one or more GPUs 1108 to perform other tasks). In at least one embodiment, one or more accelerators 1114 may be used for target workloads that are stable enough to withstand acceleration (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.). In at least one embodiment, CNNs may include region-based or region convolutional neural networks (“RCNNs”) and fast RCNNs (e.g., as used for object detection) or other types of CNNs.

[0174] In at least one embodiment, one or more accelerators 1114 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators (“DLAs”). In at least one embodiment, one or more DLAs may include, but are not limited to, one or more tensor processing units (“TPUs”), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and inference. In at least one embodiment, a TPU may be an accelerator configured and optimized to perform image processing functions (e.g., for CNNs, RCNNs, etc.). In at least one embodiment, one or more DLAs may be further optimized for a particular set of neural network types and floating-point operations as well as inference. In at least one embodiment, the design of one or more DLAs may provide higher performance per millimeter than a typical general-purpose GPU and generally far exceed the performance of a CPU. In at least one embodiment, one or more TPUs may perform several functions, including supporting, for example, INT8, INT16, and FP16 data types for single-instance convolution functions for features and weights as well as post-processor functions. In at least one embodiment, one or more DLAs may execute neural networks, especially CNNs, quickly and efficiently on processed or unprocessed data for any of a variety of functions, including, for example, but not limited to: CNNs for object recognition and detection using data from camera sensors; CNNs for distance estimation using data from camera sensors; CNNs for emergency vehicle detection as well as identification and detection using data from microphones; CNNs for face recognition and vehicle owner identification using data from camera sensors; and / or CNNs for protection and / or security-related events.

[0175] In at least one embodiment, one or more DLAs may perform any function of one or more GPUs 1108, and by using an inference accelerator, for example, a designer may target one or more DLAs or one or more GPUs 1108 for any function. For example, in at least one embodiment, a designer may concentrate the processing and floating-point operations of a CNN on one or more DLAs and leave other functions to one or more GPUs 1108 and / or one or more accelerators 1114.

[0176] In at least one embodiment, one or more accelerators 1114 may include a programmable vision accelerator (“PVA”), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, the PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 1138, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. In at least one embodiment, the PVA may provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA may include, for example but not limited to, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”), and / or any number of vector processors.

[0177] In at least one embodiment, the RISC cores may interact with an image sensor (e.g., the image sensor of any of the cameras described herein), an image signal processor, etc. In at least one embodiment, each RISC core may include any number of memories. In at least one embodiment, depending on the embodiment, the RISC cores may use any one of a variety of protocols. In at least one embodiment, the RISC cores may execute a real-time operating system (“RTOS”). In at least one embodiment, one or more integrated circuit devices, application specific integrated circuits (“ASICs”), and / or memory devices may be used to implement the RISC cores. For example, in at least one embodiment, the RISC cores may include an instruction cache and / or tightly coupled RAM.

[0178] In at least one embodiment, the DMA may enable the components of the PVA to access system memory independently of one or more CPUs 1106. In at least one embodiment, the DMA may support any number of features for optimizing the delivery to the PVA, including but not limited to, supporting multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA may support up to six or more dimensions of addressing, which may include but are not limited to block width, block height, block depth, horizontal block stride, vertical block stride, and / or depth stride.

[0179] In at least one embodiment, the vector processor can be a programmable processor that can be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA can include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core can include a processor subsystem, one or more DMA engines (e.g., two DMA engines) and / or other peripherals. In at least one embodiment, the vector processing subsystem can operate as the main processing engine of the PVA and can include a vector processing unit (“VPU”), an instruction cache and / or a vector memory (e.g., “VMEM”). In at least one embodiment, the VPU core can include a digital signal processor, such as, for example, a single instruction multiple data (“SIMD”), very long instruction word (“VLIW”) digital signal processor. In at least one embodiment, the combination of SIMD and VLIW can improve throughput and speed.

[0180] In at least one embodiment, each vector processor can include an instruction cache and can be coupled to a dedicated memory. Thus, in at least one embodiment, each vector processor can be configured to execute independently of other vector processors. In at least one embodiment, the vector processors included in a particular PVA can be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA can execute a general computer vision algorithm, but on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA can simultaneously execute different computer vision algorithms on one image, or even execute different algorithms on a sequence of images or portions of an image. In at least one embodiment, any number of PVAs can be included in a hardware acceleration cluster, and any number of vector processors can be included in each PVA. In at least one embodiment, the PVA can include additional error correction code (“ECC”) memory for enhancing overall system security.

[0181] In at least one embodiment, one or more accelerators 1114 may include an on-chip computer vision network and static random access memory (“SRAM”) to provide high-bandwidth, low-latency SRAM for the one or more accelerators 1114. In at least one embodiment, the on-chip memory may include at least 4 MB of SRAM, which includes, for example but not limited to, eight field-configurable memory blocks that can be accessed by both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and the DLA may access the memory via a backbone that provides high-speed access to the memory for the PVA and the DLA. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and the DLA to the memory (e.g., using APB).

[0182] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and the DLA provide ready and valid signals before transmitting any control signals / address / data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals / address / data, as well as burst-type communication for continuous data transfer. In at least one embodiment, the interface may conform to the International Organization for Standardization (“ISO”) 26262 or the International Electrotechnical Commission (“IEC”) 61508 standard, although other standards and protocols may be used.

[0183] In at least one embodiment, one or more SoCs 1104 may include a real-time ray tracing hardware accelerator. In at least one embodiment, the real-time ray tracing hardware accelerator may be used to quickly and efficiently determine the position and extent of an object (e.g., within a world model) to generate a real-time visualization simulation for RADAR signal interpretation, for sound propagation synthesis and / or analysis, for SONAR system simulation, for general wave propagation simulation, for comparison with LIDAR data for positioning and / or other functions, and / or for other uses.

[0184] In at least one embodiment, one or more accelerators 1114 can have a wide range of uses for autonomous driving. In at least one embodiment, PVA can be used in key processing stages in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of PVA at low power and low latency match well with algorithmic domains that require predictable processing. In other words, PVA excels in semi-dense or dense conventional computations, even on small data sets that may require predictable runtimes with low latency and low power. In at least one embodiment, such as in vehicle 1100, PVA can be designed to run classic computer vision algorithms as they can be efficient in object detection and integer math operations.

[0185] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, algorithms based on semi-global matching can be used in some examples, but this is not meant to be limiting. In at least one embodiment, applications for level 3-5 autonomous driving use motion estimation / stereo matching in operation (e.g., structure from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, PVA can perform computer stereo vision functions on inputs from two monocular cameras.

[0186] In at least one embodiment, PVA can be used to perform dense optical flow. For example, in at least one embodiment, PVA can process raw RADAR data (e.g., using 4D fast Fourier transform) to provide processed RADAR data. In at least one embodiment, for example, PVA is used for time-of-flight depth processing by processing raw time-of-flight data to provide processed time-of-flight data.

[0187] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, for example but not limited to, neural networks, the output of which is a measure of the confidence for each object detection. In at least one embodiment, the confidence can be represented or interpreted as a probability, or as providing a relative "weight" of each detection compared to other detections. In at least one embodiment, the confidence measure enables the system to make further decisions, namely, regarding which detections should be considered true positive detections rather than false positive detections. In at least one embodiment, the system can set a threshold for the confidence, and only consider detections that exceed the threshold as true positive detections. In an embodiment using an automatic emergency braking ("AEB") system, false positive detections will cause the vehicle to automatically perform emergency braking, which is clearly undesirable. In at least one embodiment, highly confident detections can be considered as triggers for AEB. In at least one embodiment, the DLA can run a neural network for regressing confidence values. In at least one embodiment, the neural network can take at least some subset of parameters as its input, such as bounding box dimensions, a ground plane estimate obtained (e.g., from another subsystem), the outputs of one or more IMU sensors 1166 related to the vehicle 1100 direction, distance, 3D position estimate of an object obtained from the neural network and / or other sensors (e.g., one or more LIDAR sensors 1164 or one or more RADAR sensors 1160).

[0188] In at least one embodiment, one or more SoCs 1104 can include one or more data stores 1116 (e.g., memories). In at least one embodiment, one or more data stores 1116 can be on-chip memories of one or more SoCs 1104, which can store neural networks to be executed on one or more GPUs 1108 and / or DLA. In at least one embodiment, one or more data stores 1116 can have a large enough capacity to store multiple instances of neural networks for redundancy and safety. In at least one embodiment, one or more data stores 1116 can include one or more L2 or L3 caches.

[0189] In at least one embodiment, one or more SoCs 1104 may include any number of processors 1110 (e.g., embedded processors). In at least one embodiment, one or more processors 1110 may include a boot and power management processor, which may be a dedicated processor and subsystem for handling boot power and management functions as well as related secure execution. In at least one embodiment, the boot and power management processor may be part of the boot sequence of one or more SoCs 1104 and may provide runtime power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist in system low-power state transitions, manage one or more SoC 1104 thermal and temperature sensors, and / or manage the power state of one or more SoCs 1104. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and one or more SoCs 1104 may use the ring oscillator to detect the temperature of one or more CPUs 1106, one or more GPUs 1108, and / or one or more accelerators 1114. In at least one embodiment, if it is determined that the temperature exceeds a threshold, the boot and power management processor may enter a temperature fault routine and place one or more SoCs 1104 in a lower power state and / or place the vehicle 1100 in a driver's safe parking mode (e.g., safely park the vehicle 1100).

[0190] In at least one embodiment, one or more processors 1110 may further include a set of embedded processors that may be used as an audio processing engine, and the audio processing engine may be an audio subsystem that provides full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core that has a digital signal processor with dedicated RAM.

[0191] In at least one embodiment, one or more processors 1110 may further include an always-on processor engine that may provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the always-on processor engine may include, but is not limited to, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0192] In at least one embodiment, one or more processors 1110 may further include a security cluster engine, which includes but is not limited to a dedicated processor subsystem for handling security management of automotive applications. In at least one embodiment, the security cluster engine may include but is not limited to two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.) and / or routing logic. In a security mode, in at least one embodiment, two or more cores may operate in a lockstep mode and may be used as a single core with comparison logic for detecting any differences between their operations. In at least one embodiment, one or more processors 1110 may further include a real-time camera engine, which may include but is not limited to a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 1110 may further include a high-dynamic range signal processor, which may include but is not limited to an image signal processor, which is a hardware engine as part of a camera processing pipeline.

[0193] In at least one embodiment, one or more processors 1110 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements the video post-processing functions required for a video playback application to produce a final image for a player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 1170, one or more surround cameras 1174, and / or one or more in-cabin monitoring camera sensors. In at least one embodiment, preferably, the in-cabin monitoring camera sensors are monitored by a neural network running on another instance of the SoC 1104, which is configured to identify in-cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform but is not limited to lip reading to activate cellular services and make calls, indicate emails, change the destination of the vehicle, activate or change the vehicle's infotainment system and settings, or provide voice-activated web surfing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode and are otherwise disabled.

[0194] In at least one embodiment, the video image synthesizer may include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, in the case of motion occurring in the video, the noise reduction appropriately weights the spatial information, thereby reducing the weight of the information provided by adjacent frames. In at least one embodiment, in the case where an image or a part of the image does not include motion, the temporal noise reduction performed by the video image synthesizer may use information from a previous image to reduce the noise in the current image.

[0195] In at least one embodiment, the video image synthesizer may also be configured to perform stereoscopic correction on the input stereoscopic camera frames. In at least one embodiment, when the operating system desktop is in use, the video image synthesizer may also be used for user interface synthesis and does not require one or more GPUs 1108 to continuously render new surfaces. In at least one embodiment, when one or more GPUs 1108 are powered on and active for 3D rendering, the video image synthesizer may be used to offload one or more GPUs 1108 to improve performance and responsiveness.

[0196] In at least one embodiment, one or more of the SoCs 1104 may further include a Mobile Industry Processor Interface ("MIPI") camera serial interface, a high-speed interface, and / or a video input block for receiving video and inputs from cameras, which can be used for camera and related pixel input functions. In at least one embodiment, one or more of the SoCs 1104 may further include an input / output controller, which can be software-controlled and can be used to receive I / O signals that are not committed to a specific role.

[0197] In at least one embodiment, one or more of the SoCs 1104 may further include a wide range of peripheral interfaces for enabling communication with peripheral devices, audio encoder / decoders ("codecs"), power management, and / or other devices. In at least one embodiment, one or more of the SoCs 1104 can be used to process data from cameras (e.g., connected via Gigabit Multimedia Serial Link and Ethernet channels), sensors (e.g., one or more LIDAR sensors 1164, one or more RADAR sensors 1160, etc., which can be connected via Ethernet channels), data from the bus 1102 (e.g., the speed of the vehicle 1100, the steering wheel position, etc.), data from one or more GNSS sensors 1158 (e.g., connected via Ethernet bus or CAN bus), etc. In at least one embodiment, one or more of the SoCs 1104 may further include dedicated high-performance mass storage controllers, which may include their own DMA engines and can be used to free one or more CPUs 1106 from routine data management tasks.

[0198] In at least one embodiment, one or more SoCs 1104 can be an end-to-end platform with a flexible architecture that spans automation levels 3-5, thus providing an integrated functional safety architecture for a platform that leverages and effectively uses computer vision and ADAS technologies to achieve diversity and redundancy, and provides a flexible, reliable driving software stack as well as deep learning tools. In at least one embodiment, one or more SoCs 1104 can be faster, more reliable, and even more energy-efficient and space-efficient than conventional systems. For example, in at least one embodiment, one or more accelerators 1114, when combined with one or more CPUs 1106, one or more GPUs 1108, and one or more data stores 1116, can provide a fast, efficient platform for level 3-5 autonomous vehicles.

[0199] In at least one embodiment, computer vision algorithms can be executed on a CPU, which can be configured using a high-level programming language (such as C) to execute various processing algorithms on various visual data. However, in at least one embodiment, a CPU generally cannot meet the performance requirements of many computer vision applications, such as performance requirements related to execution time and power consumption. In at least one embodiment, many CPUs cannot execute complex object detection algorithms in real time, which are used in in-vehicle ADAS applications and actual level 3-5 autonomous vehicles.

[0200] The embodiments described herein allow multiple neural networks to be executed simultaneously and / or sequentially, and allow the results to be combined to achieve level 3-5 autonomous driving functions. For example, in at least one embodiment, a CNN executed on a DLA or discrete GPU (e.g., one or more GPUs 1120) can include text and word recognition, thus allowing traffic signs to be read and understood, including signs for which the neural network has not been specifically trained. In at least one embodiment, the DLA can also include a neural network that can recognize, interpret, and provide semantic understanding of the signs, and pass that semantic understanding to a path planning module running on a CPU complex.

[0201] In at least one embodiment, for level 3, 4, or 5 driving, multiple neural networks can be run simultaneously. For example, in at least one embodiment, a warning sign that states "Caution: flashing lights indicate icy conditions", along with the electric lights, can be interpreted independently or jointly by several neural networks. In at least one embodiment, the warning sign itself can be recognized as a traffic sign by a first deployed neural network (e.g., a neural network that has been trained), and the text "flashing lights indicate icy conditions" can be interpreted by a second deployed neural network, which notifies the vehicle's path planning software (preferably executed on the CPU complex) that when flashing lights are detected, there is an icy condition. In at least one embodiment, a third deployed neural network can operate on multiple frames to identify the flashing lights and notify the vehicle's path planning software of the presence (or absence) of the flashing lights. In at least one embodiment, all three neural networks can run simultaneously, e.g., within the DLA and / or on one or more GPUs 1108.

[0202] In at least one embodiment, a CNN for face recognition and vehicle owner recognition can use data from camera sensors to identify the presence of an authorized driver and / or the owner of the vehicle 1100. In at least one embodiment, when the owner approaches the driver's door and turns on the lights, a normally open sensor processing engine can be used to unlock the vehicle, and in a security mode, when the owner leaves the vehicle, it can be used to disable the vehicle. In this way, one or more SoCs 1104 provide protection against theft and / or carjacking.

[0203] In at least one embodiment, a CNN for emergency vehicle detection and recognition can use data from the microphone 1196 to detect and recognize emergency vehicle sirens. In at least one embodiment, one or more SoCs 1104 use CNNs to classify environmental and urban sounds, as well as visual data. In at least one embodiment, a CNN running on the DLA is trained to recognize the relative approach speed of an emergency vehicle (e.g., by using the Doppler effect). In at least one embodiment, the CNN can also be trained to recognize emergency vehicles specific to the local area in which the vehicle is operating, as identified by one or more GNSS sensors 1158. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while in North America, the CNN will seek to recognize only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used, with the assistance of one or more ultrasonic sensors 1162, to execute emergency vehicle safety routines, slow down the vehicle, drive the vehicle to the side of the road, stop, and / or idle the vehicle until the emergency vehicle has passed.

[0204] In at least one embodiment, vehicle 1100 may include one or more CPUs 1118 (e.g., one or more discrete CPUs or one or more dCPUs), which may be coupled to one or more SoCs 1104 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, one or more CPUs 1118 may include, for example, X86 processors. One or more CPUs 1118 can be used to perform any of a variety of functions, such as arbitrating potentially inconsistent results between ADAS sensors and one or more SoCs 1104, and / or monitoring the status and health of one or more controllers 1136 and / or on-chip infotainment system (“infotainment SoC”) 1130. In at least one embodiment, one or more SoCs 1104 include one or more interconnects, and the interconnects may include Peripheral Component Interconnect Express (PCIe).

[0205] In at least one embodiment, vehicle 1100 may include one or more GPUs 1120 (e.g., one or more discrete GPUs or one or more dGPUs), which may be coupled to one or more SoCs 1104 via a high-speed interconnect (e.g., NVIDIA's NVLINK channels). In at least one embodiment, one or more GPUs 1120 may provide additional artificial intelligence capabilities, such as by executing redundant and / or different neural networks, and may be used to train and / or update neural networks at least in part based on inputs (e.g., sensor data) from sensors of vehicle 1100.

[0206] In at least one embodiment, vehicle 1100 may further include a network interface 1124, which may include but is not limited to one or more wireless antennas 1126 (e.g., one or more wireless antennas for different communication protocols, such as cellular antennas, Bluetooth antennas, etc.). In at least one embodiment, network interface 1124 may be used to implement wireless connections to Internet cloud services (e.g., with servers and / or other network devices), with other vehicles, and / or with computing devices (e.g., a passenger's client device). In at least one embodiment, to communicate with other vehicles, a direct link may be established between vehicle 1100 and another vehicle and / or an indirect link (e.g., via a network and the Internet) may be established. In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide the direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 1100 with information about vehicles in the vicinity of vehicle 1100 (e.g., vehicles in front of, to the side of, and / or behind vehicle 1100). In at least one embodiment, the foregoing functionality may be part of the cooperative adaptive cruise control function of vehicle 1100.

[0207] In at least one embodiment, network interface 1124 may include a SoC that provides modulation and demodulation functions and enables one or more controllers 1136 to communicate over a wireless network. In at least one embodiment, network interface 1124 may include a radio frequency front end for up-converting from baseband to radio frequency and down-converting from radio frequency to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed by known processes and / or using a super-heterodyne process. In at least one embodiment, the radio frequency front end functions may be provided by a separate chip. In at least one embodiment, the network interface may include wireless capabilities for communicating over LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0208] In at least one embodiment, vehicle 1100 may further include one or more data stores 1128, which may include, but are not limited to, off-chip (e.g., one or more off-chip SoCs 1104) storage. In at least one embodiment, one or more data stores 1128 may include, but are not limited to, one or more storage elements, including RAM, SRAM, dynamic random access memory (“DRAM”), video random access memory (“VRAM”), flash memory, hard disks, and / or other components and / or devices capable of storing at least one bit of data.

[0209] In at least one embodiment, vehicle 1100 may further include one or more GNSS sensors 1158 (e.g., GPS and / or assisted GPS sensors) to assist in mapping, perception, occupancy grid generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 1158 may be used, including, for example but not limited to, a GPS using a USB connector with an Ethernet to serial interface (e.g., RS-232) bridge.

[0210] In at least one embodiment, vehicle 1100 may further include one or more RADAR sensors 1160. In at least one embodiment, the one or more RADAR sensors 1160 may be used by vehicle 1100 for remote vehicle detection, even in dark and / or adverse weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. In at least one embodiment, the one or more RADAR sensors 1160 may use the CAN bus and / or bus 1102 (e.g., for transmitting data generated by the one or more RADAR sensors 1160) to control and access object tracking data and, in some examples, may access an Ethernet channel to access raw data. In at least one embodiment, a variety of RADAR sensor types may be used. For example but not limited to, the one or more RADAR sensors 1160 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more of the one or more RADAR sensors 1160 are pulsed Doppler RADAR sensors.

[0211] In at least one embodiment, the one or more RADAR sensors 1160 may include different configurations, such as long range with a narrow field of view, short range with a wide field of view, short range side coverage, etc. In at least one embodiment, long range RADAR may be used for the adaptive cruise control function. In at least one embodiment, the long range RADAR system may provide a wide field of view achieved through two or more independent scans (e.g., within a range of 250 m (meters)). In at least one embodiment, the one or more RADAR sensors 1160 may assist in differentiating between static and moving objects and may be used by the ADAS system 1138 for emergency braking assistance and forward collision warning. In at least one embodiment, one or more of the sensors 1160 included in the long range RADAR system may include but are not limited to a monostatic multimodal RADAR having multiple (e.g., six or more) fixed RADAR antennas and high speed CAN and FlexRay interfaces. In at least one embodiment, with six antennas, the central four antennas may create a focused beam pattern designed to record the surrounding environment of vehicle 1100 at a relatively high speed with minimal traffic interference from adjacent lanes. In at least one embodiment, the other two antennas may widen the field of view, enabling it to quickly detect vehicles entering or leaving the lane of vehicle 1100.

[0212] In at least one embodiment, by way of example, a mid-range RADAR system may include a range of up to 160 m (front) or 80 m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, a short-range RADAR system may include, but is not limited to, any number of RADAR sensors 1160 designed to be mounted at both ends of the rear bumper. When mounted at both ends of the rear bumper, in at least one embodiment, the RADAR sensor system may generate two beams that continuously monitor the rear direction of the vehicle and the blind spots in the vicinity. In at least one embodiment, the short-range RADAR system may be used in the ADAS system 1138 for blind spot detection and / or lane change assistance.

[0213] In at least one embodiment, the vehicle 1100 may further include one or more ultrasonic sensors 1162. In at least one embodiment, one or more ultrasonic sensors 1162 that may be positioned at the front, rear, and / or side positions of the vehicle 1100 may be used for parking assistance and / or creating and updating an occupancy grid. In at least one embodiment, a variety of ultrasonic sensors 1162 may be used, and different ultrasonic sensors 1162 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensors 1162 may operate at a functional safety level of ASIL B.

[0214] In at least one embodiment, the vehicle 1100 may include one or more LIDAR sensors 1164. In at least one embodiment, one or more LIDAR sensors 1164 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, one or more LIDAR sensors 1164 may operate at a functional safety level of ASIL B. In at least one embodiment, the vehicle 1100 may include multiple (e.g., two, four, six, etc.) LIDAR sensors 1164 that may use an Ethernet channel (e.g., to provide data to a gigabit Ethernet switch).

[0215] In at least one embodiment, one or more LIDAR sensors 1164 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, commercially available one or more LIDAR sensors 1164 may, for example, have an advertised range of approximately 100 m, an accuracy of 2 cm - 3 cm, and support an Ethernet connection of 100 Mbps. In at least one embodiment, one or more non-protruding LIDAR sensors may be used. In such an embodiment, one or more LIDAR sensors 1164 may include small devices that can be embedded in the front, rear, sides, and / or corner positions of the vehicle 1100. In at least one embodiment, one or more LIDAR sensors 1164, in such an embodiment, may provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, even for low-reflectivity objects, and have a range of 200 m. In at least one embodiment, the one or more forward-mounted LIDAR sensors 1164 may be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0216] In at least one embodiment, LIDAR technologies such as 3D flash LIDAR may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate up to approximately 200 m around the vehicle 1100. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the laser pulse propagation time and the reflected light on each pixel, which in turn corresponds to the range from the vehicle 1100 to the object. In at least one embodiment, flash LIDAR may allow for the generation of a highly accurate and distortion-free image of the surrounding environment using each laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, with one on each side of the vehicle 1100. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D staring array LIDAR camera that has no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device may use a Class I (eye-safe) laser pulse of 5 nanoseconds per frame and may capture the reflected laser as a 3D range point cloud and co-registered intensity data.

[0217] In at least one embodiment, vehicle 1100 may further include one or more IMU sensors 1166. In at least one embodiment, one or more IMU sensors 1166 may be located at the center of the rear axle of vehicle 1100. In at least one embodiment, one or more IMU sensors 1166 may include, for example but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, one or more magnetic compasses, and / or other sensor types. In at least one embodiment, for example in a six-axis application, one or more IMU sensors 1166 may include but not limited to accelerometers and gyroscopes. In at least one embodiment, for example in a nine-axis application, one or more IMU sensors 1166 may include but not limited to accelerometers, gyroscopes, and magnetometers.

[0218] In at least one embodiment, one or more IMU sensors 1166 may be implemented as a miniature high-performance GPS-aided inertial navigation system (“GPS / INS”) that combines microelectromechanical system (“MEMS”) inertial sensors, a high-sensitivity GPS receiver, and advanced Kalman filtering algorithms for providing estimates of position, velocity, and attitude. In at least one embodiment, one or more IMU sensors 1166 may enable vehicle 1100 to estimate its heading by directly observing and correlating speed changes from GPS to one or more IMU sensors 1166 without input from magnetic sensors. In at least one embodiment, one or more IMU sensors 1166 and one or more GNSS sensors 1158 may be combined in a single integrated unit.

[0219] In at least one embodiment, vehicle 1100 may include one or more microphones 1196 placed inside and / or around vehicle 1100. In at least one embodiment, one or more microphones 1196 may be used for emergency vehicle detection and identification.

[0220] In at least one embodiment, vehicle 1100 may further include any number of camera types, including one or more stereo cameras 1168, one or more wide-angle cameras 1170, one or more infrared cameras 1172, one or more surround cameras 1174, one or more long-range cameras 1198, one or more mid-range cameras 1176, and / or other camera types. In at least one embodiment, the cameras can be used to capture image data around the entire periphery of vehicle 1100. In at least one embodiment, the type of camera used depends on vehicle 1100. In at least one embodiment, any combination of camera types can be used to provide the necessary coverage around vehicle 1100. In at least one embodiment, the number of cameras deployed can vary according to the embodiment. For example, in at least one embodiment, vehicle 1100 can include six cameras, seven cameras, ten cameras, twelve cameras, or other numbers of cameras. In at least one embodiment, the cameras can support, by way of example but not limitation, Gigabit Multimedia Serial Link (“GMSL”) and / or Gigabit Ethernet communications. In at least one embodiment, each camera was described in more detail previously herein with reference to Figure 11A and Figure 11B Each camera was described in more detail previously herein with reference to

[0221] In at least one embodiment, vehicle 1100 may further include one or more vibration sensors 1142. In at least one embodiment, one or more vibration sensors 1142 can measure the vibration of components of vehicle 1100 (e.g., the axle). For example, in at least one embodiment, a change in vibration can indicate a change in the road surface. In at least one embodiment, when two or more vibration sensors 1142 are used, the difference between the vibrations can be used to determine the friction or skidding of the road surface (e.g., when there is a vibration difference between a power-driven axle and a freely rotating axle).

[0222] In at least one embodiment, vehicle 1100 can include an ADAS system 1138. In at least one embodiment, the ADAS system 1138 may include, in some examples, but not be limited to, a SoC. In at least one embodiment, the ADAS system 1138 can include, but not be limited to, any number and any combination of autonomous / adaptive / automatic cruise control (“ACC”) systems, cooperative adaptive cruise control (“CACC”) systems, forward collision warning (“FCW”) systems, automatic emergency braking (“AEB”) systems, lane departure warning (“LDW”) systems, lane keeping assist (“LKA”) systems, blind spot warning (“BSW”) systems, rear cross traffic warning (“RCTW”) systems, collision warning (“CW”) systems, lane centering (“LC”) systems, and / or other systems, features, and / or functions.

[0223] In at least one embodiment, the ACC system may use one or more RADAR sensors 1160, one or more LIDAR sensors 1164, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle immediately in front of vehicle 1100 and automatically adjusts the speed of vehicle 1100 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system performs distance keeping and recommends that vehicle 1100 change lanes when necessary. In at least one embodiment, the lateral ACC is related to other ADAS applications, such as LC and CW.

[0224] In at least one embodiment, the CACC system uses information from other vehicles, which may be received indirectly from other vehicles via the network interface 1124 and / or one or more wireless antennas 1126 via a wireless link or through a network connection (e.g., via the Internet). In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle (“V2V”) communication link, while the indirect link may be provided by an infrastructure-to-vehicle (“I2V”) communication link. Generally, V2V communication provides information about the vehicle immediately ahead (e.g., a vehicle immediately in front of and in the same lane as vehicle 1100), while I2V communication provides information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of the I2V and V2V information sources. In at least one embodiment, given information about the vehicles ahead of a given vehicle 1100, the CACC system may be more reliable and has the potential to improve the smoothness of traffic flow and reduce road congestion.

[0225] In at least one embodiment, the FCW system is designed to warn the driver of a hazard so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward camera and / or one or more RADAR sensors 1160, which are coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration component. In at least one embodiment, the FCW system may provide warnings, such as in the form of a sound, visual warning, vibration, and / or a rapid braking pulse.

[0226] In at least one embodiment, the AEB system detects an impending forward collision with another vehicle or other object and can automatically apply the brakes if the driver does not take corrective action within specified time or distance parameters. In at least one embodiment, the AEB system can use one or more forward cameras and / or one or more RADAR sensors 1160 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, it typically first warns the driver to take corrective action to avoid the collision, and, if the driver does not take corrective action, the AEB system can automatically apply the brakes in an attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system can include technologies such as dynamic brake support and / or collision imminent braking.

[0227] In at least one embodiment, when vehicle 1100 crosses a lane marker, the LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibration, to warn the driver. In at least one embodiment, the LDW system does not activate when the driver indicates an intentional lane departure, such as by activating a turn signal. In at least one embodiment, the LDW system can use a forward-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback such as a display, speaker, and / or vibration component. In at least one embodiment, the LKA system is a variant of the LDW system. In at least one embodiment, if vehicle 1100 begins to leave its lane, the LKA system provides steering input or braking to correct vehicle 1100.

[0228] In at least one embodiment, the BSW system detects and warns the driver that the vehicle is in the blind spot of the vehicle. In at least one embodiment, the BSW system can provide visual, audible, and / or tactile alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system can provide additional warnings when the driver uses a turn signal. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 1160 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to driver feedback such as a display, speaker, and / or vibration component.

[0229] In at least one embodiment, when the vehicle 1100 detects an object outside the rear camera range while reversing, the RCTW system can provide visual, auditory, and / or tactile notifications. In at least one embodiment, the RCTW system includes an AEB system for ensuring that vehicle braking is applied to avoid a collision. In at least one embodiment, the RCTW system can use one or more rear-facing RADAR sensors 1160 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback such as a display, speaker, and / or vibration component.

[0230] In at least one embodiment, conventional ADAS systems may be prone to producing false positive results, which may annoy and distract the driver, but are generally not catastrophic because conventional ADAS systems will warn the driver and allow the driver to decide whether a safety situation truly exists and take action accordingly. In at least one embodiment, in the case of conflicting results, the vehicle 1100 itself decides whether to follow the result of the primary computer or the secondary computer (e.g., the first controller or the second controller in the controller 1136). For example, in at least one embodiment, the ADAS system 1138 can be a backup and / or secondary computer for providing perception information to the backup computer rationality module. In at least one embodiment, the backup computer rationality monitor can run various software redundantly on hardware components to detect faults in perception and dynamic driving tasks. In at least one embodiment, the output from the ADAS system 1138 can be provided to the supervisory MCU. In at least one embodiment, if the output from the primary computer conflicts with the output from the secondary computer, the supervisory MCU decides how to reconcile the conflict to ensure safe operation.

[0231] In at least one embodiment, the primary computer can be configured to provide a confidence score to the supervisory MCU, which indicates the primary computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU can follow the instructions of the primary computer, regardless of whether the secondary computer provides conflicting or inconsistent results. In at least one embodiment, in the case where the confidence score does not meet the threshold and the primary computer and the secondary computer indicate different results (e.g., conflict), the supervisory MCU can arbitrate between the computers to determine an appropriate result.

[0232] In at least one embodiment, the supervisory MCU can be configured to run a neural network that is trained and configured to determine conditions under which the auxiliary computer provides an error alert based at least in part on outputs from the host computer and outputs from the auxiliary computer. In at least one embodiment, one or more neural networks in the supervisory MCU can learn when the output of the auxiliary computer can be trusted and when it cannot be trusted. For example, in at least one embodiment, when the auxiliary computer is a RADAR-based FCW system, one or more neural networks in the supervisory MCU can learn when the FCW system is identifying a metallic object that is not actually a hazard, such as a drain grate or manhole cover that would trigger an alert. In at least one embodiment, when the auxiliary computer is a camera-based LDW system, the neural network in the supervisory MCU can learn to override the LDW when there is a bicyclist or pedestrian present and lane departure is actually the safest course of action. In at least one embodiment, the supervisory MCU can include at least one of a DLA or GPU suitable for running one or more neural networks with associated memory. In at least one embodiment, the supervisory MCU can be included as and / or be included in components of one or more SoCs 1104.

[0233] In at least one embodiment, the ADAS system 1138 can include an auxiliary computer that performs ADAS functions using traditional computer vision rules. In at least one embodiment, the auxiliary computer can use classical computer vision rules (if-then), and the presence of one or more neural networks in the supervisory MCU can improve reliability, safety, and performance. For example, in at least one embodiment, the diverse implementations and intentional non-identity make the overall system more fault-tolerant, especially for faults caused by software (or software-hardware interface) functions. For example, in at least one embodiment, if there is a software vulnerability or error in the software running on the host computer and the not-identical software code running on the auxiliary computer provides a consistent overall result, the supervisory MCU can have greater confidence that the overall result is correct, and the vulnerability in the software or hardware on the host computer will not result in a major error.

[0234] In at least one embodiment, the output of the ADAS system 1138 can be fed into the perception block of the host computer and / or the dynamic driving task block of the host computer. For example, in at least one embodiment, if the ADAS system 1138 indicates a forward collision warning due to an object directly ahead, the perception block can use that information when the object is identified. In at least one embodiment, as described herein, the auxiliary computer can have its own neural network that is trained to reduce the risk of false alarms.

[0235] In at least one embodiment, vehicle 1100 may further include an infotainment SoC 1130 (e.g., in-vehicle infotainment (IVI)). Although shown and described as an SoC, in at least one embodiment, infotainment system SoC 1130 may not be an SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, infotainment SoC 1130 may include, but is not limited to, a combination of hardware and software that may be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., television, movies, streaming, etc.), telephone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.), and / or information services (e.g., navigation systems, rear parking assist, radio data system, vehicle-related information such as fuel level, total covered distance, brake fuel level, oil level, door open / closed, air filter information, etc.) to vehicle 1100. For example, infotainment SoC 1130 may include a radio, disk player, navigation system, video player, USB and Bluetooth connectivity, in-vehicle computer, in-vehicle entertainment system, WiFi, steering wheel audio control, hands-free voice control, head-up display (“HUD”), HMI display 1134, telematics device, control panel (e.g., for controlling various components, features, and / or systems and / or interacting therewith), and / or other components. In at least one embodiment, infotainment SoC 1130 may further be used to provide information (e.g., visual and / or auditory information) to one or more users of vehicle 1100, such as information from ADAS system 1138, autonomous driving information (such as planned vehicle maneuvers), trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0236] In at least one embodiment, infotainment SoC 1130 may include any number and type of GPU functionality. In at least one embodiment, infotainment SoC 1130 may communicate with other devices, systems, and / or components of vehicle 1100 via bus 1102. In at least one embodiment, infotainment SoC 1130 may be coupled to a supervisory MCU such that the GPU of the infotainment system may perform some autonomous driving functions in the event of a failure of one or more main controllers 1136 (e.g., the main computer and / or standby computer of vehicle 1100). In at least one embodiment, infotainment SoC 1130 may place vehicle 1100 into a driver-to-safe parking mode as described herein.

[0237] In at least one embodiment, vehicle 1100 may further include a dashboard 1132 (e.g., a digital dashboard, an electronic dashboard, a digital instrument panel, etc.). In at least one embodiment, dashboard 1132 may include, but is not limited to, a controller and / or a supercomputer (e.g., a discrete controller or supercomputer). In at least one embodiment, dashboard 1132 may include, but is not limited to, any number and combination of a set of gauges, such as a speedometer, fuel level, oil pressure, tachometer, odometer, turn indicator, shift position indicator, one or more seatbelt warning lights, one or more parking brake warning lights, one or more engine fault lights, auxiliary restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between the infotainment SoC 1130 and dashboard 1132. In at least one embodiment, dashboard 1132 may be included as part of infotainment SoC 1130, and vice versa.

[0238] Figure 11D is according to at least one embodiment between one or more cloud-based servers and Figure 11A1. A diagram of a system for communicating between autonomous vehicles 1100. In at least one embodiment, the system may include, but is not limited to, one or more servers 1178, one or more networks 1190, and any number and type of vehicles, including vehicle 1100. In at least one embodiment, one or more servers 1178 may include, but are not limited to, multiple GPUs 1184(A)-1184(H) (collectively referred to herein as GPUs 1184), PCIe switches 1182(A)-1182(D) (collectively referred to herein as PCIe switches 1182), and / or CPUs 1180(A)-1180(B) (collectively referred to herein as CPUs 1180). In at least one embodiment, GPUs 1184, CPUs 1180, and PCIe switches 1182 may be interconnected with a high-speed interconnect, such as, for example, but not limited to, NVLink interface 1188 and / or PCIe connection 1186 developed by NVIDIA. In at least one embodiment, the GPUs 1184 are connected via NVLink and / or NVSwitch SoCs, and the GPUs 1184 and PCIe switches 1182 are connected via PCIe interconnects. Although eight GPUs 1184, two CPUs 1180, and four PCIe switches 1182 are shown, this is not intended to be limiting. In at least one embodiment, each of the one or more servers 1178 may include, but is not limited to, any number of GPUs 1184, CPUs 1180, and / or PCIe switches 1182 in any combination. For example, in at least one embodiment, one or more servers 1178 may each include eight, sixteen, thirty-two, and / or more GPUs 1184.

[0239] In at least one embodiment, one or more servers 1178 may receive image data representing an image from a vehicle via one or more networks 1190 that shows an unexpected or changed road condition, such as a recently started road project. In at least one embodiment, one or more servers 1178 may send updated neural networks 1192 and / or map information 1194 to the vehicle via one or more networks 1190, including, but not limited to, information about traffic and road conditions. In at least one embodiment, updates to the map information 1194 may include, but are not limited to, updates to the HD map 1122, such as information about construction sites, potholes, access roads, flooding, and / or other obstacles. In at least one embodiment, the neural network 1192 and / or map information 1194 may have been generated by new training and / or experience represented in data received from any number of vehicles in the environment, and / or based at least on training performed at a data center (e.g., using one or more servers 1178 and / or other servers).

[0240] In at least one embodiment, one or more servers 1178 may be used to train a machine learning model (e.g., a neural network) at least in part based on training data. In at least one embodiment, the training data may be generated by the vehicle and / or may be generated in simulation (e.g., using a game engine). In at least one embodiment, any amount of training data may be labeled (e.g., in the case where the associated neural network benefits from supervised learning) and / or may undergo other preprocessing. In at least one embodiment, no amount of training data may be labeled and / or preprocessed (e.g., in the case where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model may be used by the vehicle (e.g., sent to the vehicle via one or more networks 1190, and / or the machine learning model may be used by one or more servers 1178 to remotely monitor the vehicle).

[0241] In at least one embodiment, one or more servers 1178 may receive data from the vehicle and apply the data to a latest real-time neural network for real-time intelligent inference. In at least one embodiment, one or more servers 1178 may include a deep learning supercomputer powered by one or more GPUs 1184 and / or a dedicated AI computer, such as DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 1178 may include a deep learning infrastructure of a data center powered by a CPU.

[0242] In at least one embodiment, the deep learning infrastructure of one or more servers 1178 may be capable of performing fast, real-time inference and may use that capability to evaluate and validate the health of the processors, software, and / or associated hardware in vehicle 1100. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 1100, such as an image sequence and / or objects located in the image sequence by vehicle 1100 (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify the objects and compare them to the objects identified by vehicle 1100, and if the results do not match and the deep learning infrastructure determines that the AI in vehicle 1100 is malfunctioning, one or more servers 1178 may send a signal to vehicle 1100 that instructs the fail-safe computer in vehicle 1100 to take control, notify the passengers, and complete a safe parking operation.

[0243] In at least one embodiment, one or more servers 1178 may include one or more GPUs 1184 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3 device). In at least one embodiment, the combination of GPU-driven servers and inference acceleration can enable real-time response. In at least one embodiment, in cases where performance is less critical, servers driven by CPUs, FPGAs, and other processors can be used for inference. In at least one embodiment, one or more hardware structures 815 are used to execute one or more embodiments. This document provides details regarding Figure 8A and / or Figure 8B hardware structure 815.

[0244] Computer system

[0245] Figure 12 is a block diagram showing an exemplary computer system according to at least one embodiment. The exemplary computer system may be a system with interconnected devices and components, a system-on-chip (SOC), or some combination thereof formed with a processor that may include execution units for executing instructions. In at least one embodiment, according to the present disclosure, such as in the embodiments described herein, computer system 1200 may include, but is not limited to, components such as processor 1202 for executing algorithms for processing data using execution units (including logic). In at least one embodiment, computer system 1200 may include a processor such as those available from Intel Corporation of Santa Clara, California, processor families, XeonTM, XScaleTM and / or StrongARMTM, CoreTM or NervanaTM microprocessors, although other systems (including PCs, engineering workstations, set-top boxes, etc. with other microprocessors) may also be used. In at least one embodiment, computer system 1200 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0246] Embodiments can be used in other devices such as handheld devices and embedded applications. Some examples of handheld devices include cellular telephones, Internet Protocol devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, an embedded application can include a microcontroller, a digital signal processor (“DSP”), a system-on-chip, a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0247] In at least one embodiment, computer system 1200 can include, but is not limited to, a processor 1202 that can include, but is not limited to, one or more execution units 1208 for performing machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, computer system 1200 is a single-processor desktop or server system, but in another embodiment, computer system 1200 can be a multi-processor system. In at least one embodiment, processor 1202 can include, but is not limited to, for example, a complex instruction set computer (“CISC”) microprocessor, a reduced instruction set computing (“RISC”) microprocessor, a very long instruction word (“VLIW”) microprocessor, a processor implementing an instruction set combination, or any other processor device such as a digital signal processor. In at least one embodiment, processor 1202 can be coupled to a processor bus 1210 that can transfer data signals between processor 1202 and other components in computer system 1200.

[0248] In at least one embodiment, processor 1202 can include, but is not limited to, a level 1 (“L1”) internal cache memory (“cache”) 1204. In at least one embodiment, processor 1202 can have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory can reside external to processor 1202. Depending on the particular implementation and requirements, other embodiments can also include a combination of internal and external caches. In at least one embodiment, register file 1206 can store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0249] In at least one embodiment, execution unit 1208, which includes, but is not limited to, logic for performing integer and floating point operations, is also located in processor 1202. In at least one embodiment, processor 1202 may also include a microcode (“ucode”) read only memory (“ROM”) that stores microcode for certain macroinstructions. In at least one embodiment, execution unit 1208 may include logic for processing a packed instruction set 1209. In at least one embodiment, by including the packed instruction set 1209 in the instruction set of a general purpose processor and the associated circuitry to execute instructions, operations used by many multimedia applications may be performed using packed data in processor 1202. In at least one embodiment, many multimedia applications may be accelerated and executed more efficiently by performing operations on packed data using the full width of the processor's data bus, which may eliminate the need to transfer smaller data units over the processor's data bus to perform one or more operations on one data element at a time.

[0250] In at least one embodiment, execution unit 1208 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 1200 may include, but is not limited to, memory 1220. In at least one embodiment, memory 1220 may be a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a flash memory device, or other memory device. In at least one embodiment, memory 1220 may store one or more instructions 1219 and / or data 1221 represented by data signals that may be executed by processor 1202.

[0251] In at least one embodiment, a system logic chip can be coupled to a processor bus 1210 and a memory 1220. In at least one embodiment, the system logic chip can include, but is not limited to, a memory controller hub (“MCH”) 1216, and a processor 1202 can communicate with the MCH 1216 via the processor bus 1210. In at least one embodiment, the MCH 1216 can provide a high-bandwidth memory path 1218 to the memory 1220 for instruction and data storage and for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1216 can direct data signals among the processor 1202, the memory 1220, and other components in the computer system 1200, and bridge data signals among the processor bus 1210, the memory 1220, and a system I / O interface 1222. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1216 can be coupled to the memory 1220 via the high-bandwidth memory path 1218, and a graphics / video card 1212 can be coupled to the MCH 1216 via an Accelerated Graphics Port (“AGP”) interconnect 1214.

[0252] In at least one embodiment, the computer system 1200 can use the system I / O interface 1222 as a proprietary hub interface bus to couple the MCH 1216 to an I / O controller hub (“ICH”) 1230. In at least one embodiment, the ICH 1230 can provide direct connections to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus can include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to the memory 1220, the chipset, and the processor 1202. Examples can include, but are not limited to, an audio controller 1229, a firmware hub (“flash BIOS”) 1228, a wireless transceiver 1226, a data storage 1224, a legacy I / O controller 1223 including a user input and keyboard interface 1225, a serial expansion port 1227 (such as a Universal Serial Bus (“USB”) port), and a network controller 1234. In at least one embodiment, the data storage 1224 can include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash device, or other mass storage devices.

[0253] In at least one embodiment, Figure 12 a system including interconnected hardware devices or “chips” is shown, while in other embodiments, Figure 12 an exemplary SoC can be shown. In at least one embodiment, Figure 12The devices shown in can be interconnected using proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 1200 are interconnected using Compute Express Link (CXL) interconnects.

[0254] Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. This is described herein in conjunction with Figure 8A and / or Figure 8B Details regarding logic 815 are provided. In at least one embodiment, logic 815 can be used in computer system 1200 to perform inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0255] In at least one embodiment, computer system 1200 is used to at least partially implement text-based object generation as shown in Figures 1 - 6

[0256] Figure 13 is a block diagram showing an electronic device 1300 for utilizing a processor 1310 according to at least one embodiment. In at least one embodiment, electronic device 1300 can be, for example but not limited to, a laptop computer, tower server, rack server, blade server, laptop, desktop computer, tablet, mobile device, phone, embedded computer, or any other suitable electronic device.

[0257] In at least one embodiment, electronic device 1300 can include, but is not limited to, a processor 1310 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, processor 1310 is coupled using a bus or interface, such as an I2C bus, System Management Bus (“SMBus”), Low Pin Count (LPC) bus, Serial Peripheral Interface (“SPI”), High Definition Audio (“HDA”) bus, Serial Advanced Technology Attachment (“SATA”) bus, Universal Serial Bus (“USB”) (versions 1, 2, 3, etc.), or Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, Figure 13 shows a system that includes interconnected hardware devices or “chips,” while in other embodiments, Figure 13 an exemplary SoC can be shown. In at least one embodiment, Figure 13 the devices shown in can be interconnected using proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 13 one or more components of are interconnected using Compute Express Link (CXL) interconnects.

[0258] In at least one embodiment, Figure 13 it may include a display 1324, a touch screen 1325, a touchpad 1330, a near field communication unit (“NFC”) 1345, a sensor hub 1340, a thermal sensor 1346, a fast chipset (“EC”) 1335, a trusted platform module (“TPM”) 1338, BIOS / firmware / flash memory (“BIOS, FW Flash”) 1322, a DSP 1360, a drive 1320 (such as a solid state disk (“SSD”) or a hard disk drive (“HDD”)), a wireless local area network unit (“WLAN”) 1350, a Bluetooth unit 1352, a wireless wide area network unit (“WWAN”) 1356, a global positioning system (GPS) unit 1355, a camera (“USB 3.0 camera”) 1354 (such as a USB 3.0 camera) and / or a low power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1315 implemented in accordance with, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0259] In at least one embodiment, other components may be communicatively coupled to the processor 1310 via the components described herein. In at least one embodiment, an accelerometer 1341, an ambient light sensor (“ALS”) 1342, a compass 1343, and a gyroscope 1344 may be communicatively coupled to the sensor hub 1340. In at least one embodiment, a thermal sensor 1339, a fan 1337, a keyboard 1336, and a touchpad 1330 may be communicatively coupled to the EC 1335. In at least one embodiment, a speaker 1363, headphones 1364, and a microphone (“mic”) 1365 may be communicatively coupled to an audio unit (“audio codec and class-D amplifier”) 1362, which may in turn be communicatively coupled to the DSP 1360. In at least one embodiment, the audio unit 1362 may include, for example but not limited to, an audio encoder / decoder (“codec”) and a class-D amplifier. In at least one embodiment, a subscriber identity module (“SIM”) 1357 may be communicatively coupled to the WWAN unit 1356. In at least one embodiment, components (such as the WLAN unit 1350, the Bluetooth unit 1352, and the WWAN unit 1356) may be implemented in a next generation form factor (“NGFF”).

[0260] Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. This is described herein in connection with Figure 8A and / or Figure 8BProvide details regarding logic 815. In at least one embodiment, logic 815 may be used in an electronic device 1300 for performing inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0261] In at least one embodiment, the processor 1310 is used to at least partially implement text-based object generation as shown in Figures 1 - 6 as shown.

[0262] Figure 14 A computer system 1400 is shown in accordance with at least one embodiment. In at least one embodiment, the computer system 1400 is configured to implement the various processes and methods described throughout this disclosure.

[0263] In at least one embodiment, the computer system 1400 includes, but is not limited to, at least one central processing unit (“CPU”) 1402 connected to a communication bus 1410 implemented using any suitable protocol, such as PCI (“Peripheral Component Interconnect”), Peripheral Component Interconnect Express (“PCI-Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, the computer system 1400 includes, but is not limited to, a main memory 1404 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data is stored in the main memory 1404, which may take the form of random access memory (“RAM”). In at least one embodiment, a network interface subsystem (“network interface”) 1422 provides an interface to other computing devices and networks for receiving data from other systems and sending data to other systems using the computer system 1400.

[0264] In at least one embodiment, the computer system 1400 includes, but is not limited to, an input device 1408, a parallel processing system 1412, and a display device 1406 in at least one embodiment, which may be implemented using a conventional cathode ray tube (“CRT”), liquid crystal display (“LCD”), light emitting diode (“LED”) display, plasma display, or other suitable display technology. In at least one embodiment, user input is received from the input device 1408 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each module described herein may be located on a single semiconductor platform to form a processing system.

[0265] Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. This is described herein in connection with Figure 8A and / or Figure 8BProvide details regarding inference and / or training logic 815. In at least one embodiment, logic 815 may be used in computer system 1400 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0266] In at least one embodiment, computer system 1400 is used to at least partially implement text-based object generation as shown in Figures 1 - 6 the following.

[0267] Figure 15 FIG. shows computer system 1500 according to at least one embodiment. In at least one embodiment, computer system 1500 includes, but is not limited to, computer 1510 and USB drive 1520. In at least one embodiment, computer 1510 may include, but is not limited to, any number and type of processors (not shown) and memories (not shown). In at least one embodiment, computer 1510 includes, but is not limited to, servers, cloud instances, laptop computers, and desktop computers.

[0268] In at least one embodiment, USB drive 1520 includes, but is not limited to, processing unit 1530, USB interface 1540, and USB interface logic 1550. In at least one embodiment, processing unit 1530 may be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, processing unit 1530 may include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, processing unit 1530 includes an application specific integrated circuit (“ASIC”) that is optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, processing unit 1530 is a tensor processing unit (“TPC”) that is optimized to perform machine learning inference operations. In at least one embodiment, processing unit 1530 is a vision processing unit (“VPU”) that is optimized to perform machine vision and machine learning inference operations.

[0269] In at least one embodiment, USB interface 1540 may be any type of USB connector or USB socket. For example, in at least one embodiment, USB interface 1540 is a USB 3.0 Type-C socket for data and power. In at least one embodiment, USB interface 1540 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1550 may include any number and type of logic that enables processing unit 1530 to interface with a device (such as computer 1510) via USB connector 1540.

[0270] Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. As described herein in connection with Figure 8A and / or Figure 8B details regarding Logic 815 are provided. In at least one embodiment, Logic 815 may be used in computer system 1500 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0271] In at least one embodiment, computer system 1500 is used to at least partially implement text-based object generation as shown in Figures 1 - 6 .

[0272] Figure 16A An exemplary architecture is shown in which multiple GPUs 1610(1)-1610(N) are communicatively coupled to multiple multi-core processors 1605(1)-1605(M) via high-speed links 1640(1)-1640(N) (e.g., buses, point-to-point interconnects, etc.). In at least one embodiment, high-speed links 1640(1)-1640(N) support a communication throughput of 4GB / s, 30GB / s, 80GB / s, or higher. In at least one embodiment, various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. In the various figures, "N" and "M" represent positive integers, the values of which may vary from figure to figure. In at least one embodiment, as disclosed in Figure 19A and Figure 19B one or more of the multiple GPUs 1610(1)-1610(N) include one or more graphics cores (also simply referred to as "cores") 1900. In at least one embodiment, one or more graphics cores 1900 may be referred to as streaming multiprocessors ("SMs"), stream processors ("SPs"), stream processing units ("SPUs"), compute units ("CUs"), execution units ("EUs"), and / or slices, where a slice in this context may refer to a portion of the processing resources in a processing unit (e.g., 16 cores, ray tracing units, thread directors, or schedulers).

[0273] In addition, in at least one embodiment, two or more GPUs 1610 are interconnected by high-speed links 1629(1)-1629(2), which can be implemented using a protocol / link similar to or different from the protocol / link used for high-speed links 1640(1)-1640(N). Similarly, two or more multi-core processors 1605 can be connected by a high-speed link 1628, which can be a symmetric multi-processor (SMP) bus operating at a speed of 20 GB / s, 30 GB / s, 120 GB / s or higher. Alternatively, all communications between the various system components shown in Figure 16A can be accomplished using a similar protocol / link (e.g., via a common interconnect structure). In at least one embodiment, one or more of the multiple GPUs 1610(1)-1610(N) include one or more graphics cores (which may also be simply referred to as "cores") 1900 as disclosed in Figure 19A and 19B . In at least one embodiment, one or more graphics cores 1900 may be referred to as stream multi-processors ("SMs"), stream processors ("SPs"), stream processing units ("SPUs"), compute units ("CUs"), execution units ("EUs"), and / or slices, where a slice in this context may refer to a portion of the processing resources in a processing unit (e.g., a 16-core, ray tracing unit, thread director or scheduler).

[0274] In at least one embodiment, each multi-core processor 1605 is communicatively coupled to a processor memory 1601(1)-1601(M) via a memory interconnect 1626(1)-1626(M), and each GPU 1610(1)-1610(N) is communicatively coupled to a GPU memory 1620(1)-1620(N) via a GPU memory interconnect 1650(1)-1650(N). In at least one embodiment, the memory interconnects 1626 and 1650 may utilize similar or different memory access technologies. By way of example and not limitation, the processor memories 1601(1)-1601(M) and the GPU memory 1620 may be volatile memories such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memories such as 3D XPoint or Nano-Ram. In at least one embodiment, some portions of the processor memory 1601 may be volatile memory while another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0275] As described herein, although each multi-core processor 1605 and GPU 1610 may be physically coupled to a specific memory 1601, 1620, respectively, and / or a unified memory architecture may be implemented, where the virtual system address space (also referred to as the "effective address" space) is distributed among the respective physical memories. For example, processor memories 1601(1)-1601(M) may each include 64 GB of system memory address space, and GPU memories 1620(1)-1620(N) may each include 32 GB of system memory address space, such that when M = 2 and N = 4, a total of 256 GB of addressable memory results. Other values of N and M are possible.

[0276] Figure 16B Additional details of the interconnection between the multi-core processor 1607 and the graphics acceleration module 1646 are shown in accordance with one exemplary embodiment. In at least one embodiment, the graphics acceleration module 1646 may include one or more GPU chips integrated on a line card that is coupled to the processor 1607 via a high-speed link 1640 (e.g., a PCIe bus, NVLink, etc.). In at least one embodiment, the graphics acceleration module 1646 may alternatively be integrated on a package or chip with the processor 1607.

[0277] In at least one embodiment, the processor 1607 includes multiple cores 1660A-1660D (which may be referred to as "execution units"), each core having a translation lookaside buffer ("TLB") 1661A-1661D and one or more caches 1662A-1662D. In at least one embodiment, the cores 1660A-1660D may include various other components (not shown) for executing instructions and processing data. In at least one embodiment, the caches 1662A-1662D may include level 1 (L1) and level 2 (L2) caches. Additionally, one or more shared caches 1656 may be included within the caches 1662A-1662D and shared by groups of cores 1660A-1660D. For example, one embodiment of the processor 1607 includes 24 cores, each having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. In at least one embodiment, the processor 1607 and the graphics acceleration module 1646 are connected to a system memory 1614, which may include Figure 16A processor memories 1601(1)-1601(M) therein.

[0278] In at least one embodiment, cache coherence for data and instructions stored in respective caches 1662A - 1662D, 1656, and system memory 1614 is maintained via an inter - core communication over coherence bus 1664. In at least one embodiment, for example, each cache may have cache coherence logic / circuit associated therewith to communicate over coherence bus 1664 in response to detecting a read or write to a particular cache line. In at least one embodiment, a cache snooping protocol is implemented over coherence bus 1664 to snoop cache accesses.

[0279] In at least one embodiment, proxy circuit 1625 communicatively couples graphics acceleration module 1646 to coherence bus 1664, thereby allowing graphics acceleration module 1646 to participate in the cache coherence protocol as a peer to cores 1660A - 1660D. In particular, in at least one embodiment, interface 1635 provides a connection to proxy circuit 1625 via high - speed link 1640, and interface 1637 connects graphics acceleration module 1646 to high - speed link 1640.

[0280] In at least one embodiment, accelerator integrated circuit 1636 provides cache management, memory access, context management, and interrupt management services on behalf of the plurality of graphics processing engines 1631(1) - 1631(N) of graphics acceleration module 1646. In at least one embodiment, each of graphics processing engines 1631(1) - 1631(N) may include a separate graphics processing unit (GPU). In at least one embodiment, the plurality of graphics processing engines 1631(1) - 1631(N) of graphics acceleration module 1646 includes one or more of the graphics cores 1900 discussed in conjunction Figure 19A and Figure 19B with. In at least one embodiment, graphics processing engines 1631(1) - 1631(N) may alternatively include different types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoder / decoder), samplers, and blit engines. In at least one embodiment, graphics acceleration module 1646 may be a GPU having a plurality of graphics processing engines 1631(1) - 1631(N), or the graphics processing engines 1631(1) - 1631(N) may be individual GPUs integrated on a common package, line card, or chip.

[0281] In at least one embodiment, the accelerator integrated circuit 1636 includes a memory management unit (MMU) 1639 for performing various memory management functions such as virtual-to-physical memory translation (also known as effective-to-real memory translation), and also includes a memory access protocol for accessing system memory 1614. In at least one embodiment, the MMU 1639 may also include a translation lookaside buffer (“TLB”) (not shown) for caching virtual / effective-to-physical / real address translations. In at least one embodiment, the cache 1638 may store commands and data for efficient access by the graphics processing engines 1631(1)-1631(N). In at least one embodiment, an acquisition unit 1644 may be used to keep the data stored in the cache 1638 and the graphics memories 1633(1)-1633(M) coherent with the core caches 1662A-1662D, 1656, and the system memory 1614. As previously described, this may be representative of the cache 1638 and the memories 1633(1)-1633(M) being implemented via the proxy circuit 1625 (e.g., sending updates related to modifications / accesses of cache lines on the processor caches 1662A-1662D, 1656 to the cache 1638 and receiving updates from the cache 1638).

[0282] In at least one embodiment, a set of registers 1645 stores context data for the threads executed by the graphics processing engines 1631(1)-1631(N), and the context management circuit 1648 manages the thread contexts. For example, the context management circuit 1648 may perform save and restore operations to save and restore the contexts of individual threads during a context switch (e.g., where the first thread is saved and the second thread is stored so that the second thread can be executed by the graphics processing engine). For example, the context management circuit 1648, during a context switch, may store the current register values into a specified area in memory (e.g., identified by a context pointer). Then, the register values can be restored when returning to the context. In at least one embodiment, the interrupt management circuit 1647 receives and processes interrupts received from system devices.

[0283] In at least one embodiment, the MMU 1639 converts virtual / valid addresses from the graphics processing engine 1631 into real / physical addresses in the system memory 1614. In at least one embodiment, the accelerator integrated circuit 1636 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1646 and / or other accelerator devices. In at least one embodiment, the graphics accelerator module 1646 can be dedicated to a single application executing on the processor 1607 or can be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented where the resources of the graphics processing engines 1631(1)-1631(N) are shared among multiple applications or virtual machines (VMs). In at least one embodiment, the resources can be subdivided into "slices" based on the processing requirements and priorities associated with the VMs and / or applications and are allocated to different VMs and / or applications.

[0284] In at least one embodiment, the accelerator integrated circuit 1636 functions as a bridge for the system of the graphics accelerator modules 1646 and provides address translation and system memory cache services. Additionally, in at least one embodiment, the accelerator integrated circuit 1636 can provide virtualization facilities for the host processor to manage the virtualization, interrupts, and memory management of the graphics processing engines 1631(1)-1631(N).

[0285] In at least one embodiment, since the hardware resources of the graphics processing engines 1631(1)-1631(N) are explicitly mapped to the real address space seen by the host processor 1607, any host processor can directly address these resources using valid address values. In at least one embodiment, one function of the accelerator integrated circuit 1636 is the physical separation of the graphics processing engines 1631(1)-1631(N) such that they appear as independent units to the system.

[0286] In at least one embodiment, one or more graphics memories 1633(1)-1633(M) are coupled to each of the graphics processing engines 1631(1)-1631(N), and N = M. In at least one embodiment, the graphics memories 1633(1)-1633(M) store the instructions and data being processed by each of the graphics processing engines 1631(1)-1631(N). In at least one embodiment, the graphics memories 1633(1)-1633(M) can be volatile memories such as DRAM (including stacked DRAM), GDDR memories (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memories such as 3D XPoint or Nano-Ram.

[0287] In at least one embodiment, to reduce data traffic on the high-speed link 1640, a biasing technique may be used to ensure that the data stored in the graphics memories 1633(1)-1633(M) is the data most frequently used by the graphics processing engines 1631(1)-1631(N), and preferably is data not used (at least not frequently used) by the cores 1660A-1660D. Similarly, in at least one embodiment, the biasing mechanism attempts to keep the data required by the cores (and preferably not required by the graphics processing engines 1631(1)-1631(N)) in the caches 1662A-1662D, 1656, and the system memory 1614.

[0288] Figure 16C Another exemplary embodiment is shown, in which the accelerator integrated circuit 1636 is integrated within the processor 1607. In this embodiment, the graphics processing engines 1631(1)-1631(N) communicate directly with the accelerator integrated circuit 1636 via the interfaces 1637 and 1635 (again, which can be any form of bus or interface protocol) over the high-speed link 1640. In at least one embodiment, the accelerator integrated circuit 1636 may perform operations similar to the operations described with respect to Figure 16B but may have higher throughput due to its close proximity to the coherence bus 1664 and the caches 1662A-1662D, 1656. In at least one embodiment, the accelerator integrated circuit supports different programming models, which include a process-specific programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), and the programming models may include a programming model controlled by the accelerator integrated circuit 1636 and a programming model controlled by the graphics acceleration module 1646.

[0289] In at least one embodiment, the graphics processing engines 1631(1)-1631(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application may funnel other application requests to the graphics processing engines 1631(1)-1631(N), thereby providing virtualization within a VM / partition.

[0290] In at least one embodiment, the graphics processing engines 1631(1)-1631(N) can be shared by multiple VM / application partitions. In at least one embodiment, a sharing model can use a hypervisor to virtualize the graphics processing engines 1631(1)-1631(N) to allow each operating system to access them. In at least one embodiment, for a single-partition system without a hypervisor, the operating system owns the graphics processing engines 1631(1)-1631(N). In at least one embodiment, the operating system can virtualize the graphics processing engines 1631(1)-1631(N) to provide access to each process or application.

[0291] In at least one embodiment, the graphics acceleration module 1646 or individual graphics processing engines 1631(1)-1631(N) use a process handle to select process elements. In at least one embodiment, the process elements are stored in the system memory 1614 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle can be an implementation-specific value that is provided to the host process when registering its context with the graphics processing engines 1631(1)-1631(N) (i.e., calling the system software to add the process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle can be the offset of the process element in the process element linked list.

[0292] Figure 16D An exemplary accelerator integration slice 1690 is shown. In at least one embodiment, a "slice" includes a designated portion of the processing resources of the accelerator integrated circuit 1636. In at least one embodiment, an application is the effective address space 1682 in the system memory 1614 that stores the process element 1683. In at least one embodiment, in response to a GPU call 1681 from an application 1680 executing on the processor 1607, the process element 1683 is stored. In at least one embodiment, the process element 1683 contains the process state of the corresponding application 1680. In at least one embodiment, the work descriptor (WD) 1684 contained in the process element 1683 can be a single job requested by the application or can contain a pointer to a job queue. In at least one embodiment, the WD 1684 is a pointer to a job request queue in the effective address space 1682 of the application.

[0293] In at least one embodiment, the graphics acceleration module 1646 and / or each of the graphics processing engines 1631(1)-1631(N) may be shared by all processes or a subset of processes in the system. In at least one embodiment, an infrastructure may be included for setting the process state and sending the WD 1684 to the graphics acceleration module 1646 to start a job in a virtualized environment.

[0294] In at least one embodiment, the process-specific programming model is implementation-specific. In at least one embodiment, in this model, a single process owns the graphics acceleration module 1646 or an individual graphics processing engine 1631. In at least one embodiment, when the graphics acceleration module 1646 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition, and when the graphics acceleration module 1646 is assigned, the operating system initializes the accelerator integrated circuit 1636 for the owned process.

[0295] In at least one embodiment, in operation, the WD fetch unit 1691 in the accelerator integration slice 1690 fetches the next WD 1684, which includes an indication of work to be completed by one or more of the graphics processing engines of the graphics acceleration module 1646. In at least one embodiment, the data from the WD 1684 may be stored in the register 1645 and used by the MMU 1639, the interrupt management circuit 1647, and / or the context management circuit 1648, as shown. For example, one embodiment of the MMU 1639 includes a segment / page walk circuit for accessing the segment / page table 1686 within the OS virtual address space 1685. In at least one embodiment, the interrupt management circuit 1647 may process the interrupt event 1692 received from the graphics acceleration module 1646. In at least one embodiment, when performing a graphics operation, the effective address 1693 generated by the graphics processing engines 1631(1)-1631(N) is translated by the MMU 1639 into a real address.

[0296] In at least one embodiment, the register 1645 is replicated for each of the graphics processing engines 1631(1)-1631(N) and / or the graphics acceleration module 1646, and the register 1645 may be initialized by the hypervisor or the operating system. In at least one embodiment, each of these replicated registers may be included in the accelerator integration slice 1690. Exemplary registers that may be initialized by the hypervisor are shown in Table 1.

[0297] Table 1 - Registers Initialized by the Hypervisor

[0298]

[0299] Exemplary registers that may be initialized by the operating system are shown in Table 2.

[0300] Table 2 - Registers for Operating System Initialization

[0301]

[0302] In at least one embodiment, each WD 1684 is specific to a particular graphics acceleration module 1646 and / or graphics processing engine 1631(1)-1631(N). In at least one embodiment, it contains all the information required for the graphics processing engine 1631(1)-1631(N) to do its work, or it can be a pointer to a memory location where the application has set up a command queue for the work to be done.

[0303] Figure 16E Additional details of an exemplary embodiment of the shared model are shown. This embodiment includes a hypervisor real address space 1698 in which a list of process elements 1699 is stored. In at least one embodiment, the hypervisor real address space 1698 can be accessed via the hypervisor 1696, which virtualizes the graphics acceleration module engine for the operating system 1695.

[0304] In at least one embodiment, the shared programming model allows all processes or a subset of processes from all partitions or a subset of partitions in the system to use the graphics acceleration module 1646. In at least one embodiment, there are two programming models in which the graphics acceleration module 1646 is shared by multiple processes and partitions, namely time slice sharing and graphics directed sharing.

[0305] In at least one embodiment, in this model, the system hypervisor 1696 owns the graphics acceleration module 1646 and makes its functions available to all operating systems 1695. In at least one embodiment, for the graphics acceleration module 1646 to support virtualization through the system hypervisor 1696, the graphics acceleration module 1646 may have to comply with certain requirements, such as (1) the job requests of the application must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 1646 must provide a context save and restore mechanism, (2) the graphics acceleration module 1646 guarantees that the job requests of the application are completed within a specified amount of time, including any translation errors, or the graphics acceleration module 1646 provides the ability to preempt job processing, and (3) when operating in the directed sharing programming model, it must be ensured that the graphics acceleration module 1646 is fair among processes.

[0306] In at least one embodiment, the application 1680 is required to use a graphics acceleration module type, a work descriptor (WD), a permission mask register (AMR) value, and a context save / restore area pointer (CSRP) for an operating system 1695 system call. In at least one embodiment, the graphics acceleration module type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module type can be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 1646 and can take the form of a graphics acceleration module 1646 command, a valid address pointer to a user-defined structure, a valid address pointer to a command queue, or any other data structure that describes the work to be done by the graphics acceleration module 1646.

[0307] In at least one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to the application that sets the AMR. In at least one embodiment, if the implementation of the accelerator integrated circuit 1636 (not shown) and the graphics acceleration module 1646 does not support the user authority mask override register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in a hypervisor call. In at least one embodiment, the hypervisor 1696 may selectively apply the current permission mask override register (AMOR) value before placing the AMR in the process element 1683. In at least one embodiment, the CSRP is one of the registers 1645 that contains the valid address of a region in the valid address space 1682 of the application for the graphics acceleration module 1646 to save and restore the context state. In at least one embodiment, if it is not necessary to save the state between jobs or when a job is preempted, the pointer is optional. In at least one embodiment, the context save / restore area can be a fixed system memory.

[0308] Upon receiving the system call, the operating system 1695 can verify that the application 1680 has been registered and granted permission to use the graphics acceleration module 1646. Then, in at least one embodiment, the operating system 1695 uses the information shown in Table 3 to call the hypervisor 1696.

[0309] Table 3 - Operating System to Hypervisor Call Parameters

[0310]

[0311] In at least one embodiment, upon receiving a hypervisor call, the hypervisor 1696 verifies that the operating system 1695 is registered and has been granted permission to use the graphics acceleration module 1646. Then, in at least one embodiment, the hypervisor 1696 places the process element 1683 into a process element linked list corresponding to the type of the graphics acceleration module 1646. In at least one embodiment, the process element may include the information shown in Table 4.

[0312] Table 4 - Process Element Information

[0313]

[0314] 11 Real Address (RA) Hypervisor Accelerator Utilization Record Pointer

[0315] 12 Storage Descriptor Register (SDR)

[0316] In at least one embodiment, the hypervisor initializes the registers 1645 of multiple accelerator integration slices 1690.

[0317] As Figure 16F shown, in at least one embodiment, a unified memory is used, and the unified memory can be addressed via a common virtual memory address space for accessing the physical processor memories 1601(1)-1601(N) and the GPU memories 1620(1)-1620(N). In this implementation, operations executed on the GPUs 1610(1)-1610(N) utilize the same virtual / effective memory address space to access the processor memories 1601(1)-1601(M), and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to the processor memory 1601(1), a second portion is allocated to the second processor memory 1601(N), a third portion is allocated to the GPU memory 1620(1), and so on. In at least one embodiment, thus the entire virtual / effective memory space (sometimes referred to as the effective address space) is distributed across each of the processor memory 1601 and the GPU memory 1620, thereby allowing any processor or GPU to access the memory using a virtual address mapped to any physical memory.

[0318] In at least one embodiment, the bias / coherency management circuits 1694A-1694E within one or more MMUs 1639A-1639E ensure cache coherency between one or more host processors (e.g., 1605) and the caches of the GPUs 1610, and implement a bias technique for indicating the physical memory in which certain types of data should be stored. In at least one embodiment, although Figure 16FMultiple instances of the bias / coherency management circuits 1694A - 1694E are shown, but the bias / coherency circuits may be implemented within the MMU of one or more host processors 1605 and / or within the accelerator integrated circuit 1636.

[0319] One embodiment allows the GPU memory 1620 to be mapped as part of the system memory and accessed using shared virtual memory (SVM) techniques without suffering the performance penalties associated with full system cache coherency. In at least one embodiment, the ability of the GPU memory 1620 to be accessed as system memory without heavy cache coherency overhead provides a favorable operating environment for GPU offloading. In at least one embodiment, this arrangement allows software of the host processor 1605 to set operands and access computation results without the overhead of traditional I / O DMA data copies. In at least one embodiment, such traditional copies include driver calls, interrupts, and memory mapped I / O (MMIO) accesses, which are all less efficient than simple memory accesses. In at least one embodiment, the ability to access the GPU memory 1620 without cache coherency overhead may be critical to the execution time of offloaded computations. In at least one embodiment, for example, in the case of a large amount of streaming write memory traffic, the cache coherency overhead can significantly reduce the effective write bandwidth seen by the GPU 1610. In at least one embodiment, the efficiency of operand setting, the efficiency of result access, and the efficiency of GPU computation may play a role in determining the effectiveness of GPU offloading.

[0320] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. In at least one embodiment, for example, a bias table may be used, which may be a page granularity structure (e.g., controlled at the granularity of memory pages), and this page granularity structure includes 1 or 2 bits per GPU - attached memory page. In at least one embodiment, with or without a bias cache in the GPU 1610 (e.g., for caching frequently / most recently used entries of the bias table), the bias table may be implemented in the stolen memory ranges of one or more GPU memories 1620. Alternatively, in at least one embodiment, the entire bias table may be maintained within the GPU.

[0321] In at least one embodiment, before actually accessing the GPU memory, the bias table entry associated with each access to the GPU attached memory 1620 is accessed, thereby causing the following operations. In at least one embodiment, a local request from the GPU 1610 that finds its page in the GPU bias is directly forwarded to the corresponding GPU memory 1620. In at least one embodiment, a local request from the GPU that finds its page in the host bias is forwarded to the processor 1605 (e.g., via the high-speed link described herein). In at least one embodiment, a request from the processor 1605 that finds the requested page in the host processor bias completes a request similar to a normal memory read. Alternatively, a request pointing to a GPU bias page can be forwarded to the GPU 1610. In at least one embodiment, if the GPU is not currently using a page, the GPU can migrate the page to the host processor bias. In at least one embodiment, the bias state of a page can be changed by a software-based mechanism, a software mechanism assisted by hardware, or in a limited set of cases by a purely hardware-based mechanism.

[0322] In at least one embodiment, a mechanism for changing the bias state employs an API call (e.g., OpenCL), which in turn calls the device driver of the GPU. The device driver in turn sends a message (or enqueues a command descriptor) to the GPU, instructing the GPU to change the bias state and perform a cache flush operation in the host in certain migrations. In at least one embodiment, the cache flush operation is used for migrating from the host processor 1605 bias to the GPU bias, but not for the reverse migration.

[0323] In at least one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages that cannot be cached by the host processor 1605. In at least one embodiment, to access these pages, the processor 1605 can request access from the GPU 1610, and the GPU 1610 may or may not immediately grant access. Thus, in at least one embodiment, to reduce communication between the processor 1605 and the GPU 1610, it is beneficial to ensure that GPU bias pages are pages required by the GPU rather than the host processor 1605, and vice versa.

[0324] One or more hardware structures 815 are used to implement one or more embodiments. Details regarding one or more hardware structures 815 may be provided herein in conjunction with Figure 8A and / or Figure 8B provide details about one or more hardware structures 815.

[0325] Figure 17Illustrated is an exemplary integrated circuit and associated graphics processor in accordance with various embodiments described herein, which may be fabricated using one or more IP cores. In addition to what is illustrated, in at least one embodiment, other logic and circuitry may also be included, including additional graphics processors / cores, peripheral interface controllers, or general processor cores.

[0326] Figure 17 FIG. 4 is a block diagram of an exemplary system on a chip integrated circuit 1700 that may be fabricated using one or more IP cores. In at least one embodiment, integrated circuit 1700 includes one or more application processors 1705 (e.g., CPUs), at least one graphics processor 1710, and may additionally include an image processor 1715 and / or a video processor 1720, any of which may be a modular IP core. In at least one embodiment, integrated circuit 1700 includes peripheral or bus logic, which includes a USB controller 1725, a UART controller 1730, an SPI / SDIO controller 1735, and an I2S / I2C controller 1740. In at least one embodiment, integrated circuit 1700 may include a display device 1745 coupled to one or more of a high definition multimedia interface (HDMI) controller 1750 and a mobile industry processor interface (MIPI) display interface 1755. In at least one embodiment, storage may be provided by a flash memory subsystem 1760 that includes flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1765 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1770.

[0327] Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 815 are provided herein in connection with Figure 8A and / or Figure 8B In at least one embodiment, logic 815 may be in integrated circuit 1700 for inferring or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0328] In at least one embodiment, integrated circuit 1700 is used to at least partially implement text-based object generation as shown in Figures 1 - 6 FIG. 16.

[0329] Figures 18A - 18BIllustrated is an exemplary integrated circuit and associated graphics processor according to various embodiments described herein, which may be fabricated using one or more IP cores. In addition to those illustrated, in at least one embodiment other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general processor cores.

[0330] Figures 18A - 18B is a block diagram illustrating an exemplary graphics processor used within a SoC according to an embodiment described herein. Figure 18A Illustrated is an exemplary graphics processor 1810 of a system-on-a-chip integrated circuit according to at least one embodiment, which may be fabricated using one or more IP cores. Figure 18B Illustrated is an additional exemplary graphics processor 1840 of a system-on-a-chip integrated circuit according to at least one embodiment, which may be fabricated using one or more IP cores. In at least one embodiment, Figure 18A the graphics processor 1810 is a low-power graphics processor core. In at least one embodiment, Figure 18B the graphics processor 1840 is a higher-performance graphics processor core. In at least one embodiment, each of the graphics processors 1810, 1840 may be Figure 17 a variation of the graphics processor 1710.

[0331] In at least one embodiment, the graphics processor 1810 includes a vertex processor 1805 and one or more fragment processors 1815A - 1815N (e.g., 1815A, 1815B, 1815C, 1815D through 1815N-1, and 1815N). In at least one embodiment, the graphics processor 1810 may execute different shader programs via separate logic such that the vertex processor 1805 is optimized to perform operations for vertex shader programs, while the one or more fragment processors 1815A - 1815N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the vertex processor 1805 executes the vertex processing stage of a 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the one or more fragment processors 1815A - 1815N use the primitives and vertex data generated by the vertex processor 1805 to produce a frame buffer for display on a display device. In at least one embodiment, the one or more fragment processors 1815A - 1815N are optimized to execute fragment shader programs as provided in the OpenGL API, which may be used to perform operations similar to those provided by pixel shader programs in the Direct 3D API.

[0332] In at least one embodiment, the graphics processor 1810 additionally includes one or more memory management units (MMUs) 1820A-1820B, one or more caches 1825A-1825B, and one or more circuit interconnects 1830A-1830B. In at least one embodiment, one or more MMUs 1820A-1820B provide virtual-to-physical address mapping for the graphics processor 1810 (including for the vertex processor 1805 and / or fragment processors 1815A-1815N), and in addition to vertex or image / texture data stored in one or more caches 1825A-1825B, it can also reference vertex or image / texture data stored in memory. In at least one embodiment, one or more MMUs 1820A-1820B can be synchronized with other MMUs within the system, including one or more MMUs associated with one or more application processors 1705, image processors 1715, and / or video processors 1720 of Figure 17 such that each processor 1705-1720 can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1830A-1830B enable the graphics processor 1810 to interface with other IP cores within the SoC via the internal bus of the SoC or via a direct connection.

[0333] In at least one embodiment, the graphics processor 1840 includes one or more shader cores 1855A-1855N (e.g., 1855A, 1855B, 1855C, 1855D, 1855E, 1855F to 1855N-1 and 1855N) as shown in Figure 18B which provides a unified shader core architecture where a single core or type of core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1840 includes an inter-core task manager 1845 that acts as a thread dispatcher for dispatching execution threads to one or more shader cores 1855A-1855N and a tiling unit 1858 to accelerate tiling operations for tile-based rendering, where the rendering operation of the scene is subdivided in the image space, e.g., to take advantage of local spatial coherence within the scene or to optimize the use of internal caches.

[0334] Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. This is described in conjunction with Figure 8A and / or Figure 8BProvide details regarding logic 815. In at least one embodiment, logic 815 may be used in graphics processor 1810 and / or 1840 to perform inference or prediction operations at least in part based on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0335] In at least one embodiment, graphics processor 1840 is used to at least partially implement text-based object generation as Figures 1 - 6 shown.

[0336] Figures 19A - 19B Additional exemplary graphics processor logic according to embodiments described herein is shown. In at least one embodiment, the components shown in Figures 19A - 19B and described with respect to Figures 19A - 19B are integrated into a single system, such as a graphics processing unit (GPU), system-on-chip (SoC), or other type of processor. In at least one embodiment, Figure 19A shown may be included within the graphics core 1900 of Figure 17 graphics processor 1710, and in at least one embodiment, it may be a unified shader core 1855A - 1855N as Figure 18B shown. Figure 19B A highly parallel general-purpose graphics processing unit (“GPGPU,” which may be referred to as a “graphics processing unit”) 1930 suitable for deployment on a multi-chip module is shown in at least one embodiment. In at least one embodiment, graphics processing unit 1930 is a GPGPU that includes a graphics processor. In at least one embodiment, integrated circuit 1700 includes graphics core 1900, e.g., for forming an integrated circuit and / or forming an SoC, where such an integrated circuit and / or such an SoC performs the operations described herein.

[0337] In at least one embodiment, the graphics core 1900 includes a shared instruction cache 1902, texture units 1918, and cache / shared memory 1920 (e.g., including L1, L2, L3, last-level cache, or other caches), which are shared for the execution resources within the graphics core 1900. In at least one embodiment, the graphics core 1900 may include multiple slices 1901A - 1901N or partitions per core, and the graphics processor may include multiple instances of the graphics core 1900. In at least one embodiment, each of the slices 1901A - 1901N refers to the graphics core 1900. In at least one embodiment, the slices 1901A - 1901N have sub-slices that are part of the slices 1901A - 1901N. In at least one embodiment, the slices 1901A - 1901N are independent of or dependent on other slices. In at least one embodiment, the slices 1901A - 1901N may include support logic, which includes local instruction caches 1904A - 1904N, thread schedulers (orderers) 1906A - 1906N, thread dispatchers 1908A - 1908N, and a set of registers 1910A - 1910N. In at least one embodiment, the slices 1901A - 1901N may include a set of additional functional units (AFUs 1912A - 1912N), floating-point units (FPUs 1914A - 1914N), integer arithmetic logic units (ALUs 1916A - 1916N), address calculation units (ACUs 1913A - 1913N), double-precision floating-point units (DPFPUs 1915A - 1915N), and matrix processing units (MPUs 1917A - 1917N). In at least one embodiment, the MPUs 1917A - 1917N are referred to as matrix engines.

[0338] In at least one embodiment, each of the slices 1901A - 1901N includes one or more engines for floating - point and integer vector operations and one or more engines for accelerating convolutional and matrix operations in artificial intelligence, machine learning, or large - dataset workloads. In at least one embodiment, one or more of the slices 1901A - 1901N include one or more vector engines for computing vectors (e.g., performing mathematical operations on vectors). In at least one embodiment, the vector engines can compute vector operations in 16 - bit floating - point (also referred to as "FP16"), 32 - bit floating - point (also referred to as "FP32"), or 64 - bit floating - point (also referred to as "FP64"). In at least one embodiment, one or more of the slices 1901A - 1901N include 16 vector engines that are paired with 16 matrix math units to compute matrix / tensor operations, where the vector engines and math units are exposed through matrix expansion. In at least one embodiment, a slice is a designated portion of the processing resources of a processing unit, e.g., 16 cores and ray - tracing units or 8 cores, a thread scheduler, a thread dispatcher, and additional functional units of the processor. In at least one embodiment, the graphics core 1900 includes one or more matrix engines for computing matrix operations, e.g., when computing tensor operations.

[0339] In at least one embodiment, one or more of the slices 1901A - 1901N include one or more ray - tracing units for computing ray - tracing operations (e.g., 16 ray - tracing units per slice 1901A - 1901N). In at least one embodiment, the ray - tracing units compute ray traversal, triangle intersection, bounding - box intersection, or other ray - tracing operations.

[0340] In at least one embodiment, one or more of the slices 1901A - 1901N include a media slice that encodes, decodes, and / or transcodes data; scales data and / or converts the format of data; and / or performs video - quality operations on video data.

[0341] In at least one embodiment, one or more slices 1901A - 1901N are linked to an L2 cache and memory structure, a link connector, a high - bandwidth memory (HBM) (e.g., HBM2e, HBM3) stack, and a media engine. In at least one embodiment, one or more slices 1901A - 1901N include a plurality of cores (e.g., 16 cores) and a plurality of ray - tracing units (e.g., 16) paired with each core. In at least one embodiment, one or more slices 1901A - 1901N have one or more L1 caches. In at least one embodiment, one or more slices 1901A - 1901N include one or more vector engines; one or more instruction caches for storing instructions; one or more L1 caches for caching data; one or more shared local memories (SLMs) for storing data (e.g., data corresponding to instructions); one or more samplers for sampling data; one or more ray - tracing units for performing ray - tracing operations; one or more geometry units for performing operations in a geometry pipeline and / or applying geometric transformations to vertices or polygons; one or more rasterizers for describing an image in a vector - graphics format (e.g., a shape) and converting it into a raster image (e.g., a series of pixels, points, or lines that, when displayed together, create an image represented by the shape); one or more hierarchical depth buffers (Hiz) for buffering data; and / or one or more pixel back - ends. In at least one embodiment, slices 1901A - 1901N include a memory structure, e.g., an L2 cache.

[0342] In at least one embodiment, FPUs 1914A - 1914N can perform single - precision (32 - bit) and half - precision (16 - bit) floating - point operations, while DPFPU 1915A - 1915N perform double - precision (64 - bit) floating - point operations. In at least one embodiment, ALUs 1916A - 1916N can perform variable - precision integer operations with 8 - bit, 16 - bit, and 32 - bit precision and can be configured for mixed - precision operations. In at least one embodiment, MPUs 1917A - 1917N can also be configured for mixed - precision matrix operations, including half - precision floating - point operations and 8 - bit integer operations. In at least one embodiment, MPUs 1917A - 1917N can perform various matrix operations to accelerate machine - learning application frameworks, including enabling support for accelerated general matrix - to - matrix multiplication (GEMM). In at least one embodiment, AFUs 1912A - 1912N can perform additional logical operations not supported by a floating - point unit or an integer unit, including trigonometric operations (e.g., sine, cosine, etc.).

[0343] Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. This is described herein in connection with Figure 8A and / or Figure 8B Details regarding Logic 815 are provided. In at least one embodiment, Logic 815 may be used in Graphics Core 1900 to perform inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0344] In at least one embodiment, Graphics Core 1900 includes an interconnect and link structure sub-layer attached to a switch and a GPU-GPU bridge that enables multiple graphics processors 1900 (e.g., 8) to be interconnected with load / store units (LSUs), data transfer units, and synchronization semantics across multiple graphics processors 1900 without gluing to each other. In at least one embodiment, the interconnect includes a standardized interconnect (e.g., PCIe) or some combination thereof.

[0345] In at least one embodiment, Graphics Core 1900 includes multiple tiles. In at least one embodiment, a tile is an individual die or one or more dies, where individual dies may be connected using an interconnect (e.g., Embedded Multi-Die Interconnect Bridge (EMIB)). In at least one embodiment, Graphics Core 1900 includes compute tiles, memory tiles (e.g., where memory tiles may be accessed specifically by different tiles or different chip sets such as Rambo tiles), substrate tiles, base tiles, HMB tiles, link tiles, and EMIB tiles, where all tiles are encapsulated together in Graphics Core 1900 as part of the GPU. In at least one embodiment, Graphics Core 1900 may include multiple tiles (also referred to as a "multi-tile package") in a single package. In at least one embodiment, a compute tile may have 8 Graphics Cores 1900, an L1 cache; and a base tile may have a host interface employing PCIe 5.0, HBM2e, MDFI, and EMIB, a link tile with 8 links, and 8 ports with an embedded switch. In at least one embodiment, the tiles are connected in a face-to-face (F2F) on-chip bonding manner using fine-pitch 36-micron microbumps (e.g., copper pillars). In at least one embodiment, Graphics Core 1900 includes a memory structure (which includes memory) and is a tile accessible to multiple tiles. In at least one embodiment, Graphics Core 1900 stores, accesses, or loads its own hardware context in memory, where the hardware context is a dataset loaded from registers prior to process restoration, and where the hardware context may indicate the state of the hardware (e.g., the state of the GPU).

[0346] In at least one embodiment, the graphics core 1900 includes serializer / deserializer (SERDES) circuitry that converts a serial data stream into a parallel data stream or converts a parallel data stream into a serial data stream.

[0347] In at least one embodiment, the graphics core 1900 includes a high-speed coherent unified fabric (GPU-to-GPU), load / store units, bulk data transfer and synchronization semantics, and GPUs connected by an embedded switch, where the GPU-GPU bridge is controlled by a controller.

[0348] In at least one embodiment, the graphics core 1900 executes an API, where the API abstracts the hardware of the graphics core 1900 and accesses a library with instructions to perform mathematical operations (e.g., Math Kernel Library), deep neural network operations (e.g., Deep Neural Network Library), vector operations, collective communications, thread building blocks, video processing, data analysis libraries, and / or ray tracing operations.

[0349] In at least one embodiment, the graphics core 1900 is used to at least partially implement Figures 1 - 6 text-based object generation as shown in

[0350] Figure 19B Shown is a GPGPU 1930 in at least one embodiment, which can be configured such that highly parallel computing operations can be performed by an array of graphics processing units. In at least one embodiment, the GPGPU 1930 can be directly linked to other instances of the GPGPU 1930 to create a multi-GPU cluster to increase the training speed for deep neural networks. In at least one embodiment, the GPGPU 1930 includes a host interface 1932 for implementing a connection to a host processor. In at least one embodiment, the host interface 1932 is a PCI Express interface. In at least one embodiment, the host interface 1932 can be a vendor-specific communication interface or communication fabric. In at least one embodiment, the GPGPU 1930 receives commands from the host processor and uses a global scheduler 1934 (which can be referred to as a thread sequencer and / or asynchronous compute engine) to allocate execution threads associated with those commands to a set of compute clusters 1936A - 1936H. In at least one embodiment, the compute clusters 1936A - 1936H share a cache memory 1938. In at least one embodiment, the cache memory 1938 can serve as a higher-level cache for the cache memories within the compute clusters 1936A - 1936H. In at least one embodiment, the compute clusters 1936A - 1936H include slices or are also referred to as "slices". In at least one embodiment, the GPGPU 1930 is part of a SoC, such as part of the integrated circuit 1700 (Figure 17 )。

[0351] In at least one embodiment, the GPGPU 1930 includes memories 1944A - 1944B, which are coupled to the compute clusters 1936A - 1936H via a set of memory controllers 1942A - 1942B (e.g., one or more controllers for HBM2e). In at least one embodiment, the memories 1944A - 1944B may include various types of memory devices, which include dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), which includes graphics double data rate (GDDR) memory.

[0352] In at least one embodiment, each of the compute clusters 1936A - 1936H includes a set of graphics cores, such as Figure 19A the graphics core 1900, which may include various types of integer and floating - point logic units that can perform computational operations over a range of precisions suitable for machine - learning computations. For example, in at least one embodiment, at least a subset of the floating - point units in each compute cluster 1936A - 1936H may be configured to perform 16 - bit or 32 - bit floating - point operations, while a different subset of the floating - point units may be configured to perform 64 - bit floating - point operations.

[0353] In at least one embodiment, multiple instances of the GPGPU 1930 may be configured to operate as compute clusters. In at least one embodiment, the communication for synchronization and data exchange among the compute clusters 1936A - 1936H varies between embodiments. In at least one embodiment, multiple instances of the GPGPU 1930 communicate via the host interface 1932. In at least one embodiment, the GPGPU 1930 includes an I / O hub 1939, which couples the GPGPU 1930 to the GPU link 1940, and the GPU link 1940 enables a direct connection to other instances of the GPGPU 1930. In at least one embodiment, the GPU link 1940 is coupled to a dedicated GPU - to - GPU bridge, which enables communication and synchronization among multiple instances of the GPGPU 1930. In at least one embodiment, the GPU link 1940 is coupled to a high - speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of the GPGPU 1930 are located in separate data - processing systems and communicate via network devices accessible via the host interface 1932. In at least one embodiment, in addition to or as an alternative to the host interface 1932, the GPU link 1940 may also be configured to enable a connection to the host processor.

[0354] In at least one embodiment, the GPGPU 1930 can be configured to train a neural network. In at least one embodiment, the GPGPU 1930 can be used within an inference platform. In at least one embodiment, in the case of using the GPGPU 1930 for inference, the GPGPU 1930 can include fewer compute clusters 1936A - 1936H as compared to when using the GPGPU 1930 to train a neural network. In at least one embodiment, the memory technology associated with memories 1944A - 1944B can differ between inference and training configurations, with higher bandwidth memory technology dedicated to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 1930 can support inference - specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8 - bit integer dot - product instructions that can be used during the inference operation of a deployed neural network.

[0355] Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 815 are provided herein in connection with Figure 8A and / or Figure 8B In at least one embodiment, logic 815 can be used in the GPGPU 1930 to perform inference or prediction operations at least in part based on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0356] In at least one embodiment, the GPGPU 1930 is used to at least partially implement text - based object generation as shown in Figures 1 - 6

[0357] Figure 20is a block diagram showing a computing system 2000 according to at least one embodiment. In at least one embodiment, the computing system 2000 includes a processing subsystem 2001 having one or more processors 2002 and system memory 2004 communicating via an interconnect path that may include a memory hub 2005. In at least one embodiment, the memory hub 2005 may be a separate component within a chipset component or may be integrated within one or more processors 2002. In at least one embodiment, the memory hub 2005 is coupled to an I / O subsystem 2011 via a communication link 2006. In at least one embodiment, the I / O subsystem 2011 includes an I / O hub 2007 that may enable the computing system 2000 to receive input from one or more input devices 2008. In at least one embodiment, the I / O hub 2007 may enable a display controller, which may be included in one or more processors 2002, to provide output to one or more display devices 2010A. In at least one embodiment, one or more display devices 2010A coupled to the I / O hub 2007 may include a local, internal, or embedded display device.

[0358] In at least one embodiment, the processing subsystem 2001 includes one or more parallel processors 2012 coupled to the memory hub 2005 via a bus or other communication link 2013. In at least one embodiment, the communication link 2013 may use any number of standards based on communication link technologies or protocols such as, but not limited to, PCI Express, or may be a vendor-specific communication interface or communication fabric. In at least one embodiment, one or more parallel processors 2012 form a parallel or vector processing system in a computing cluster that may include a large number of processing cores and / or processing clusters such as an integrated many-core (MIC) processor. In at least one embodiment, some or all of the one or more parallel processors 2012 form a graphics processing subsystem that may output pixels to one of the one or more display devices 2010A coupled via the I / O hub 2007. In at least one embodiment, one or more parallel processors 2012 may also include a display controller and a display interface (not shown) for enabling a direct connection to one or more display devices 2010B. In at least one embodiment, one or more parallel processors 2012 include one or more cores such as the graphics core 1900 discussed herein.

[0359] In at least one embodiment, the system storage unit 2014 can be connected to the I / O hub 2007 to provide a storage mechanism for the computing system 2000. In at least one embodiment, the I / O switch 2016 can be used to provide an interface mechanism for enabling connections between the I / O hub 2007 and other components, such as a network adapter 2018 and / or a wireless network adapter 2019 that may be integrated into the platform, as well as various other devices that can be added via one or more additional devices 2020. In at least one embodiment, the network adapter 2018 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 2019 can include one or more of Wi-Fi, Bluetooth, Near Field Communication (NFC), or other network devices including one or more radio devices.

[0360] In at least one embodiment, the computing system 2000 can include other components (not explicitly shown) that can also be connected to the I / O hub 2007, including USB or other port connections, optical storage drives, video capture devices, etc. In at least one embodiment, any suitable protocol (such as a PCI (Peripheral Component Interconnect)-based protocol (e.g., PCI-Express) or other bus or point-to-point communication interface and / or protocol (such as NV-Link high-speed interconnect or interconnect protocol)) can be used to implement the communication paths between the various components. Figure 20 of the various components.

[0361] In at least one embodiment, one or more parallel processors 2012 include circuitry optimized for graphics and video processing, which includes, for example, video output circuitry and constitutes a Graphics Processing Unit (GPU). For example, one or more parallel processors 2012 include a graphics core 1900. In at least one embodiment, one or more parallel processors 2012 include circuitry optimized for general-purpose processing. In at least one embodiment, the components of the computing system 2000 can be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 2012, the memory hub 2005, one or more processors 2002, and the I / O hub 2007 can be integrated into a System-on-Chip (SoC) integrated circuit. In at least one embodiment, the components of the computing system 2000 can be integrated into a single package to form a System-in-Package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computing system 2000 can be integrated into a Multi-Chip Module (MCM), which can be interconnected with other multi-chip modules into a modular computing system.

[0362] Logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8B Details are provided regarding logic 815. In at least one embodiment, logic 815 can be used in computing system 2000 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0363] In at least one embodiment, the computing system 2000 is used to implement, at least in part, Figures 1 - 6 The text-based object generation shown in .

[0364] Processor

[0365] Figure 21A 2100 according to at least one embodiment. In at least one embodiment, the various components of the parallel processor 2100 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). In at least one embodiment, the parallel processor 2100 shown is a processor according to an exemplary embodiment. Figure 20 Variations of one or more parallel processors 2012 are shown. In at least one embodiment, parallel processors 2100 include one or more graphics cores 1900.

[0366] In at least one embodiment, parallel processor 2100 includes parallel processing unit 2102. In at least one embodiment, parallel processing unit 2102 includes I / O unit 2104, which enables communication with other devices, including other instances of parallel processing unit 2102. In at least one embodiment, I / O unit 2104 can be directly connected to other devices. In at least one embodiment, I / O unit 2104 is connected to other devices via the use of a hub or switch interface (e.g., memory hub 2105). In at least one embodiment, the connection between memory hub 2105 and I / O unit 2104 forms a communication link 2113. In at least one embodiment, I / O unit 2104 is connected to a host interface 2106 and a memory crossbar switch 2116, wherein host interface 2106 receives commands for performing processing operations and memory crossbar switch 2116 receives commands for performing memory operations.

[0367] In at least one embodiment, when the host interface 2106 receives a command buffer via the I / O unit 2104, the host interface 2106 may direct the work operations for executing those commands to the front end 2108. In at least one embodiment, the front end 2108 is coupled to a scheduler 2110 (which may be referred to as an orderer), and the scheduler 2110 is configured to allocate commands or other work items to the array of processing clusters 2112. In at least one embodiment, the scheduler 2110 ensures that the array of processing clusters 2112 is properly configured and in an active state before tasks are allocated to the clusters in the array of processing clusters 2112. In at least one embodiment, the scheduler 2110 is implemented via firmware logic executed on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2110 may be configured to perform complex scheduling and work allocation operations at both a coarse-grained and a fine-grained level, enabling fast preemption and context switching of the threads executing on the array of processing clusters 2112. In at least one embodiment, the host software may attest to the workload to be scheduled on the array of processing clusters 2112 via one of the multiple graphics processing paths. In at least one embodiment, the workload may then be automatically allocated on the array of processing clusters 2112 by the scheduler 2110 logic within the microcontroller that includes the scheduler 2110.

[0368] In at least one embodiment, the array of processing clusters 2112 may include up to “N” processing clusters (e.g., cluster 2114A, cluster 2114B through cluster 2114N), where “N” represents a positive integer (which may be a different integer “N” than the integer used in other figures). In at least one embodiment, each of the clusters 2114A - 2114N of the array of processing clusters 2112 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 2110 may use various scheduling and / or work allocation algorithms to allocate work to the clusters 2114A - 2114N in the array of processing clusters 2112, and these algorithms may vary depending on the workload generated for each type of program or computation. In at least one embodiment, the scheduling may be handled dynamically by the scheduler 2110 or may be assisted in part by compiler logic during the compilation of the program logic configured to be executed by the array of processing clusters 2112. In at least one embodiment, different clusters 2114A - 2114N in the array of processing clusters 2112 may be assigned to process different types of programs or to perform different types of computations.

[0369] In at least one embodiment, the processing cluster array 2112 may be configured to perform various types of parallel processing operations. In at least one embodiment, the processing cluster array 2112 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing cluster array 2112 may include logic for performing processing tasks that include filtering of video and / or audio data, performing modeling operations, including physics operations, and performing data transformations.

[0370] In at least one embodiment, the processing cluster array 2112 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2112 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, and tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster array 2112 may be configured to execute shader programs related to graphics processing, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2102 may transfer data from the system memory via the I / O unit 2104 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2122) during processing and then written back to the system memory.

[0371] In at least one embodiment, when the parallel processing unit 2102 is used to perform graphics processing, the scheduler 2110 may be configured to divide the processing workload into tasks of approximately equal size to better enable the distribution of graphics processing operations to the multiple clusters 2114A - 2114N in the processing cluster array 2112. In at least one embodiment, various parts of the processing cluster array 2112 may be configured to perform different types of processing. For example, in at least one embodiment, the first part may be configured to perform vertex shading and topology generation, the second part may be configured to perform tessellation and geometry shading, and the third part may be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of the clusters 2114A - 2114N may be stored in a buffer to allow the transfer of intermediate data between the clusters 2114A - 2114N for further processing.

[0372] In at least one embodiment, the processing cluster array 2112 may receive processing tasks to be executed via a scheduler 2110 that receives commands defining the processing tasks from a front end 2108. In at least one embodiment, the processing tasks may include an index of data to be processed, such as surface (patch) data, raw data, vertex data, and / or pixel data, as well as status parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, the scheduler 2110 may be configured to obtain an index corresponding to the task or may receive the index from the front end 2108. In at least one embodiment, the front end 2108 may be configured to ensure that the processing cluster array 2112 is configured in a valid state before starting a workload specified by an incoming command buffer (e.g., a batch-buffer, a push buffer, etc.).

[0373] In at least one embodiment, each of one or more instances of the parallel processing units 2102 may be coupled to a parallel processor memory 2122. In at least one embodiment, the parallel processor memory 2122 may be accessed via a memory crossbar 2116 that may receive memory requests from the processing cluster array 2112 as well as the I / O unit 2104. In at least one embodiment, the memory crossbar 2116 may access the parallel processor memory 2122 via a memory interface 2118. In at least one embodiment, the memory interface 2118 may include a plurality of partitioning units (e.g., partitioning unit 2120A, partitioning unit 2120B to partitioning unit 2120N), each of which may be coupled to a portion (e.g., a memory unit) of the parallel processor memory 2122. In at least one embodiment, the number of partitioning units 2120A - 2120N is configured to be equal to the number of memory units such that the first partitioning unit 2120A has a corresponding first memory unit 2124A, the second partitioning unit 2120B has a corresponding second memory unit 2124B, and the Nth partitioning unit 2120N has a corresponding Nth memory unit 2124N. In at least one embodiment, the number of partitioning units 2120A - 2120N may not be equal to the number of memory units.

[0374] In at least one embodiment, the memory units 2124A - 2124N can include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, the memory units 2124A - 2124N can also include 3D stacked memory, including but not limited to high bandwidth memory (HBM), HBM2e, or HBM3. In at least one embodiment, render targets such as frame buffers or texture maps can be stored across the memory units 2124A - 2124N, allowing the partitioning units 2120A - 2120N to write portions of each render target in parallel to efficiently utilize the available bandwidth of the parallel processor memory 2122. In at least one embodiment, local instances of the parallel processor memory 2122 can be excluded in favor of a unified memory design that utilizes system memory as well as local cache memory.

[0375] In at least one embodiment, any one of the clusters 2114A - 2114N in the cluster array 2112 of processing clusters can process data to be written into any of the memory units 2124A - 2124N within the parallel processor memory 2122. In at least one embodiment, the memory crossbar 2116 can be configured to transmit the output of each cluster 2114A - 2114N to any of the partitioning units 2120A - 2120N or to another cluster 2114A - 2114N, and the other cluster 2114A - 2114N can perform additional processing operations on the output. In at least one embodiment, each cluster 2114A - 2114N can communicate with the memory interface 2118 through the memory crossbar 2116 to read from or write to various external memory devices. In at least one embodiment, the memory crossbar 2116 has a connection to the memory interface 2118 for communicating with the I / O unit 2104, as well as a connection to a local instance of the parallel processor memory 2122, which enables processing units within different processing clusters 2114A - 2114N to communicate with system memory or other memory that is not local to the parallel processing units 2102. In at least one embodiment, the memory crossbar 2116 can use virtual channels to separate the traffic flow between the clusters 2114A - 2114N and the partitioning units 2120A - 2120N.

[0376] In at least one embodiment, multiple instances of the parallel processing unit 2102 can be provided on a single add-in card, or multiple add-in cards can be interconnected. In at least one embodiment, different instances of the parallel processing unit 2102 can be configured to operate with each other, even if the different instances have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 2102 can include floating-point units with higher precision relative to other instances. In at least one embodiment, a system that includes one or more instances of the parallel processing unit 2102 or parallel processor 2100 can be implemented in various configurations and form factors, including but not limited to desktop computers, laptop computers, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0377] Figure 21B is a block diagram of a partitioning unit 2120 according to at least one embodiment. In at least one embodiment, the partitioning unit 2120 is Figure 21A an instance of one of the partitioning units 2120A - 2120N. In at least one embodiment, the partitioning unit 2120 includes an L2 cache 2121, a frame buffer interface 2125, and a ROP 2126 (raster operation unit). In at least one embodiment, the L2 cache 2121 is a read / write cache that is configured to perform load and store operations received from the memory crossbar 2116 and the ROP 2126. In at least one embodiment, the L2 cache 2121 outputs read misses and urgent write-back requests to the frame buffer interface 2125 for processing. In at least one embodiment, updates can also be sent to the frame buffer via the frame buffer interface 2125 for processing. In at least one embodiment, the frame buffer interface 2125 interfaces with one of the memory units (such as Figure 21A the memory units 2124A - 2124N (e.g., within the parallel processor memory 2122)) of

[0378] In at least one embodiment, ROP 2126 is a processing unit that performs raster operations such as stencil, z-test, blending, etc. In at least one embodiment, ROP 2126 then outputs the processed graphics data stored in the graphics memory. In at least one embodiment, ROP 2126 includes compression logic for compressing depth or color data written to the memory and decompressing depth or color data read from the memory. In at least one embodiment, the compression logic can be lossless compression logic that utilizes one or more of a variety of compression algorithms. In at least one embodiment, the type of compression performed by ROP 2126 can vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, delta color compression is performed on depth and color data per tile.

[0379] In at least one embodiment, ROP 2126 is included within each processing cluster (e.g., Figure 21A clusters 2114A - 2114N), rather than within the partitioning unit 2120. In at least one embodiment, read and write requests for pixel data rather than pixel fragment data are transmitted through the memory crossbar 2116. In at least one embodiment, the processed graphics data can be displayed on a display device (such as Figure 20 one of one or more display devices 2010), routed by the processor 2002 for further processing, or routed by Figure 21A one of the processing entities within the parallel processor 2100 of

[0380] Figure 21C is a block diagram of a processing cluster 2114 within a parallel processing unit according to at least one embodiment. In at least one embodiment, the processing cluster is Figure 21A an instance of one of the processing clusters 2114A - 2114N. In at least one embodiment, the processing cluster 2114 can be configured to execute many threads in parallel, where a "thread" refers to an instance of a particular program executed on a particular set of input data. In at least one embodiment, single instruction multiple data (SIMD) instruction issue techniques are used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread (SIMT) techniques are used to support the parallel execution of a large number of generally synchronized threads using a common instruction unit that is configured to issue instructions to a set of processing engines within each processing cluster.

[0381] In at least one embodiment, the operation of the processing cluster 2114 can be controlled via a pipeline manager 2132 that assigns processing tasks to the SIMT parallel processor. In at least one embodiment, the pipeline manager 2132 receives from Figure 21AThe scheduler 2110 receives instructions and manages the execution of these instructions via the graphics multiprocessor 2134 and / or the texture unit 2136. In at least one embodiment, the graphics multiprocessor 2134 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of different architectures may be included within the processing cluster 2114. In at least one embodiment, one or more instances of the graphics multiprocessor 2134 may be included within the processing cluster 2114. In at least one embodiment, the graphics multiprocessor 2134 may process data, and the data crossbar 2140 may be used to distribute the processed data to one of multiple possible destinations (including other shader units). In at least one embodiment, the pipeline manager 2132 may facilitate the distribution of the processed data by specifying the destination of the processed data to be distributed via the data crossbar 2140.

[0382] In at least one embodiment, each graphics multiprocessor 2134 within the processing cluster 2114 may include the same set of functional execution logic (e.g., arithmetic logic units, load-store units, etc.). In at least one embodiment, the functional execution logic may be configured in a pipelined manner, where new instructions may be issued before the previous instructions are completed. In at least one embodiment, the functional execution logic supports various operations, including integer and floating-point arithmetic, comparison operations, boolean operations, bit shifts, and the calculation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may exist.

[0383] In at least one embodiment, the instructions transmitted to the processing cluster 2114 constitute threads. In at least one embodiment, a set of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, the thread group executes a general program on different input data. In at least one embodiment, each thread within the thread group may be assigned to a different processing engine within the graphics multiprocessor 2134. In at least one embodiment, the thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 2134. In at least one embodiment, when the thread group includes fewer threads than the number of processing engines, one or more processing engines may be idle during the cycle of processing the thread group. In at least one embodiment, the thread group may also include more threads than the number of processing engines within the graphics multiprocessor 2134. In at least one embodiment, when the thread group includes more threads than the number of processing engines within the graphics multiprocessor 2134, processing may be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups may be executed concurrently on the graphics multiprocessor 2134.

[0384] In at least one embodiment, the graphics multiprocessor 2134 includes an internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2134 may forego the internal cache and use the cache memory within the processing cluster 2114 (e.g., the L1 cache 2148). In at least one embodiment, each graphics multiprocessor 2134 may also access the L2 cache within the partition units (e.g., Figure 21A the partition units 2120A-2120N) of Figure 21A , which are shared among all processing clusters 2114 and can be used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 2134 may also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to the parallel processing unit 2102 can be used as global memory. In at least one embodiment, the processing cluster 2114 includes multiple instances of the graphics multiprocessor 2134, which may share common instructions and data that can be stored in the L1 cache 2148.

[0385] In at least one embodiment, each processing cluster 2114 may include a memory management unit (“MMU”) 2145 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 2145 may reside within Figure 21A the memory interface 2118 of Figure 21A . In at least one embodiment, the MMU 2145 includes a set of page table entries (PTEs) for mapping virtual addresses to the physical addresses of tiles and optionally to cache line indices. In at least one embodiment, the MMU 2145 may include a translation lookaside buffer (TLB) or a cache that may reside within the graphics multiprocessor 2134 or the L1 cache 2148 or the processing cluster 2114. In at least one embodiment, the physical addresses are processed to allocate surface data access locality for efficient request interleaving between partition units. In at least one embodiment, the cache line index can be used to determine whether a request to a cache line is a hit or a miss.

[0386] In at least one embodiment, the processing cluster 2114 can be configured such that each graphics multiprocessor 2134 is coupled to a texture unit 2136 to perform texture mapping operations that determine texture sample locations, read texture data, and filter texture data. In at least one embodiment, texture data is read as needed from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2134, and texture data is fetched from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 2134 outputs the processed tasks to a data crossbar 2140 to provide the processed tasks to another processing cluster 2114 for further processing, or stores the processed tasks in an L2 cache, local parallel processor memory, or in system memory via a memory crossbar 2116. In at least one embodiment, the preROP 2142 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 2134 and direct the data to a ROP unit that can be located with the partitioning units (e.g., Figure 21A partitioning units 2120A - 2120N) described herein. In at least one embodiment, the PreROP 2142 unit can perform optimizations for color blending, organizing pixel color data, and performing address translation.

[0387] Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the logic 815 are provided herein in connection with Figure 8A and / or Figure 8B In at least one embodiment, the logic 815 can be used in the graphics processing cluster 2114 for inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0388] In at least one embodiment, the graphics multiprocessor 2134 is used to at least partially implement text-based object generation as shown in Figures 1 - 6

[0389] Figure 21DIllustrates a graphics multiprocessor 2134 according to at least one embodiment. In at least one embodiment, the graphics multiprocessor 2134 is coupled to a pipeline manager 2132 of a processing cluster 2114. In at least one embodiment, the graphics multiprocessor 2134 has an execution pipeline that includes, but is not limited to, an instruction cache 2152, an instruction unit 2154, an address mapping unit 2156, a register file 2158, one or more general-purpose graphics processing unit (GPGPU) cores 2162, and one or more load / store units 2166, where one or more load / store units 2166 may perform load / store operations to load / store instructions corresponding to execution operations. In at least one embodiment, the GPGPU cores 2162 and the load / store units 2166 are coupled to a cache memory 2172 and a shared memory 2170 via a memory and cache interconnect 2168. In at least one embodiment, the GPGPU cores 2162 are part of a system-on-chip (SoC) (such as Figure 17 a part of the integrated circuit 1700 in).

[0390] In at least one embodiment, the instruction cache 2152 receives a stream of instructions to be executed from the pipeline manager 2132. In at least one embodiment, the instructions are cached in the instruction cache 2152 and dispatched for execution by the instruction unit 2154. In at least one embodiment, the instruction unit 2154 may dispatch instructions as a thread group (e.g., a warp, a wavefront, a wave), where each thread in the thread group is assigned to a different execution unit within the GPGPU core 2162. In at least one embodiment, instructions may access any local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, the address mapping unit 2156 may be used to convert an address in the unified address space into a different memory address that can be accessed by the load / store unit 2166.

[0391] In at least one embodiment, the register file 2158 provides a set of registers for the functional units of the graphics multiprocessor 2134. In at least one embodiment, the register file 2158 provides temporary storage for the operands of the data paths of the functional units (e.g., GPGPU cores 2162, load / store units 2166) connected to the graphics multiprocessor 2134. In at least one embodiment, the register file 2158 is divided among each functional unit such that a dedicated portion of the register file 2158 is allocated to each functional unit. In at least one embodiment, the register file 2158 is divided among different warps (which may be referred to as wavefronts and / or waves) being executed by the graphics multiprocessor 2134.

[0392] In at least one embodiment, the GPGPU cores 2162 may each include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 2134. In at least one embodiment, the architectures of the respective GPGPU cores 2162 may be similar or may be different. In at least one embodiment, a first portion of the GPGPU core 2162 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point algorithms or enable variable-precision floating-point algorithms. In at least one embodiment, the graphics multiprocessor 2134 may additionally include one or more fixed-function or special-function units for performing specific functions, such as copy rectangle or pixel blend operations. In at least one embodiment, one or more of the GPGPU cores 2162 may also include fixed or special-function logic.

[0393] In at least one embodiment, the GPGPU core 2162 includes SIMD logic capable of executing a single instruction on multiple sets of data. In at least one embodiment, the GPGPU core 2162 may physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core may be generated by a shader compiler at compile time or automatically generated when executing a program written and compiled for a single-program multiple-data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for the SIMT execution model may be executed via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations may be executed in parallel via a single SIMD8 logic unit.

[0394] In at least one embodiment, the memory and cache interconnect 2168 is an interconnect network that connects each functional unit of the graphics multiprocessor 2134 to the register file 2158 and the shared memory 2170. In at least one embodiment, the memory and cache interconnect 2168 is a crossbar interconnect that allows the load / store unit 2166 to perform load and store operations between the shared memory 2170 and the register file 2158. In at least one embodiment, the register file 2158 can operate at the same frequency as the GPGPU core 2162, so that the latency of data transfer between the GPGPU core 2162 and the register file 2158 is very low. In at least one embodiment, the shared memory 2170 can be used to implement communication between threads executing on the functional units within the graphics multiprocessor 2134. In at least one embodiment, the cache memory 2172 can be used as, for example, a data cache for caching texture data communicated between the functional units and the texture unit 2136. In at least one embodiment, the shared memory 2170 can also be used as a program-managed cache. In at least one embodiment, in addition to the automatically cached data stored in the cache memory 2172, the threads executing on the GPGPU core 2162 can also programmatically store data in the shared memory.

[0395] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the SoC includes a parallel processor or GPGPU as described herein, where the parallel processor or the GPGPU is executed on the SoC. In at least one embodiment, the GPU can be integrated with the core in a package or on a chip and communicatively coupled to the core via an internal processor bus / interconnect within the package or chip. In at least one embodiment, regardless of the manner in which the GPU is connected, the processor core can allocate work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0396] The logic 815 is used to perform inference and / or training operations associated with one or more embodiments. As described herein in connection with Figure 8A and / or Figure 8BProvide details about logic 815. In at least one embodiment, logic 815 may be used in the graphics multiprocessor 2134 to perform inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0397] In at least one embodiment, the graphics multiprocessor 2134 is used to at least partially implement text-based object generation as shown in Figures 1 - 6 the text.

[0398] Figure 22 A multi-GPU computing system 2200 according to at least one embodiment is shown. In at least one embodiment, the multi-GPU computing system 2200 may include a processor 2202 coupled to a plurality of general-purpose graphics processing units (GPGPUs) 2206A-D via a host interface switch 2204. In at least one embodiment, the host interface switch 2204 is a PCI Express switch device that couples the processor 2202 to a PCI Express bus, and the processor 2202 may communicate with the GPGPUs 2206A-D via the PCI Express bus. In at least one embodiment, the GPGPUs 2206A-D may be interconnected via a set of high-speed P2P (peer-to-peer) GPU-to-GPU links 2216. In at least one embodiment, the GPU-to-GPU link 2216 is connected to each of the GPGPUs 2206A-D via a dedicated GPU link. In at least one embodiment, the P2P GPU link 2216 enables direct communication between each of the GPGPUs 2206A-D without communicating through the host interface bus 2204 to which the processor 2202 is connected. In at least one embodiment, in the case where GPU-to-GPU traffic is directed to the P2P GPU link 2216, the host interface bus 2204 remains available for system memory access or communication with other instances of the multi-GPU computing system 2200 via one or more network devices. Although in at least one embodiment, the GPGPUs 2206A-D are connected to the processor 2202 via the host interface switch 2204, in at least one embodiment, the processor 2202 includes direct support for the P2P GPU link 2216 and may be directly connected to the GPGPUs 2206A-D. In at least one embodiment, the GPGPUs 2206A-D are part of an SoC (such as Figure 17 part of the integrated circuit 1700 in the text), where the GPGPUs 2206A-D perform the operations described herein.

[0399] Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. As described herein in connection withFigure 8A and / or Figure 8B Provide details about the logic 815. In at least one embodiment, the logic 815 can be used in the multi-GPU computing system 2200 for performing inference or prediction operations at least in part based on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0400] In at least one embodiment, the multi-GPU computing system 2200 includes one or more graphics cores 1900.

[0401] In at least one embodiment, the multi-GPU computing system 2200 is used to at least partially implement text-based object generation as shown in Figures 1 - 6 as shown.

[0402] Figure 23 is a block diagram of a graphics processor 2300 according to at least one embodiment. In at least one embodiment, the graphics processor 2300 includes a ring interconnect 2302, a pipeline front end 2304, a media engine 2337, and graphics cores 2380A - 2380N. In at least one embodiment, the ring interconnect 2302 couples the graphics processor 2300 to other processing units, which include other graphics processors or one or more general processor cores. In at least one embodiment, the graphics processor 2300 is one of many processors integrated within a multi-core processing system. In at least one embodiment, the graphics processor 2300 includes the graphics core 1900.

[0403] In at least one embodiment, the graphics processor 2300 receives multiple batches of commands via the ring interconnect 2302. In at least one embodiment, the input commands are interpreted by a command streamer 2303 in the pipeline front end 2304. In at least one embodiment, the graphics processor 2300 includes scalable execution logic for performing 3D geometry processing and media processing via the graphics cores 2380A - 2380N. In at least one embodiment, for 3D geometry processing commands, the command streamer 2303 provides the commands to the geometry pipeline 2336. In at least one embodiment, for at least some media processing commands, the command streamer 2303 provides the commands to the video front end 2334, which is coupled to the media engine 2337. In at least one embodiment, the media engine 2337 includes a video quality engine (VQE) 2330 for video and image post-processing, and a multi-format encoding / decoding (MFX) 2333 engine for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2336 and the media engine 2337 each generate execution threads for thread execution resources provided by at least one graphics core 2380.

[0404] In at least one embodiment, the graphics processor 2300 includes scalable thread execution resources featuring graphics cores 2380A - 2380N (which may be modular and sometimes referred to as core slices), each graphics core having a plurality of sub - cores 2350A - 2350N, 2360A - 2360N (sometimes referred to as core sub - slices). In at least one embodiment, the graphics processor 2300 can have any number of graphics cores 2380A. In at least one embodiment, the graphics processor 2300 includes a graphics core 2380A having at least a first sub - core 2350A and a second sub - core 2360A. In at least one embodiment, the graphics processor 2300 is a low - power processor having a single sub - core (e.g., 2350A). In at least one embodiment, the graphics processor 2300 includes a plurality of graphics cores 2380A - 2380N, each graphics core including a set of first sub - cores 2350A - 2350N and a set of second sub - cores 2360A - 2360N. In at least one embodiment, each of the first sub - cores 2350A - 2350N includes at least a first set of execution units 2352A - 2352N and media / texture samplers 2354A - 2354N. In at least one embodiment, each of the second sub - cores 2360A - 2360N includes at least a second set of execution units 2362A - 2362N and samplers 2364A - 2364N. In at least one embodiment, each of the sub - cores 2350A - 2350N, 2360A - 2360N shares a set of shared resources 2370A - 2370N. In at least one embodiment, the shared resources include shared cache memory and pixel operation logic. In at least one embodiment, the graphics processor 2300 includes load / store units in the pipeline front - end 2304.

[0405] Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding Figure 8A and / or Figure 8B are provided. In at least one embodiment, logic 815 can be used in the graphics processor 2300 to perform inference or prediction operations at least in part based on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0406] In at least one embodiment, the graphics processor 2300 is used to at least partially implement text - based object generation as shown in Figures 1 - 6 ...

[0407] Figure 24is a block diagram showing a microarchitecture for a processor 2400 according to at least one embodiment, the processor 2400 may include logic circuitry for executing instructions. In at least one embodiment, the processor 2400 may execute instructions including x86 instructions, ARM instructions, special instructions for application specific integrated circuits (ASICs), etc. In at least one embodiment, the processor 2400 may include registers for storing packed data, such as 64-bit wide MMXTM registers in a microprocessor implemented with Intel Corporation's MMX technology in Santa Clara, California. In at least one embodiment, MMX registers available in both integer and floating-point forms may operate with packed data elements, the packed data elements accompanying single instruction multiple data (“SIMD”) and streaming SIMD extensions (“SSE”) instructions. In at least one embodiment, 128-bit wide XMM registers related to SSE2, SSE3, SSE4, AVX or beyond (commonly referred to as “SSEx”) technology may hold such packed data operands. In at least one embodiment, the processor 2400 may execute instructions to accelerate machine learning or deep learning algorithms, training or inference.

[0408] In at least one embodiment, the processor 2400 includes an in-order front end (“front end”) 2401 for fetching instructions to be executed and preparing the instructions for later use in the processor pipeline. In at least one embodiment, the front end 2401 may include several units. In at least one embodiment, the instruction prefetcher 2426 fetches instructions from memory and feeds the instructions to the instruction decoder 2428, which in turn decodes or interprets the instructions. For example, in at least one embodiment, the instruction decoder 2428 decodes the received instructions into one or more operations of so-called “micro-operations” or “micro-instructions” (also referred to as “micro ops” or “uops” or “μ-ops”) that are machine-executable. In at least one embodiment, the instruction decoder 2428 parses the instructions into an opcode and corresponding data and control fields, which may be used by the microarchitecture to perform operations according to at least one embodiment. In at least one embodiment, the trace cache 2430 may assemble the decoded micro-operations into a program-ordered sequence or trace in the micro-operation queue 2434 for execution. In at least one embodiment, when the trace cache 2430 encounters a complex instruction, the microcode ROM 2432 provides the micro-operations required to complete the operation.

[0409] In at least one embodiment, some instructions can be converted into a single micro-operation, while other instructions require several micro-operations to complete the entire operation. In at least one embodiment, if more than four micro-operations are required to complete an instruction, the instruction decoder 2428 can access the microcode ROM 2432 to execute the instruction. In at least one embodiment, an instruction can be decoded into a small number of micro-operations for processing at the instruction decoder 2428. In at least one embodiment, if multiple micro-operations are required to complete the operation, the instruction can be stored in the microcode ROM 2432. In at least one embodiment, the trace cache 2430 references an entry point programmable logic array (“PLA”) to determine the correct micro-instruction pointer for reading a microcode sequence from the microcode ROM 2432 to complete one or more instructions according to at least one embodiment. In at least one embodiment, after the microcode ROM 2432 finishes serializing the micro-operations for an instruction, the front end 2401 of the machine can resume fetching micro-operations from the trace cache 2430.

[0410] In at least one embodiment, an out-of-order execution engine ("out-of-order engine") 2403 may prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the instruction stream to optimize performance as the instruction stream proceeds down the pipeline and is scheduled for execution. In at least one embodiment, the out-of-order execution engine 2403 includes, but is not limited to, an allocator / register renamer 2440, a memory micro-operation queue 2442, an integer / floating-point micro-operation queue 2444, a memory scheduler 2446, a fast scheduler 2402, a slow / general floating-point scheduler ("slow / general FP scheduler") 2404, and a simple floating-point scheduler ("simple FP scheduler") 2406. In at least one embodiment, the fast scheduler 2402, the slow / general floating-point scheduler 2404, and the simple floating-point scheduler 2406 are also collectively referred to herein as "micro-operation schedulers 2402, 2404, 2406". In at least one embodiment, the allocator / register renamer 2440 allocates the machine buffers and resources required for each micro-operation for execution. In at least one embodiment, the allocator / register renamer 2440 renames logical registers to entries in the register file. In at least one embodiment, the allocator / register renamer 2440 also allocates entries for each micro-operation in one of the two micro-operation queues, with the memory micro-operation queue 2442 for memory operations and the integer / floating-point micro-operation queue 2444 for non-memory operations, in front of the memory scheduler 2446 and the micro-operation schedulers 2402, 2404, 2406. In at least one embodiment, the micro-operation schedulers 2402, 2404, 2406 determine when a micro-operation is ready for execution based on the readiness of their dependent input register operands sources and the availability of the execution resources required for the micro-operation to complete its operation. In at least one embodiment, the fast scheduler 2402 may be scheduled on each half of the main clock cycle, while the slow / general floating-point scheduler 2404 and the simple floating-point scheduler 2406 may be scheduled once per main processor clock cycle. In at least one embodiment, the micro-operation schedulers 2402, 2404, 2406 arbitrate the dispatch ports to schedule micro-operations for execution.

[0411] In at least one embodiment, execution block 2411 includes, but is not limited to, integer register file / bypass network 2408, floating-point register file / bypass network (“FP register file / bypass network”) 2410, address generation units (“AGU”) 2412 and 2414, fast arithmetic logic units (ALU) (“fast ALU”) 2416 and 2418, slow arithmetic logic unit (“slow ALU”) 2420, floating-point ALU (“FP”) 2422, and floating-point move unit (“FP move”) 2424. In at least one embodiment, integer register file / bypass network 2408 and floating-point register file / bypass network 2410 are also referred to herein as “register files 2408, 2410”. In at least one embodiment, AGU 2412 and 2414, fast ALU 2416 and 2418, slow ALU 2420, floating-point ALU 2422, and floating-point move unit 2424 are also referred to herein as “execution units 2412, 2414, 2416, 2418, 2420, 2422, and 2424”. In at least one embodiment, execution block 2411 may include, but is not limited to, any number (including zero) and type of register files, bypass networks, address generation units, and execution units in any combination.

[0412] In at least one embodiment, register networks 2408, 2410 may be arranged between micro-operation schedulers 2402, 2404, 2406 and execution units 2412, 2414, 2416, 2418, 2420, 2422, and 2424. In at least one embodiment, integer register file / bypass network 2408 performs integer operations. In at least one embodiment, floating-point register file / bypass network 2410 performs floating-point operations. In at least one embodiment, each of register networks 2408, 2410 may include, but is not limited to, a bypass network that may bypass or forward to a new related micro-operation a just-completed result that has not yet been written to the register file. In at least one embodiment, register networks 2408, 2410 may communicate data with each other. In at least one embodiment, integer register file / bypass network 2408 may include, but is not limited to, two separate register files, one for low-order 32-bit data and the other for high-order 32-bit data. In at least one embodiment, floating-point register file / bypass network 2410 may include, but is not limited to, 128-bit-wide entries because floating-point instructions typically have operands with widths from 64 bits to 128 bits.

[0413] In at least one embodiment, execution units 2412, 2414, 2416, 2418, 2420, 2422, 2424 may execute instructions. In at least one embodiment, register networks 2408, 2410 store integer and floating-point data operand values for the microinstructions to execute. In at least one embodiment, processor 2400 may include, but is not limited to, any number of execution units 2412, 2414, 2416, 2418, 2420, 2422, 2424 and combinations thereof. In at least one embodiment, floating-point ALU 2422 and floating-point move unit 2424 may execute floating-point, MMX, SIMD, AVX, and SSE or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 2422 may include, but is not limited to, a 64-bit by 64-bit floating-point divider for performing division, square root, and remainder micro-operations. In at least one embodiment, instructions involving floating-point values may be processed with floating-point hardware. In at least one embodiment, ALU operations may be passed to fast ALUs 2416, 2418. In at least one embodiment, fast ALUs 2416, 2418 may execute fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations go to slow ALU 2420 because slow ALU 2420 may include, but is not limited to, integer execution hardware for long-latency type operations such as multipliers, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations may be performed by AGUs 2412, 2414. In at least one embodiment, fast ALU 2416, fast ALU 2418, and slow ALU 2420 may perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2416, fast ALU 2418, and slow ALU 2420 may be implemented to support various data bit sizes including sixteen, thirty-two, 128, 256, etc. In at least one embodiment, floating-point ALU 2422 and floating-point move unit 2424 may be implemented to support a range of operands with various widths of bits, such as supporting 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0414] In at least one embodiment, the micro - operation schedulers 2402, 2404, 2406 dispatch dependent operations before the parent load has completed execution. In at least one embodiment, since micro - operations can be speculatively scheduled and executed in the processor 2400, the processor 2400 may also include logic for handling memory misses. In at least one embodiment, if a data load miss occurs in the data cache, there may be dependent operations running in the pipeline, which leaves the scheduler temporarily without the correct data. In at least one embodiment, a replay mechanism tracks and re - executes instructions that used incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and independent operations may be allowed to complete. In at least one embodiment, the scheduler and the replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences for text - string comparison operations.

[0415] In at least one embodiment, a "register" may refer to an on - board processor storage location that can be used as part of an instruction to identify an operand. In at least one embodiment, registers may be those that can be used from outside the processor (from the programmer's perspective). In at least one embodiment, registers may not be limited to a particular type of circuit. Instead, in at least one embodiment, registers can store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein can be implemented by circuits within the processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, a combination of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, integer registers store 32 - bit integer data. The register file of at least one embodiment also contains eight multimedia SIMD registers for packing data.

[0416] In at least one embodiment, the processor 2400 or each core in the processor 2400 includes one or more prefetchers, one or more fetchers, one or more pre - decoders, one or more decoders for decoding data (e.g., instructions), one or more instruction queues for processing instructions (e.g., instructions corresponding to operations or API calls), one or more μOP caches for storing micro - operations (μOPs), one or more micro - operation (μOP) queues, an in - order execution engine, one or more load buffers, one or more store buffers, one or more re - order buffers, one or more fill buffers, an out - of - order execution engine, one or more ports, one or more shift and / or shifter units, one or more fused multiply - add (FMA) units, one or more load and store units (“LSU”) for performing load / store operations corresponding to loading / storing data (e.g., instructions) to perform operations (e.g., execute an API, API call), one or more matrix multiply - add (MMA) units, and / or one or more shuffle units for performing any of the functions further described herein with respect to the processor 2400. In at least one embodiment, the processor 2400 can access, use, implement, or execute instructions corresponding to calling an API.

[0417] In at least one embodiment, the processor 2400 includes one or more Ultra - Path Interconnects (UPI) (e.g., which are point - to - point processor interconnects); one or more PCIe; one or more accelerators for accelerating computations or operations; and / or one or more memory controllers. In at least one embodiment, the processor 2400 includes a shared last - level cache (LLC) coupled to one or more memory controllers that can allow shared memory access across processor cores.

[0418] In at least one embodiment, the processor 2400 or the cores of the processor 2400 have a mesh architecture, where the processor cores, on-chip caches, memory controllers, and I / O controllers are organized into rows and columns, and at each intersection, they are connected with wires and switches to allow turns. In at least one embodiment, the processor 2400 has one or more higher memory bandwidths (HMB, e.g., HMBe) for storing or caching data in, for example, double data rate 5 synchronous dynamic random access memory (DDR5 SDRAM). In at least one embodiment, one or more components in the processor 2400 are interconnected using Compute Express Link (CXL) interconnects. In at least one embodiment, the memory controller uses the "least recently used" (LRU) method to determine what to store in the cache. In at least one embodiment, the processor 2400 includes one or more PCIe (e.g., PCIe 5.0).

[0419] Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the logic 815 are provided herein in conjunction with Figure 8A and / or [[ID and / or. In at least one embodiment, part or all of the logic 815 can be incorporated into execution block 2411 and other memories or registers shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein can use one or more ALUs shown in execution block 2411. Additionally, weight parameters can be stored in on-chip or off-chip memories and / or registers (shown or not shown), which configure the ALUs of execution block 2411 to perform one or more of the machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0420] In at least one embodiment, the processor 2400 is used to at least partially implement text-based object generation as shown in ​ and / or.

[0421] ​The deep learning application processor 2500 according to at least one embodiment is shown. In at least one embodiment, the deep learning application processor 2500 uses instructions that, if executed by the deep learning application processor 2500, cause the deep learning application processor 2500 to perform some or all of the processes and techniques described throughout this disclosure. In at least one embodiment, the deep learning application processor 2500 is an application specific integrated circuit (ASIC). In at least one embodiment, as a result of executing one or more instructions or both, the application processor 2500 performs matrix multiplication operations or is "hardwired" into the hardware. In at least one embodiment, the deep learning application processor 2500 includes, but is not limited to, processing clusters 2510(1)-2510(12), inter-chip links ("ICL") 2520(1)-2520(12), inter-chip controllers ("ICC") 2530(1)-2530(2), second generation high bandwidth memories ("HBM2") 2540(1)-2540(4), memory controllers ("Mem Ctrlr") 2542(1)-2542(4), high bandwidth memory physical layers ("HBM PHY") 2544(1)-2544(4), management controller central processing units ("management controller CPU") 2550, serial peripheral interfaces, internal integrated circuits, and general purpose input / output blocks ("SPI, I2C, GPIO") 2560, peripheral component interconnect express controllers and direct memory access blocks ("PCIe controller and DMA") 2570, and sixteen-channel peripheral component interconnect express ports ("PCI Express x16") 2580.

[0422] In at least one embodiment, the processing clusters 2510 may perform deep learning operations, including inference or prediction operations based on weight parameters calculated using one or more training techniques, including those described herein. In at least one embodiment, each processing cluster 2510 may include, but is not limited to, any number and type of processors. In at least one embodiment, the deep learning application processor 2500 may include any number and type of processing clusters 2500. In at least one embodiment, the inter-chip link 2520 is bidirectional. In at least one embodiment, the inter-chip link 2520 and the inter-chip controller 2530 enable multiple deep learning application processors 2500 to exchange information, including activation information resulting from executing one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, the deep learning application processor 2500 may include any number (including zero) and type of ICLs 2520 and ICCs 2530.

[0423] In at least one embodiment, the HBM2 2540 provides a total of 32 GB of memory. In at least one embodiment, the HBM2 2540(i) is associated with both a memory controller 2542(i) and an HBM PHY 2544(i), where "i" is any integer. In at least one embodiment, any number of HBM2 2540s can provide any type and amount of high-bandwidth memory and can be associated with any number (including zero) and type of memory controllers 2542 and HBM PHYs 2544. In at least one embodiment, any number and type of blocks implementing any number and type of communication standards can replace SPI, I2C, GPIO 2560, a PCIe controller and DMA 2570, and / or PCIe 2580 in any technically feasible manner.

[0424] Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the logic 815 are provided herein in connection with ​ and / or ​ In at least one embodiment, a deep learning application processor is used to train a machine learning model (such as a neural network) to predict or infer information provided to the deep learning application processor 2500. In at least one embodiment, the deep learning application processor 2500 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the deep learning application processor 2500. In at least one embodiment, the processor 2500 can be used to perform one or more of the neural network use cases described herein.

[0425] In at least one embodiment, the application processor 2500 is used to at least partially implement text-based object generation as shown in ​ FIG.

[0426] ​is a block diagram of a neuromorphic processor 2600 according to at least one embodiment. In at least one embodiment, the neuromorphic processor 2600 may receive one or more inputs from a source external to the neuromorphic processor 2600. In at least one embodiment, these inputs may be transmitted to one or more neurons 2602 within the neuromorphic processor 2600. In at least one embodiment, the neurons 2602 and their components may be implemented using circuitry or logic including one or more arithmetic logic units (ALUs). In at least one embodiment, the neuromorphic processor 2600 may include, but is not limited to, thousands or millions of instances of neurons 2602, but any suitable number of neurons 2602 may be used. In at least one embodiment, each instance of the neuron 2602 may include a neuron input 2604 and a neuron output 2606. In at least one embodiment, the neuron 2602 may generate an output that may be transmitted to inputs of other instances of the neuron 2602. For example, in at least one embodiment, the neuron input 2604 and the neuron output 2606 may be interconnected via a synapse 2608.

[0427] In at least one embodiment, neurons 2602 and synapses 2608 may be interconnected such that the neuromorphic processor 2600 operates to process or analyze information received by the neuromorphic processor 2600. In at least one embodiment, when the input received via neuron input 2604 exceeds a threshold, neuron 2602 may send an output pulse (or “fire” or “spike”). In at least one embodiment, neuron 2602 may sum or integrate the signals received at neuron input 2604. For example, in at least one embodiment, neuron 2602 may be implemented as a leaky integrate-and-fire neuron, where if the sum (referred to as the “membrane potential”) exceeds a threshold, neuron 2602 may use a transfer function such as a sigmoid or threshold function to produce an output (or “fire”). In at least one embodiment, a leaky integrate-and-fire neuron may sum the signals received at neuron input 2604 into a membrane potential and may also apply a decay factor (or leak) to reduce the membrane potential. In at least one embodiment, if a plurality of input signals are received at neuron input 2604 fast enough to exceed the threshold (i.e., before the membrane potential decays too low to fire), then the leaky integrate-and-fire neuron may fire. In at least one embodiment, neuron 2602 may be implemented using circuitry or logic that receives inputs, integrates the inputs into a membrane potential, and decays the membrane potential. In at least one embodiment, the inputs may be averaged, or any other suitable transfer function may be used. Additionally, in at least one embodiment, neuron 2602 may include, but is not limited to, comparator circuitry or logic that produces an output spike at neuron output 2606 when the result of applying a transfer function to neuron input 2604 exceeds a threshold. In at least one embodiment, once neuron 2602 fires, it may ignore previously rece...

Claims

1. A processor, comprising: one or more circuits configured to use one or more first neural networks to adjust one or more three-dimensional (3D) models of one or more objects to be adjusted, at least in part based on a text using one or more second neural networks, to generate the one or more 3D models.

2. The processor according to claim 1, wherein the one or more first neural networks are trained at least in part based on an indication generated by the one or more second neural networks as to whether the adjusted 3D model matches the text.

3. The processor according to claim 1, wherein the one or more second neural networks include a diffusion model.

4. The processor according to claim 1, wherein the one or more first neural networks include a convolutional neural network.

5. The processor according to claim 1, wherein the one or more first neural networks are trained to identify features of the one or more 3D models that can be adjusted such that the adjusted 3D model matches the text.

6. The processor according to claim 1, wherein the one or more first neural networks are configured to adjust one or more textures of the one or more 3D models.

7. The processor according to claim 1, wherein the one or more first neural networks are configured to adjust one or more meshes of the one or more 3D models.

8. A method, comprising: using one or more first neural networks to adjust one or more three-dimensional (3D) models of one or more objects to be adjusted, at least in part based on a text using one or more second neural networks, to generate the one or more 3D models.

9. The method according to claim 8, wherein the one or more first neural networks are trained at least in part based on an indication generated by the one or more second neural networks as to whether the adjusted 3D model matches the text.

10. The method according to claim 8, wherein the one or more second neural networks include a diffusion model.

11. The method according to claim 8, wherein the one or more first neural networks include a convolutional neural network.

12. The method according to claim 8, wherein the one or more first neural networks are trained to identify features of the one or more 3D models that can be adjusted such that the adjusted 3D model matches the text.

13. The method according to claim 8, wherein the one or more first neural networks are configured to adjust one or more textures of the one or more 3D models.

14. The method according to claim 8, wherein the one or more first neural networks are configured to adjust one or more meshes of the one or more 3D models.

15. A system, comprising: One or more processors, the one or more processors being configured to use one or more first neural networks to adjust one or more three-dimensional (3D) models of one or more objects to be adjusted, at least in part based on text using one or more second neural networks, to adjust the one or more 3D models.

16. The system according to claim 15, wherein the one or more first neural networks are trained at least in part based on an indication generated by the one or more second neural networks as to whether the adjusted 3D model matches the text.

17. The system according to claim 15, wherein the one or more second neural networks include a diffusion model.

18. The system according to claim 15, wherein the one or more first neural networks include a convolutional neural network.

19. The system according to claim 15, wherein the one or more first neural networks are configured to adjust one or more textures of the one or more 3D models.

20. The system according to claim 15, wherein the one or more first neural networks are configured to adjust one or more meshes of the one or more 3D models.

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