Gate drive circuit, gate drive circuit detection method and display panel

Abstract

The present application belongs to the field of display drive technology, and specifically relates to a gate drive circuit, a gate drive circuit detection method and a display panel, wherein the gate drive circuit includes multiple clock signal lines and N cascaded drive circuit modules; each drive circuit module includes a circuit unit, and the circuit unit includes at least a control node and an output transistor; each drive circuit module also includes a node lead line, and the first end of the node lead line is electrically connected to the control node; the node lead line is configured to transmit an external test voltage to the control node during a test phase to control the output transistor to be in an off state; the present application realizes separate control of the timing voltage of the control node, and can detect the source-drain short circuit anomaly of the output transistor during the test phase, thereby improving the comprehensiveness and accuracy of the detection of GDL products during the test phase, preventing abnormal products from flowing into the back-end process, and improving the yield and cost control of the back-end products.

Description

Technical Field

[0001] The present disclosure belongs to the field of display drive technology, and particularly relates to a gate drive circuit, a gate drive circuit detection method, and a display panel. Background Art

[0002] Currently, in the ATT (Array Test Technology) stage of GDL (Gate Driver on Array), defect detection for GDL mainly adopts the principle of "repairable ones are repaired promptly, and unrepairable ones are scrapped promptly." This principle can improve the back-end yield and reduce production costs.

[0003] However, with the current GDL circuit design, the source-drain short-circuit anomaly of the GDL's internal output transistor cannot be effectively detected during the ATT stage, causing GDL products with potential defects to flow into the back-end process, affecting the product's back-end yield and cost control.

[0004] Therefore, how to detect the source-drain short circuit anomaly of the output transistor inside the GDL is a problem that needs to be solved urgently. Summary of the Invention

[0005] The present application provides a gate drive circuit, a gate drive circuit detection method and a display panel, which solve the problem of detecting source-drain short circuit anomalies of output transistors inside a GDL, thereby improving the accuracy of gate drive circuit detection during the test phase.

[0006] In a first aspect, the present application provides a gate drive circuit, which includes: multiple clock signal lines and N cascaded drive circuit modules; each drive circuit module includes a circuit unit, the circuit unit includes at least a control node and an output transistor, the control end of the output transistor is electrically connected to the control node, the first end of the output transistor is electrically connected to the corresponding clock signal line, and the second end of the output transistor is electrically connected to the corresponding scan line; the output transistor is configured to output a gate drive signal to the corresponding scan line according to the clock signal on the clock signal line under the action of the operating voltage on the control node; each drive circuit module also includes a node lead line, the first end of the node lead line is electrically connected to the control node; the node lead line is configured to transmit an external test voltage to the control node during a test phase to control the output transistor to be in an off state.

[0007] Optionally, the second end of the node lead is defined as a first test connection end, and the first test connection end is configured to be electrically connected to a device that outputs the external test voltage during a test phase.

[0008] Optionally, the gate drive circuit also includes: a first detection line, one end of the first detection line is defined as a second test connection terminal, and the second test connection terminal is configured to be electrically connected to a device that outputs a control voltage during a test phase; a second detection line, one end of the second detection line is defined as a third test connection terminal, and the third test connection terminal is configured to be electrically connected to a device that outputs the external test voltage during a test phase; each drive circuit module also includes a first control transistor, the control end of the first control transistor is electrically connected to the first detection line, the first end of the first control transistor is electrically connected to the second end of the node lead line, and the second end of the first control transistor is electrically connected to the second detection line.

[0009] Optionally, the gate drive circuit further includes: a first detection line, one end of the first detection line is defined as a second test connection end, and the second test connection end is configured to be electrically connected to a device that outputs a control voltage during a test phase; each drive circuit module further includes: a first control transistor, the control end of the first control transistor is electrically connected to the first detection line, and the first end of the first control transistor is electrically connected to the second end of the node lead-out line; a second control transistor, the control end of the second control transistor is electrically connected to the first detection line, and the first end of the second control transistor is connected to the second end of the first control transistor; a third detection line, the first end of the third detection line is connected to the second end of the first control transistor of the current-stage drive circuit module, and the second end of the third detection line is connected to the second end of the second control transistor of the previous-stage drive circuit module connected; or the first end of the third detection line is connected to the second end of the second control transistor of the current-stage driving circuit module, and the second end of the third detection line is connected to the second end of the first control transistor of the next-stage driving circuit module; wherein, when the second end of the third detection line is connected to the second end of the second control transistor of the previous-stage driving circuit module, the second end of the third detection line of the first-stage driving circuit module is defined as a third test connection end, and the third test connection end is configured to be electrically connected to the device that outputs the external test voltage during the test phase; when the second end of the third detection line is connected to the second end of the first control transistor of the next-stage driving circuit module, the second end of the third detection line of the N-stage driving circuit module is defined as a third test connection end, and the third test connection end is configured to be electrically connected to the device that outputs the external test voltage during the test phase.

[0010] Optionally, the gate drive circuit further includes: a pull-down control line, the pull-down control line being configured to be electrically connected to a device that outputs the control voltage during a test phase; and one end of the first detection line being electrically connected to the pull-down control line.

[0011] Optionally, the multiple clock signal lines extend along the cascade direction of N driving circuit modules, the node lead lines are arranged perpendicular to the multiple clock signal lines, and the first detection line and the second detection line are respectively arranged parallel to the clock signal lines.

[0012] In a second aspect, the present application provides a gate drive circuit detection method, which is applied to a gate drive circuit. In a test phase, the detection method includes: using a node lead line to output an external test voltage to a control node to put the output transistor in an off state; using a clock signal line to output a drive voltage to the first end of the output transistor; and detecting the relationship between the output voltage of the second end of the output transistor and the drive voltage to determine the short-circuit state of the output transistor.

[0013] Optionally, when the gate drive circuit includes a first detection line and a second detection line, the use of a node lead line to output an external test voltage to a control node includes: using the first detection line to receive a control voltage so that the first control transistor is in an on state; and using the second detection line to receive the external test voltage so that the node lead line outputs the external test voltage to the control node.

[0014] Optionally, when the gate drive circuit includes a first detection line and a third detection line, the use of a node lead line to output an external test voltage to a control node includes: using the first detection line to receive a control voltage so that the first control transistor and the second control transistor are in an open state; and using the third detection line to receive the external test voltage so that the node lead line outputs the external test voltage to the control node.

[0015] In a third aspect, the present application provides a display panel comprising a display area and a non-display area, wherein the display area comprises a plurality of scan lines; the non-display area comprises a gate drive circuit, and a drive output end of a circuit unit in the gate drive circuit is electrically connected to at least one scan line.

[0016] The technical solution provided by this application has at least the following beneficial effects:

[0017] The present application uses node lead wires to connect the control node lead wires encapsulated inside the circuit unit to the outside of the circuit unit, and then uses an external detection device to input a corresponding external test voltage to the node lead wires, thereby achieving independent control of the timing voltage of the control node. The source-drain short circuit anomaly of the output transistor can be detected during the test phase, thereby improving the comprehensiveness and accuracy of the detection of GDL products during the test phase, preventing abnormal products from flowing into the back-end process, and improving the yield and cost control of the back-end products. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0019] Figure 1 Shown is a structural schematic diagram of the first gate drive circuit provided in an embodiment of the present application.

[0020] Figure 2 Shown is a circuit schematic diagram of a circuit unit provided in an embodiment of the present application.

[0021] Figure 3 Shown is a schematic diagram of an arrangement of multiple display panels provided in an embodiment of the present application.

[0022] Figure 4 Shown is a front schematic diagram of a display panel provided in an embodiment of the present application.

[0023] Figure 5 The figure shows a timing diagram of a normal detection of a circuit unit provided by an embodiment of the present application.

[0024] Figure 6 Shown is a schematic diagram of the design of an output transistor provided in an embodiment of the present application.

[0025] Figure 7 The figure shows a timing diagram of short circuit abnormality detection provided by an embodiment of the present application.

[0026] Figure 8 Shown is a schematic diagram of a gate drive circuit design provided in an embodiment of the present application.

[0027] Figure 9 Shown is a structural schematic diagram of a second gate drive circuit provided in an embodiment of the present application.

[0028] Figure 10 Shown is a schematic diagram of another gate drive circuit design provided in an embodiment of the present application.

[0029] Figure 11 Shown is a structural schematic diagram of a third gate drive circuit provided in an embodiment of the present application.

[0030] Figure 12 FIG. 1 is a schematic diagram showing another arrangement of multiple display panels provided in an embodiment of the present application.

[0031] Figure 13 Shown is a front schematic diagram of another display panel provided in an embodiment of the present application.

[0032] Figure 14 Shown is a structural schematic diagram of the fourth gate drive circuit provided in an embodiment of the present application.

[0033] Figure 15 Shown is a structural schematic diagram of the fifth gate drive circuit provided in an embodiment of the present application.

[0034] Figure 16 FIG2 is a flow chart of a gate drive circuit detection method provided in an embodiment of the present application.

[0035] Description of reference numerals:

[0036] 100, gate drive circuit; 200, scan line; 310, input signal terminal in the gate drive circuit; 320, connection terminal for external detection device; 330, through hole;

[0037] 110, clock signal line; 120, drive circuit module; 121, circuit unit; 1211, precharge unit; 1212, pull-down control unit; 1213, reset unit; 122, node lead line; 123, third detection line; 130, first detection line; 140, second detection line;

[0038] Q, control node; C, storage capacitor; T0, output transistor; T1, first control transistor; T2, second control transistor; Pad1, first test connection terminal; Pad2, second test connection terminal; Pad3, third test connection terminal; LC, pull-down control line; VGL, cathode signal line; STV, reset signal line. DETAILED DESCRIPTION

[0039] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art.

[0040] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner.In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, it will be appreciated by those skilled in the art that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps etc. can be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0041] The present application is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limiting the present application.

[0042] In a first aspect, the present application provides a gate drive circuit, specifically including the following embodiments:

[0043] Figure 1 FIG. 1 is a schematic structural diagram of a first gate drive circuit provided in an embodiment of the present application; FIG. Figure 1 As shown, the gate drive circuit 100 includes a plurality of clock signal lines 110, and each clock signal line 110 outputs a clock signal of a different timing. Figure 1 There are four clock signal lines, corresponding to CK1, CK2, CK3 and CK4 respectively, and the output timing of each clock signal line is different.

[0044] The gate drive circuit 100 of this embodiment includes N cascaded drive circuit modules 120, each of which includes a circuit unit 121. The circuit unit 121 includes at least a control node Q and an output transistor T0. The control end of the output transistor T0 is electrically connected to the control node Q, the first end of the output transistor T0 is electrically connected to the corresponding clock signal line 110, and the second end of the output transistor T0 is electrically connected to the corresponding scan line 200. The output transistor T0 is configured to output a gate drive signal to the corresponding scan line 200 according to the clock signal on the clock signal line 110 under the action of the operating voltage on the control node Q.

[0045] It should be noted that the control node Q, commonly known as the Q point, is used to control the on and off state of the output transistor T0. When the output transistor T0 is an N-type MOS transistor, when the voltage on the control node Q is high, the output transistor T0 turns on, outputting the clock signal on the clock signal line 110 as a gate drive signal to the scan line 200 within the panel, thereby turning on the transistor within the panel that controls pixel charging. Conversely, when the voltage on the control node Q is low, the output transistor T0 turns off, ceasing to output the gate drive signal. Furthermore, when the output transistor T0 is a P-type MOS transistor, its operating principle is opposite to that of an N-type MOS transistor and will not be further described here. The operating voltage in this embodiment refers to the voltage that can turn on the output transistor during the normal scanning phase.

[0046] It is worth noting that the circuit unit 121 includes not only the control node Q and the output transistor T0, but also Figure 2The pre-charge unit 1211, pull-down control unit 1212, storage capacitor C and reset unit 1213 are shown; for the n-th level circuit unit, the pre-charge unit 1211 is used to pre-charge its control node Q through the gate drive signal output by the n-4-th level circuit unit, so that the output transistor T0 is turned on in advance before the arrival of the n-th level clock signal; the pull-down control unit 1212 is used to pull down and maintain the voltage on the control node Q and the second end of the output transistor T0 through the pull-down control signal output on the pull-down control line LC, that is, noise reduction processing; the reset unit 1213 is used to reset the voltage on the control node Q through the reset signal on the reset signal line STV; the storage capacitor C is used to store the voltage on the control node Q. Figure 2 This is just an example of a specific circuit structure of the circuit unit 121 . As long as the circuit unit 121 includes the control node Q and the output transistor T0 , it is applicable to the present application.

[0047] In addition, from Figure 2 As can be seen from the circuit structure, the gate driving circuit 100 not only includes a plurality of clock signal lines 110, but also includes at least a pull-down control line LC, a reset signal line STV and a cathode signal line VGL.

[0048] Figure 3 FIG. 1 is a schematic diagram showing an arrangement of multiple display panels according to an embodiment of the present application; FIG. Figure 3 As shown, four display panels of the same size are prepared on a glass panel at the same time, each display panel is Figure 4 The double-ended drive shown, Figure 3 The reference numeral 310 in the figure represents the input signal terminal in the gate drive circuit 100, such as the clock signal line 110, the pull-down control line LC, the reset signal line STV and the cathode signal line VGL, and the reference numeral 320 represents the connection terminal of the external detection device. The connection terminal of the external detection device is electrically connected to the input signal terminal of the gate drive circuit 100. The test voltage can be sent to the display gate drive circuit 100 through the external detection device, so as to detect the abnormality of the display panel in real time, so as to achieve the purpose of timely repair of the repairable ones and timely scrapping of the unrepairable ones.

[0049] Here with Figure 2 Taking the GDL circuit structure as an example, the current detection method for the gate drive circuit 100 in the ATT stage is:

[0050] (1) When all input signals of the circuit unit 121 are set to high potential, the potential of the control node Q in the circuit unit 121 is also high, and the gate drive signals output by all circuit units 121 are all high potential, and all pixel rows in the plane are turned on at the same time.

[0051] (2) All input signals in the circuit unit 121 are kept in normal timing, and all pixel rows in the plane are turned on row by row. The waveform of the Q point is as follows: Figure 5 As shown; among them, Figure 5 In the figure, STV represents the waveform on the reset signal line STV, which is also the frame start signal; G1 represents the output waveform of the first-stage circuit unit 121, G2 represents the output waveform of the second-stage circuit unit 121, Q1 represents the Q-point waveform of the first-stage circuit unit 121, and Q2 represents the Q-point waveform of the second-stage circuit unit 121.

[0052] (3) When all input signals of the circuit unit 121 are set to low potential, no gate drive signal is output and all pixel rows in the plane are turned off.

[0053] However, the above three detection methods cannot detect whether there is a short circuit abnormality at the source and drain of the output transistor T0.

[0054] like Figure 6 As shown, 6a is a normal schematic diagram of the output transistor T0, and 6b is an abnormal schematic diagram of the output transistor T0 with a source-drain short circuit. As can be seen from 6b, no matter what voltage the gate of the output transistor T0 is at, the source and drain are both turned on. In order to detect whether there is a short circuit abnormality in the source and drain of the output transistor T0, the gate voltage of the output transistor T0 is set to the off voltage, and whether the drain voltage changes with the change of the source voltage is detected. In other words, when the output transistor T0 is in the off state, the source-drain short circuit abnormality can be detected by detecting whether there is a pixel row open in the detection plane.

[0055] The inventors of this application have found that by individually controlling the timing of the control node Q in the circuit unit 121, the source-drain short circuit abnormality of the output transistor T0 can be detected during the test phase. Specifically:

[0056] like Figure 1 As shown, each driving circuit module 120 also includes a node lead line 122, a first end of which is electrically connected to the control node Q; the node lead line 122 is configured to transmit an external test voltage to the control node Q during the test phase to control the output transistor T0 to be in an off state.

[0057] In this embodiment, when the second end of the node lead line 122 is used as the first test connection terminal Pad1, the first test connection terminal Pad1 is configured to be electrically connected to a device that outputs an external test voltage during the test phase; wherein the device that outputs an external test voltage can be an external detection device directly connected to the first test connection terminal Pad1.

[0058] It should be noted that, in this embodiment, the control node Q inside the circuit unit 121 is led out to the outside of the circuit unit through the node lead line 122, and the timing of the control node Q is independently controlled by the node lead line 122, so that the source-drain short circuit abnormality of the output transistor T0 can be detected during the test phase. The specific detection process is as follows:

[0059] (1) In the ATT phase, the second end of each node lead 122 is used as the first test connection terminal Pad1, and the external detection device is directly electrically connected to the first test connection terminal Pad1. The external test voltage output by the external detection device is a low level to the first test connection terminal Pad1, and then the low level is output to the control node Q through the node lead 122, thereby turning off the output transistor T0.

[0060] (2) At the same time, the clock signal line 110 corresponding to the circuit unit 121 is controlled to output a driving voltage; if it is detected that the pixel row in the plane is lit, it means that the source and drain of the output transistor T0 in the circuit unit 121 have a short circuit abnormality; if it is detected that the pixel row in the plane is not lit, it means that the source and drain of the output transistor T0 in the circuit unit 121 do not have a short circuit abnormality; the specific timing is as follows Figure 7 As shown, Figure 7 CK in FIG. 1 represents a waveform on the clock signal line 110 , Q represents a waveform on the control node Q, and short-circuit output represents an output waveform when a short-circuit abnormality occurs between the source and drain of the output transistor T0 .

[0061] It should also be noted that the above detection process only describes whether the source and drain of the output transistor T0 are short-circuited. Other abnormality detection of the circuit unit 121 and abnormality detection of the in-plane scan line 200 and data line can be performed normally according to relevant technologies and will not be repeated here. In addition, when checking whether the in-plane pixel row is lit, it is necessary to simultaneously input data signals to all column data lines.

[0062] In addition, in this embodiment, the level type of the external test voltage is determined by the type of the output transistor T0. If the output transistor T0 is an N-type MOS tube, the external test voltage is a low level. If the output transistor T0 is a P-type MOS tube, the external test voltage is a high level. Similarly, the level type of the driving voltage is determined by the type of the control transistor in the panel that controls the opening and closing of the scan line 200. If the control transistor in the panel is an N-type MOS tube, the driving voltage is a high level. If the control transistor is a P-type MOS tube, the driving voltage is a low level.

[0063] It should be noted that when detecting the source-drain short circuit of the output transistor T0 through the node lead 122 during the test phase, one or more circuit units 121 may be detected simultaneously, and adaptive compatibility may be performed according to the connection pins of the external detection device.

[0064] In addition, the wiring method of the node lead wire 122 of this embodiment can be led out along the longitudinal arrangement of the circuit unit 121 (i.e., vertical arrangement or approximately vertical arrangement), or can be led out perpendicular to the longitudinal arrangement of the circuit unit 121 (i.e., horizontal arrangement or approximately horizontal arrangement). Since the vertical arrangement of the node lead wire 122 will increase the length of the lead wire and the complexity of the cross-line, it is preferred to adopt a horizontal arrangement, such as Figure 8 As shown in the design diagram, the circuit unit 121 includes not only the control node Q and the output transistor T0, but also other reset transistors, pre-charge transistors and pull-down control transistors, which will not be described in detail here.

[0065] On the left side of the circuit unit 121, multiple clock signal lines 110, pull-down control lines LC, cathode signal lines VGL, and reset signal lines STV are vertically arranged. The node lead lines 122 corresponding to each circuit unit 121 are respectively arranged in different layers and cross with the clock signal lines 110, pull-down control lines LC, cathode signal lines VGL, and reset signal lines STV. In other words, the node lead lines 122 intersect with the clock signal lines 110 but are not connected. Figure 8 The multiple clock signal lines 110, the pull-down control line LC, the cathode signal line VGL, the reset signal line STV and the gate of the transistor are designed in the same metal layer M1, and the node lead line 122 and the source and drain of the transistor are designed in another metal layer M2. If the metal layer M1 and the metal layer M2 are to be turned on, it can be done by Figure 8 The through holes 330 in the circuit are electrically connected.

[0066] Furthermore, in order to reduce the coupling effect between the node lead line 122 and other metal lines, this embodiment can avoid it by reducing the wiring width of the node lead line 122; in addition, since the node lead line 122 is only used when the output transistor T0 is individually tested during the test phase, and the input is also a low potential, it will hardly affect the normal operation of other circuits in the display panel.

[0067] It can be seen from this that the present application uses the node lead line 122 to lead the control node Q encapsulated inside the circuit unit 121 to the outside of the circuit unit, and then inputs the corresponding voltage to the node lead line 122 through an external detection device, so as to achieve independent control of the timing voltage of the control node Q, and can detect the source-drain short circuit anomaly of the output transistor T0 during the test phase, thereby improving the comprehensiveness and accuracy of the detection of the GDL product during the test phase, avoiding abnormal products from flowing into the back-end process, and improving the yield and cost control of the back-end products.

[0068] During the invention process, the inventors of the present application discovered that there are too many first test connection terminals Pad1 in the above embodiment, and the number that can be detected simultaneously by the external detection device is limited, resulting in a problem of low detection efficiency.

[0069] In order to solve the above-mentioned problem of low detection efficiency, the present application provides another gate driving circuit 100, which specifically includes the following embodiments:

[0070] Figure 9 FIG. 1 is a schematic structural diagram of a second gate drive circuit 100 provided in an embodiment of the present application; Figure 9 As shown, in Figure 1 On the basis of this, the gate drive circuit 100 also includes a first detection line 130 and a second detection line 140; wherein, one end of the first detection line 130 is defined as a second test connection terminal Pad2, and the second test connection terminal Pad2 is configured to be electrically connected to a device that outputs a control voltage during a test phase; one end of the second detection line 140 is defined as a third test connection terminal Pad3, and the third test connection terminal Pad2 is configured to be electrically connected to a device that outputs an external test voltage during a test phase.

[0071] In addition, each driving circuit module 120 also includes a first control transistor T1, the control end of the first control transistor T1 is electrically connected to the first detection line 130, the first end of the first control transistor T1 is electrically connected to the second end of the node lead line 122, and the second end of the first control transistor T1 is electrically connected to the second detection line 140.

[0072] It should be noted that, in this embodiment, the voltage on the control node Q is individually controlled so that the source-drain detection result of the output transistor T0 is detected in the test phase, which specifically includes the following steps:

[0073] (1) During the test phase, the external detection device outputs a control voltage to the second test connection terminal Pad2, turns on the first control transistor T1 through the first detection line 130, and electrically connects the second end of the node lead line 122 to the second detection line 140; that is, the control voltage is a turn-on signal of the first control transistor T1. When the first control transistor T1 is turned on, each node lead line 122 is electrically connected to the second detection line 140. Since one end of the node lead line 122 is connected to the control node Q and the other end of the node lead line 122 is connected to the second detection line 140, it is equivalent to that the control node Q of each circuit unit 121 is connected to the second detection line 140.

[0074] (2) During the test phase, the external detection device outputs an external test voltage to the third test connection terminal Pad3, and outputs the external test voltage to the control node Q through the second detection line 140 and the node lead line 122, thereby turning off the output transistor T0; the external test voltage on the second detection line 140 can simultaneously turn off the output transistors T0 in all circuit units 121.

[0075] (3) At the same time, the external detection device controls the output of a driving voltage that can turn on the scanning line 200 on each clock signal line 110; when it is detected that there is a pixel row that is lit in the display panel, it means that the second end of the output transistor T0 in the corresponding row also outputs the driving voltage, that is, the source-drain detection result of the output transistor T0 is abnormal; if the pixel row in the display panel is not lit, it means that the second end of the corresponding output transistor T0 has no signal output, that is, the source-drain detection result of the output transistor T0 is normal.

[0076] (4) In the non-test phase, there is no signal output on the first detection line 130 and the second detection line 140, and all the first control transistors T1 are in the off state, thereby avoiding the short circuit problem between the control nodes Q.

[0077] It can be seen from this that this embodiment can achieve the purpose of simultaneously detecting the source and drain of all output transistors T0 by only using two detection lines, which greatly improves the detection efficiency. Figure 1 and Figure 9 From the comparison, we can see that Figure 1 N first test connection terminals Pad1, Figure 2 Only one second test connection terminal Pad2 and one third test connection terminal Pad3 (equivalent to two test connection terminals) are required. This embodiment greatly reduces the demand for test connection terminals, while improving the detection efficiency and reducing the demand for external detection devices.

[0078] In this embodiment, Figure 9 The design diagram of the gate drive circuit is shown in Figure 10 As shown, Figure 10 The first control transistor T1 is only used as an example. The gate of the first control transistor T1 and the first detection line 130 belong to the same metal layer, and the source and drain of the first control transistor T1 and the second detection line 140 belong to another metal layer.

[0079] like Figure 10 As shown, in this embodiment, multiple clock signal lines 110 extend along the cascade direction of N driving circuit modules, the node lead lines 122 are arranged perpendicularly or approximately perpendicularly to the multiple clock signal lines 110, and the first detection line 130 and the second detection line 140 are respectively arranged parallel or approximately parallel to the clock signal lines 110.

[0080] In order to solve the above-mentioned problem of low detection efficiency, the present application also provides another gate drive circuit, which specifically includes the following embodiments:

[0081] Figure 11 FIG. 1 is a schematic structural diagram of a third gate drive circuit provided in an embodiment of the present application; FIG. Figure 11 As shown, in Figure 1 On the basis of this, the gate drive circuit 100 further includes: a first detection line 130, one end of which is defined as a second test connection terminal Pad2, and the second test connection terminal Pad2 is configured to be electrically connected to a device that outputs a control voltage during a test phase.

[0082] In addition, each driving circuit module 120 also includes a first control transistor T1, a second control transistor T2 and a third detection line 123; the control end of the first control transistor T1 is electrically connected to the first detection line 130, and the first end of the first control transistor T1 is electrically connected to the second end of the node lead line 122; the control end of the second control transistor T2 is electrically connected to the first detection line 130, and the first end of the second control transistor T2 is connected to the second end of the first control transistor T1; the first end of the third detection line 123 is connected to the second end of the first control transistor T1 of the current-stage driving circuit module, and the second end of the third detection line 123 is connected to the second end of the second control transistor T2 of the previous-stage driving circuit module; or the first end of the third detection line 123 is connected to the second end of the second control transistor T2 of the current-stage driving circuit module, and the second end of the third detection line 123 is connected to the second end of the first control transistor T1 of the next-stage driving circuit module.

[0083] In this embodiment, when the second end of the third detection line 123 is connected to the second end of the second control transistor T2 of the previous-stage driving circuit module, the second end of the third detection line 123 of the first-stage driving circuit module is defined as the third test connection terminal Pad3, and the third test connection terminal Pad3 is configured to be electrically connected to a device that outputs an external test voltage during the test phase.

[0084] When the second end of the third detection line 123 is connected to the second end of the first control transistor T1 of the next-stage driving circuit module, the second end of the third detection line 123 of the N-stage driving circuit module is defined as the third test connection terminal Pad3, and the third test connection terminal Pad3 is configured to be electrically connected to a device that outputs an external test voltage during the test phase.

[0085] It should be noted that, in this embodiment, the voltage on the control node Q is individually controlled so that the source-drain detection result of the output transistor T0 is detected in the test phase, which specifically includes the following steps:

[0086] (1) During the test phase, the external detection device outputs a control voltage to the second test connection terminal Pad2, and simultaneously turns on all the first control transistors T1 and the second control transistors T2 through the first detection line 130, so that the second ends of the node lead lines 122 are electrically connected to the corresponding third detection lines 123, and all the third detection lines 123 are also electrically connected; that is, the control voltage is the turn-on voltage of the first control transistor T1 and the second control transistor T2. When the first control transistor T1 is turned on, each node lead line 122 is electrically connected to the third detection line 123. Since one end of the node lead line 122 is connected to the control node Q and the other end of the node lead line 122 is connected to the third detection line 123, it is equivalent to that the control node Q of each circuit unit 121 is connected to the third detection line 123; and since the turned-on second control transistor T2 connects all the third detection lines 123, the control node Q of each circuit unit 121 is equivalent to being connected to the third test connection terminal Pad3.

[0087] (2) During the test phase, the external detection device outputs an external test voltage to the third test connection terminal Pad3, and outputs the external test voltage to the control node Q through the third detection line 123 and the node lead line 122, thereby turning off the output transistor T0; that is, the external test voltage on the third detection line 123 can simultaneously turn off the output transistors T0 in all circuit units 121.

[0088] (3) At the same time, the external detection device controls the output of a driving voltage that can turn on the scanning line 200 on each clock signal line 110; when it is detected that there is a pixel row that is lit in the display panel, it means that the second end of the output transistor T0 in the corresponding row also outputs the driving voltage, that is, the source-drain detection result of the output transistor T0 is abnormal; if the pixel row in the display panel is not lit, it means that the second end of the corresponding output transistor T0 has no signal output, that is, the source-drain detection result of the output transistor T0 is normal.

[0089] (4) In the non-test phase, there is no signal output on the first detection line 130 and the second detection line 140, and all the first control transistors T1 and the second control transistors T2 are in the off state, thereby avoiding the short circuit problem between the control nodes Q.

[0090] In summary, this embodiment can achieve the purpose of simultaneously detecting the source and drain of all output transistors T0, greatly improving the detection efficiency; in addition, Figure 1 and Figure 11 By comparison, we can see that Figure 1 N first test connection terminals Pad1, Figure 2 Only one second test connection terminal Pad2 and one third test connection terminal Pad3 (equivalent to two test connection terminals) are required. This embodiment greatly reduces the demand for test connection terminals, while improving the detection efficiency and reducing the demand for external detection devices.

[0091] from Figure 9 and Figure 11 From the comparison, we can see that the two solutions are parallel solutions with the same technical concept. The difference between the two solutions is: Figure 9 The second detection line 140 is originally a complete wire. Figure 11 The multiple segments of the third detection line are connected in series into a complete wire through N second control transistors T2; the difference in technical effects is: Figure 9 The second detection line 140 is connected to the control node Q in all circuit units through the first control transistor T1. Although the transistor controlled by the first detection line 130 is turned on and off, the timing of inputting voltage to the control node Q in different circuit units is different due to the difference in the working timing of the GDL between different circuit units. As a result, the change of the Q-point voltage may affect the upper and lower adjacent GDLs, causing the fluctuation of the Q-point potential and affecting the operation of the GDL during normal display. Therefore, Figure 11 By adding the second control transistor T2 between the multiple third detection lines, the influence of the voltage on the GDL circuit can be further blocked.

[0092] refer to Figure 12 As shown, Figure 3 Compared to the previous example, two lines are added to the display panel, corresponding to Figure 9 The first detection line 130 and the second detection line 140 can also correspond to Figure 11 The first detection line 130 and the third detection line 123; wherein, Figure 12 The corresponding third detection line 123 is only the third detection line 123 in the first stage driving circuit module 120 or the Nth stage driving circuit module 120; Figure 13 As shown, Figure 4In comparison, two lines are added on both sides of the display panel, corresponding to Figure 9 The first detection line 130 and the second detection line 140; wherein, Figure 13 The first control transistor T1 and the second control transistor T2 are not shown.

[0093] In another embodiment, the gate driving circuit 100 further includes: a pull-down control line LC configured to be electrically connected to a device outputting a control voltage during a test phase; and one end of the first detection line 130 is electrically connected to the pull-down control line LC.

[0094] It should be noted that in order to further reduce the number of test signals output by the external detection device, Figure 9 and Figure 11 One end of the first detection line in the gate drive circuit is electrically connected to the original pull-down control line, so that in the test phase, the control voltage is output to the first detection line 130 through the pull-down control line LC. Figure 14 and Figure 15 As shown; the gate drive circuit usually includes one or two pull-down control lines LC. On this basis, this embodiment does not need to add a second test connection terminal, and only needs a third test connection terminal, which further reduces the functional requirements of the external detection device and does not have any redundant signals and GDL lines overlapping to affect the normal operation performance of the GDL.

[0095] In a second aspect, the present application provides a gate drive circuit detection method, which specifically includes the following embodiments:

[0096] Figure 16 FIG. 1 is a flow chart of a gate drive circuit detection method provided in an embodiment of the present application. The detection method is applied to the gate drive circuit shown in the above embodiment, and specifically includes the following steps in the test phase:

[0097] Step S100: outputting an external test voltage to the control node via a node lead line to turn off the output transistor.

[0098] Step S200: outputting a driving voltage to the first terminal of the output transistor via the clock signal line.

[0099] Step S300 : detecting a relationship between an output voltage at a second terminal of the output transistor and a driving voltage to determine a short-circuit state of the output transistor.

[0100] Furthermore, when the gate drive circuit includes a first detection line and a second detection line, the node lead line is used to output the external test voltage to the control node, including: using the first detection line to receive the control voltage so that the first control transistor is in an open state; using the second detection line to receive the external test voltage so that the node lead line outputs the external test voltage to the control node.

[0101] Furthermore, when the gate drive circuit includes a first detection line and a third detection line, the node lead line is used to output the external test voltage to the control node, including: using the first detection line to receive the control voltage so that the first control transistor and the second control transistor are in an open state; using the third detection line to receive the external test voltage so that the node lead line outputs the external test voltage to the control node.

[0102] It should be noted that the specific principle of the gate drive circuit detection method is the same as that of the above embodiment and will not be repeated here.

[0103] In a third aspect, the present application provides a display panel comprising a display area and a non-display area, the display area comprising a plurality of scan lines; the non-display area comprising the gate drive circuit described in the above embodiment, the drive output end of the circuit unit in the gate drive circuit being electrically connected to at least one scan line.

[0104] Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first," "second," or "third" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0105] In the description of this specification, the reference terms "some embodiments", "exemplarily", etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0106] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent application.

Claims

1. A gate drive circuit, characterized in that: The gate drive circuit includes: Multiple clock signal lines and N cascaded drive circuit modules; Each driving circuit module includes a circuit unit, the circuit unit including at least a control node and an output transistor, the control terminal of the output transistor being electrically connected to the control node, the first terminal of the output transistor being electrically connected to the corresponding clock signal line, and the second terminal of the output transistor being electrically connected to the corresponding scan line; the output transistor being configured to output a gate drive signal to the corresponding scan line according to a clock signal on the clock signal line under the action of an operating voltage on the control node; Each driving circuit module further includes a node lead line, a first end of which is electrically connected to the control node; the node lead line is configured to transmit an external test voltage to the control node during a test phase to control the output transistor to be in an off state; The gate drive circuit further includes: a first detection line, one end of the first detection line is defined as a second test connection end, and the second test connection end is configured to be electrically connected to a device that outputs a control voltage during a test phase; each drive circuit module further includes: a first control transistor, wherein a control terminal of the first control transistor is electrically connected to the first detection line, and a first terminal of the first control transistor is electrically connected to the second terminal of the node lead line; a second control transistor, wherein a control terminal of the second control transistor is electrically connected to the first detection line, and a first terminal of the second control transistor is connected to a second terminal of the first control transistor; a third detection line, wherein a first end of the third detection line is connected to the second end of the first control transistor of the current-stage driving circuit module, and a second end of the third detection line is connected to the second end of the second control transistor of the previous-stage driving circuit module; or a first end of the third detection line is connected to the second end of the second control transistor of the current-stage driving circuit module, and a second end of the third detection line is connected to the second end of the first control transistor of the next-stage driving circuit module; Among them, when the second end of the third detection line is connected to the second end of the second control transistor of the previous-level driving circuit module, the second end of the third detection line of the first-level driving circuit module is defined as a third test connection terminal, and the third test connection terminal is configured to be electrically connected to the device that outputs the external test voltage during the test phase; when the second end of the third detection line is connected to the second end of the first control transistor of the next-level driving circuit module, the second end of the third detection line of the N-level driving circuit module is defined as a third test connection terminal, and the third test connection terminal is configured to be electrically connected to the device that outputs the external test voltage during the test phase.

2. The gate drive circuit according to claim 1, wherein: The gate drive circuit further includes: a pull-down control line, the pull-down control line being configured to be electrically connected to a device that outputs the control voltage during a test phase; One end of the first detection line is electrically connected to the pull-down control line.

3. The gate drive circuit according to claim 1, wherein: The multiple clock signal lines extend along the cascade direction of the N driving circuit modules, the node lead lines are arranged perpendicular to the multiple clock signal lines, and the first detection lines are arranged parallel to the clock signal lines.

4. A gate drive circuit detection method, characterized in that: Applied to the gate drive circuit according to any one of claims 1 to 3, during a testing phase, the detection method includes: Utilizing the first detection line to receive a control voltage so as to turn on the first control transistor and the second control transistor; Utilizing the third detection line to receive an external test voltage, causing the node lead line to output the external test voltage to the control node, so that the output transistor is in an off state; outputting a driving voltage to the first end of the output transistor using a clock signal line; The relationship between the output voltage of the second terminal of the output transistor and the driving voltage is detected to determine the short-circuit state of the output transistor.

5. A display panel comprising a display area and a non-display area, wherein the display area comprises a plurality of scan lines; The non-display area includes the gate driving circuit according to any one of claims 1 to 3, and a driving output end of a circuit unit in the gate driving circuit is electrically connected to at least one scan line.

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