Pixel circuit and driving method thereof, display panel and display device

Abstract

The invention provides a pixel circuit and a driving method thereof, a display panel and a display device. A pixel circuit according to an embodiment includes: a driving sub-circuit configured to generate a driving current from a first power signal terminal to a second power signal terminal; the compensation sub-circuit comprises a first capacitor and a second capacitor, the first capacitor is electrically connected between the first power supply signal end and a first node corresponding to the control electrode of the driving transistor, and the second capacitor is electrically connected between the first node and a second node corresponding to the second electrode of the driving transistor; the write-in sub-circuit is configured to electrically connect a data signal end with a first node based on a signal of a data control end; the setting sub-circuit is configured to electrically connect the setting signal end with the first node based on a signal of the setting control end. According to the embodiment of the invention, the setting sub-circuit is matched with the first capacitor and the second capacitor, so that the threshold voltage of the driving transistor and the potential compensation of the first power supply signal end are realized, and the display uniformity is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to a pixel circuit, a driving method thereof, a display panel, and a display device. Background Art

[0002] An organic light-emitting diode (OLED) is a new type of flat panel display device, which has the advantages of self-luminescence, high contrast ratio, wide color gamut, and wide operating temperature range, making it have broad application prospects.

[0003] In existing OLED displays, the different positions of each pixel result in different power supply voltage drops (I-R Drops). Currently, conventional pixel driving circuits cannot compensate for the power supply I-R Drop, resulting in uneven light emission of the OLED display and deteriorating the visual experience of the display screen. Summary of the Invention

[0004] To solve at least one of the above problems, a first aspect of the present disclosure provides a pixel circuit, including: a driving sub-circuit, a compensation sub-circuit, a writing sub-circuit, a setting sub-circuit, and a light-emitting unit. The driving sub-circuit includes a driving transistor, which is electrically connected between a first power supply signal terminal and a second power supply signal terminal, and is configured to generate a driving current from the first power supply signal terminal through the light-emitting unit to the second power supply signal terminal.

[0005] The compensation sub-circuit includes a first capacitor and a second capacitor. The first capacitor is electrically connected between the first power supply signal terminal and a first node corresponding to the control electrode of the driving transistor, and the second capacitor is electrically connected between the first node and a second node corresponding to the second electrode of the driving transistor.

[0006] The writing sub-circuit is electrically connected to a data signal terminal, the first node, and a data control terminal, and is configured to electrically connect the data signal terminal and the first node based on the signal of the data control terminal.

[0007] The setting sub-circuit is electrically connected to a setting signal terminal, a setting control terminal, and the first node, and is configured to electrically connect the setting signal terminal and the first node based on the signal of the setting control terminal.

[0008] Optionally, the writing sub-circuit includes: a first transistor, the first electrode of the first transistor is electrically connected to the data signal terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the writing control terminal.

[0009] Optionally, the setting sub-circuit includes: a second transistor, the first electrode of the second transistor is electrically connected to the setting signal terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the setting control terminal.

[0010] Optionally, a first reset sub - circuit is electrically connected to the first pole of the light - emitting unit, a first reset signal terminal, and a first reset control terminal, and is configured to electrically connect the first reset signal terminal to the first pole based on the signal of the first reset control terminal.

[0011] Optionally, it further includes: a first light - emitting control sub - circuit and a second light - emitting control circuit. The first light - emitting control sub - circuit is electrically connected to a first power signal terminal, a third node corresponding to the first pole of the driving transistor, and a first light - emitting control terminal, and is configured to electrically connect the first power signal terminal to the third node based on the signal of the first light - emitting control terminal;

[0012] The second light - emitting control sub - circuit is electrically connected to a fourth node corresponding to the first pole of the light - emitting unit, a second node, and a second light - emitting control terminal, and is configured to electrically connect the second node to the fourth node based on the signal of the second light - emitting control terminal.

[0013] Optionally, the first light - emitting control sub - circuit includes a third transistor, and the second light - emitting control sub - circuit includes a fourth transistor. The first pole of the third transistor is electrically connected to the first power signal terminal, the second pole is electrically connected to the third node, and the control pole is electrically connected to the first light - emitting control terminal. The first pole of the fourth transistor is electrically connected to the second node, the second pole is electrically connected to the fourth node, and the control pole is electrically connected to the second light - emitting control terminal.

[0014] Optionally, the first reset sub - circuit includes a fifth transistor. The first pole of the fifth transistor is electrically connected to the first reset signal terminal, the second pole is electrically connected to the fourth node, and the control pole is electrically connected to the first reset control terminal.

[0015] Optionally, the third transistor is a low - temperature polysilicon transistor.

[0016] A second aspect of the present disclosure provides a display panel, including the pixel circuit described above.

[0017] Optionally, it includes a display area and a non - display area surrounding the display area. The display area includes: a plurality of data signal lines extending along a first direction and arranged along a second direction, and the data signal lines are correspondingly electrically connected to the data signal terminals of a column of pixel circuits along the first direction;

[0018] The non - display area includes: a detection switch corresponding to at least one of the plurality of data signal lines, and a crack detection line at least partially surrounding the display area;

[0019] The first pole of the detection switch is electrically connected to an input signal line, the second pole is electrically connected to at least one data signal line, the control pole is electrically connected to the first end of the crack detection line, and the other end of the crack detection line is electrically connected to a detection control terminal to receive a detection signal.

[0020] Optionally, the display panel includes a normal display phase and a crack detection phase. The detection switch is a metal oxide transistor. In the crack detection phase, the detection signal is at a first level, and in the normal display phase, the detection signal is at a second level. The first level is less than the second level so that the detection switch is in the linear region of the detection switch in the crack detection phase and in the saturation region of the detection switch in the normal display phase.

[0021] A third aspect of the present disclosure provides a display device, including the display panel described above.

[0022] A fourth aspect of the present disclosure provides a driving method for the pixel circuit described above, including: a compensation phase, electrically connecting the first power signal terminal to a third node corresponding to the first pole of the driving transistor based on the signal of the first light emission control terminal and transmitting the signal of the data signal terminal to the first node based on the signal of the data control terminal;

[0023] A setting phase, transmitting the signal of the setting signal terminal to the first node based on the signal of the setting control terminal, and the driving transistor generating the driving current based on the signal of the first node.

[0024] The beneficial effects of the present disclosure are as follows:

[0025] In view of the existing problems, the present disclosure formulates a pixel circuit, a driving method thereof, a display panel and a display device, and provides a setting sub-circuit, a compensation sub-circuit including a first capacitor and a second capacitor, and a writing sub-circuit. The compensation sub-circuit is electrically connected between the first power signal terminal and the driving transistor, and the setting sub-circuit and the writing sub-circuit are both electrically connected to the control pole of the driving transistor. By using the cooperation between the structures, double compensation for the threshold voltage of the driving transistor and the voltage of the first power signal terminal is achieved, thereby improving the display uniformity of the display product, improving the display effect and user experience, and having broad application prospects. Description of the Drawings

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0027] Figure 1 An exemplary circuit schematic diagram showing a typical pixel circuit of the related art;

[0028] Figure 2 Show Figure 1 The driving timing diagram of the pixel circuit shown;

[0029] Figure 3 Shows the circuit schematic diagram of a pixel circuit according to an embodiment of the present disclosure;

[0030] Figure 4 Shows Figure 3 The driving timing diagram of the pixel circuit shown;

[0031] Figures 5 to 8 Shows Figure 3 The conduction schematic diagram of the pixel circuit shown under driving timing control;

[0032] Figure 9 And Figure 10 Shows the crack detection schematic diagram in a display panel of the related art;

[0033] Figure 11 Shows the schematic diagram of a display panel according to an embodiment of the present disclosure;

[0034] Figure 12 Shows the specific schematic diagram of the crack detection circuit and the pixel circuit according to an embodiment of the present disclosure;

[0035] Figure 13 And Figure 14 Shows the characteristic curve of the detection switch of the NMOS type LPTO transistor in the display panel. Detailed implementation manners

[0036] To illustrate the present disclosure more clearly, the present disclosure will be further described below in conjunction with preferred embodiments and the accompanying drawings. Similar components in the drawings are denoted by the same reference numerals. Those skilled in the art should understand that the content specifically described below is illustrative rather than restrictive, and should not be used to limit the protection scope of the present disclosure.

[0037] It should be noted that unless otherwise defined, the technical terms or scientific terms used in the present disclosure should have the ordinary meaning understood by those of ordinary skill in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "a", "one" or "the" do not denote a quantity limitation, but mean that there is at least one. Words such as "including" or "comprising" mean that the elements or objects appearing before this word cover the elements or objects listed after this word and their equivalents, without excluding other elements or objects.

[0038] Figure 1A traditional 7T1C circuit is shown, in which the transistor M3 serves as a driving transistor to generate a driving current for driving the OLED to emit light; the transistor M2 serves as a compensation transistor, and when it is turned on currently, it is used to perform threshold compensation on the driving transistor; the transistor M4 is a data writing transistor; the capacitor Cst is used to store the potential of the node N corresponding to the control electrode of the transistor M3; the transistors M5 and M6 are light-emitting control transistors, and the other transistors M1 and M7 are initialization transistors.

[0039] Combined with Figure 2 the timing diagram, it can be seen that during the period t2, the signal terminal Gate is at an effective level, and the transistors M3, M4, and M2 are all turned on. The signal of the signal terminal V Data is used to charge the node N, and the charging stops when the potential of the node N is V Data +Vth, so as to complete the extraction of the threshold voltage Vth of the transistor M3 and the signal of the signal terminal V Data is written. At this time, the voltage value of the capacitor Cst is V Data +Vth-VDD, that is, the threshold voltage of the transistor M3 is stored in the capacitor Cst. During the period t3, the signal terminal EM is at an effective level, forming a path from the power supply terminal VDD to the OLED, and transmitting the driving current to the OLED to drive it to emit light. The potential of the first pole of the driving transistor is VDD, Vgs = V Data +Vth-VDD, and the current is K(V Data -VDD) 2 , where K is the intrinsic factor of the transistor.

[0040] It can be seen that although the driving current flowing through the OLED has nothing to do with the threshold voltage of the transistor M3 serving as the driving transistor, it is related to the power supply terminal VDD. That is to say, only the threshold of the driving transistor is compensated, and the potential of the power supply terminal VDD cannot be compensated. However, the voltage drop (I-R Drop) of the power supply itself causes the actual potential values of the actual power supply VDD received by the pixel circuits at different positions in the display to be different, and usually the power supply VDD belongs to a unidirectional input signal terminal, which leads to obvious problems of inconsistent picture brightness at different positions in the display product. Especially as the size of the display product increases and the PPI increases, the problem of current uniformity has a more significant impact on display uniformity.

[0041] In view of this, an embodiment of the present disclosure provides a pixel circuit, including: a driving sub-circuit, a compensation sub-circuit, a writing sub-circuit, a setting sub-circuit, and a light-emitting unit. The driving sub-circuit includes a driving transistor, which is electrically connected between a first power supply signal terminal and a second power supply signal terminal, and is configured to generate a driving current from the first power supply signal terminal through the light-emitting unit to the second power supply signal terminal;

[0042] A compensation sub - circuit, including a first capacitor and a second capacitor. The first capacitor is electrically connected between a first power signal terminal and a first node corresponding to the control electrode of a driving transistor, and the second capacitor is electrically connected between the first node and a second node corresponding to the second electrode of the driving transistor;

[0043] A writing sub - circuit is electrically connected to a data signal terminal, the first node, and a data control terminal, and is configured to electrically connect the data signal terminal to the first node based on a signal of the data control terminal;

[0044] A setting sub - circuit is electrically connected to a set signal terminal, a set control terminal, and the first node, and is configured to electrically connect the set signal terminal to the first node based on a signal of the set control terminal.

[0045] In this embodiment, by providing a setting sub - circuit, a compensation sub - circuit including a first capacitor and a second capacitor, and a writing sub - circuit, and the compensation sub - circuit is electrically connected between the first power signal terminal and the driving transistor, and both the setting sub - circuit and the writing sub - circuit are electrically connected to the control electrode of the driving transistor. The cooperation between the structures is used to achieve double compensation for the threshold voltage of the driving transistor and the voltage of the first power signal terminal, so as to improve the display uniformity of the display product, and improve the display effect and user experience.

[0046] In a specific example, referring to Figure 3 as shown, the pixel circuit includes: a driving sub - circuit 31, a compensation sub - circuit 32, a writing sub - circuit 33, a setting sub - circuit 34, and a light - emitting unit D.

[0047] Among them, the light - emitting unit D can be an OLED, or a quantum dot light - emitting diode (abbreviated as QLED) or a micro light - emitting diode (abbreviated as MicroLED), etc. In the embodiments of the present disclosure, as long as it is a light - emitting element that can emit light under a driving current. In addition, in the embodiments of the present disclosure, the light - emitting element is represented by D, and Figure 1 only one light - emitting element is shown in

[0048] it, but it is only for illustration. The light - emitting unit D may also include a series connection of multiple light - emitting elements.

[0049] The compensation sub - circuit 32 includes a first capacitor Ca and a second capacitor Cs. The first capacitor Ca is electrically connected between the first power - signal terminal VDD and the first node N1 corresponding to the control electrode of the driving transistor TD, and the second capacitor is electrically connected between the first node N1 and the second node N2 corresponding to the second electrode of the driving transistor TD.

[0050] Specifically, referring to Figure 3 As shown, the first pole of the first capacitor Ca is electrically connected to the first power - signal terminal VDD, the second pole is electrically connected to the first node N1, the first pole of the second capacitor Cs is electrically connected to the first node N1, and the second pole is electrically connected to the second node N2.

[0051] The writing sub - circuit 33 is electrically connected to the data - signal terminal Vdata, the first node N1, and the data - control terminal GW, and is configured to electrically connect the data - signal terminal Vdata to the first node N1 based on the signal of the data - control terminal GW.

[0052] Specifically, the writing sub - circuit 33 includes a first transistor T1. The first pole of the first transistor T1 is electrically connected to the data - signal terminal Vdata, the second pole is electrically connected to the first node N1, and the control electrode is electrically connected to the writing - control terminal GW. When the writing - control terminal GW receives a signal of an effective level, the first transistor T1 is turned on, electrically connecting the data - signal terminal Vdata to the first node N1 to transmit the signal of the data - signal Vdata to the first node N1. It should be noted that in the embodiments of the present disclosure, the effective level refers to the signal level that enables the corresponding transistor to conduct, which will not be elaborated below.

[0053] The setting sub - circuit 34 is electrically connected to the setting - signal terminal Var, the setting - control terminal GB, and the first node N1, and is configured to electrically connect the setting - signal terminal Var to the first node N1 based on the signal of the setting - control terminal GB.

[0054] Specifically, the setting sub - circuit 34 includes a second transistor T2. The first pole of the second transistor T2 is electrically connected to the setting - signal terminal Var, the second pole is electrically connected to the first node N1, and the control electrode is electrically connected to the setting - control terminal GB. When the setting - control terminal GB receives a signal of an effective level, the first transistor T1 is turned on, electrically connecting the data - signal terminal Vdata to the first node N1 to transmit the signal of the data - signal Vdata to the first node N1.

[0055] In an embodiment of the present disclosure, a compensation transistor is formed by setting a first capacitor Ca and a second capacitor Cs that are simultaneously connected to a first node N1. The set sub-circuit 34 is also electrically connected to the first node N1, which is the intermediate position between the first capacitor Ca and the second capacitor Cs. By using the structure of the write sub-circuit 33 and the cooperation of the compensation sub-circuit 32 and the set sub-circuit 34, it is possible to simultaneously compensate the threshold voltage of the driving transistor TD and the potential of the first power signal terminal VDD. The specific compensation principle will be described in detail below in combination with the timing of the specific circuit and will not be elaborated here.

[0056] Optionally, continuing to refer to Figure 3 As shown, the pixel circuit may further include: a first light emission control sub-circuit 35 and a second light emission control circuit 36.

[0057] Among them, the first light emission control sub-circuit 35 is electrically connected to the first power signal terminal VDD, the third node N3 corresponding to the first pole of the driving transistor TD, and the first light emission control terminal EMA, and is configured to electrically connect the first power signal terminal VDD and the third node N3 based on the signal of the first light emission control terminal EMA.

[0058] The second light emission control sub-circuit 36 is electrically connected to the fourth node N4 corresponding to the first pole of the light emitting unit D, the second node N2, and the second light emission control terminal EMB, and is configured to electrically connect the second node N2 and the fourth node N4 based on the signal of the second light emission control terminal EMB.

[0059] Specifically, the first light emission control sub-circuit 35 includes a third transistor T3. The first pole of the third transistor T3 is electrically connected to the first power signal terminal VDD, the second pole is electrically connected to the third node N3, and the control pole is electrically connected to the first light emission control terminal EMA. When a signal with an effective level is applied to the first light emission control terminal EMA, the first power signal terminal VDD and the third node N3 are electrically connected to form a path from the first power signal terminal VDD to the third node N3.

[0060] The second light emission control sub-circuit 36 includes a fourth transistor T4. The first pole of the fourth transistor T4 is electrically connected to the second node N2, the second pole is electrically connected to the fourth node N4, and the control pole is electrically connected to the second light emission control terminal EMB. When a signal with an effective level is applied to the second light emission control terminal EMB, the second node N2 and the fourth node N4 are electrically connected to form a path from the second node N2 to the fourth node N4.

[0061] It is worth mentioning that considering that the third transistor T3 is directly electrically connected to the high-level first power signal terminal VDD, if a Low Temperature Polycrystalline Oxide (LTPO) transistor is used, when the transistor is turned on, the turn-on voltage is large due to the direct connection to the first power signal terminal VDD, resulting in a large power consumption of the circuit and thus a large overall power consumption of the product.

[0062] Optionally, the third transistor T3 is a Low Temperature Poly-Silicon (LTPS) transistor. Specifically, referring to Figure 3 As shown, when the third transistor T3 is an LTPS transistor, its conduction type is P-type.

[0063] Optionally, other transistors in the pixel circuit can be LTPO transistors. At this time, the conduction type of other transistors can be N-type. When other transistors are LTPO transistors, the display product has the advantages of simple LTPO transistor process, excellent current on / off ratio, low off-current (Ioff), and high response. It can also enable the display product to achieve a perfect black screen and high contrast, and at the same time achieve high and low frequency driving (1 - 120Hz), reducing the power consumption of the product.

[0064] Optionally, continuing to refer to Figure 3 As shown, the pixel circuit further includes: a first reset sub-circuit 35.

[0065] The first reset sub-circuit 37 is electrically connected to the first pole of the light-emitting unit D, the first reset signal terminal Vinit, and the first reset control terminal G1, and is configured to electrically connect the first reset signal terminal Vinit to the first pole of the light-emitting unit D based on the signal of the first reset control terminal G1.

[0066] Specifically, the first reset sub-circuit 37 may include a fifth transistor T5. The first pole of the fifth transistor T5 is electrically connected to the first reset signal terminal Vinit, the second pole is electrically connected to the fourth node N4 corresponding to the first pole of the light-emitting unit D, and the control pole is electrically connected to the first reset control terminal G1. When the first reset control terminal G1 receives a signal with an effective level, the fifth transistor T5 conducts, electrically connecting the first reset signal terminal Vinit to the fourth node N4, and inputting the signal received by the first reset signal terminal Vinit into the fourth node N4 for resetting. Optionally, the signal received by the first reset signal terminal Vinit may be the same as the signal received by the set signal terminal Var.

[0067] To further understand the structure and function of the pixel circuit of the present disclosure embodiment, the following combines Figure 4 the timing diagram ofFigures 5 to 8 The conduction and cutoff principle diagram of [X] describes the specific working process of the pixel circuit.

[0068] It should be noted that Figure 3 In the example of [X], except that the third transistor T3 is a P-type transistor, the other transistors are all N-type transistors. The following will take this as an example for illustration. However, those skilled in the art should understand that the embodiments of the present disclosure are not limited to this, and other structures that can satisfy the above overall connection relationship and achieve the following functions are within the protection scope of the present disclosure.

[0069] Specifically, the driving process of the pixel circuit in the embodiment of the present disclosure includes: the first stage T1, the second stage T2, the third stage T3, and the fourth stage T4. For the convenience of understanding and description, the signals accessed or output from the signal ports in this article are represented by the labels corresponding to the signal ports, and will not be elaborated below.

[0070] The first stage T1 is the initialization stage. Referring to Figure 4 and Figure 5 As shown, in this stage, the data control terminal GW, the second light emission control terminal EMB, and the first reset control terminal G1 are at high level. The first transistor T1, the fourth transistor T4, and the fifth transistor T5 are turned on, and the second transistor T2 and the third transistor T3 are turned off. After the first transistor T1 is turned on, the signal of the data signal terminal Vdata is written into the first node N1 and charges the first capacitor Ca and the second capacitor Cs, causing the driving transistor TD to also be turned on. After the fourth transistor T4 and the fifth transistor T5 are turned on, the signal of the first reset signal terminal Vinit is written into the second node N2 via the fifth transistor T5, the fourth node N4, and the fourth transistor T4. At this time, the potential of the first node VN1 = Vdata, and the potentials of the second node N2, the third node N3, and the fourth node N4 are VN2 = VN3 = VN4 = Vinit = Var. The signal of the first reset signal terminal Vinit is the same as the signal of the set signal terminal Var, and this potential should also be equal to Var.

[0071] The second stage T2 is the write compensation stage. Referring to Figure 4 and Figure 6As shown, the data control terminal GW is at a high level, the first light-emitting control terminal EMA changes from a high level to a low level, and the first reset control terminal G1 is at a high level. The first transistor T1, the third transistor T3, and the fifth transistor T5 are turned on. The fourth transistor T4 and the second transistor T2 are turned off. The signal of the data signal terminal Vdata continues to be written into the first node N1. Since the second node N2 stored Var at the previous moment, at this time, Vgs-Vth of the driving transistor TD = Vdata-Var-Vth > 0, so the driving transistor TD is turned on. Since the third transistor T3 is turned on, the potential of the third node N3 is higher than that of the second node N2. Thus, the second node N2 discharges to the third node N3 through the turned-on driving transistor TD until the potential of the third node N3 discharges to VN2 and VN2 = Vdata-Vth, then the driving transistor TD is turned off and the discharging ends. At this time, the potential VN1 of the first node N1 = Vdata.

[0072] It should be noted that in this stage, the moment when the signal connected to the first light-emitting control terminal EMA becomes the effective level should be after the moment when the signal connected to the second light-emitting control terminal EMB becomes the invalid level. In other words, after the fourth transistor T4 is turned off, the third transistor T3 should be controlled to turn on, so as to prevent the discharge current of the third node N3 from flowing to the first pole of the light-emitting unit D and avoid the premature turn-on of the light-emitting unit D.

[0073] In addition, during this period, a signal with an effective level is connected to the first reset control terminal G1 to control the fifth transistor T5 to turn on, so as to ensure that the reset signal is written into the fourth node N4. Through this setting, the premature turn-on of the light-emitting unit D caused by the leakage current of the fourth transistor T4 can be prevented.

[0074] The third stage T3 is the setting stage. Refer to Figure 4 and Figure 7 As shown, the signal connected to the setting control terminal GW becomes a high level, the signal connected to the data control terminal GW becomes a low level, the signal connected to the first light-emitting control terminal EMA becomes a high-level invalid signal, the signal connected to the second light-emitting control terminal EMB remains a low-level invalid signal, and the first reset control terminal G1 still accesses a high-level signal.

[0075] The first transistor T1, the third transistor T3, and the fourth transistor T4 are turned off. The second transistor T2 and the fifth transistor T5 are turned on.

[0076] It should be noted that in this stage, the setting signal of the setting signal terminal Var needs to be written into the first node N1. Therefore, the setting process should be carried out after the first transistor T1 is turned off, that is, after the influence of the data signal terminal Vdata is eliminated. Therefore, in this stage, the moment when the signal connected to the setting control terminal GB becomes the effective level should be after the moment when the signal connected to the data control terminal GW becomes the invalid level.

[0077] Continue to refer to Figure 4 and Figure 7 As shown, due to the coupling effect of the capacitors, the change in charge of the first node N1 and the second node N2 corresponding to the two poles of the second capacitor Cs is equal. That is, ΔN1×(Ca + Cs) = ΔN2×Cs, where ΔN1 = Var - Vdata, ΔN2 = VN2 - (Vdata - Vth), then (Var - Vdata)×(Ca + Cs) = (VN2 - (Vdata - Vth))×Cs. From this equation, it can be deduced that: VN2 = (Vdata - Vth) + (Var - Vdata)×(Ca + Cs) / Cs. At this time, Vgs - Vth of the driving transistor TD = VN1 - VN2 - Vth = (Vdata - Var)×Ca / Cs > 0, where VN1 = Var, so the driving transistor TD is turned on.

[0078] It should be noted that here, the first poles of the first capacitor Cs and the second capacitor Ca are electrically connected together. The first node N1 is located at the common connection point, and the second node N2 is located at one end of the series-connected first capacitor Ca and second capacitor Cs. Therefore, the equivalent capacitors at the first node N1 and the second node N2 form a parallel relationship.

[0079] In addition, because the data signals of each column are different, the voltage of the fourth node N4 will also be different when the light-emitting unit is lit. To ensure the uniformity of the light emission display, at this stage, by turning on the fifth transistor T5, all the fourth nodes N4 in the display product are reset, so as to ensure that the voltages of the light-emitting units in each column are equal before light emission, playing the role of anode initialization and ensuring that the voltages before the pixels are lit are consistent. By initializing through resetting the fourth node N4, the brightness uniformity of the display product is further ensured.

[0080] The fourth stage T4 is the light-emitting stage. Refer to Figure 4 and Figure 8 As shown, in this stage, the data control terminal GW, the set control terminal GB, and the first reset control terminal G1 are connected to low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are all turned off. The first light-emitting control terminal EMA is connected to a low-level signal, and the second light-emitting control terminal EMB is connected to a high-level signal. The third transistor T3 and the fourth transistor T4 are turned on.

[0081] In addition, the driving transistor TD maintains the potential after being set at the previous moment, and Vgs-Vth of the driving transistor TD = (Vdata-Var)×Ca / Cs > 0. The driving transistor TD is turned on, forming a driving current I from the first power signal terminal VDD through the light-emitting unit D to the second power signal terminal VSS, thereby driving the light-emitting unit D to emit light. The driving current I = (1 / 2)μ×Cox×(W / L)((Vdata-Var)×Ca / Cs) 2 . Wherein, W / L is the aspect ratio of the driving transistor TD, μ is the hole mobility, and Cox is the gate capacitance.

[0082] It can be seen that the driving current I that finally drives the light-emitting unit D to emit light is not only independent of the threshold voltage Vth of the driving transistor TD, but also independent of any power signal terminal, especially VDD. The pixel circuit of the embodiment of the present disclosure realizes double compensation for the threshold voltage Vth of the driving transistor TD and the voltage of the first power signal terminal VDD.

[0083] In addition, compared with the first power signal terminal VDD that usually inputs signals unidirectionally from one side of the display area, the set signal terminal Var is a signal input bidirectionally on both sides of the display area. That is to say, the set signal line Var is not intended for the opposite sides of the display area, and is respectively located at both ends of a row of pixel circuits, and the set signal lines at both ends input signals from both sides to the set signal terminal Var. Therefore, compared with the signal of the first power signal terminal VDD, the signals accessed by the set signal terminal Var are of the same size and do not have obvious IR Drop. Thus, by compensating the threshold voltage of the driving transistor TD and the voltage of the first power signal terminal VDD, the long-range uniformity of the current at different positions in the display product is effectively improved, thereby improving the light-emitting uniformity of the display product and enhancing the user experience.

[0084] It is worth further explaining that referring to the above process, in the setting stage, the first capacitor Ca and the second capacitor Cs electrically connected to the first node N1 cooperate with the setting sub-circuit 34 that sets the first node N1, and use the voltage division coupling of the parallel equivalent capacitor to couple the voltage accessed by the set signal terminal Var to the first node N1 and the second node N2, thereby avoiding the first power signal terminal VDD from existing in the expression of the final driving current I.

[0085] Based on the same inventive concept, the embodiment of the present disclosure also provides a driving method for the above pixel circuit, including:

[0086] Compensation stage: Based on the signal of the first light control terminal, electrically connect the first power signal terminal to the third node corresponding to the first pole of the driving transistor, and based on the signal of the data control terminal, transmit the signal of the data signal terminal to the first node;

[0087] In the setting stage, the signal at the setting signal terminal is transmitted to the first node based on the signal at the setting control terminal, and the driving transistor generates the driving current based on the signal at the first node.

[0088] Since the driving method provided by the embodiments of the present disclosure has been described in detail when describing the working process of the pixel circuit above, and the specific process corresponds to each stage provided by the above embodiments, the previous embodiments are also applicable to the driving method provided by this embodiment, and will not be described in detail in this embodiment.

[0089] In this embodiment, by adopting this driving method in cooperation with the above circuit structure, it is possible to simultaneously compensate for the threshold voltage and the power supply voltage of the driving transistor, improve the display uniformity, and improve the user experience.

[0090] Based on the same inventive concept, the embodiments of the present disclosure also provide a display panel, including the pixel circuit described in the above embodiments. Since the pixel circuit included in the display panel provided by the embodiments of the present disclosure corresponds to the pixel circuit provided by the above embodiments, the previous embodiments are also applicable to the display device provided by this embodiment, and will not be described in detail in this embodiment.

[0091] By providing the pixel circuit including the above embodiments, the display panel can improve the problem of uneven emission brightness of pixel points at different positions in the picture display, improve the display uniformity of the display picture, and improve the user experience.

[0092] On the other hand, the inventors further found through research that in the related art, as referred to Figure 9 and Figure 10 described, usually multiple data signal lines and multiple columns of pixel circuits electrically connected to these data lines are used to implement the edge crack (Crack) detection of the display panel. As shown in Figure 9 , usually several turns of metal traces around the periphery of the display panel are used as the crack detection line PCD (Panel Crack Detection). One end of these traces is connected to several data signal lines in the display panel, and these data signal lines are electrically connected to the data signal terminals Vdata of a column of pixel circuits in the display panel. The amplifier circuit is usually a triode, which is used to control whether the crack detection is carried out under the control of the control signal, that is, to control whether the crack detection line PCD is serially connected between the detection signal terminal ET_In and the data signal terminal Vdata; the detection signal terminal ET signal In represents the port of the detection signal accessed in the crack detection stage. Specifically, in the crack detection stage, the data signal is provided by the detection signal terminal ET_In. The pixel circuit connected with the crack detection forms a structure as shown in Figure 10The equivalent circuit relationship shown, where since the amplifier circuit does not affect the series relationship of the crack detection line PCD, the triode transistor amplifier circuit is omitted. Refer to Figure 10 As shown, the PCD trace is serially connected between the detection signal terminal ET_In that provides the data signal and the data signal terminal Vdata of the pixel circuit, which is equivalent to adding an extra series-connected trace resistance of the crack detection line PCD between them. Additionally, it should be understood that when crack detection is not performed, the data signal is still provided by the corresponding input signal line.

[0093] According to the current detection principle, it is expected to use the change in the equivalent resistance when a crack appears to perform crack detection. Specifically, during crack detection, if there is no crack at the edge of the display panel, the equivalent resistance between the data input terminal Vdata of the corresponding several columns of pixel circuits and the input signal line Vdata In is small, and there is no obvious dark line during the screen display. If there is a crack at the edge of the display panel, the equivalent resistance increases, and multiple dark lines often appear during the screen display, thereby achieving the purpose of detecting cracks in the film layer.

[0094] However, with the update of display products, the increase in size, the increase in pixel density (Pixels Per Inch, PPI), and the continuous improvement of the requirements for narrow bezel products, the size of the crack detection line PCD has been continuously extended. In some cases where there is only one bezel detection switch, the equivalent resistance of the crack detection line PCD has reached a non-negligible level. That is to say, for several columns of pixel circuits connected to the crack detection line PCD, even when there is no crack, due to the shunt of the equivalent resistance, a visually recognizable dark line appears, which will lead to misjudgment of crack detection and thus affect the yield of display products.

[0095] To solve this technical problem, continue to refer to Figure 11 and Figure 12 As shown, the display panel of the embodiment of the present disclosure includes: a display area AA and a non-display area NA surrounding the display area AA. The display area AA includes: a plurality of data signal lines Da extending along the first direction Y and arranged along the second direction X, and the data signal lines Da are correspondingly electrically connected to the data signal terminals Vdata of a column of pixel circuits along the first direction Y; the non-display area NA includes: a detection switch G-Switch corresponding to at least one of the plurality of data signal lines Da, and at least part of the crack detection line PCD surrounding the display area AA. Among them, the first pole of the detection switch G-Switch is electrically connected to the input signal line Vdata In, the second pole is electrically connected to at least one data signal line Da, and the control pole is electrically connected to the first end of the crack detection line. The crack detection line PD is connected to the detection control terminal CT-SW to receive a detection signal. Among them, the input signal line Vdata In is used to access the data signal to be connected to the data signal terminal Vdata.

[0096] Referring to Figure 12 as shown, in this embodiment, the crack detection line PCD is serially connected between the control electrode of the detection switch G-Switch and the detection control terminal CT-SW. With this setting, when there is no crack in the display panel, the equivalent resistance of the detection signal line PCD itself will not affect the specific amplitude of the signal Vdata input from the input signal terminal Vdata In providing the data signal to the first node N1, thus will not affect the value of the driving current I of the corresponding column pixel circuit, nor will it affect the brightness of the light-emitting units of these pixel circuits, and thus will not form a misjudgment of crack detection.

[0097] Regarding the crack detection process of this embodiment, referring to Figure 13 and Figure 14 the IdVg curve graph of the LTPO transistor shown, in which the IdVg curves of the detection switches of the NMOS-type LTPO transistors measured at different detection points on the crack detection line PCD in different display panels are represented by different colors in the figure. For the NMOS-type LTPO transistor, referring to Figure 13 it can be seen that when in the saturation region, the fluctuation of the gate voltage Vg of the transistor has almost no obvious influence on the source-drain current Ids. Referring to Figure 14 it can be seen that when it is in the sub-threshold swing (SS) region (or the linear region of the LTPO transistor), for the NMOS LTPO transistor, the absolute value of the source-drain current changes approximately linearly or greatly with the change of the voltage of the control electrode of the transistor, and a small change in Vg has an obvious influence on the current Ids. The inventor utilizes this characteristic of the transistor to adopt different voltage amplitudes for the detection signal connected to the detection terminal CT-SW during the detection period and the normal lighting period, so that during the detection period, the detection switch G-Switch is in the sub-threshold swing region, thus the equivalent resistance value on the crack detection line PCD changes, and the current Ids of the detection switch G-Switch changes significantly with the voltage amplitude connected to the control electrode; while during the normal electrical connection period, the detection switch G-Switch belongs to the saturation region of the detection switch, so when the crack detection line PCD is 1Ω and 1MΩ, the output current Ids is almost the same. Therefore, even if the resistance value of the crack detection line PCD is very large, and even if its resistance value changes due to environmental fluctuations, it will not have an obvious influence on the current Ids flowing through the detection switch G-Switch, achieving the effect of shielding the amplifier circuit for crack detection.

[0098] Specifically and optionally, the display panel includes a normal display stage and a crack detection stage. The detection switch is a metal oxide transistor. In the crack detection stage, the detection signal is at a first level, and in the normal display stage, the detection signal is at a second level. The first level is less than the second level so that the detection switch is in the linear region of the detection switch in the crack detection stage and in the saturation region of the detection switch in the normal display stage.

[0099] Exemplarily, when the present embodiment does not enter the crack detection stage, that is, the normal display stage, the voltage of the detection terminal CT-SW can be constantly set at 7V. The Vgs of this transistor is, for example, 7 - 13V, and it is in the Ion stage of the Vdata-G-CTSW TFT characteristic curve. The fluctuation of the gate voltage Vg has no obvious influence on the Ids output. When the present embodiment enters the crack detection stage, the detection terminal CT-SW can be adjusted to about 2.0V. When Vdata is about 4V, since Vgs = 6V, the detection switch G-Switch conducts, but it will be in the subthreshold swing (SS) interval of the normal NMOS characteristic curve, and a slight change in Vgs has an obvious influence on the current.

[0100] Optionally, at the same time, since the writing efficiency of the data signal terminal Vdata drops significantly, VDD can be adjusted to about 1 - 2V, so that the Vgs of the driving transistor TD of LTPO decreases, and the driving transistor TD also operates in the subthreshold swing SS interval. Through the resistance change of the crack detection line PCD, it can be quickly and accurately analyzed whether there is an abnormality in the crack detection line PCD. When the resistance of the crack detection line PCD changes from 1Ω to 1MΩ, the driving current I changes significantly. As the resistance change of the crack detection line PCD intensifies, the change of the driving current I output becomes more obvious. By adjusting the size of VDD, the working interval of the driving transistor TD can be adjusted, and the sensitivity to the resistance value change of the crack detection line PCD can be adjusted, so as to effectively distinguish whether there is a Crack around the display panel indicated by the crack detection line PCD.

[0101] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, including the display panel described in the above embodiment. Since the display panel included in the display device provided by the embodiment of the present disclosure corresponds to the display panel provided by the above embodiment, the previous implementation manners are also applicable to the display device provided by the present embodiment, and will not be described in detail in the present embodiment.

[0102] In the present embodiment, the display device can be any product or component with a display function, such as an in-vehicle display device, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, or a navigator. When the above display panel is used in a display device, it can significantly improve display unevenness and enhance the user experience. In addition, the display device can also avoid misjudgment and over-detection problems of crack detection, and improve the yield of the display device.

[0103] Obviously, the above-mentioned embodiments of the present disclosure are merely examples for clearly illustrating the present disclosure, rather than limitations on the implementation manners of the present disclosure. For those of ordinary skill in the art, other different forms of changes or variations can be made based on the above description. It is impossible to list all the implementation manners here. Any obvious changes or variations derived from the technical solutions of the present disclosure are still within the protection scope of the present disclosure.

Claims

1. A pixel circuit, characterized in that, Comprising: A driving sub - circuit, a compensating sub - circuit, a writing sub - circuit, a setting sub - circuit, and a light - emitting unit. The driving sub - circuit includes a driving transistor, electrically connected between a first power - signal terminal and a second power - signal terminal, configured to generate a driving current from the first power - signal terminal via the light - emitting unit to the second power - signal terminal. The compensating sub - circuit includes a first capacitor and a second capacitor. The first capacitor is electrically connected between the first power - signal terminal and a first node corresponding to the control electrode of the driving transistor. The second capacitor is electrically connected between the first node and a second node corresponding to the second electrode of the driving transistor. The writing sub - circuit is electrically connected to a data - signal terminal, the first node, and a data - control terminal, and is configured to electrically connect the data - signal terminal to the first node based on a signal of the data - control terminal. The setting sub - circuit is electrically connected to a set - signal terminal, a set - control terminal, and the first node, and is configured to electrically connect the set - signal terminal to the first node based on a signal of the set - control terminal.

2. The pixel circuit according to claim 1, wherein The writing sub - circuit includes: a first transistor. A first electrode of the first transistor is electrically connected to the data - signal terminal, a second electrode is electrically connected to the first node, and a control electrode is electrically connected to the writing - control terminal.

3. The pixel circuit according to claim 1, wherein The setting sub - circuit includes: a second transistor. A first electrode of the second transistor is electrically connected to the set - signal terminal, a second electrode is electrically connected to the first node, and a control electrode is electrically connected to the set - control terminal.

4. The pixel circuit according to claim 1, wherein A first reset sub - circuit, electrically connected to a first electrode of the light - emitting unit, a first reset - signal terminal, and a first reset - control terminal, and is configured to electrically connect the first reset - signal terminal to the first electrode based on a signal of the first reset - control terminal.

5. The pixel circuit according to claim 1, wherein Further comprising: A first light - emission control sub - circuit and a second light - emission control circuit. The first light - emission control sub - circuit is electrically connected to the first power - signal terminal, a third node corresponding to a first electrode of the driving transistor, and a first light - emission control terminal, and is configured to electrically connect the first power - signal terminal to the third node based on a signal of the first light - emission control terminal. The second light - emission control sub - circuit is electrically connected to a fourth node corresponding to a first electrode of the light - emitting unit, the second node, and a second light - emission control terminal, and is configured to electrically connect the second node to the fourth node based on a signal of the second light - emission control terminal.

6. The pixel circuit according to claim 5, wherein The first light - emission control sub - circuit includes a third transistor, and the second light - emission control sub - circuit includes a fourth transistor. A first electrode of the third transistor is electrically connected to the first power - signal terminal, a second electrode is electrically connected to the third node, and a control electrode is electrically connected to the first light - emission control terminal. A first electrode of the fourth transistor is electrically connected to the second node, a second electrode is electrically connected to the fourth node, and a control electrode is electrically connected to the second light - emission control terminal.

7. The pixel circuit according to claim 4, wherein The first reset sub - circuit includes a fifth transistor. A first electrode of the fifth transistor is electrically connected to the first reset - signal terminal, a second electrode is electrically connected to the fourth node, and a control electrode is electrically connected to the first reset - control terminal.

8. The pixel circuit according to claim 6, wherein The third transistor is a low - temperature polysilicon transistor.

9. A display panel, characterized in that, Including the pixel circuit according to any one of claims 1-8.

10. The display panel according to claim 9, wherein, Including a display area and a non-display area surrounding the display area, The display area includes: a plurality of data signal lines extending in a first direction and arranged in a second direction, and the data signal lines are correspondingly electrically connected to the data signal terminals of a column of the pixel circuits in the first direction, The non-display area includes: a detection switch corresponding to at least one of the plurality of data signal lines, and a crack detection line at least partially surrounding the display area, A first pole of the detection switch is electrically connected to an input signal line, a second pole is electrically connected to the at least one data signal line, a control pole is electrically connected to a first end of the crack detection line, and the other end of the crack detection line is electrically connected to a detection control end to receive a detection signal.

11. The display panel according to claim 10, wherein, The display panel includes a normal display stage and a crack detection stage, The detection switch is a metal oxide transistor, the detection signal is a first level in the crack detection stage, and the detection signal is a second level in the normal display stage, The first level is less than the second level so that the detection switch is in the linear region of the detection switch in the crack detection stage and in the saturation region of the detection switch in the normal display stage.

12. A display device, characterized in that, Including the display panel according to any one of claims 9-11.

13. A driving method for the pixel circuit according to any one of claims 1-8, characterized in that, Including: A compensation stage, electrically connecting a third node corresponding to the first pole of the driving transistor to the first power signal terminal based on a signal of a first light emission control terminal, and transmitting a signal of the data signal terminal to the first node based on a signal of the data control terminal; A setting stage, transmitting a signal of the setting signal terminal to the first node based on a signal of the setting control terminal, and the driving transistor generates the driving current based on the signal of the first node.

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