Memory and storage device

Abstract

The invention discloses a memory and storage equipment, the memory comprises a storage array, an interface module, a decoding circuit and a first-in first-out storage module, the interface module multiplexes command address information and data information in a transmission user instruction; the decoding circuit is connected between the interface module and the first-in first-out storage module; the first-in first-out storage module is arranged between the storage array and the decoding circuit, the storage array executes memory operation based on the current user instruction to be in an occupied state, and the first-in first-out storage module temporarily stores command address information in the analyzed next user instruction in response to the next user instruction received by the interface module; and after the occupation state of the storage array is released, the first-in first-out storage module takes out command address information in the temporarily stored analyzed next user instruction and sends the command address information to the storage array for execution. When the storage array is occupied, the user instruction can still be received continuously, execution of the user instruction cannot be delayed, and high-frequency data transmission is achieved.

Description

Technical Field

[0001] This application relates to the technical field of memories, and particularly to a memory and a storage device. Background Art

[0002] A memory generally consists of a storage array, a data path, and a control circuit. Taking a pseudo-static random access memory as an example, the pseudo-static random access memory protocol clearly stipulates the read and write latency times under different operating frequencies and the internal refresh state of the chip. During normal operation, it meets the internal time requirements and there will be no occupation between user instructions. However, in some extreme scenarios, since users do not pay attention to the internal occupation state of the memory when performing read and write operations on the pseudo-static random access memory, if the memory is in an occupied state when the user sends read and write instructions and the instructions are not processed, the read and write operations will fail. In the prior art, a new output pin is added to memory chips such as single-chip microcontrollers. When the output pin of the chip outputs a high level, it represents that the memory is in an occupied state and cannot receive instructions and data. However, setting this pin still delays user instructions and reduces data transmission efficiency. Summary of the Invention

[0003] To solve the above problems, this application provides a memory and a storage device.

[0004] To solve the above technical problems, a technical solution adopted by this application is: to provide a memory, which includes a storage array, an interface module, a decoding circuit, and a first-in first-out storage module. The interface module multiplexes the transmission of command address information and data information in user instructions; the decoding circuit is connected between the interface module and the first-in first-out storage module to parse the command address information; the first-in first-out storage module is arranged between the storage array and the decoding circuit. When the storage array is in an occupied state based on the execution of a memory operation for the current user instruction, in response to the interface module receiving the next user instruction, the decoding circuit parses the command address information of the next user instruction, and the first-in first-out storage module temporarily stores the parsed command address information in the next user instruction. After the storage array releases the occupied state, the first-in first-out storage module takes out the temporarily stored parsed command address information in the next user instruction and sends it to the storage array for execution.

[0005] Wherein, the memory further includes a data buffer circuit, which is connected between the interface module and the storage array and is also connected to the decoding circuit, and cooperates with the storage array to execute memory operations based on the parsed command address information.

[0006] Wherein, the interface module is further used to receive the chip select signal sent by the host controller. In response to the chip select signal being pulled low, the interface module allows receiving user instructions; in response to the chip select signal being pulled high, the interface module prohibits receiving user instructions.

[0007] Among them, the decoding circuit is further configured to generate a first internal state execution signal based on the decoding state. In response to the chip select signal being pulled low and the decoding circuit being operating on the current user instruction, the first internal state execution signal is at a logic high level. In response to the chip select signal being pulled high, the first internal state execution signal is at a logic low level.

[0008] Among them, the decoding circuit includes a command decoding module. The command decoding module is connected to the first-in first-out storage module, the interface module, and the data buffer circuit. After decoding the command address information in the current user instruction, the command decoding module pulls high the first internal state execution signal, and generates a corresponding enable signal after a fixed pipeline delay to enable the data buffer circuit to receive the data corresponding to the current user instruction.

[0009] Among them, the decoding circuit further includes an address decoding module. The address decoding module is connected to the first-in first-out storage module and the interface module. The address decoding module sequentially decodes the command address information in the current user instruction and the next user instruction to obtain an address signal corresponding to the command address information for addressing in the storage array.

[0010] Among them, the first-in first-out storage module is configured to generate a second internal state execution signal based on the internal state of the storage array. In response to the current user instruction occupying the storage array, the second internal state execution signal is at a logic high level; in response to the current user instruction releasing the occupation of the storage array, the second internal state execution signal switches to a logic low level. When the second internal state execution signal switches to a logic low level, the first-in first-out storage module takes out the parsed command address information in the next user instruction temporarily stored and sends it to the storage array for execution.

[0011] Among them, the data buffer circuit includes a data input / output module, a serial-to-parallel conversion module, and a sense amplifier module. The data input / output module is connected to the interface module. In response to receiving the enable signal, the data input / output module is enabled to enable the data input / output module to read and write data with the storage array; the serial-to-parallel conversion module is connected to the data input / output module and is used to convert between serial transmission and parallel transmission during the data read and write process; the sense amplifier module is connected to the serial-to-parallel conversion module and the storage array and is used to sense and amplify the data during the data read and write process.

[0012] Among them, the memory further includes a mode configuration module. The mode configuration module is respectively connected to the interface module and the serial-to-parallel conversion module and is used to configure the mode of the serial-to-parallel conversion module.

[0013] Among them, the interface module includes a multi-IO serial interface.

[0014] To solve the above technical problems, another technical solution adopted by this application is: to provide a storage device, which includes the memory of any one of the above.

[0015] Different from the prior art, the memory of this application includes a storage array, an interface module, a decoding circuit, and a first-in first-out (FIFO) storage module. The interface module multiplexes the transmission of command address information and data information in the user instruction; the decoding circuit is connected between the interface module and the FIFO storage module to parse the command address information; the FIFO storage module is arranged between the storage array and the decoding circuit. The storage array is in an occupied state based on the execution of the memory operation by the current user instruction. In response to the interface module receiving the next user instruction, the decoding circuit parses the command address information of the next user instruction, and the FIFO storage module temporarily stores the parsed command address information in the next user instruction. After the storage array is released from the occupied state, the FIFO storage module retrieves the temporarily stored parsed command address information in the next user instruction and sends it to the storage array for execution. In the above manner, the memory of this application can continue to receive user instructions even when the storage array is occupied, and will not delay the execution of user instructions, realizing high-frequency data transmission. In this way, when the memory is in an occupied state, the user does not need to wait for a new operation, which reduces the time required for batch sending of user instructions to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings. Among them:

[0017] Figure 1 is a schematic structural diagram of the first embodiment of the memory of this application;

[0018] Figure 2 is a schematic structural diagram of the second embodiment of the memory of this application;

[0019] Figure 3 is a schematic structural diagram of the third embodiment of the memory of this application;

[0020] Figure 4 is a timing schematic diagram of the memory of this application executing user instructions;

[0021] Figure 5 is a schematic structural diagram of the fourth embodiment of the memory of this application;

[0022] Figure 6 is a schematic structural diagram of an embodiment of the storage device of this application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It can be understood that the specific embodiments described herein are only used to explain the present application, rather than limiting the present application. In addition, it should be noted that, for the sake of description, only the parts related to the present application rather than all the structures are shown in the drawings. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the scope of protection of the present application.

[0024] The mention of "embodiment" in this document means that the specific features, structures, or characteristics described in connection with the embodiment may be included in at least one embodiment of the present application. The phrase appears at various positions in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein may be combined with other embodiments.

[0025] A memory generally consists of a storage array, a data path, and a control circuit. Taking a pseudo-static random access memory as an example, the pseudo-static random access memory protocol clearly stipulates the read and write latency times under different operating frequencies and the internal refresh state of the chip. During normal operation, it meets the internal time requirements and there will be no occupation between user instructions. However, in some extreme scenarios, since users do not pay attention to the internal occupation state of the memory when performing read and write operations on the pseudo-static random access memory, if the memory is in an occupied state when the user sends read and write instructions and the instructions are not processed, the read and write operations will fail. In the prior art, a method is to add an output pin to a memory chip such as a single-chip microcomputer. When the output pin of the chip outputs a high level, it represents that the memory is in an occupied state and cannot receive instructions and data. However, setting this pin will still delay user instructions and reduce the data transmission efficiency.

[0026] To solve the above problems, the present application first proposes a memory. Please refer to Figure 1 , Figure 1 which is a schematic structural diagram of the first embodiment of the memory of the present application. As Figure 1 shown, the memory 100 of this embodiment includes an interface module 10, a first-in first-out storage module 20, a decoding circuit 30, and a storage array 40.

[0027] In this embodiment, the interface module 10 multiplexes and transmits the command address information and data information in the user instruction; the decoding circuit 30 is connected between the interface module 10 and the first-in first-out storage module 20 to parse the command address information; the first-in first-out storage module 20 is arranged between the storage array 40 and the decoding circuit 30. The storage array 40 is in an occupied state based on the execution of the memory operation for the current user instruction. In response to the interface module 10 receiving the next user instruction, the decoding circuit 30 parses the command address information of the next user instruction. The first-in first-out storage module 20 temporarily stores the parsed command address information in the next user instruction, and after the storage array 40 releases the occupied state, the first-in first-out storage module 20 retrieves the temporarily stored parsed command address information in the next user instruction and sends it to the storage array 40 for execution.

[0028] In this embodiment, the memory 100 of this embodiment can be set as a flash memory, a random pseudo-random memory, or other memories. Among them, taking the random access memory as an example, the interface module 10 in this embodiment multiplexes and transmits the command address information and data information in the user instruction, that is, when receiving the user instruction, the data line of the interface module 10 in this embodiment multiplexes and transmits the command address information and data information in the user instruction. When the interface module 10 receives the user instruction, it first receives the command address information of the user command and then receives the corresponding data information. Among them, the interface module 10 of this embodiment can be set as a multi-IO serial interface. For example, the interface module 10 is a QSPI or xSPI interface with 4 or 8 IO ports. These IO ports are used to transmit both the command address information (command / address) and the data information (data) in the user instruction, that is, the interface module 10 is multiplexed to transmit the command address information and data information in the user instruction.

[0029] The first-in first-out storage module 20 can be set as a first-in first-out register in this embodiment. The first-in first-out register is a register with special functions. It stores data in the order in which the data arrives at the input port and sends out the data in the same order from the output port. This structure enables the writing and reading of data in the first-in first-out register to be controlled only by the read and write request signals without the need for read and write address lines. Among them, in this embodiment, the first-in first-out register is used to cache the parsed command address information corresponding to the next user instruction when the storage array 40 is in an occupied state and the interface module 10 receives the next user instruction and the decoding circuit 30 parses the command address information of the next user instruction.

[0030] The decoding circuit 30 is the decoding module in this embodiment and is used to decode the command address information. In this embodiment, when the interface module 10 receives the next user instruction, the decoding circuit 30 can parse the command address information in the next user instruction and send the parsed command address information in the next user instruction to the first-in first-out storage module 20 for temporary storage. The specific structure of the decoding circuit 30 is described below and will not be elaborated here.

[0031] Different from the prior art, the memory 100 of the present application includes a storage array 40, an interface module 10, a decoding circuit 30, and a first-in first-out storage module 20. The interface module 10 multiplexes the transmission of the command address information and the data information in the user instruction; the decoding circuit 30 is connected between the interface module 10 and the first-in first-out storage module 20 to parse the command address information; the first-in first-out storage module 20 is arranged between the storage array 40 and the decoding circuit 30. The storage array 40 is in an occupied state based on the execution of the memory operation of the current user instruction. In response to the interface module 10 receiving the next user instruction, the decoding circuit 30 parses the command address information of the next user instruction, and the first-in first-out storage module 20 temporarily stores the parsed command address information in the next user instruction. After the storage array 40 is released from the occupied state, the first-in first-out storage module 20 retrieves the temporarily stored parsed command address information in the next user instruction and sends it to the storage array 40 for execution. Through the above method, the memory 100 of the present application can still receive user instructions when the storage array 40 is occupied, and will not delay the execution of user instructions, realizing high-frequency data transmission. In this way, when the memory 100 is in an occupied state internally, the user does not need to wait for a new operation, and to a certain extent, the time required for batch sending of user instructions is reduced.

[0032] Optionally, please refer to Figure 2 , Figure 2 which is a schematic structural diagram of the second embodiment of the memory of the present application. As Figure 2 shown, the memory 100 of this embodiment further includes a data buffer circuit 50. The data buffer circuit 50 is connected between the interface module 10 and the storage array 40 and is connected to the decoding circuit 30, and cooperates with the storage array 40 to execute the memory operation based on the parsed command address information.

[0033] In this embodiment, after the command address information corresponding to the user instruction is input to the decoding circuit 30, the decoding circuit 30 can parse the command address information to obtain the corresponding enable signal and address signal. Based on the address signal, the decoding circuit 30 can perform addressing in the storage array 40. The decoding circuit 30 can generate an enable signal after a fixed pipeline latency and send it to the data buffer circuit 50, so that the data buffer circuit 50 receives the data information corresponding to the user instruction and performs corresponding memory operations on the storage array 40. The specific structure of the data buffer circuit 50 is described below and will not be elaborated here.

[0034] Optionally, based on Figure 2 the above-described embodiment, in this embodiment, the interface module 10 is further configured to receive a chip select signal issued by the host controller. In response to the chip select signal being pulled low, the interface module 10 allows reception of user instructions; in response to the chip select signal being pulled high, the interface module 10 prohibits reception of user instructions.

[0035] In this embodiment, the chip select signal is a signal used to select a specific memory, and is used to indicate which user commands among the memories connected to the bus are sent to this memory. The generation mechanism of the chip select signal is generated by a logic circuit when dividing the address space. When the processor needs to access a certain memory, it will send a chip select signal to select this memory. This signal instructs the selected memory to perform the memory operation corresponding to the user instruction, while other memories ignore these user instructions.

[0036] When the chip select signal is at a logic low level, it means that this memory 100 is selected and can be used to perform the memory operation corresponding to the sent user instruction. At this time, the interface module 10 of this memory 100 allows reception of user instructions; when the chip select signal is at a logic high level, it means that this memory 100 is not selected. At this time, the interface module 10 of this memory 100 prohibits reception of user instructions.

[0037] Optionally, based on Figure 2 the above-described embodiment, in this embodiment, the decoding circuit 30 is further configured to generate a first internal state execution signal based on the decoding state. In response to the chip select signal being pulled low and the decoding circuit 30 being operating on the current user instruction, the first internal state execution signal is at a logic high level. In response to the chip select signal being pulled high, the first internal state execution signal is at a logic low level.

[0038] That is, in this embodiment, the decoding circuit 30 generates a first internal state execution signal based on the chip select signal and the decoding state. The first internal state execution signal represents the states of the decoding circuit 30 performing read / write instruction / address decoding and data read / write that the user synchronously sees. When the first internal state execution signal is at a logic high level, it represents that the decoding circuit 30 is operating on the current user instruction. When the first internal state execution signal is at a logic low level, it represents that the data interaction between the user and the storage array 40 through the data buffer circuit 50 is completed.

[0039] Optionally, based on the above embodiment, please refer to Figure 3 , Figure 3 which is a schematic structural diagram of the third embodiment of the memory of the present application. As Figure 3 shown, the decoding circuit 30 of this embodiment includes a command decoding module 31. The command decoding module 31 is connected to the first-in first-out storage module 20, the interface module 10, and the data buffer circuit 50. After decoding the command address information in the current user instruction, the command decoding module 31 raises the first internal state execution signal, and after a fixed pipeline delay, it generates a corresponding enable signal to enable the data buffer circuit 50 to receive the data corresponding to the current user instruction.

[0040] In this embodiment, as described above, the first internal state execution signal represents the states of the decoding circuit 30 performing read / write instruction / address decoding and data read / write that the user synchronously sees. When the command decoding module 31 receives and decodes the command address information in the current user instruction, it can raise the first internal state execution signal. At this time, when the first internal state execution signal is at a logic high level, it represents that the command decoding module 31 is operating on the current user instruction. In addition, after a fixed pipeline delay, the command decoding module 31 also generates a corresponding enable signal to enable the data buffer circuit 50 to receive the data corresponding to the current user instruction.

[0041] When the chip select signal is raised, the first internal state execution signal will switch to a logic low level, which represents that the data interaction between the user and the storage array 40 through the data buffer circuit 50 is completed.

[0042] Optionally, based on the above embodiment, as Figure 3 shown, the decoding circuit 30 further includes an address decoding module 32. The address decoding module 32 is connected to the first-in first-out storage module 20 and the interface module 10. The address decoding module 32 sequentially decodes the command address information in the current user instruction and the next user instruction to obtain an address signal corresponding to the command address information for addressing in the storage array 40.

[0043] As described above, in this embodiment, the address decoding module 32 sequentially decodes the command address information in the current user instruction and the next user instruction to obtain an address signal corresponding to the command address information for addressing in the storage array 40. The address signal may include a row address and a column address for specifying a storage unit in the storage array 40. The address decoding module 32 may decode the address signal to select at least one word line corresponding to the row address, activate the selected word line, and select at least one bit line corresponding to the column address, so as to perform a corresponding memory operation on the storage unit corresponding to the command address signal.

[0044] For example, see Figure 4 , Figure 4 This is a timing diagram of the memory of this application executing user instructions. Figure 4 As shown, CEB is Figure 2 and Figure 3 The chip select signals CMD1 STA1 and CMD2 STA1 described in the embodiment are Figure 2 and Figure 3 The first internal state execution signal described in the embodiment is used to characterize the execution of read and write instructions / address decoding and data reading and writing states synchronously seen by the user. It is assumed that the current user instruction is CMD1 and the next user instruction is CMD2. When the chip select signal CEB is pulled low, after the memory receives the current user instruction CMD1, the command decoding module 31 receives the current user instruction CMD1 and decodes it, pulls the first internal state execution signal CMD1 STA1 high and executes the pipeline delay corresponding to the command to generate an enable signal, and sends the enable signal to the data buffer circuit 50, so that the data buffer circuit 50 receives the corresponding data of the current user instruction CMD1. When the data corresponding to the current user instruction CMD1 is exchanged with the data of the storage array 40, the chip select signal CEB is pulled high, and at this time, the first internal state execution signal CMD1 STA1 is pulled low, which indicates that the data information interaction between the user and the memory is completed. If the user sends the next user command CMD2 to the memory, the chip select signal CEB needs to be pulled low again and then the next user command CMD2 is sent to the memory. The next user command CMD2 will still be received by the command decoding module 31 and after the corresponding decoding is completed, the above steps are repeated and the first internal state execution signal CMD2 STA1 corresponding to the next user command CMD2 is generated.

[0045] Optionally, based on the above embodiment, Figure 2 and Figure 3As shown, the first-in first-out storage module 20 is configured to generate a second internal state execution signal based on the internal state of the storage array 40. When the storage array 40 is in an occupied state in response to the current user instruction, the second internal state execution signal is at a logic high level; when the storage array 40 is released from the occupied state in response to the current user instruction, the second internal state execution signal switches to a logic low level; when the second internal state execution signal switches to a logic low level, the first-in first-out storage module 20 retrieves the command address information in the parsed next user instruction that has been temporarily stored and sends it to the storage array 40 for execution.

[0046] In this embodiment, the first-in first-out storage module 20 generates a second internal state execution signal based on the internal state of the storage array 40. When the second internal state execution signal is at a logic high level, it represents that the storage array 40 is in an occupied state, and when the second internal state execution signal is at a logic low level, it represents that the storage array 40 is released from the occupied state. Therefore, when the storage array 40 is in an occupied state while performing a memory operation based on the current user instruction, at this time, the second internal state execution signal is at a logic high level. If the interface module 10 receives the next user instruction and the decoding circuit 30 has completed parsing the command address information corresponding to the next user instruction, at this time, the first-in first-out storage module 20 can temporarily store the command address information in the parsed next user instruction; when the internal state execution signal is at a logic low level, at this time, it represents that the storage array 40 has been released from the occupied state and can perform data reading and writing based on the next user instruction. At this time, the first-in first-out storage module 20 can retrieve the previously temporarily stored command address information in the next user instruction and send it to the storage array 40 so that the storage array 40 executes the next user instruction. At this time, when the storage array 40 is in an occupied state while executing the next user instruction, the second internal state execution signal corresponding to the next user instruction still needs to be pulled high to a logic high level.

[0047] Exemplarily, as Figure 4 shown, CEB is Figure 2 and Figure 3 the chip select signal described in the embodiment, and CMD1 STA1 and CMD2 STA1 are Figure 2 and Figure 3 the first internal state execution signals described in the embodiment, which are used to represent the states such as the execution of read / write instructions / address decoding and data reading and writing that the user synchronously sees; CMD1 STA2 and CMD2 STA2 are Figure 2 and Figure 3 the second internal state execution signals described in the embodiment, which are used to represent the execution state of the current read / write instruction inside the storage array 40.

[0048] Among them, it is assumed that the current user instruction is CMD1 and the next user instruction is CMD2. After the chip select signal CEB is pulled low, after the memory receives the current user instruction CMD1, the command decoding module 31 receives the current user instruction CMD1 and decodes it, then raises the first internal state execution signal CMD1 STA1 and executes the pipeline delay generation enable signal corresponding to the command, and sends the enable signal to the data buffer circuit 50 so that the data buffer circuit 50 receives the data corresponding to the current user instruction CMD1; while the command decoding module 31 raises the first internal state execution signal CMD1 STA1, the first-in-first-out storage module 20 also raises the second internal state execution signal CMD1 STA2 at this time to indicate that the storage array 40 is in an occupied state due to the current user instruction CMD1. When the data corresponding to the current user instruction CMD1 is exchanged with the data in the storage array 40, the chip select signal CEB is raised. At this time, the first internal state execution signal CMD1 STA1 is pulled low, which indicates that the data information interaction between the user and the memory is completed. However, at this time, the storage array 40 is still in an occupied state due to the current user instruction CMD1. Therefore, the second internal state execution signal CMD1 STA2 is still at a logic high level.

[0049] If the user sends the next user instruction CMD2 to the memory again, at this time, the chip select signal CEB needs to be pulled low again to send the next user instruction CMD2 to the memory. The next user instruction CMD2 will still be received by the command decoding module 31 and corresponding decoding will be completed. At this time, the command decoding module 31 raises the first internal state execution signal CMD2 STA1 and executes the pipeline delay generation enable signal corresponding to the command, and sends the enable signal to the data buffer circuit 50 so that the data buffer circuit 50 receives the data corresponding to the next user instruction CMD2. At this time, since the second internal state execution signal CMD1 STA2 corresponding to the current user instruction CMD1 is still at a logic high level, therefore, the second internal state execution signal CMD2 STA2 corresponding to the next user instruction CMD2 needs to be maintained at a logic low level, that is, the next user instruction CMD2 does not execute the internal operation of the memory. After the current user instruction CMD1 is executed, that is, when the second internal state execution signal CMD1 STA2 corresponding to the current user instruction CMD1 is pulled low to a logic low level, at this time, the parsed command address information corresponding to the next user instruction CMD2 can be taken out from the first-in-first-out storage module 20, and the second internal state execution signal CMD2 STA2 corresponding to the next user instruction CMD2 is raised to perform the corresponding memory operation of the next user instruction CMD2.

[0050] Optionally, as Figure 5 shown, Figure 5 is a schematic structural diagram of the fourth embodiment of the memory of the present application. AsFigure 5 As shown, in this embodiment, the data buffer circuit 50 includes a data input / output module 51, a serial-to-parallel conversion module 52, and a sense amplifier module 53. The data input / output module 51 is connected to the interface module 10. In response to receiving an enable signal, the data input / output module 51 is enabled to perform data read / write with the storage array 40. The serial-to-parallel conversion module 52 is connected to the data input / output module 51 and is used to convert between serial transmission and parallel transmission during the data read / write process. The sense amplifier module 53 is connected to the serial-to-parallel conversion module 52 and the storage array 40 and is used to sense and amplify the data during the data read / write process.

[0051] Among them, in this embodiment, when the user instruction is a read operation, after the data input / output module 51 receives the enable signal corresponding to the read operation, it can output the data information read by the sense amplifier module 53 from the corresponding address signal on the storage array 40. When the user instruction is a write operation, after the data input / output module 51 receives the enable signal corresponding to the write operation, it can also write data to the storage array 40. Serial data transmission transmits the code elements that make up the data and characters bit by bit in sequence over time, and parallel data transmission transmits a fixed number of data and character code elements to the receiving end simultaneously. In this embodiment, the serial-to-parallel conversion module 52 is used to complete the conversion between the above two transmission methods. The sense amplifier module 53 can be set as a sensitive amplifier circuit in this embodiment to amplify and read the data information in the storage array 40.

[0052] Optionally, as Figure 5 shown, the memory of this embodiment further includes a mode configuration module 60. The mode configuration module 60 is respectively connected to the interface module 10 and the serial-to-parallel conversion module 52 and is used to configure the mode of the serial-to-parallel conversion module 52.

[0053] As Figure 5 shown, in this embodiment, the mode configuration module 60 is connected to the interface module 10, receives the mode instruction in the user instruction, and performs corresponding mode configuration on the serial-to-parallel conversion module 52. It can be to convert serial data transmission to parallel data transmission or to convert parallel data transmission to serial data transmission, which is not limited here. The specific mode configuration can be set based on the actual situation.

[0054] Optionally, please refer to Figure 6 , Figure 6 which is a schematic structural diagram of an embodiment of the storage device of the present application. As Figure 6 shown, the storage device 200 of this embodiment includes the memory 100 of any of the above embodiments.

[0055] The above are only the embodiments of the present application, and do not thereby limit the patent scope of the present application. Any equivalent structural or equivalent process transformations made according to the content of the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, are equally included in the patent protection scope of the present application.

Claims

1. A memory, characterized in that, It includes a storage array, an interface module, a decoding circuit, and a first-in-first-out storage module; wherein, The pins of the interface module for transmitting the command address information and data information in the user instruction are multiplexed; The decoding circuit is connected between the interface module and the first-in-first-out storage module to parse the command address information; The first-in-first-out storage module is arranged between the storage array and the decoding circuit. The storage array is in an occupied state based on the execution of the memory operation for the current user instruction. In response to the interface module receiving the next user instruction, the decoding circuit parses the command address information of the next user instruction, and the first-in-first-out storage module temporarily stores the parsed command address information in the next user instruction. After the storage array releases the occupied state, the first-in-first-out storage module retrieves the temporarily stored parsed command address information in the next user instruction and sends it to the storage array for execution.

2. The memory according to claim 1, wherein It further includes: A data buffer circuit, connected between the interface module and the storage array and connected to the decoding circuit, and cooperates with the storage array to execute the memory operation based on the parsed command address information.

3. The memory according to claim 2, wherein The interface module is further configured to receive a chip select signal issued by the host controller. In response to the chip select signal being pulled low, the interface module allows the reception of user instructions; in response to the chip select signal being pulled high, the interface module prohibits the reception of the user instructions.

4. The memory according to claim 3, wherein The decoding circuit is further configured to generate a first internal state execution signal based on the decoding state. In response to the chip select signal being pulled low and the decoding circuit being operating on the current user instruction, the first internal state execution signal is at a logic high level. In response to the chip select signal being pulled high, the first internal state execution signal is at a logic low level.

5. The memory according to claim 4, wherein The decoding circuit includes: A command decoding module, connected to the first-in-first-out storage module, the interface module, and the data buffer circuit. The command decoding module decodes the command address information in the current user instruction and then pulls high the first internal state execution signal, and generates a corresponding enable signal after a fixed pipeline delay to enable the data buffer circuit to receive the data corresponding to the current user instruction.

6. The memory according to claim 5, wherein The decoding circuit further includes: An address decoding module, connected to the first-in-first-out storage module and the interface module. The address decoding module sequentially decodes the command address information in the current user instruction and the next user instruction to obtain an address signal corresponding to the command address information for addressing in the storage array.

7. The memory according to claim 1, wherein The first-in-first-out storage module is configured to generate a second internal state execution signal based on the internal state of the storage array. When the current user instruction occupies the storage array, the second internal state execution signal is at a logic high level; when the current user instruction releases the occupancy of the storage array, the second internal state execution signal switches to a logic low level; when the second internal state execution signal switches to the logic low level, the first-in-first-out storage module retrieves the command address information in the parsed next user instruction that is temporarily stored and sends it to the storage array for execution.

8. The memory according to claim 2, wherein, The data buffer circuit includes: A data input / output module, which is connected to the interface module and enables the data input / output module in response to receiving an enable signal, so that the data input / output module can perform data reading and writing with the storage array; A serial-to-parallel conversion module, which is connected to the data input / output module and is used to convert between serial transmission and parallel transmission during data reading and writing; A sense amplifier module, which is connected to the serial-to-parallel conversion module and the storage array and is used to sense and amplify data during data reading and writing.

9. The memory according to claim 8, characterized in that, characterized in that, It further includes a mode configuration module, which is respectively connected to the interface module and the serial-to-parallel conversion module and is used to configure the mode of the serial-to-parallel conversion module.

10. The memory according to claim 1, characterized in that, The interface module includes a multi-IO serial interface.

11. A storage device, characterized in that, It includes the memory according to any one of claims 1-10.

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