Method for preparing electronic chip

Abstract

The invention relates to a method for preparing an electronic chip. A method of manufacturing an electronic chip is provided. An example method includes fabricating an electronic chip having passivated flanks from a semiconductor substrate having a first surface covered with connection terminals and having a chip formed therein, the method including: depositing a protective layer onto the first surface of the substrate; forming a groove or a cavity between the chips; depositing an insulating layer into the trench or the cavity by atomic layer deposition; and removing the protective layer.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of priority of French Patent Application No. 2400541, entitled "Procédé de fabrication de puces électroniques", filed on January 19, 2024, which is incorporated herein by reference in its entirety to the maximum extent permitted by law. Technical field

[0003] This disclosure relates to the field of CSP (chip - scale package) chip types. More particularly, it relates to methods for manufacturing bare die or bare chips. Background art

[0004] A bare chip includes a substrate made of semiconductor material, inside which electronic circuits are fabricated. The substrate is covered with connection terminals to allow the assembly of the chip, for example, with a printed circuit board. During chip assembly, the connection terminals are soldered or welded to the metal tracks or components of the printed circuit. However, during assembly, the solder may rise along the flanks of the chip. Now, since the sides of the chip are made of semiconductor material, this may cause a loss of electrical performance (short - circuits, leakage currents...). Therefore, it is necessary to avoid this phenomenon.

[0005] Such chips are particularly advantageous in many fields. Summary of the invention

[0006] It is necessary to at least partially improve certain aspects of known methods for manufacturing electronic chips.

[0007] This object is achieved by a method for manufacturing an electronic chip with passivated flanks from a semiconductor substrate, the semiconductor substrate having a first surface covered with connection terminals and having a chip formed inside it, the method comprising the following steps:

[0008] - depositing a protective layer onto the first surface of the substrate,

[0009] - forming trenches or cavities between the chips,

[0010] - depositing a ceramic insulating layer into the trenches or cavities by atomic layer deposition,

[0011] - removing the protective layer.

[0012] According to an embodiment, trenches are formed that extend from the first surface of the substrate to the second surface of the substrate.

[0013] According to an embodiment, cavities are formed by partially cutting the substrate from the first surface.

[0014] According to an embodiment, the method includes thinning the substrate from a second surface of the substrate to reach a cavity during a step.

[0015] According to an embodiment, the insulating layer is made of alumina.

[0016] According to an embodiment, the protective layer is a water-soluble layer.

[0017] The method according to any one of claims 1 to 5, wherein the protective layer (130) is an adhesive layer sensitive to ultraviolet radiation.

[0018] The protective layer may be a first adhesive layer, and its adhesive properties may be reduced to have a lower final adhesiveness for peeling. In various embodiments, the protective layer may be an ultraviolet strip.

[0019] According to an embodiment, before or after depositing the insulating layer, the method includes a step of subjecting the protective layer to ultraviolet radiation during a step to reduce its adhesive properties.

[0020] According to an embodiment, the step of removing the protective layer is performed by bonding an additional adhesive layer and by simultaneously removing the additional adhesive layer and the protective layer.

[0021] This object is achieved by an electronic chip having passivated flanks, the electronic chip including a semiconductor substrate having a first surface, a second surface, and flanks covered with connection terminals, and at least a part of the flanks is formed by a ceramic insulating layer extending from the first surface of the substrate.

[0022] According to an embodiment, the insulating layer covers a part of the first surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The foregoing features and advantages, as well as other features and advantages, will be described in detail in the remainder of the disclosure of specific embodiments given in an illustrative but non-limiting manner, with reference to the accompanying drawings, in which:

[0024] Figure 1A 、 Figure 1B 、 Figure 1C 、 Figure 1D 、 Figure 1E and Figure 1F show cross-sectional views illustrating steps of a method of manufacturing an electronic chip having passivated flanks according to a specific embodiment;

[0025] Figure 2A 、 Figure 2B 、 Figure 2C 、 Figure 2D 、 Figure 2E 、 Figure 2F and Figure 2G show cross-sectional views illustrating steps of a method of manufacturing an electronic chip having passivated flanks according to another specific embodiment;

[0026] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E and Figure 3F show a cross - sectional view of steps illustrating a method of manufacturing an electronic chip with passivated side wings according to another specific embodiment. Detailed Description

[0027] Similar features are denoted by like reference numerals in the respective figures. In particular, structural and / or functional features common to the various embodiments may have the same reference numerals, and the same structures, dimensions, and material properties may be arranged.

[0028] For clarity, only the steps and elements useful for understanding the described embodiments are illustrated and described in detail.

[0029] Unless otherwise stated, when referring to two elements connected together, this means a direct connection with no intermediate elements other than a conductor, and when referring to two elements coupled together, this means that the two elements may be connected or they may be coupled via one or more other elements.

[0030] In the following description, when referring to terms that define absolute positions such as "edge", "rear", "top", "bottom", "left", "right", etc., or terms that define relative positions such as "above", "below", "upper", "lower", etc., or terms that define directions such as "horizontal", "vertical", etc., unless otherwise stated, they refer to the orientation of the drawings.

[0031] Unless otherwise stated, the expressions "about", "approximate", "substantially", and "around" mean plus or minus 10%, preferably plus or minus 5%.

[0032] A method of manufacturing a bare die or bare chip with passivated side wings includes at least the following steps:

[0033] a) Providing a semiconductor substrate 110 having a first surface 111 covered with connection terminals 107 and having a chip 100 formed therein,

[0034] b) Depositing a protective layer 130 onto the first surface 111 of the substrate 110 to cover the connection terminals 107,

[0035] c) Forming trenches or cavities 120 between the chips 100,

[0036] d) Depositing a ceramic insulating layer 121 into the trenches or cavities 120 by atomic layer deposition,

[0037] e) Remove the protective layer 130.

[0038] According to a first alternative embodiment, with reference to Figures 1A to 1F and Figures 2A to 2G , a method for manufacturing an electronic chip with passivated flanks comprises the following steps:

[0039] a) Provide a semiconductor substrate 110 having a first surface 111 covered with connection terminals 107 and having a chip 100 formed therein ( Figure 1A , Figure 2A ),

[0040] b) Deposit a protective layer 130 ( Figure 1B , Figure 2B ) on the first surface 111 of the substrate 110, the protective layer 130 being soluble in an aqueous or organic solvent, preferably in water,

[0041] − Preferably, form an opening 119 ( Figure 1C , Figure 2C ) in the protective layer 130,

[0042] c) Form trenches or cavities 120 between the chips 100, the width of the trenches 120 being less than or equal to, preferably less than, the width of the opening 119 ( Figure 1D , Figure 2D ),

[0043] d) Deposit a ceramic insulating layer 121 into the trenches or cavities 120 by atomic layer deposition ( Figure 1E , Figure 2E ),

[0044] e) Remove the protective layer 130 by dissolving the protective layer 130 in an aqueous or organic solvent ( Figure 1F , Figure 2F ),

[0045] − Optionally, thin the substrate 110 on the back side ( Figure 2G ).

[0046] According to a second alternative embodiment, with reference to Figures 3A to 3F , the method may comprise the following steps:

[0047] a) Provide a semiconductor substrate 110 having a first surface 111 covered with connection terminals 107 and having a chip 100 formed therein,

[0048] b) Deposit a protective layer 130 ( Figure 3A ) on the first surface 111 of the substrate 110, for example, the adhesion of the protective layer being sensitive to ultraviolet radiation,

[0049] - Optionally, an opening 119 is formed in the protective layer 130,

[0050] c) A trench or cavity 120 is formed between the chips 100 ( Figure 3B ),

[0051] d) A ceramic insulating layer 121 is deposited into the trench or cavity 120 by atomic layer deposition ( Figure 3C ),

[0052] - The adhesion property of the protective layer 130 is reduced, for example, by exposing the protective layer to ultraviolet radiation to reduce its adhesion property ( Figure 3D ),

[0053] - Optionally, the substrate 110 is back-thinned,

[0054] e) The protective layer 130 is removed by bonding an additional adhesive layer 131 and simultaneously removing the adhesive layer 130 and the additional adhesive layer ("peeling") ( Figure 3E and Figure 3F ).

[0055] In various embodiments, the protective layer can be a first adhesive layer, the adhesion property of which can be reduced to have a lower final adhesiveness for peeling. In various embodiments, the protective layer can be an ultraviolet strip.

[0056] According to this second embodiment, the adhesion force of the protective layer 130 is high enough to adhere during deposition and low enough that once its adhesion property is reduced, it will not cause the components to move during removal. For example, the adhesive portion of the protective layer is sensitive to ultraviolet radiation.

[0057] With this method, the sides 113 of the chips 100 thus obtained are passivated by the insulating layer 121. This avoids potential contamination (due to defective assembly with the board), and the electrical performance is not degraded.

[0058] In step a), the fabrication of the (one or more) discrete components and / or integrated circuits has been completed. The chips 100 are formed in the same substrate 110 and have not been singulated yet.

[0059] The substrate 110 includes a first surface 111 (upper surface or front surface) and a second surface 112 (lower surface or back surface). The two surfaces 111 and 112 are parallel to each other. The surfaces 111 and 112 are connected together by sidewalls.

[0060] The substrate 110 is, for example, a semiconductor substrate, such as made of silicon. It can also be made of SiC.

[0061] The substrate 110 has a thickness in the range of, for example, from 100 to 1200 μm, preferably from 300 to 900 μm, for example, a thickness of approximately 725 μm.

[0062] One or more connection terminals 107 (also referred to as electrical contacts) are formed on the upper surface 111 of the substrate 110 of the electronic chip 100, enabling it to be connected to other components (chips or electronic devices). Preferably, at least two connection terminals 107 are formed on the upper surface 111 of the substrate 110.

[0063] The electrical connection terminals 107 are located at a distance, for example, from 10 to 30 μm from the sidewall of the chip. The electrical connections 107 can be positioned on the upper surface 111 of the chip 100 or flush with the upper surface 111 (i.e., at the level of the upper surface 111 of the chip 100).

[0064] The electrical connection terminals 107 are also referred to as "UBM" (i.e., "under bump metallization"). The electrical connection terminals 107 are made of a conductive material. The electrical connection terminals 107 advantageously include at least one of the following elements: gold, titanium, nickel, copper, or tungsten. Preferably, they include gold.

[0065] The chip 100 can include one or more discrete components. The (one or more) discrete components are, for example, selected from transistors, diodes, thyristors, triacs, filters, etc. The chip 100 can include one or more electronic circuits. The chip 100 enables different electronic functions to be implemented.

[0066] The substrate provided in step a) is positioned on the support 200. The support 200 is generally an adhesive strip.

[0067] During step b), a protective layer is formed on the first surface 111 of the substrate 110. This protective layer covers the connection terminals 107 and protects the connection terminals 107 during the deposition of the insulating layer 121.

[0068] According to a first advantageous alternative embodiment, the protective layer 130 is a layer soluble in a solvent. Preferably, it is water-soluble. For example, it is a polymer such as carboxymethyl cellulose. These can also include vinyl acetate-ethylene copolymer (VAE), ethylene-vinyl acetate emulsion (EVA), polyvinyl alcohol (PVOH), and polyanionic cellulose (PAC). Products sold under the reference TOK TLDP-300 or reference DaeCoat can also be selected.

[0069] According to a second advantageous alternative embodiment, the protective layer 130 is an adhesive layer whose adhesive properties can be reduced when affected by external factors. For example, it can be sensitive to ultraviolet radiation. By being sensitive to ultraviolet radiation, this means that when the layer is exposed to ultraviolet radiation (usually between 280 and 400 nm), its adhesive properties are greatly or even completely reduced. Then the layer 130 can be easily removed by peeling.

[0070] The protective layer 130 can be fully adhesive. For example, it can be an acrylic adhesive on a polymer film made of polyethylene (PE), polyethylene terephthalate (PET), polyvinyl chloride (PVC), or polyolefin (PO), especially polyethylene (PE) or polypropylene (PP).

[0071] Alternatively, it can include a first adhesive part sensitive to UV radiation and a second part that is non - adhesive and / or insensitive to UV radiation. The first part is in contact with the substrate 110. For example, it can be a thin adhesive layer and a non - adhesive base, such as made of polyolefin.

[0072] The protective layer 130 sensitive to ultraviolet radiation can be exposed to radiation before or after the deposition of the insulating layer 121.

[0073] After step b), the method can include a step of forming an opening 119 in the protective layer 130 during that time. Depending on the nature of the protective layer, the opening can be formed by mechanical action (especially sawing) or by laser. For a protective layer 130 soluble in a solvent, a dry process such as a laser process will be preferred.

[0074] During step c), a cavity or trench 120 is formed in the substrate 110.

[0075] The cavity or trench 120 defines the lateral profile of the chip 100. More particularly, the cavity or trench 120 extends from the upper surface 111 of the substrate 110. The trench or cavity 120 has a specified depth and width to ensure the precise separation of the chip, for example, during trench formation or during the thinning step of the substrate 110.

[0076] According to a first alternative embodiment, for example as Figure 1D and Figure 3B shown, the trench completely traverses the substrate 110, that is, the substrate 110 is cut from the first surface 111 to the second surface 112.

[0077] The thickness of the trench 120 is, for example, in the range from 10 to 80 μm.

[0078] According to a second alternative embodiment, for example as Figure 2D shown, the cavity 120 has a depth less than the thickness of the substrate 110.

[0079] The depth of the cavity 120 is, for example, in the range from 10 to 300 μm, preferably in the range from 20 to 250 μm.

[0080] The thickness of the cavity 120 is, for example, in the range from 10 to 80 μm.

[0081] The bottom of the cavity can be flat or concave.

[0082] This step c) is carried out by means of a cutting device. The cutting device is, for example, a mechanical etching tool (such as a saw), or a laser etching tool. According to a preferred embodiment, the cutting device is a laser, and preferably, the die is singulated by a laser (laser cutting or stealth cutting).

[0083] Preferably, for the water-soluble protective layer 130, the cutting is laser cutting. For the adhesive protective layer 130, the cutting can be mechanical cutting.

[0084] When an opening 119 has been previously formed in the protective layer 130, the width of the trench or cavity 120 is less than or equal to the width of the opening 119. Preferably, the width of the trench or cavity 120 is less than the width of the opening 119.

[0085] The opening 119 and the trench / cavity 120 can be formed in the same step, so that they have the same width.

[0086] During step d), an insulating layer 121 is deposited. The deposition is carried out on the front side 111 of the substrate 110. The deposition is a full-wafer deposition. The insulating layer 121 is deposited into the cavity 120, on the protective layer 130, and, if relevant, at the level of the opening 119 on the first surface of the substrate 111.

[0087] The insulating layer 121 is deposited by atomic layer deposition (ALD). The deposition is a conformal deposition, even for high-aspect-ratio topologies.

[0088] The insulating layer 121 is made of ceramic.

[0089] The insulating layer 121 can be a nitride or an oxide. It can also be a boride or a carbide. Preferably, the insulating layer 121 is alumina. It can also be TiO2 or Y2O3.

[0090] During step e), the protective layer is removed. Removing the protective layer 130 enables the simultaneous removal of the part of the insulating layer 121 that has been deposited thereon.

[0091] When the protective layer 130 is a layer soluble in a solvent, it is brought into contact with such a solvent, for example, by immersion or preferably by high-pressure cleaning, to remove it. The solvent can be an organic solvent or an aqueous solvent. Preferably, the solvent is water.

[0092] When the protective layer 130 is an adhesive layer, it is removed according to the following sub-steps:

[0093] − An additional adhesive layer 131 is bonded above the protective layer 130, and in particular on the portion of the insulating layer 121 that has been deposited on the protective layer 130 ( Figure 3E ), and then

[0094] − The additional adhesive layer 131 is removed ( Figure 3F ).

[0095] Since the additional adhesive layer 131 is bonded to the protective layer via the insulating layer 121, when the additional adhesive layer 131 is removed, this enables the simultaneous removal of the protective layer 130.

[0096] The adhesive properties are selected such that when step e) is performed, a stack including the following successive layers is removed: the protective layer 130, the portion of the insulating layer 121 located on the protective layer 130, the additional adhesive layer 131.

[0097] The method may also include a step of back thinning ( Figure 2G ). This step is preferably performed before step e). It can also be performed after step e). To this end, the structure is flipped and bonded to the support 201 via its front face 111. The support 201 is, for example, an adhesive strip. Then, the structure is thinned from its back face 112 such that its substrate 110 has its final thickness. The thinning step is preferably performed when forming the cavity in step c) in order to thin the substrate 110 all the way to the cavity 120 to separate the substrate of the chip 100.

[0098] At the end of the method, the obtained chip 100 includes passivated flanks 113. The passivation is due to the presence of the ceramic insulating layer 121. When assembling the unit on a PCB, the solder material does not wet the insulating layer 121.

[0099] According to an advantageous variant, only a part of the side face 113 can be passivated. The side face includes a first part made of semiconductor material formed in the substrate 110 and a second part made of the insulator 121. The passivated part of the flank is the part closest to the active region (i.e., close to the UBM).

[0100] According to another advantageous variant, the entire side face 113 is passivated.

[0101] When an opening 119 has been formed in the protective layer 130, the first surface 111 of the substrate 110 is also locally covered by the insulating layer 121, which then (partially or entirely) covers the side face 113 and continues onto the first surface 111 of the substrate 110.

[0102] The chip can be a bump-less CSP chip with simple, solderable, conductive metal contact areas (UBM, metal pads, etc.), or a bumped CSP chip with additional connections (bumps, pillars, etc.) protruding from the chip itself.

[0103] Then, the chip 100 can be bonded to an external device, e.g., a printed circuit board or other component, through its upper surface 111.

[0104] For this purpose, solder is positioned between the chip 103 and the external device. During soldering, the chip can still operate normally even if the solder rises along the sides of the chip.

[0105] Such CSP-type electronic chips are used in many industrial fields, especially in the telephone field, the automotive field, or the medical field.

[0106] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations can be combined, and other variations will occur to those skilled in the art.

[0107] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variations is within the capabilities of those skilled in the art.

Claims

1. A method of manufacturing an electronic chip with passivated flanks from a semiconductor substrate, the semiconductor substrate having a first surface covered with connection terminals and a chip formed therein, the method comprising: Depositing a protective layer onto the first surface of the substrate, wherein the protective layer is a water-soluble layer or an adhesive layer sensitive to ultraviolet radiation; Forming trenches or cavities between the chips; Depositing a ceramic insulating layer into the trenches or the cavities by atomic layer deposition, wherein the ceramic insulating layer is made of alumina; And Removing the protective layer.

2. The method according to claim 1, wherein, Forming trenches that extend from the first surface of the substrate to the second surface of the substrate.

3. The method according to claim 1, wherein Forming cavities by partially cutting the substrate from the first surface.

4. The method according to claim 3, wherein, The method includes the step of thinning the substrate from the second surface of the substrate during to reach the cavities.

5. The method according to claim 1, wherein The insulating layer is made of alumina.

6. The method according to claim 1, wherein, The protective layer is a water-soluble layer.

7. The method according to claim 1, wherein The protective layer is an adhesive layer sensitive to ultraviolet radiation.

8. The method according to claim 7, wherein, The method further includes: subjecting the protective layer to ultraviolet radiation before or after depositing the insulating layer to reduce its adhesive properties.

9. The method according to claim 7, wherein Removing the protective layer by bonding an additional adhesive layer and by simultaneously removing the additional adhesive layer and the protective layer.

10. An electronic chip with passivated flanks, the electronic chip including a semiconductor substrate having a first surface, a second surface, and a plurality of flanks covered with connection terminals, wherein at least a portion of the plurality of flanks is formed by a ceramic insulating layer extending from the first surface of the substrate.

11. The electronic chip according to claim 10, wherein, The insulating layer covers a portion of the first surface.

12. The electronic chip according to claim 10, wherein, The trenches or cavities have a specified depth and width to ensure precise separation of the chips.

13. A method of manufacturing an electronic chip with passivated flanks from a semiconductor substrate, the semiconductor substrate having a first surface covered with connection terminals and a chip formed therein, the method comprising: Depositing a protective layer onto the first surface of the substrate, wherein the protective layer is an adhesive layer, and the adhesive properties of the adhesive layer can be reduced to have a lower final adhesiveness for peeling; Forming trenches or cavities between the chips; Depositing a ceramic insulating layer into the trenches or the cavities by atomic layer deposition, wherein the ceramic insulating layer is made of alumina; And Removing the protective layer.

14. The method according to claim 13, wherein The adhesive layer consists of an adhesive sensitive to ultraviolet radiation.

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