Optical-communication module packaging structure and preparation method

Abstract

The embodiments of the present application relate to the technical field of semiconductor packaging. Disclosed are an optical-communication module packaging structure and a preparation method. The optical-communication module packaging structure comprises a packaging substrate, wherein a first recess is provided in an upper surface of the packaging substrate, a first chip is embedded in the first recess, an upper surface of the first chip is flush with the upper surface of the packaging substrate, and the upper surface of the first chip is an active surface; and a first packaging structure, wherein a second chip is packaged in the first packaging structure, the first packaging structure is arranged on the upper surface of the packaging substrate and the upper surface of the first chip, the first packaging structure is separately electrically connected to the packaging substrate and the first chip by means of a plurality of first solders isolated from each other, the first chip is an optical chip, and the second chip is an electronic chip. The optical-communication module packaging structure and the preparation method provided in the embodiments of the present application can satisfy a short interconnection length between packaged chips and also reduce packaging costs.

Description

Optical communication module packaging structure and fabrication method

[0001] This application claims priority to Chinese Patent Application No. 202410782048.6, filed on June 17, 2024, entitled "Packaging Structure and Preparation Method of Optical Communication Module", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor packaging technology, and in particular to an optical communication module packaging structure and preparation method. Background Technology

[0003] With the development of technologies such as communication and artificial intelligence, the demand for massive data flow and transfer is increasing, and the demand for data transmission is rapidly rising. This requires optical modules to have high bandwidth and high integration. In order to meet the functional requirements of optical communication modules, the interconnection length between the electrical chips (such as driver chips and transimpedance amplifier chips) and optical chips (such as modem chips and photodetector chips) integrated in the optical communication module is as short as possible to meet the requirements of high-bandwidth interconnection signals.

[0004] In existing optical communication module solutions, electrical and optical chips are typically placed flat or vertically, with the active surface of the optical chip located away from the substrate. The leads of the electrical and optical chips are then connected to the substrate via wires to achieve interconnection with other chips. This approach, limited by the lead length, results in long link paths and poor high-bandwidth signal quality. Therefore, the industry has proposed a flip-chip approach, horizontally bonding the optical and electrical chips to the substrate at intervals, and achieving interconnection between them through wiring layers in the substrate. This approach requires bump processing on the active surface of the optical chip, which can easily lead to optical port contamination, resulting in high process complexity and cost. Furthermore, the interconnection path between the electrical and optical chips on the substrate cannot be further reduced, decreasing the integration density of the optical communication module. Therefore, reducing the process complexity of optical communication module packaging, minimizing the interconnection path between chips, and improving the integration density of optical communication modules have become problems that need to be solved. Summary of the Invention

[0005] The packaging structure and fabrication method of the optical communication module provided in this application can achieve ultra-short interconnections between electrical and optical chips in a low-cost manner, meeting the requirements of ultra-high bandwidth. To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, embodiments of this application provide a packaging structure for an optical communication module. The packaging structure includes: a packaging substrate, a first groove formed on the upper surface of the packaging substrate, a first chip embedded in the first groove, the upper surface of the first chip being flush with the upper surface of the packaging substrate, and the upper surface of the first chip being an active surface; a first packaging structure, in which a second chip is packaged; wherein the first packaging structure is disposed on the upper surface of the packaging substrate and the upper surface of the first chip, and the first packaging structure is electrically connected to the packaging substrate and the first chip respectively through a plurality of mutually isolated first solders.

[0007] The first chip in this embodiment can be an optical chip to realize the transmission and reception of optical signals and the conversion of photoelectric signals, such as including but not limited to: one or more of the following: a coupler (e.g., a side coupler or a grating coupler) for coupling fiber optic array units, a photodetector, or a modem. The second chip can be an electrical chip to realize the amplification and processing of electrical signals, such as including but not limited to: a driver chip or a transamplifier chip.

[0008] The optical communication module packaging structure provided in this application provides a first groove on a packaging substrate, in which a first chip (e.g., an optical chip) is placed, making the first chip flush with the upper surface of the packaging substrate. A packaging structure containing a second chip (e.g., an electrical chip) is then placed on top of the first chip and the packaging substrate, spanning the upper surface of the packaging substrate and the upper surface of the first chip. This allows the second chip to occupy only a portion of the upper surface area of ​​the first chip. The upper surface of the first chip can be an active surface, and the ports on the second chip can be directly interconnected with the active surface of the first chip via solder. This reduces the interconnection path between the first and second chips, which is beneficial for achieving a large bandwidth in the optical communication module. Furthermore, by setting the active surface of the first chip upwards, the optical chip does not need to use flip-chip bonding, thus reducing the process complexity of the optical communication module packaging. Additionally, when the first chip has complex optical waveguide and optical port structures, the complex optical waveguide and optical port structures can be better laid out, improving the integration of the optical communication module. In addition, in this embodiment of the application, by setting the upper surface of the first chip flush with the upper surface of the packaging substrate, it is possible to avoid using different solders to electrically connect the first packaging structure to the packaging substrate and the first chip respectively (for example, using large solder balls to electrically connect the first packaging structure to the packaging substrate and using small solder balls to electrically connect the first packaging structure to the first chip), thereby improving the stability of the first packaging structure on the packaging substrate and the first chip, and also reducing the process complexity of the optical communication module packaging structure.

[0009] Based on the first aspect, in one possible implementation, the first packaging structure further includes a third chip, which is an electrical chip; the first packaging structure also includes a carrier board, the second chip and the third chip are disposed on the upper surface of the carrier board, and the lower surface of the carrier board is connected to the upper surface of the packaging substrate and the upper surface of the first chip respectively through mutually isolated first solder.

[0010] Based on the first aspect, in one possible implementation, the plurality of first solders include a plurality of second solders for connecting the first package structure and the upper surface of the package substrate, with insulating material filling between the plurality of second solders; a blocking structure is provided on the upper surface of the package substrate, the blocking structure being disposed on the side of the upper surface of the package substrate and in a position region close to the first chip, the blocking structure being used to prevent insulating material from flowing into the first groove and onto the first chip.

[0011] By setting up a blocking structure, the insulating material (also known as the underfill material) filling the space between the second solders can be prevented from flowing into the first groove and the first chip, thereby preventing the first chip from failing due to the inflow of insulating material.

[0012] Based on the first aspect, in one possible implementation, a fiber array unit is disposed on the side of the first chip away from the first packaging structure.

[0013] Based on the first aspect, in one possible implementation, the first packaging structure may further include a fourth chip disposed on the upper surface of the carrier board; the fourth chip is electrically connected to the second chip and the third chip through at least one wiring layer on the carrier board.

[0014] Based on the first aspect, in one possible implementation, the optical communication module packaging structure further includes a heat sink, which includes a first part disposed on the upper surface of the packaging substrate and a second part disposed on the first packaging structure. The second part of the heat sink is perpendicularly disposed to the first part of the heat sink and is in contact with each other. The first part and the second part of the heat sink form a semi-enclosed structure for the first packaging structure. The upper surfaces of the second chip and the third chip are deposited with a first thermal interface material, and the second part of the heat sink is separated from the second chip and the third chip by the first thermal interface material.

[0015] Based on the first aspect, in one possible implementation, a fourth chip is further disposed on the upper surface of the packaging substrate, and the fourth chip is disposed side by side with the first packaging structure at intervals; the lower surface of the fourth chip is electrically connected to the packaging substrate through a third solder; wherein, the fourth chip is electrically connected to the first packaging structure through the third solder, the packaging substrate and the second solder.

[0016] When a fourth chip is packaged in the optical communication module packaging structure, the fourth chip and the first packaging structure are arranged side-by-side and spaced apart on the packaging substrate. The chips packaged in the first packaging structure and the fourth chip are directly interconnected through the wiring layer on the packaging substrate. This eliminates the need to interconnect the chips packaged in the first packaging structure via the first chip and the fourth chip, and also eliminates the need for an FPC to interconnect the fourth chip with the chips packaged in the first packaging structure. Therefore, the optical communication module packaging structure provided in this application, when containing both a fourth chip and a first packaging structure, can shorten the interconnection path between the chips and improve the bandwidth of the optical communication module.

[0017] Based on the first aspect, in one possible implementation, the fourth chip is disposed inside the heat sink, and the fourth chip is disposed between the first part of the heat sink and the first package structure; a second thermal interface material is deposited on the upper surface of the fourth chip, and the second part of the heat sink is separated from the fourth chip by the second thermal interface material.

[0018] Based on the first aspect, in one possible implementation, the heat sink further includes a third portion disposed on the upper surface of the packaging substrate, wherein the third portion of the heat sink is perpendicularly disposed to the first portion of the heat sink and in contact with each other; wherein the third portion of the heat sink is disposed between the fourth chip and the first packaging structure.

[0019] Based on the first aspect, in one possible implementation, a second groove is formed on the upper surface of the packaging substrate, and a fourth chip is disposed in the second groove. The upper surface of the fourth chip is flush with the upper surface of the packaging substrate. The optical communication module packaging structure further includes a second packaging structure, in which a fifth chip and a sixth chip are encapsulated. The second packaging structure is disposed above the upper surface of the packaging substrate and the upper surface of the fourth chip, and spans across the upper surface of the packaging substrate and the upper surface of the fourth chip. The second packaging structure is connected to the upper surface of the packaging substrate and the upper surface of the fourth chip respectively through a plurality of mutually isolated fourth chips. A seventh chip is also disposed on the upper surface of the packaging substrate, and the seventh chip is disposed between the first packaging structure and the second packaging structure. The first packaging structure is electrically connected to the fourth chip through at least one wiring layer on the packaging substrate, and the second packaging structure is electrically connected to the fourth chip through at least one wiring layer on the packaging substrate.

[0020] Secondly, embodiments of this application provide a board card, which includes a printed circuit board, a power management chip, and an optical communication module packaging structure as described in the first aspect; the power management chip and the optical communication packaging structure are disposed on the printed circuit board and connected through conductive lines on the printed circuit board.

[0021] Thirdly, embodiments of this application provide a communication device, which includes a power supply module and a board as described in the second aspect; the board is connected to the power supply module, and the power supply module supplies power to the first chip and the second chip packaged in the optical communication module packaging structure through a power management chip on the board.

[0022] Fourthly, embodiments of this application provide a method for fabricating an optical communication module packaging structure. The method includes: obtaining a packaging substrate with a first groove; embedding a first chip in the first groove, wherein the upper surface of the first chip is flush with the upper surface of the packaging substrate, and the upper surface of the first chip is an active surface; and depositing a pre-prepared first packaging structure onto the upper surface of the first chip and the upper surface of the packaging substrate using a plurality of first solders, wherein the first packaging structure spans the upper surface of the first chip and the upper surface of the packaging substrate, and a second chip is packaged in the first packaging structure; the first chip is an optical chip, and the second chip is an electrical chip.

[0023] Based on the fourth aspect, in one possible implementation, the first packaging structure also encapsulates a third chip, and the first packaging structure is one of the following: a flip-chip ball grid array packaging structure, a flip-chip level packaging structure, a fan-out packaging structure, a 2.5D through-silicon via packaging structure, a 3D stacked packaging structure, or a glass substrate packaging structure.

[0024] Based on the fourth aspect, in one possible implementation, obtaining a packaging substrate includes: providing an initial substrate, defining a first region on the initial substrate for setting a first chip, etching the first region to form a first groove; preparing at least one wiring layer on a second region on the initial substrate adjacent to the first region; and forming a packaging substrate based on the preparation result.

[0025] Based on the fourth aspect, in one possible implementation, the method further includes: a fourth chip is disposed on the upper surface of the packaging substrate and on the side of the first packaging structure, the fourth chip being disposed parallel to and spaced apart from the first packaging structure; the fourth chip is connected to the first packaging structure through at least one wiring layer.

[0026] It should be understood that the second to fourth aspects of this application are consistent with the technical solutions of the first aspect of this application, and the beneficial effects achieved by each aspect and the corresponding feasible implementation are similar, so they will not be described again. Attached Figure Description

[0027] Figures 1A and 1B are schematic diagrams of the packaging structure of optical communication modules in the prior art;

[0028] Figure 2 is a schematic diagram of the optical communication module packaging structure provided in an embodiment of this application;

[0029] Figure 3A is another structural schematic diagram of the optical communication module packaging structure provided in the embodiment of this application;

[0030] Figure 3B is another structural schematic diagram of the optical communication module packaging structure provided in the embodiment of this application;

[0031] Figure 4 is another structural schematic diagram of the optical communication module packaging structure provided in the embodiment of this application;

[0032] Figure 5 is another structural schematic diagram of the optical communication module packaging structure provided in the embodiment of this application;

[0033] Figure 6 is another structural schematic diagram of the optical communication module packaging structure provided in the embodiment of this application;

[0034] Figure 7 is a flowchart of the fabrication method of the optical communication module packaging structure shown in Figure 3A provided in the embodiment of this application;

[0035] Figures 8A-8G are schematic diagrams of the various structures in the fabrication process of the optical communication module packaging structure shown in Figure 3A. Detailed Implementation

[0036] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the embodiments of this application.

[0037] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0038] The terms "first" and "second," etc., in the specification and drawings of the embodiments of this application are used to distinguish different objects or to distinguish different treatments of the same object, rather than to describe a specific order of objects.

[0039] Furthermore, the terms "comprising" and "having," and any variations thereof, used in the description of the embodiments of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the steps or units listed, but may optionally include other steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0040] It should be noted that in the description of the embodiments of this application, the words "exemplarily" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design scheme described as "exemplarily" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of the words "exemplarily" or "for example" is intended to present the relevant concepts in a specific manner.

[0041] In the description of the embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0042] Please refer to Figure 1A, which is a schematic diagram of a package structure for an optical communication module in the prior art. As shown in Figure 1A, the optical communication module includes an optical module GT, which includes an optical chip and an electrical chip. The electrical chip is mounted on the upper surface of the optical chip via solder balls. The leads of both the optical and electrical chips are led to the substrate via leads to connect the electrical and optical chips to other chips. As can be seen from Figure 1A, since the upper surface of the optical chip is an active surface, relatively long leads are required to bring the leads of the optical and electrical chips to the substrate. This results in a long signal transmission path and poor high-bandwidth signal quality. For example, when the optical module GT is packaged with a digital signal processing (DSP) chip, both the DSP chip and the optical module GT are mounted on the substrate, and the electrical chips in the DSP chip and the optical module GT are interconnected through wiring layers on the substrate. As can be seen from Figure 1A, the interconnection path between the DSP chip and the optical module GT on the PCB is long, resulting in significant passive losses and making it unsuitable for the evolution of high baud rates. In addition, since the electrical chip occupies too much area of ​​the optical chip, when the optical chip has a complex optical waveguide and optical port structure, the existing optical communication module solutions cannot lay out the complex optical waveguide and optical port structure well, which reduces the integration of the optical communication module.

[0043] Therefore, the industry has further proposed using a flip-chip method to package the optical and electrical chips, as shown in Figure 1B. In Figure 1B, the optical and electrical chips are flip-chip bonded to substrate 1 with horizontal spacing. The interconnection between the optical and electrical chips is achieved through the wiring layer in substrate 1, forming the packaged optical module GT. Then, a flexible printed circuit board (FPC) is used to bridge the DSP chip and the optical module GT. The FPC bridging method avoids the need for interconnecting lines on the PCB, thereby reducing signal loss. However, the size of the FPC pads is limited by the soldering process and cannot be further reduced, so the passive link loss of the FPC cannot be further reduced. Therefore, the impedance continuity and return loss in the FPC bridging method cannot meet the higher bandwidth requirements. In addition, this solution requires bump processing on the active surface of the optical chip, which can easily lead to optical port contamination problems, resulting in high process complexity and cost. Moreover, the interconnection path between the electrical and optical chips on the substrate cannot be further reduced. In summary, the packaging structure of existing optical communication modules suffers from high process complexity, long interconnection paths between chips, and low integration. Furthermore, when a DSP is packaged with the existing optical communication module packaging structure, the long interconnection paths between the DSP and the electrical chips in the optical communication module result in low bandwidth for the optical communication module.

[0044] The optical communication module packaging structure provided in this application provides a groove on the packaging substrate, in which a first chip (i.e., an optical chip) is placed, making the first chip flush with the upper surface of the packaging substrate. A packaging structure containing a second chip (i.e., an electrical chip) is then placed on top of the first chip and the packaging substrate. This allows the second chip to occupy only a portion of the upper surface area of ​​the first chip. The upper surface of the first chip can be an active surface, and the ports on the second chip can be directly interconnected with the active surface of the first chip via solder. This reduces the interconnection path between the first and second chips, which is beneficial for achieving a large bandwidth in the optical communication module. Furthermore, by setting the active surface of the first chip upwards, the optical chip does not need to use flip-chip bonding, thereby reducing the process complexity of the optical communication module packaging. Additionally, when the first chip has complex optical waveguide and optical port structures, the complex optical waveguide and optical port structures can be better laid out, improving the integration of the optical communication module. In addition, in this embodiment of the application, by setting the upper surface of the first chip flush with the upper surface of the packaging substrate, it is possible to avoid using different solders to electrically connect the first packaging structure to the packaging substrate and the first chip respectively (for example, using large solder balls to electrically connect the first packaging structure to the packaging substrate and using small solder balls to electrically connect the first packaging structure to the first chip), thereby improving the stability of the first packaging structure on the packaging substrate and the first chip, and also reducing the process complexity of the optical communication module packaging structure.

[0045] Furthermore, in other possible implementations, when the optical communication module packaging structure also needs to encapsulate chips such as DSPs, the DSP chips can be arranged side-by-side with the packaging structure on the aforementioned packaging substrate. The second chip on the packaging structure is directly interconnected with the DSP chip through the wiring layer on the packaging substrate. Compared with the prior art shown in Figure 1A, it is not necessary to interconnect the second chip with the DSP chip through the first chip; compared with the prior art shown in Figure 1B, it is not necessary to set up an FPC. Therefore, the optical communication module packaging structure provided in this application embodiment can shorten the interconnection path between chips and improve the bandwidth of the optical communication module when the second chip needs to be packaged with chips such as DSPs.

[0046] The optical communication module packaging structure provided in this application embodiment can package multiple chips within the same package. These multiple chips can be connected to other chips, a common power supply, and a common ground to enable signal exchange between the chips. The chips described in this application embodiment can be bare chips, or chips formed by simple packaging of bare chips with other chips or components (active or passive devices, etc.), or chip packaging structures formed after packaging; no limitation is made here. The multiple chips packaged in the optical communication module packaging structure can include photonics integrated circuit (PIC) chips (hereinafter referred to as optical chips). The optical chip realizes the transmission and reception of optical signals and the conversion of photoelectric signals. The devices integrated in the optical chip may include, but are not limited to, couplers (e.g., side couplers or grating couplers) for coupling fiber array units (FAUs), photo detectors (PDs), and modems. These devices can be integrated into one or more bare chips or packages to form one or more optical chips. Furthermore, the multiple chips encapsulated in the optical communication module's packaging structure may include not only optical chips but also electronic integrated circuit (EIC) chips (hereinafter referred to as electrical chips). Electrical chips amplify and process electrical signals, and may include, but are not limited to, driver chips and trans-impedance amplifier (TIA) chips. Further, the optical communication module packaging structure provided in this application embodiment may also encapsulate various types of chips such as DSP chips or conversion chips, with these chips interconnected and cooperating to achieve optical communication functionality. Additionally, the optical communication module packaging structure described in this application embodiment can be chip-level packaging or packaging via wafer reconstruction followed by dicing into multiple independent optical communication modules.

[0047] The optical communication module packaging structure shown in this application embodiment can be applied in various scenarios. First, the optical communication module packaging structure can be applied in routing devices or data centers. In this scenario, the optical communication module packaging structure may not include a DSP, and can be an optical engine structure of a linear drive pluggable optic (LPO). For example, the optical communication module packaging structure in the embodiment shown in Figure 2 can be used in this scenario. Second, the optical communication module packaging structure can be applied in scenarios involving photoelectric conversion and photoelectric signal processing. In this scenario, the optical communication module packaging structure may include a DSP chip. For example, the optical communication module packaging structure in the embodiments shown in Figures 3A to 5 can be used in this scenario. Third, the optical communication module packaging structure can be applied to coherent optical modules, short-range optical modules, or switches. In this scenario, the optical communication module packaging structure can include multiple encapsulated structures of optical and electrical chips. Information exchange between each pair of encapsulated structures is achieved through a switching chip. The optical communication module packaging structure can be a co-packaged optical module (CPO) structure. For example, the optical communication module packaging structure shown in Figure 6 can be an example of the structure described below. The optical communication module packaging structure provided in this application embodiment will be described below with specific examples and in conjunction with the structural schematic diagrams shown in Figures 2-6.

[0048] Please refer to Figure 2, which is a schematic diagram of an optical communication module packaging structure 100 provided in an embodiment of this application. As shown in Figure 2, the optical communication module packaging structure 100 includes a packaging substrate 10, a chip 11, and a packaging structure 12. The packaging substrate 10 can be a PCB, FPC, or redistribution layer, etc. In addition, the packaging substrate 10 can be a substrate formed of various types of materials such as silicon material, silicon carbide material, resin material, organic polymer material, or glass-based material. Along the vertical direction y shown in Figure 2, the packaging substrate 10 includes an upper surface and a lower surface, and a groove 101 is provided on the upper surface of the packaging substrate 10.

[0049] In one possible implementation, along the horizontal direction x, which is perpendicular to the vertical direction y in Figure 2, the groove 11 has a groove wall S1 only on the side near the packaging structure 12. The groove wall on the other side of the groove 101 (i.e., the side away from the packaging structure 12) is cut off, so that the upper surface of the packaging substrate 10 presents a "stepped" structure, as shown in Figure 2. In another possible implementation, along the direction x shown in Figure 2, the groove wall on the other side of the groove 11 (i.e., the side away from the packaging structure 12) can be retained, but the groove wall along the direction x is punched through to form a hollow structure to accommodate the FAU. This structure is not shown in the figure. In yet another possible implementation, when the optical chip is a modem chip or a detector chip, that is, when the optical chip does not need to be provided with a FAU, in this case, the groove wall on the other side of the groove 101 (i.e., the side away from the packaging structure 12) is completely retained. The embodiments of this application do not specifically limit the implementation of the groove 101, but set it according to the needs of the scenario. Chip 11 is disposed in groove 11. The lower surface of chip 11 can be adhered to the bottom of groove 101 using adhesive material. The lower surface of chip 11 adhered to the bottom of groove 101 is a passive surface, and the upper surface of chip 11 opposite to the lower surface is an active surface. In this embodiment, the active surface of the chip can be a surface with patterned conductive lines and a functional port, which is used for electrical connection with other chips and conductive lines. As shown in Figure 2, the upper surface of chip 11 is flush with the upper surface of the packaging substrate 10. It should be noted that due to limitations in actual manufacturing processes, the upper surface of chip 11 and the upper surface of packaging substrate 10 cannot be made to be absolutely on the same horizontal plane. The statement that the upper surface of chip 11 is flush with the upper surface of packaging substrate 10 can mean that the relative height difference between the upper surface of packaging substrate 10 and the upper surface of chip 11 along the y-direction is within a preset range, such as ±5μm. Chip 11 can be an optical chip. The package structure 12 can encapsulate at least one electrical chip, such as one or two electrical chips. This application embodiment does not impose specific limitations. Figure 2 schematically shows two electrical chips, chip 121 and chip 122, encapsulated in the package structure 12. When the package structure 12 encapsulates one chip, the chip can be a driver chip or a cross-group amplifier chip; when the package structure 12 encapsulates two chips, the two chips can be a driver chip and a cross-group amplifier chip. The package structure 12 is disposed on the upper surface of the package substrate 10 and the upper surface of the chip 11. Specifically, the package structure 12 includes an upper surface and a lower surface, the lower surface being the surface close to the upper surface of the package substrate 10. A plurality of mutually insulating solder joints 126 are disposed on the lower surface of the package structure 12.The upper surface of chip 11 may be provided with multiple pads 112, which are located on the chip 11 in the region near the upper surface of the packaging substrate 10. The upper surface of chip 11 may also be provided with patterned conductive lines, which are electrically connected to the pads 112. Package structure 12 is disposed on the upper surface of the packaging substrate 10 and the upper surface of chip 11 via multiple mutually insulated solder joints 126. When package structure 12 is disposed on chip 11, the solder joints 126 used to connect package structure 12 and chip 11 are respectively soldered to the multiple pads 112 of chip 11. Solder joints 126 may be, for example, solder balls, microbumps, or micro-bumps, and the material of solder joints 126 may be gold, tin, or tin-containing compounds (e.g., tin-silver or tin-bismuth). Thus, chips 121 and 122 encapsulated in package structure 12 are connected to conductive lines on chip 11 via solder 126 and pads 112 on chip 11, achieving interconnection between chips 121, 122, and chip 11. It should be noted that, to prevent adjacent solder pads 126 on chip 11 from conducting, in one possible implementation, the distance between any two pads 112 on chip 11 can be greater than or equal to 20 μm.

[0050] As can be seen from the optical communication module packaging structure 100 shown in Figure 2, in this embodiment, a groove 101 is provided on the packaging substrate 10, and an optical chip 11 is placed in the groove 101, so that the chip 11 is flush with the upper surface of the packaging substrate 10. The packaging structure 12, which encapsulates the chips 121 and 122, is placed on the chip 11 and the packaging substrate 10, and the packaging structure 12 spans the upper surface of the packaging substrate 10 and the upper surface of the chip 11. Thus, the chips 121 and 122 only occupy a portion of the area of ​​the upper surface of the chip 11. The upper surface of the chip 11 can be an active surface, and the ends of the chips 121 and 122 are... The port can be directly interconnected with the active surface of chip 11 through solder 126, thereby reducing the interconnection path between chip 11 and chip 121 and chip 122, which is beneficial to achieving a large bandwidth of the optical communication module. In addition, by setting the active surface of chip 11 upward, chip 11 does not need to use flip-chip bonding process, and does not need to use processes such as through holes or buried holes to electrically connect the upper and lower surfaces of chip 11, thereby reducing the process complexity of optical communication module packaging. Furthermore, when chip 11 has complex optical waveguide and optical port structures, the complex optical waveguide and optical port structures can be better laid out, improving the integration of the optical communication module. In addition, in this embodiment, by setting the upper surface of the chip 11 flush with the upper surface of the packaging substrate 10, it is possible to avoid using different solders to electrically connect the packaging structure 12 to the packaging substrate 10 and the chip 11 respectively (for example, using large solder balls to electrically connect the packaging structure 12 and the packaging substrate 10, and using small solder balls to electrically connect the packaging structure 10 and the chip 11). This can improve the stability of the packaging structure 12 on the packaging substrate 10 and the chip 11, and also reduce the process complexity of the optical communication module packaging structure 100.

[0051] Referring again to Figure 2, the packaging structure 12 provided in this embodiment can be of various types, including but not limited to: flip chip ball grid array (FCBGA) packaging structure, flip chip scale package (FCCSP) structure, fan-out packaging (FOP) structure, 2.5D through-silicon via (TSV) packaging structure, 3D stacked packaging structure, or glass substrate packaging structure. The packaging structure 12 includes a carrier plate 123, and chips 121 and 122 are disposed on the upper surface of the carrier plate 123. Along the horizontal direction x shown in Figure 2, chips 121 and 122 are horizontally spaced apart on the upper surface of the carrier plate 123. Solder 124 is provided on the lower surface of both chips 121 and 122, and chips 121 and 122 are disposed on the upper surface of the carrier plate 123 via the solder 124. In one possible implementation, the lower surfaces of chips 121 and 122 that are in contact with solder 124 are active surfaces, while the upper surfaces of chips 121 and 122 that are away from the carrier 123 are passive surfaces. Solder 124 can be, for example, solder balls, microbumps, or micro-bumps, and the material of solder 126 can be gold, tin, or tin-containing compounds (e.g., tin-silver or tin-bismuth). The lower surface of the carrier 123 is connected to the solder 126. Thus, chips 121 and 122 are connected to chip 11 through solder 124, carrier 123, and solder 126. Further, the carrier 123 can be one of a plastic substrate, ceramic substrate, flexible substrate, polyimide substrate, redistribution layer, or glass substrate. In the packaging structure 12, an insulating medium 127 is deposited between the upper surface of the carrier 123 and between chips 121 and 122 to insulate chips 121 and 122 from each other.

[0052] In one possible implementation, the packaging substrate 10 may include at least one wiring layer (for example, the packaging substrate 10 may be a multilayer board, each layer of which is provided with patterned conductive lines to form at least one wiring layer, and the at least one wiring layer is electrically connected to each other through vias or blind vias). The at least one wiring layer is interconnected with each other. When the packaging structure 12 is disposed on the upper surface of the packaging substrate 10, the solder 126 on the lower surface of the packaging structure 12 is connected to the at least one wiring layer on the packaging substrate 10. Thus, the chips 121 and 122 packaged in the packaging structure 12 can also be connected to the wiring layer on the packaging substrate 10 through the carrier board 123 and the solder 126, so as to be connected to the external power supply, common ground and other chips or components through the at least one wiring layer on the packaging substrate 10.

[0053] Referring again to Figure 2, in the optical communication module packaging structure 100 shown in Figure 2, an insulating medium 102 is filled between the multiple solders 126 on the packaging substrate 10 used to connect the packaging substrate 10 and the packaging structure 12. This insulating medium 102 serves to insulate and isolate the solders 126 on the packaging substrate 10, preventing the conduction of adjacent solders 126 from causing at least one of the chips 121 and 122 to fail. Furthermore, the insulating medium 102 can also be used to buffer stress at the upper and lower interfaces. Further, to prevent the insulating medium 102 from flowing into the groove 101 or onto the chip 11, in one possible implementation, a barrier structure 103 is provided on the upper surface of the packaging substrate 10, near the edge of the groove 101. This barrier structure 103 is vertically arranged along the y-direction and can be formed of an insulating material. The barrier structure 103 serves to prevent the insulating medium 102 from flowing into the groove 101 and onto the chip 11. In this embodiment, when the chip 11 shown in FIG. 2 is a side coupler or a grating coupler, a FAU 111 is also provided on the chip 11. The FAU 111 is disposed on the side of the chip 11 away from the packaging substrate 10. In addition, in order to improve the heat dissipation performance of the chip, in one possible implementation of this embodiment, the optical communication module packaging structure 100 is also provided with a heat dissipation cover 13. The heat dissipation cover 13 includes a first part 131 disposed on the packaging substrate 10 and a second part 132 disposed on the packaging structure 12. The first part 131 of the heat dissipation cover 13 extends along the vertical direction y, and the second part 132 of the heat dissipation cover 13 extends along the horizontal direction x. The first part 131 and the second part 132 of the heat dissipation cover 13 form a semi-enclosed structure for the packaging structure 12. Furthermore, a thermal interface material 125 is deposited on the upper surface of the chip 121 and the chip 122. The second part 132 of the heat dissipation cover 13 is separated from the chip 121 and the chip 122 by the thermal interface material 125. In one alternative implementation, the second portion 132 of the heat sink 13 projects onto the chip 11, covering the chip 11. In the optical communication module packaging structure 100 shown in Figure 2, solder balls 104 are also provided on the lower surface of the packaging substrate 10. Chips 121 and 122 in the packaging structure 12 can be electrically connected to the solder balls 104 through the carrier board 123, solder 126, and at least one wiring layer on the packaging substrate 10 in the packaging structure 12, thereby enabling chips 121 and 122 to communicate with chips or components outside the optical communication module packaging structure 100. Furthermore, the optical communication module packaging structure 100 can also be mounted on a system-level circuit board or PCB board via the solder balls 104 on the lower surface of the packaging substrate 10, achieving interconnection with other components.

[0054] The structure of the optical communication module packaging structure 100 has been described above with reference to Figure 2. In one possible implementation, the optical communication module packaging structure can also encapsulate more chips, such as DSP chips. Please refer to Figure 3A, which is a schematic diagram of the optical communication module packaging structure 200 provided in this embodiment. Unlike the optical communication module packaging structure 100 shown in Figure 2, the optical communication module packaging structure 200 also includes a chip 14. The chip 14 is disposed on the upper surface of the packaging substrate 10 and the side of the packaging structure 12. The chip 14 is disposed on the packaging substrate 10 by a plurality of mutually insulating solders 141, thereby interconnecting the chip 14 with the chip 121 and the chip 122 through at least one wiring layer on the packaging substrate 10. The solder 141 can be, for example, solder balls, microbumps, or microbumps, and the material of the solder 126 can be gold, tin, or tin-containing compounds (such as tin-silver or tin-bismuth). In addition, an insulating medium 102 is filled between the multiple solder balls 141 used for soldering the chip 14 and the upper surface of the packaging substrate 10 to prevent electrical connection between adjacent leads of the chip 14, which could lead to chip 14 failure. Furthermore, unlike the optical communication module packaging structure 100 shown in FIG. 2, the heat sink 13 shown in FIG. 3A covers not only the packaging structure 12 but also the chip 14; that is, the chip 14 is disposed within the heat sink 13. Additionally, a thermal interface material 142 is deposited on the upper surface of the chip 14, separating the chip 14 from the second part 132 of the heat sink 13 via the thermal interface material 142. The thermal interface material 142 deposited on the chip 14 may be the same as or different from the thermal interface material 125 deposited on the chips 121 and 122; this embodiment does not impose specific limitations. Furthermore, the chip 14 can also communicate with chips or components outside the optical communication module packaging structure 100 via solder balls 104 on the lower surface of the packaging substrate 10. The other structures of the optical communication module packaging structure 200 are the same as those of the optical communication module packaging structure 100 shown in Figure 2. The specific connection relationships, functions and beneficial effects are described in the description of the optical communication module packaging structure 100 shown in Figure 2, and will not be repeated here.

[0055] When the optical communication module packaging structure 100 also needs to encapsulate chips such as chip 14 (e.g., DSP chip), the chip 14 can be arranged side-by-side with the packaging structure 12 on the packaging substrate 10. The chip 121 (e.g., electrical chip) and chip 122 (e.g., electrical chip) on the packaging structure 12 are directly interconnected with the chip 14 (e.g., DSP chip) through the wiring layer on the packaging substrate 10. Compared with the prior art shown in FIG1A, it is not necessary to interconnect chip 121 and chip 122 with chip 14 through chip 11 (e.g., optical chip); compared with the prior art shown in FIG1B, it is not necessary to set up an FPC to interconnect the electrical chip and DSP chip. Therefore, the optical communication module packaging structure 200 provided in this application embodiment, when the optical communication module packaging structure 200 also encapsulates chips such as DSP chip, can shorten the interconnection path between chips and improve the bandwidth of the optical communication module.

[0056] As shown in Figure 3A, the optical communication module packaging structure 200 schematically illustrates that chips 121 and 122 are encapsulated in packaging structure 12, and chip 14 is disposed on the side of packaging structure 12. In one possible implementation, chip 14 can be encapsulated together with chips 121 and 122 in packaging structure 12, as shown in Figure 3B. Chip 14 can be, for example, a DSP chip, chip 121 can be, for example, an electrical chip (e.g., a driver chip), and chip 122 can be, for example, an electrical chip (e.g., a transamplifier chip). As can be seen from the optical communication module packaging structure shown in Figure 3B, chips 14, 121, and 122 are all encapsulated in packaging structure 12, and chips 14, 121, and 122 are disposed on the upper surface of carrier board 123; along the horizontal direction x shown in Figure 3B, chips 14, 121, and 122 are horizontally spaced on the upper surface of carrier board 123. Unlike the optical communication module packaging structure 200 shown in Figure 3A, in the optical communication module packaging structure shown in Figure 3B, the substrate 10 may not have a wiring layer, while the carrier board 123 may have one or more wiring layers. Chips 14, 121, and 122 are interconnected through the wiring layers in the carrier board 123. Similar to the packaging structure 12 shown in Figure 2, the packaging structure used to package chips 14, 121, and 122 may include, but is not limited to, flip-chip ball grid array packaging structures, flip-chip level packaging structures, fan-out board level packaging structures, 2.5D through-silicon via (TSV) packaging structures, 3D stacked packaging structures, or glass substrate packaging structures. The other structures of the optical communication module packaging structure shown in Figure 3B are the same as those of the optical communication module packaging structure 100 shown in Figure 2. The specific connection relationships, functions, and beneficial effects are described in the description of the optical communication module packaging structure 100 shown in Figure 2, and will not be repeated here.

[0057] As shown in Figure 3A, in the optical communication module packaging structure 200, both the chip 14 and the packaging structure 12 are provided with heat dissipation covers 13. In other possible implementations, the chip 14 may not have a heat dissipation cover 13, and only the packaging structure 12 may have a heat dissipation cover 13, as shown in Figure 4. As can be seen from Figure 4, when the heat dissipation cover 13 is only provided on the packaging structure 12, no thermal interface material needs to be deposited on the chip 14. The first part 131 of the heat dissipation cover 13 is disposed on the packaging substrate 10, between the chip 14 and the packaging structure 12, and the first part 131 of the heat dissipation cover 13 extends along the y-direction. The second part of the heat dissipation cover 13 extends along the x-direction and is disposed on the chips 121 and 122. The other structures of the optical communication module packaging structure shown in Figure 4 are the same as those of the optical communication module packaging structure 100 shown in Figure 2. Specific connections, functions, and beneficial effects are described in the description of the optical communication module packaging structure 100 shown in Figure 2, and will not be repeated here.

[0058] In another possible implementation, based on the optical communication module packaging structure 200 shown in FIG3A, the thermal interface material 142 deposited on chip 14 can be different from the thermal interface material 125 deposited on chips 121 and 122. Therefore, to avoid mutual interference between the heat dissipation of chip 14 and the heat dissipation of chips 121 and 122 packaged in the packaging structure 12, chip 14 and packaging structure 12 can be separated by a heat dissipation cover, as shown in FIG5. In the optical communication module packaging structure 200 shown in FIG5, in addition to the first part 131 and the second part 132 shown in FIG3A, the packaging cover 13 also includes a third part 133. The third part 133 of the packaging cover 13 is disposed between chip 14 and packaging structure 12, and is disposed on the packaging substrate 10 and extends in the direction y. As shown in Figure 5, the first part 131, the second part 132, and the third part 133 of the encapsulation cover 13 form a fully enclosed structure around the chip 14, so that the chip 14 is completely isolated within the encapsulation cover 13; the second part 132 and the third part 133 of the encapsulation cover 13 form a semi-enclosed structure around the encapsulation structure 12. The other structures of the optical communication module encapsulation structure shown in Figure 5 are the same as those of the optical communication module encapsulation structure 100 shown in Figure 2. For specific connection relationships, functions, and beneficial effects, please refer to the description of the optical communication module encapsulation structure 100 shown in Figure 2, which will not be repeated here.

[0059] In any of the embodiments shown in Figures 2 to 5 above, the optical communication module packaging structure only encapsulates one optical chip (chip 11) and one packaging structure 12 corresponding to the optical chip (chip 11). In other possible implementations, the optical communication module packaging structure can encapsulate multiple optical chips and multiple packaging structures. In this case, the optical communication module packaging structure can be applied to co-packaged optical modules (CPO, co-package optics) scenarios. Please refer to Figure 6, which is a structural schematic diagram of an optical communication module packaging structure 300 provided in an embodiment of this application. As shown in Figure 6, the optical communication module packaging structure 300 includes chip 11, chip 15, packaging structure 12, and packaging structure 16. Among them, chip 11 and chip 15 can both be optical chips. Chip 15 is disposed in the groove 105 of the packaging substrate 10. The structure of chip 15 and its positional relationship with the packaging substrate 10 are the same as those of chip 11. For details, please refer to the relevant description of chip 11 in Figure 2, which will not be repeated here. When chip 15 is an optical coupler, FAU151 is also disposed on chip 15. The package structure 16 can encapsulate two electrical chips, chip 161 and chip 162. The package structure 16 also includes a carrier plate 163. Chips 161 and 162 are disposed on the upper surface of the carrier plate 163 via solder 164. Chips 161 and 162 are disposed on the upper surface of the package substrate 10 and chip 15 via the carrier plate 163 and multiple mutually isolated solders 166. The package structure 16 spans the upper surface of the package substrate 10 and chip 15. The specific structure of the package structure 16 and the encapsulated chips can be the same as those of the package structure 12, as detailed in the description of the package structure 12 in Figure 2. Furthermore, a barrier 106 is provided on the package substrate 10 to prevent the insulating material filling the spaces between the solders 166 from flowing into the groove 105 and onto the chip 15, thus preventing chip 15 from failing. Furthermore, the optical communication module packaging structure 300 also includes a chip 14, which can be a switching chip for information exchange between the electrical chips packaged in packaging structure 12 and packaging structure 16. Specifically, the packaging substrate 10 may include at least one wiring layer. The packaging structure 12 is electrically connected to at least one wiring layer on the packaging substrate 10 via solder 126; similarly, the packaging structure 16 is electrically connected to at least one wiring layer on the packaging substrate 10 via solder 166; additionally, the chip 14 is electrically connected to at least one wiring layer on the packaging substrate 10 via solder 141. Thus, the chip packaged in packaging structure 12 is electrically connected to chip 14 via at least one wiring layer on the packaging substrate 10; the chip packaged in packaging structure 16 is electrically connected to chip 14 via at least one wiring layer on the packaging substrate 10.It should be noted that, as shown in Figure 6, the optical communication module packaging structure 300 schematically illustrates two optical chips and two packaging structures, forming two optical engines. In other CPO scenarios, the same optical communication module packaging structure can contain more optical chips and more packaging structures, forming more optical engines, such as three or four optical engines. This application embodiment does not specifically limit the number of optical engines included in the same optical communication module packaging structure. When the optical communication module packaging structure 300 includes more optical engines, these more optical engines can be the structure shown in Figure 2, and all of these more optical engines are connected to the chip 14 (i.e., the switching chip) through conductive lines on the substrate 10, realizing information exchange between multiple optical engines.

[0060] The embodiments shown in Figures 2 to 6 illustrate the specific structure of the optical communication module packaging structure. This application also provides a circuit board. This circuit board may include a printed circuit board, a power management chip, and the optical communication module packaging structure shown in any of the above embodiments. The printed circuit board can be a single-layer or multi-layer board. Solder balls are provided on the lower surface of the packaging substrate in the optical communication module packaging structure. The optical communication module packaging structure is mounted on the printed circuit board via the solder balls on the packaging substrate. The chip packaged in the optical communication module packaging structure is connected to the wiring layer on the printed circuit board. Furthermore, a power management chip is also provided on the circuit board. The power management chip is connected to the optical communication module packaging structure via the wiring layer on the printed circuit board, thereby achieving electrical connection with the chip packaged in the optical communication module packaging structure to supply power to the chip packaged in the optical communication module packaging structure. In addition, the circuit board also provides power lines and ground lines. The chip packaged in the optical communication module packaging structure is also connected to the power lines and ground lines to achieve common power and ground between the chips.

[0061] Furthermore, this application embodiment also provides a communication device, which includes the aforementioned board and power supply module. The communication device can be a switch, router, or server, etc. More specifically, when the communication device is a router or server, the optical communication module packaging structure included in the communication device can be, for example, the optical communication module packaging structure shown in the embodiment of FIG2; when the communication device is a short-range optical communication device or a switch, the optical communication module packaging structure in the communication device is the optical communication module packaging structure shown in the embodiment of FIG6; when the communication device is a photoelectric conversion device or a photoelectric signal processing device, the optical communication module packaging structure in the communication device can be, for example, the optical communication module packaging structure shown in the embodiments of FIG3A to FIG5. The specific structure of the optical communication module packaging structure is shown above through the embodiments shown in FIG2 to FIG6. This application embodiment also provides a method for preparing an optical communication module packaging structure. The following describes the process flow for preparing the optical communication module packaging structure in detail, taking the prepared optical communication module packaging structure shown in FIG3A as an example, combined with the process flow 700 shown in FIG7 and the structural schematic diagrams of the optical communication module packaging structure 200 preparation process shown in FIG8A-FIG. The process flow 700 includes the following steps:

[0062] Step 701: Prepare the packaging substrate 10.

[0063] In this step, the packaging substrate 10 can be a flexible circuit board, an organic substrate, or a PCB, etc. Taking an organic substrate as an example, a silicon substrate is first provided. Based on the size of the chip 11, a first region for placing the chip 11 is pre-determined in the silicon substrate. Then, on the silicon substrate, in a second region where the chip 11 is not placed, at least one wiring layer is fabricated in the second region of the silicon substrate using standard CMOS processes such as photolithography, development, and etching to form the packaging substrate 10. The structure of the fabricated packaging substrate 10 is shown in Figure 8A.

[0064] Based on the packaging substrate 10 shown in step 701, in one possible implementation, a barrier structure 103 can be formed on the upper surface of the packaging substrate 10. This barrier structure 103 is used to prevent the filler material subsequently disposed on the packaging substrate 10 from flowing onto the chip 11. Furthermore, the barrier structure 103 is disposed on the upper surface of the packaging substrate 10 in the second region near the first region. The barrier structure 103 can be formed by depositing an insulating material on the packaging substrate 10 and then etching the insulating material. The barrier structure is shown in FIG8A.

[0065] Step 702: Etch the upper surface of the packaging substrate 10 to form a groove 101. In this step, the upper surface of the packaging substrate 10 and the reserved first position area can be etched to form the groove 101. It should be noted that since the chip 11 is an optical chip, when the chip 11 is a coupler chip, in order to reserve the position for setting the FAU, the sidewalls of the groove 101 that are not equipped with the packaging structure 12 can be etched away, so that the packaging substrate 10 is stepped. The depth of the groove 101 can be the same as the thickness of the chip 11. The structure formed after this step is shown in Figure 8B.

[0066] Step 703: Chip 11 is placed in groove 101. In this step, adhesive material can first be deposited in the bottom of groove 101. Then, the back side (i.e., lower surface) of the optical chip 11 is bonded to the bottom of groove 101 using adhesive material. The back side of the optical chip 11 can be a passive surface, and the front side (i.e., upper surface) of the optical chip 11 is an active surface, meaning the upper surface of the chip 11 has conductive lines and leads. Additionally, pads 112 are provided on the chip 11 for soldering the package structure 12. The spacing between any two pads in the pads 112 can be greater than or equal to 20 μm to prevent chip failure caused by interconnection between ports soldered on adjacent pads 112. The pads 112 can connect to the conductive lines on the upper surface of the chip 11, thereby connecting to the leads of the chip 11. The upper surface of the chip 11 is flush with the upper surface of the package substrate 10. The structure formed after this step is shown in Figure 8C.

[0067] Step 704: Fabrication of package structure 12. In this embodiment, packaging processes such as FCBGA packaging, FCCSP packaging, FOP packaging, 2.5D through-silicon via (TSV) packaging, 3D stacked packaging, or glass substrate packaging can be used to package chips 121 and 122, thereby forming package structure 12. Taking FOP packaging as an example, the process steps for fabricating package structure 12 are further described. Specifically, firstly, standard CMOS processes such as photolithography, development, and etching can be used to fabricate at least one wiring layer in silicon crystal to form a carrier board 123. Next, solder 124 is applied to the leads of chips 121 and 122, respectively. The solder 124 can be, for example, solder balls, microbumps, or microbumps. Then, chip 121 is disposed on the carrier board 123 via solder 124, and chip 122 is also disposed on the carrier board 123 via solder 124. In this configuration, the leads of chip 121 are connected to conductive lines on the carrier board 123 via solder 124. Thus, chips 121 and 122 are interconnected via the carrier board 123, and the leads of chips 121 and 122 are led from the upper surface to the lower surface of the carrier board 123. Finally, multiple mutually isolated solder joints 126 are provided on the lower surface of the carrier board 123 away from chips 121 and 122.

[0068] Step 705: The package structure 12 is disposed on the upper surface of the chip 11 and the upper surface of the package substrate 10. In this step, the package structure 12 can be disposed on the upper surface of the package substrate 10 and the upper surface of the chip 11 using multiple solders 126, and the package structure 12 spans across the chip 11 and the package substrate 10. The solders 126 in the package structure 12 that connect to the chip 11 are respectively disposed on the pads 112 of the chip 11. Additionally, underfill material 102 is filled between the solders 126 and between the solders 126 and the barrier 103 to isolate the solders 126 from each other. Through this step, the leads of the chips 121 and 122 in the package structure 12 are connected to the wiring layer of the package substrate 10 through the solders 126; furthermore, the leads of the chips 121 and 122 in the package structure 12 are electrically connected to the leads of the chip 11 through the solders 126. The structure formed after this step is shown in Figure 8D.

[0069] Step 706: A chip 14 is disposed on the upper surface of the packaging substrate 10 and the side of the packaging structure 12. In this step, multiple solder joints 141 are first disposed on the lower surface of the chip 14, and then the chip 14 is disposed on the packaging substrate 10 using the solder joints 141. The chip 14 and the packaging structure 12 are disposed side-by-side with spacing, and the chip 14 is disposed on the side of the packaging structure 12, which is the side away from the chip 14. Additionally, underfill material 102 is filled between the solder joints 141 to isolate them from each other. Through this step, the leads of the chip 14 are connected to the wiring layer of the packaging substrate 10 through the solder joints 141, thereby connecting the leads of the chips 121 and 122 packaged in the packaging structure 12 through the wiring layer of the packaging substrate 10. The structure formed after this step is shown in Figure 8E.

[0070] Step 707: A package cover 13 is disposed on the chip 14 and the package structure 12. In this step, a thermal interface material can first be coated on the upper surface of the chip 14, the chip 121, and the chip 122. Then, the package cover 13 is disposed on the upper surface of the package substrate 10, the upper surface of the chip 14, and the upper surface of the package structure 12. The package cover 13 includes a first portion 131 disposed on the package substrate 10 and a second portion disposed on the chip 14, the chip 121, and the chip 122, wherein the first portion 131 is disposed on the side of the chip 14 away from the package structure 12. Thus, the package cover 13 forms a semi-enclosed structure for the chip 14 and the package structure 12. The structure formed after this step is shown in FIG8F.

[0071] Step 708: Solder balls 104 are disposed on the lower surface of the package substrate 10. In this step, solder balls 104 are disposed on the lower surface of the package substrate 10, thereby allowing the package substrate 10 to be disposed on a system-on-a-board (SoC) or PCB board, enabling interconnection with other components. The structure formed after this step is shown in Figure 8G.

[0072] Step 709: FAU is set on chip 11. In this step, the FAU is set on the side of chip 11 away from the package structure 12.

[0073] After steps 701 to 709, the optical communication module packaging structure 200 shown in Figure 3A can be fabricated. It should be noted that the order of the steps shown in Figure 7 is not specifically limited in this embodiment, but is set according to the needs of the application scenario. For example, step 704 can be placed before step 701; for another example, step 706 can be placed before step 704; for yet another example, steps 705 and 706 can be performed simultaneously, that is, the packaging structure 12 and the chip 14 are simultaneously placed on the substrate 10. Furthermore, in this embodiment, the method for fabricating the optical communication module packaging structure may include more or fewer steps. For example, steps 701 and 702 may be omitted, directly obtaining a packaging substrate 10 with grooves.

[0074] Furthermore, based on the optical communication module packaging structure 200 shown in Figure 3A, when it is necessary to prepare the optical communication module packaging structure 100 shown in Figure 2, step 706 can be omitted, and in step 707, only the packaging cover 13 is provided on the packaging structure 12. When it is necessary to prepare the optical communication module packaging structure 600 shown in Figure 6, a third region can be set on the packaging substrate 100, symmetrical to the second region. Then, using the steps shown in steps 702 to 705, a chip 15 is provided on the packaging substrate 10, and a packaging structure 16 is provided on the chip 15 and the packaging substrate 10. Then, using the steps shown in step 706, the chip 14 is interconnected with the chip in the packaging structure 12 and the chip in the packaging structure 16, respectively. Then, using the steps shown in step 707, a heat dissipation cover is provided on the chip 14, the packaging structure 12, and the packaging structure 16. Finally, solder balls 104 are provided on the lower surface of the packaging substrate 10 in step 708.

[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An optical communication module package structure, characterized by, include: A packaging substrate has a first groove on its upper surface, in which a first chip is embedded. The upper surface of the first chip is flush with the upper surface of the packaging substrate, and the upper surface of the first chip is an active surface. A first packaging structure, wherein a second chip is packaged in the first packaging structure; The first packaging structure is disposed on the upper surface of the packaging substrate and the upper surface of the first chip. The first packaging structure is electrically connected to the packaging substrate and the first chip respectively through a plurality of mutually isolated first solders. The first chip is an optical chip, and the second chip is an electrical chip.

2. The optical communication module packaging structure of claim 1, wherein, The first packaging structure also encapsulates a third chip, which is an electrical chip; The first packaging structure further includes a carrier board, the second chip and the third chip are disposed on the upper surface of the carrier board, and the lower surface of the carrier board is connected to the upper surface of the packaging substrate and the upper surface of the first chip respectively through the plurality of first solders.

3. The optical communication module packaging structure according to claim 1 or 2, characterized in that, The plurality of first solders include a plurality of second solders for connecting the first package structure and the upper surface of the package substrate, wherein insulating material is filled between the plurality of second solders; The upper surface of the packaging substrate is provided with a blocking structure. The blocking structure is located on the side of the upper surface of the packaging substrate, near the first chip. The blocking structure is used to prevent the insulating material from flowing into the first groove and onto the first chip.

4. The optical communication module packaging structure of claim 1, wherein, A fiber optic array unit is disposed on the side of the first chip away from the first packaging structure.

5. The optical communication module packaging structure of claim 2, wherein, The optical communication module packaging structure further includes a heat dissipation cover, which includes a first part disposed on the upper surface of the packaging substrate and a second part disposed on the first packaging structure. The second part of the heat dissipation cover is perpendicular to the first part of the heat dissipation cover and is in contact with each other. The first part and the second part of the heat dissipation cover form a semi-enclosed structure for the first packaging structure. The upper surfaces of the second chip and the third chip are deposited with a first thermal interface material, and the second part of the heat sink is separated from the second chip and the third chip by the first thermal interface material.

6. The optical communication module packaging structure according to claim 2 or 5, wherein, The first packaging structure also encapsulates a fourth chip, which is disposed on the upper surface of the carrier board; The fourth chip is electrically connected to the second chip and the third chip through at least one wiring layer on the carrier board.

7. The optical communication module packaging structure of claim 5, wherein, The upper surface of the packaging substrate is also provided with a fourth chip, which is arranged side by side and spaced apart from the first packaging structure. The lower surface of the fourth chip is electrically connected to the packaging substrate via a third solder. The fourth chip is electrically connected to the first package structure via the third solder, the packaging substrate, and the first solder.

8. The optical communication module packaging structure of claim 7, wherein, The fourth chip is disposed inside the heat sink cover, and the fourth chip is disposed between the first part of the heat sink cover and the first packaging structure; The upper surface of the fourth chip is deposited with a second thermal interface material, and the second part of the heat sink is separated from the fourth chip by the second thermal interface material.

9. The optical communication module packaging structure of claim 8, wherein, The heat dissipation cover further comprises a third part arranged on the upper surface of the packaging substrate, the third part of the heat dissipation cover is arranged perpendicularly to the first part of the heat dissipation cover and in contact with each other; The third part of the heat dissipation cover is arranged between the fourth chip and the first packaging structure.

10. The optical communication module packaging structure according to any one of claims 1 to 4, wherein, The upper surface of the packaging substrate is provided with a second groove, the fourth chip is arranged in the second groove, and the upper surface of the fourth chip is flush with the upper surface of the packaging substrate; The optical communication module packaging structure further comprises a second packaging structure, the fifth chip and the sixth chip are encapsulated in the second packaging structure, the second packaging structure is arranged above the upper surface of the packaging substrate and the upper surface of the fourth chip, and the second packaging structure is connected with the upper surface of the packaging substrate and the upper surface of the fourth chip through a plurality of fourth materials which are isolated from each other; The upper surface of the packaging substrate is further provided with a seventh chip, the seventh chip is arranged between the first packaging structure and the second packaging structure, the first packaging structure is electrically connected with the seventh chip through at least one wiring layer on the packaging substrate, and the second packaging structure is electrically connected with the seventh chip through at least one wiring layer on the packaging substrate.

11. A board card, characterized by The board card comprises a printed circuit board, a power management chip and the optical communication module packaging structure as claimed in any one of claims 1 to 10; The power management chip and the optical communication packaging structure are arranged on the printed circuit board and connected through conductive lines on the printed circuit board.

12. A communication device, characterized by The communication device comprises a power supply module and the board card as claimed in claim 11; The board card is connected with the power supply module, and the power supply module supplies power to the first chip and the second chip encapsulated in the optical communication module packaging structure through the power management chip on the board card.

13. A method for fabricating an optical communication module packaging structure, characterized in that, The preparation method comprises: obtaining a packaging substrate, the packaging substrate is provided with a first recess; embedding a first chip in the first recess, wherein the upper surface of the first chip is flush with the upper surface of the packaging substrate, and the upper surface of the first chip is an active surface; arranging a first packaging structure prepared in advance on the upper surface of the first chip and the upper surface of the packaging substrate through a plurality of first solders, wherein the first packaging structure encapsulates a second chip; The first chip is an optical chip, and the second chip is an electrical chip.

14. The method of claim 13, wherein, The first packaging structure further encapsulates a third chip, and the first packaging structure is one of a flip chip ball grid array packaging structure, a flip chip level packaging structure, a fan-out wafer level packaging structure, a 2.5D through silicon via packaging structure, a 3D stacked packaging structure or a glass substrate packaging structure.

15. The production method according to claim 13 or 14, characterized by, The obtaining of the packaging substrate comprises: providing an initial substrate, determining a first area for arranging the first chip on the initial substrate, etching the first area to form the first recess; preparing at least one wiring layer on a second area of the initial substrate close to the first area; forming the packaging substrate based on the preparation result.

16. The method of claim 15, wherein, The method further comprises: A fourth chip is arranged on the upper surface of the packaging substrate and the side of the first packaging structure, and the fourth chip is arranged in parallel and spaced apart from the first packaging structure; The fourth chip is connected with the first packaging structure through the at least one wiring layer.

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