Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. Structures and methods for forming an interconnect layer include forming a first metal interconnect layer, depositing a dielectric layer over the first metal interconnect layer, patterning the dielectric layer to form an opening exposing the first metal interconnect layer, forming a doped barrier layer or a mixed barrier layer along sidewalls and a lower surface of the opening, and forming a second metal interconnect layer over the first metal interconnect layer. And depositing a metal layer on the doped barrier layer or the mixed barrier layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor interconnection structure, and more particularly to the setting of its barrier layer. Background Art

[0002] The demand in the electronics industry for smaller, faster, and semiconductor devices that can simultaneously support a large number of complex functions continues to increase. In summary, the continuous trend in the semiconductor industry is to manufacture low-cost, high-performance, and low-power integrated circuits. Therefore, the main method to achieve these goals is to reduce the size of semiconductor integrated circuits (such as the minimum feature size), thereby improving production capacity and reducing related costs. However, reducing the size also increases the complexity of semiconductor manufacturing processes. Therefore, in order to achieve continuous progress in semiconductor integrated circuits and devices, semiconductor manufacturing processes and technologies need to make similar progress.

[0003] For example, forming high-quality interconnections containing reliable metal lines and vias poses challenges. Specifically, as the size of integrated circuits continues to shrink, and the thickness of the layers (such as the thickness of the metal layer, dielectric layer, and barrier layer) correspondingly shrinks, the increase in the resistance of the metal interconnection layer becomes a key issue. For example, the thickness interconnection structure in existing metallization technologies may include a barrier layer, a liner layer, and a metal interconnection layer (such as a copper layer), where the barrier layer and the liner layer are sandwiched between the metal interconnection layer and the surrounding low-k dielectric layer. As the size of the integrated circuit shrinks, the barrier layer and the liner layer occupy a larger volume ratio of the back-end interconnection structure compared to the metal interconnection layer, thereby increasing the resistance of the metal interconnection layer.

[0004] Therefore, the prior art cannot fully meet the requirements in all aspects. Summary of the Invention

[0005] An object of the present invention is to provide a semiconductor device and a method for manufacturing the same to solve at least one of the above problems.

[0006] An embodiment of the present invention provides a method for manufacturing a semiconductor device, including: forming a first metal interconnection layer; depositing a dielectric layer on the first metal interconnection layer; patterning the dielectric layer to form an opening to expose the first metal interconnection layer; forming a doped barrier layer or a hybrid barrier layer along the sidewalls and the bottom surface of the opening; and depositing a metal layer on the doped barrier layer or the hybrid barrier layer.

[0007] In another embodiment, a method of fabricating a semiconductor device includes: forming a first layer of a multi-layer interconnect network. In some embodiments, the first layer of the multi-layer interconnect network includes a first via portion and a first metal line portion. In some examples, the method further includes forming a second layer of the multi-layer interconnect network on the first layer of the multi-layer interconnect network. In some embodiments, the second layer of the multi-layer interconnect network includes a second via portion and a second metal line portion. In various examples, the first layer of the multi-layer interconnect network includes a first barrier layer disposed to at least partially surround the first via portion and the first metal line portion. In some embodiments, the second layer of the multi-layer interconnect network includes a second barrier layer disposed to at least partially surround the second via portion and the second metal line portion. The second barrier layer is disposed differently from the first barrier layer.

[0008] In yet another embodiment, a semiconductor device includes: a substrate containing one or more semiconductor devices; a first layer of a multi-layer interconnect network formed on the substrate; and a second layer of the multi-layer interconnect network formed on the first layer of the multi-layer interconnect network. In some embodiments, the first layer of the multi-layer interconnect network includes a first barrier layer to at least partially surround a first metal layer of the first layer of the multi-layer interconnect network. In some examples, the second layer of the multi-layer interconnect network includes a second barrier layer to at least partially surround a second metal layer of the second layer of the multi-layer interconnect network, and the second barrier layer is different from the first barrier layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a flowchart of a method of forming an interconnect layer in some embodiments.

[0010] Figure 2 , Figure 3 , Figure 4 and Figure 5 are cross-sectional views of intermediate stages of fabricating and processing a device according to the method of Figure 1 .

[0011] Figure 6A , Figure 6B , Figure 6C and Figure 6D are examples of different interconnect structure schemes in some embodiments.

[0012] Figure 6E , Figure 6F , Figure 6G , Figure 6H and Figure 6I are various examples of doped barrier layers in some embodiments.

[0013] Figure 6J is an example of a hybrid barrier layer in some embodiments.

[0014] Figure 7Part of a multi-layer interconnect network in some embodiments.

[0015] Figure 8 Perspective view of a metal-oxide semiconductor transistor in some embodiments.

[0016] Figure 9 Perspective view of a fin field-effect transistor device in one or more embodiments of the present invention.

[0017] Figure 10 Cross-sectional view of a fully wrapped gate device in one or more embodiments of the present invention.

[0018] Reference numerals are as follows:

[0019] AA', BB': Sections

[0020] L: Channel length

[0021] W: Channel width

[0022] 100: Method

[0023] 102, 104, 106, 108, 110, 112: Steps

[0024] 200: Device

[0025] 202, 802, 952, 1002: Substrates

[0026] 204, 502, 716, 964: Metal layers

[0027] 206, 406: Barrier layers

[0028] 208, 408, 608: Capping layers

[0029] 302, 714: Etch stop layers

[0030] 304: Interlayer dielectric layer

[0031] 402: Via opening

[0032] 505, 650, 670: Parts

[0033] 606: Doped barrier layer

[0034] 606A: Undoped barrier layer part

[0035] 606B: Doped interlayer dielectric layer part

[0036] 606C: Doped material layer

[0037] 610: Hybrid barrier layer

[0038] 652, 672: First interfaces

[0039] 654,674: Second interface

[0040] 656,658,660: Third interface

[0041] 680,682,684: Region

[0042] 700: Multilayer metal interconnect network

[0043] 702,704,706,708: Interconnect layer

[0044] 710: Via portion

[0045] 712: Metal line portion

[0046] 800: Transistor

[0047] 804,1008: Gate stack

[0048] 806,962,1007: Gate dielectric layer

[0049] 808,1009: Gate

[0050] 810,955: Source region

[0051] 812,957: Drain region

[0052] 814: Channel region

[0053] 900: Fin field-effect transistor device

[0054] 954,1004: Fin

[0055] 956,1006: Isolation region

[0056] 958: Gate structure

[0057] 960: Interface layer

[0058] 1000: All-around gate device

[0059] 1015: Semiconductor channel layer Detailed implementation manners

[0060] The following detailed description may be combined with the accompanying drawings for a better understanding of various aspects of the present invention. It should be noted that various structures are only for illustrative purposes and are not drawn to scale, as is normal in the industry. In fact, for clarity, the dimensions of various structures can be increased or decreased arbitrarily.

[0061] The different embodiments or examples provided below can implement different structures of the present invention. The embodiments of the specific components and arrangements below are used to simplify the content of the present invention rather than limit the present invention. For example, the description of forming a first component on a second component includes embodiments where the two are in direct contact, or embodiments where there are other additional components between the two rather than direct contact. In addition, the same reference numerals may be reused in multiple examples of the present invention for simplicity, but the components with the same reference numerals in multiple embodiments and / or settings do not necessarily have the same corresponding relationships.

[0062] In addition, relative spatial terms such as "below", "beneath", "lower", "above", "higher", or similar terms are used to describe the relationship between some elements or structures and another element or structure in the drawings. These relative spatial terms include different directions of the device during use or operation, as well as the directions described in the drawings. When the device turns in a different direction (rotated 90 degrees or other directions), the relative spatial adjectives used will also be interpreted according to the turned direction.

[0063] In addition, in the following content, the dimensions of a given layer or other structure (such as thickness, width, length, or similar dimensions) can sometimes be described using terms such as "substantially the same", "the same", or "about", and such terms can be understood to be within + / - 10% of the listed value or between the compared values. For example, if dimension A is described as "substantially equal to" dimension B, it should be understood that dimension A is within + / - 10% of dimension B. In another example, if the thickness of a layer is about 100 nm, it should be understood that the thickness of the layer can be between 90 nm and 110 nm.

[0064] It should be noted that an interconnect structure is adopted in the later process of the embodiments of the present invention, and the process fabricates a multi-layer metal interconnect network. In some embodiments, the interconnect structure described herein can be used for a local interconnect structure, an intermediate interconnect structure, and / or a global interconnect structure. The term "local interconnect" described herein is used to illustrate the bottom layer of the metal interconnect, which is different from the intermediate interconnect and / or the global interconnect. For example, the local interconnect crosses a shorter distance and is sometimes used to electrically interconnect the source, drain, body, and / or gate of a given device or nearby devices. In addition, the local interconnect is beneficial for vertically interconnecting one or more devices to an upper metallization layer (such as an intermediate interconnect layer), such as via one or more vias. Generally speaking, the interconnect (including local interconnect, intermediate interconnect, or global interconnect) can be part of the later fabrication process and can include a multi-layer network or metal wiring. Those skilled in the art of the present technology should understand that the embodiments of the present invention are beneficial for other embodiments of the interconnect structure.

[0065] In addition, the techniques and interconnect structures described in some embodiments can be used in other semiconductor structures, circuits, and devices, such as planar substrate metal-oxide-semiconductor field-effect transistors, complementary metal-oxide-semiconductor devices, multi-gate transistors (planar or vertical transistors such as fin field-effect transistor devices, fully wrapped gate devices, Ω-gate devices, or Π-gate devices), strained semiconductor devices, silicon-on-insulator devices, partially depleted silicon-on-insulator devices, fully depleted silicon-on-insulator devices, memory devices (such as flash memories, such as NAND or NOR flash memories), logic circuits, or other structures, circuits, or devices. Those skilled in the art should understand that the embodiments of the present invention are beneficial to other embodiments of semiconductor structures, circuits, or devices. In addition, any number of integrated circuits and / or devices can be connected by interconnects formed during the back-end process.

[0066] As the complexity of advanced semiconductor devices and circuits continues to increase and their sizes are significantly reduced, challenges arise in forming high-quality interconnects with reliable metal lines and vias. Specifically, as the size of integrated circuits continues to shrink, the corresponding thicknesses of the layers (such as the thicknesses of the metal layer, dielectric layer, and barrier layer) decrease, and the increase in the resistance of the metal interconnect layer becomes a key issue. For example, in existing metallization technologies, the back-end interconnect structure can include a barrier layer, a liner layer, and a metal interconnect layer (such as a copper layer), where the barrier layer and the liner layer are sandwiched between the metal interconnect layer and the surrounding low-dielectric-constant dielectric layer. As the size of the integrated circuit shrinks, the barrier layer and the liner layer of the metal interconnect layer occupy a relatively large volume proportion of the back-end interconnect structure, resulting in an increase in the resistance of the metal interconnect layer. Therefore, existing methods cannot meet all aspects of the requirements.

[0067] Embodiments of the present invention provide more advantages than the prior art. However, it should be understood that other embodiments may provide different advantages, and not all advantages need to be described herein, and not all embodiments need to have specific advantages. For example, the embodiments described herein include an interconnect structure and related formation methods, which can effectively overcome various disadvantages of the prior methods. Specifically, various solutions can be provided to implement the barrier layer and / or the liner layer to effectively reduce the resistance of the interconnect structure, including reducing the resistance of the metal interconnect layer. For example, the barrier layer of the interconnect structure can be doped (such as using cobalt-based materials, ruthenium-based materials, tantalum-based materials, alloys thereof, and / or other suitable metals or compounds) to form a doped barrier layer. In some examples, an in-situ treatment process (such as during or after the formation of the barrier layer) and / or a post-treatment process can be performed on the barrier layer, which can be part of the doping process or independent of the doping process. In various embodiments, a liner layer can be formed on the doped barrier layer as appropriate before forming the metal interconnect layer (such as a copper layer). In some embodiments, the interconnect structure can be changed to include a hybrid barrier layer, which is composed of metal alloys and / or compounds. In some examples, a post-treatment process can also be performed on the hybrid barrier layer as appropriate. Some embodiments can form a liner layer on the hybrid barrier layer as appropriate before forming the metal interconnect layer. Therefore, when generally implementing the barrier layer and the liner layer in the interconnect structure described herein, at least four different solutions can be provided: (i) a doped barrier layer and a liner layer; (ii) a doped barrier layer without a liner layer; (iii) a hybrid barrier layer and a liner layer; and (iv) a hybrid barrier layer without a liner layer.

[0068] Regardless of the specific implementation manner or solution, embodiments of the present invention can reduce the resistance of the interconnect structure. For example, various embodiments can reduce the thickness of the barrier layer and / or the liner layer to reduce the volume ratio of the barrier layer and / or the liner layer in the interconnect structure. In this way, the volume ratio of the metal interconnect layer (such as copper) can be correspondingly increased, thereby reducing the resistance of the metal interconnect layer. In some examples, doping the barrier layer and / or using a hybrid barrier layer can reduce the resistance of the interconnect structure. In addition, the contact resistance of the bottom layer of the interconnect structure can be reduced. The various embodiments disclosed herein can be used for any local interconnect, intermediate interconnect, or global interconnect of the multi-layer interconnect network formed in part of the back-end process. In addition, the various embodiments disclosed herein can be used for dual-damascene and / or single-damascene processes and structures. It should also be noted that in some examples, any one of the different solutions described herein can be implemented in any given interconnect layer of the multi-layer interconnect network. Additional details of the embodiments of the present invention will be provided below, and those skilled in the art in this technical field who benefit from the embodiments of the present invention will clearly understand additional advantages and / or other advantages.

[0069] Figure 1 For some embodiments, a general method 100 for forming an interconnect layer. Method 100 will be described in conjunction withFigures 2 to 5 are described below. In addition, specific variations of method 100 implemented according to a particular interconnect structure scheme will be described in conjunction with method 100 and Figures 6A to 6J and Figure 7 are described below. It should be understood that additional process steps may be implemented before, during, and after method 100, and that various embodiments of method 100 may replace or omit some of the described process steps. It should also be understood that some portions of method 100 may be common complementary metal oxide semiconductor technology process flows, and thus some processes are only briefly described herein.

[0070] Step 102 of method 100 initially provides a substrate that contains one or more semiconductor devices. As Figure 2 shown, one embodiment of step 102 may provide device 200 that contains substrate 202, where substrate 202 includes one or more semiconductor devices. In some embodiments, substrate 202 and the semiconductor devices therein may include devices described in conjunction with Figures 8 to 10 are described below. For example, semiconductor devices formed in substrate 202 may be formed as part of a front-end process.

[0071] Step 104 of method 100 forms a metal layer as part of an interconnect network. As Figure 2 shown, one embodiment of step 104 may form a portion of a multi-layer metal interconnect network on substrate 202 (such as part of a back-end process). In some examples, metal layer 204 may include a portion of a metal line of a multi-layer metal interconnect network, which includes a copper layer, an aluminum layer, an aluminum-copper alloy layer, a ruthenium layer, a cobalt layer, or other suitable metal layers. In other examples, metal layer 204 may include a portion of a metal via of a multi-layer metal interconnect network, which includes a copper layer, an aluminum layer, an aluminum-copper alloy layer, a ruthenium layer, a cobalt layer, a tungsten layer, or other suitable metal layers. In some examples, the deposition method of metal layer 204 may be physical vapor deposition, chemical vapor deposition, electroless plating, electroless deposition, atomic layer deposition, or a combination of the above. In various embodiments, additional openings and metal layers (which may include additional metal lines or metal vias) may be formed under metal layer 204 before depositing metal layer 204 to provide electrical connection between underlying semiconductor devices (such as semiconductor devices in substrate 202) and the subsequently deposited metal layer 204.

[0072] In addition, before forming the metal layer 204, a barrier layer 206 and a liner layer 208 may be formed on the substrate 202. Generally, in at least some existing embodiments, the barrier layer 206 may include tantalum nitride, and the liner layer 208 may include tantalum, and their respective deposition methods may be chemical vapor deposition, atomic layer deposition, or physical vapor deposition. However, in the embodiments of the present invention, other material compositions and layer arrangements are also possible. For example, the barrier layer 206 of various embodiments may include a doped barrier layer or a hybrid barrier layer, and a liner layer 208 may be formed on the barrier layer 206 as appropriate. In other words, a combination of the barrier layer 206 / liner layer 208 may be implemented according to one of the four solutions described herein, which may include a doped barrier layer with or without a liner layer, and a hybrid barrier layer with or without a liner layer. Additional details of the layer arrangement and material composition of the disclosed solutions will be described in conjunction with Figures 6A to 6J as follows.

[0073] After forming the metal layer 204, step 106 of method 100 deposits an etch stop layer and an interlayer dielectric layer. As Figure 2 and Figure 3 shown, an embodiment of step 106 deposits an etch stop layer 302 on the device 200. The etch stop layer 302 may include a single layer or multiple layers. In addition to providing an etch stop mechanism, the etch stop layer 302 may also improve the etch uniformity. In some embodiments, the etch stop layer 302 may include one or more of aluminum oxide, aluminum zirconium oxide, zirconium oxide, silicon carbonitride, silicon oxide, silicon oxycarbide, and other suitable materials. In some examples, the deposition method of the etch stop layer 302 may be atomic layer deposition, chemical vapor deposition, physical vapor deposition, or other suitable deposition methods.

[0074] As Figure 3 shown, other embodiments of step 106 deposit an interlayer dielectric layer 304 on the etch stop layer 302. In some embodiments, the interlayer dielectric layer 304 may include a dielectric material such as silicon carbon hydroxide, silicon oxide, or other suitable materials. In some embodiments, the interlayer dielectric layer 304 may instead include a low dielectric constant dielectric layer such as the oxide of tetraethoxysilane, undoped silicate glass, doped silicon oxide (such as borophosphosilicate glass, fluorosilicate glass, phosphosilicate glass, or borosilicate glass) and / or other suitable low dielectric constant dielectric materials. In some examples, the deposition method of the interlayer dielectric layer 304 may be atomic layer deposition, chemical vapor deposition, physical vapor deposition, sub-atmospheric chemical vapor deposition, flowable chemical vapor deposition; or other suitable deposition techniques. In some examples, after forming the interlayer dielectric layer 304, a hard mask layer, a sacrificial hard mask layer, or a combination of the above may be formed on the interlayer dielectric layer 304.

[0075] After depositing the interlayer dielectric layer 304, step 108 of method 100 patterns the etch stop layer 302 and the interlayer dielectric layer 304 (and the hard mask layer, if a hard mask layer exists) to form via openings exposing the metal layer 204. As Figure 3 and Figure 4 shown, one embodiment of step 108 may use a combination of photolithography (including depositing, exposing, and developing photoresist) and etching (such as using a wet etching process or a dry etching process) to pattern the etch stop layer 302 and the interlayer dielectric layer 304 to form via openings 402 in the etch stop layer 302 and the interlayer dielectric layer 304. In Figure 4 the example, the via opening 402 is trapezoidal. However, in some embodiments, the via opening 402 may be rectangular.

[0076] Step 110 of method 100 deposits a barrier layer and optionally a liner layer. As Figure 4 shown, one embodiment of step 110 deposits a barrier layer 406 and a liner layer 408 on the device 200 and within the via openings 402, including depositing the barrier layer 406 and the liner layer 408 along the sidewalls and bottom surface of the via openings 402. In various embodiments, the barrier layer 406 and the liner layer 408 are conformally deposited such that the thicknesses of the barrier layer 406 and the liner layer 408 are substantially uniform. Generally, in at least some existing implementations, the barrier layer 406 may include tantalum nitride and the liner layer 408 may include tantalum, and their respective deposition methods may be chemical vapor deposition, atomic layer deposition, or physical vapor deposition. However, in embodiments of the present invention, other material compositions and layer arrangements are also possible. For example, the barrier layer 406 of various embodiments may include a doped barrier layer or a hybrid barrier layer, and a liner layer 408 may be formed on the barrier layer 406 optionally. In other words, the combination of the barrier layer 406 / liner layer 408 may be formed according to one of the four schemes described herein, which may include a doped barrier layer with or without a liner layer, and a hybrid barrier layer with or without a liner layer. In many examples, the barrier layer 406 and the liner layer 408 may implement the same or different combinations of barrier / liner layers (according to one of the four schemes), such as the implementation of the barrier layer 206 and the liner layer 208 of the disclosed scheme. Other details of the layer arrangement and material composition of the disclosed scheme will be described Figures 6A to 6J below.

[0077] After depositing the barrier layer 406 (and the optionally formed liner layer 408), step 112 of method 100 deposits a metal layer. As Figure 4 and Figure 5In one embodiment of step 112 as shown, a metal layer 502 is deposited over the barrier layer 406 (or over the liner layer 408 if the liner layer 408 exists) and within the via opening 402. Thus, the metal layer 502 provides electrical contact to the underlying metal layer 204. In some examples, the method of depositing the metal layer 502 can be electroless plating, electroless deposition, physical vapor deposition, atomic layer deposition, or other suitable processes. In some examples, a seed crystal (such as a copper seed crystal when the metal layer 502 includes copper) can be deposited before forming the metal layer 502. After forming the metal layer 502, a chemical mechanical polishing process can be performed to remove the excess material and planarize the upper surface of the device 200. After method 100, the process can return to step 106 and steps 106 to 112 can be repeated to form each interconnect layer of the multi-layer metal interconnect network of the device 200.

[0078] As Figures 6A to 6D shown, a portion of the device 200 (see Figure 5 portion 505) provides different interconnect structure options such as those of method 100 described above. Specifically, Figures 6A to 6D embodiments showing various options are for implementing the barrier layer and the liner layer in the interconnect structure disclosed herein. For example, Figure 6A the embodiment of the device 200 as shown includes a doped barrier layer 606 and a liner layer 608, Figure 6B the embodiment of the device 200 as shown includes a doped barrier layer 606 without a liner layer 608, Figure 6C the embodiment of the device 200 as shown includes a hybrid barrier layer 610 and a liner layer 608, while Figure 6D the embodiment of the device 200 as shown includes a hybrid barrier layer 610 without a liner layer 608. In various embodiments, the doped barrier layer 606 and / or the hybrid barrier layer 610 can be used to implement the barrier layer 206 and / or the barrier layer 406 described above. Similarly, in some examples, the liner layer 608 can be used to implement the liner layer 208 and / or the liner layer 408 described above.

[0079] Figure 6A An embodiment of [description missing] is part of method 100, which forms a doped barrier layer 606 and forms a liner layer 608 over the doped barrier layer 606. In some embodiments, after forming the liner layer 608, a seed crystal (such as a copper seed crystal when the metal layer 502 includes copper) can be deposited before forming the metal layer 502. In some examples, the method of forming the doped barrier layer 606 can be in-situ doping while or after depositing the barrier layer material, and the deposition method can be chemical vapor deposition, atomic layer deposition, or physical vapor deposition. The method of forming the doped barrier layer 606 can be changed to depositing the barrier layer material (such as by chemical vapor deposition, atomic layer deposition, or physical vapor deposition) and then performing doping with a post-treatment process.

[0080] In some embodiments, the doping barrier layer 606 may comprise a cobalt-based material (such as elemental cobalt or in compound form). For example, the cobalt-based material may include nitrides of cobalt (CoN x , CoN, or Co x N), hydrides of cobalt (CoH x or CoH), carbides of cobalt (CoC x , CoC, or Co x C), silicides of cobalt (CoSi x , CoSi, or Co x Si) and / or metal alloys of cobalt (Co-Ru, Co-Rh, Co-Ir, Co-W, Co-Ti, Co-V, Co-Nb, Co-Ta, Co-Mn, Co-Al, Co-Mg, Co-Zn, Co-Cr, Co-Fe, Co-Ni, Co-Sn, Co-Zr, or Co-Mo). In some embodiments, the doping barrier layer 606 may comprise a ruthenium-based material (such as elemental ruthenium or in compound form). For example, the ruthenium-based material may include nitrides of ruthenium (RuN x , RuN, or Ru x N), hydrides of ruthenium (RuH x or Ru x H), carbides of ruthenium (RuC x , RuC, or Ru x C), silicides of ruthenium (RuSi x , RuSi, or Ru x Si) and / or metal alloys of ruthenium (Ru-Co, Ru-Rh, Ru-Ir, Ru-W, Ru-Ti, Ru-V, Ru-Nb, Ru-Ta, Ru-Mn, Ru-Al, Ru-Mg, Ru-Zn, Ru-Cr, Ru-Fe, Ru-Ni, Ru-Sn, Ru-Zr, or Ru-Mo). In some embodiments, the doping barrier layer 606 may comprise a tantalum-based material (such as elemental tantalum or in compound form). For example, the tantalum-based material may include nitrides of tantalum (TaN x , TaN, or Ta x N), hydrides of tantalum (TaH x or Ta x H), carbides of tantalum (TaC x , TaC, or Ta x C), silicides of tantalum (TaSi x, TaSi, or TaxSi) and / or a metal alloy of tantalum (Ta-Co, Ta-Rh, Ta-Ir, Ta-W, Ta-Ti, Ta-V, Ta-Nb, Ta-Mn, Ta-Al, Ta-Mg, Ta-Zn, Ta-Cr, Ta-Fe, Ta-Ni, Ta-Sn, Ta-Zr, or Ta-Mo). In various embodiments, the metal alloys of cobalt, ruthenium, and tantalum may include alloys having transition metals or inner transition metals.

[0081] In some embodiments, cobalt-based materials, ruthenium-based materials, tantalum-based materials, or alloys thereof may provide doping materials that can be introduced into the barrier layer to form a doped barrier layer 606. In some embodiments, when the formation method of the doped barrier layer 606 is in-situ doping, the process may include precursor soaking and plasma or heat treatment during the deposition of the doped barrier layer 606 or after the deposition of the barrier layer material to form the doped barrier layer. For example, the precursor gas, carrier gas, and / or gas materials used to form the plasma during the in-situ doping process may include hydrogen, nitrogen, ammonia, hydrogen radicals, methane, silane, or materials containing H-, OH-, N-, C-, Si-, O-, CH3-, and / or other organic alkyl groups. In some examples, when the formation method of the doped barrier layer 606 is doping via a post-treatment process, the process may include precursor soaking and plasma or heat treatment after the deposition of the barrier layer. In various examples, the precursor gas, carrier gas, and / or gas materials used to form the plasma during doping via a post-treatment process may include hydrogen, nitrogen, ammonia, hydrogen radicals, methane, silane, or materials containing H-, OH-, N-, C-, Si-, O-, CH3-, and / or other organic alkyl groups. In some embodiments, doping is performed via a post-treatment process, and the dopant material can be introduced into the barrier layer by atomic layer deposition, chemical vapor deposition, physical vapor deposition, ion implantation process, and / or gas soaking process, such that the dopant material is buried in the barrier layer and / or formed on the surface of the barrier layer. In at least some examples, in-situ doping can be performed during the deposition of the doped barrier layer 606 to introduce the doping material, and the formation method of the doped barrier layer 606 is generally to introduce the doping material after forming the barrier layer material (such as in-situ doping of the previously deposited barrier layer material or performing a post-treatment process on the previously deposited barrier layer material).

[0082] Figure 6B The illustrated embodiment is part of method 100, which forms a doped barrier layer 606 without forming a liner layer 608 on the doped barrier layer 606. Conversely, in some embodiments, after forming the doped barrier layer 606, a seed crystal (such as a copper seed crystal when the metal layer 502 contains copper) may be deposited before forming the metal layer 502. Figure 6B of the doped barrier layer 606 in the embodiment and in combination with Figure 6AThe doped barrier layer 606 described in the above embodiments may be substantially the same.

[0083] Figure 6C The illustrated embodiment is part of method 100 that forms a hybrid barrier layer 610 and then forms a liner layer 608 on the hybrid barrier layer 610. In some embodiments, after forming the liner layer 608 and before forming the metal layer 502, a seed crystal (such as a copper seed crystal when the metal layer 502 contains copper) may be deposited. In some examples, after depositing the hybrid barrier layer 610 and before forming the liner layer 608, a post-treatment process may be performed on the hybrid barrier layer 610.

[0084] In some embodiments, the hybrid barrier layer 610 may include a metal alloy such as a binary metal alloy, a ternary metal alloy, a quaternary metal alloy, or a general material system containing multiple elements. In various examples, the hybrid barrier layer 610 may include cobalt, ruthenium, tantalum, niobium, titanium, tungsten, molybdenum, zinc, aluminum, manganese, zirconium, chromium, iron, nickel, rhodium, iridium, transition metals, transition metal derivatives of carbides / oxides / hydrides / nitrides / silicides, and / or combinations thereof. In some embodiments, the hybrid barrier layer 610 may be formed using a dual-damascene or single-damascene process. Additionally, the hybrid barrier layer 610 may be formed using physical vapor deposition, chemical vapor deposition, atomic layer deposition, plasma-assisted atomic layer deposition, or plasma-assisted chemical vapor deposition. In one example, the formation temperature of the hybrid barrier layer 610 may be from about room temperature (20 to 25 °C) to about 1000 °C.

[0085] In some examples, a post-treatment process may be performed on the hybrid barrier layer 610 after forming the hybrid barrier layer 610. In some embodiments, the post-treatment process includes plasma immersion or gas treatment using argon, nitrogen, ammonia, hydrogen, or combinations thereof. Alternatively or additionally, plasma immersion or gas treatment may be performed using hydrogen radicals, methanol, silane, materials having H-, OH-, N-, C-, Si-, O-, CH3, and / or other organic alkyl groups. In some embodiments, the post-treatment process of the hybrid barrier layer 610 may additionally (or alternatively) include bombarding the hybrid barrier layer 610 with metals, metal alloys, carbides, and / or nitrides (such as using a physical vapor deposition process).

[0086] Figure 6D The illustrated embodiment is part of method 100 that forms a hybrid barrier layer 610 without forming a liner layer 608 on the hybrid barrier layer 610. Instead, in some embodiments, after forming the hybrid barrier layer 610, a seed crystal (such as a copper seed crystal when the metal layer 502 contains copper) may be deposited before forming the metal layer 502. Figure 6D The hybrid barrier layer 610 in the embodiments of Figure 6C The hybrid barrier layer 610 described in the above embodiments may be substantially the same.

[0087] The doped barrier layer 606 is typically introduced with a doping material (such as a cobalt-based material, a ruthenium-based material, a tantalum-based material, or an alloy thereof) in one or more sequential processes after the barrier layer material is formed. Compared with the doped barrier layer 606, the hybrid barrier layer 610 is formed by simultaneously depositing the barrier layer material and the doping material (such as a metal alloy, cobalt, ruthenium, tantalum, niobium, titanium, tungsten, molybdenum, zinc, aluminum, manganese, zirconium, chromium, iron, nickel, rhodium, iridium, a transition metal, a transition metal derivative of a carbide / oxide / hydride / nitride / silicide, and / or a combination of the above) as part of a single process. Due to the difference in the method of introducing the doping material into the doped barrier layer 606 and the hybrid barrier layer 610, there are structural differences between the two, such as the presence or absence of multiple material interfaces and / or elements. In the fabricated device 200, the above structural differences can be measured using a transmission electron microscope, a scanning electron microscope, an energy dispersive X-ray spectrometer, or other suitable metrology tools or techniques. For example, Figures 6E to 6I showing Figure 6B a portion 650 of the device 200 provides different examples of the structure of a portion of the doped barrier layer 606. Figure 6J showing Figure 6D a portion 670 of the device 200 provides an example of the structure of a portion of the hybrid barrier layer 610. Overall, Figures 6E to 6J the structural differences present in the fabricated device are emphasized, and the device includes a doped barrier layer 606 or a hybrid barrier layer 610.

[0088] In Figure 6E an example, the doped barrier layer 606 is formed on the interlayer dielectric layer 304, and the metal layer 502 is formed on the doped barrier layer 606 (or on the liner layer 608, if the liner layer 608 exists), as described above. Figure 6E In the example shown, the doping material (the doping material introduced into the doped barrier layer 606) does not mix with the adjacent layer, and the doping material is substantially uniformly mixed throughout the previously deposited barrier layer material, so that a first interface 652 can be defined between the metal layer 502 and the doped barrier layer 606, and a second interface 654 can be defined between the doped barrier layer 606 and the interlayer dielectric layer 304. Figures 6F to 6I is Figure 6E a variation of the example. For example, Figure 6FIn the example shown, the doping material introduced into the previously deposited barrier layer material does not fully reach the bottom of the barrier layer material, so that the undoped barrier layer portion 606A can be sandwiched between the doped barrier layer 606 and the underlying interlayer dielectric layer 304. In this way, a first interface 652 can be defined between the metal layer 502 and the doped barrier layer 606, a second interface 654 can be defined between the undoped barrier layer portion 606A and the interlayer dielectric layer 304, and a third interface 656 can be defined between the doped barrier layer 606 and the undoped barrier layer portion 606A.

[0089] Figure 6C In the example shown, the doping material introduced into the previously deposited barrier layer can diffuse into or mix with the underlying interlayer dielectric layer 304, so that the doped interlayer dielectric layer portion 606B can be sandwiched between the doped barrier layer 606 and the underlying interlayer dielectric layer 304. In this way, a first interface 652 can be defined between the metal layer 502 and the doped barrier layer 606, a second interface 654 can be defined between the doped barrier layer 606 and the doped interlayer dielectric layer portion 606B, and a third interface 658 can be defined between the doped interlayer dielectric layer portion 606B and the interlayer dielectric layer 304.

[0090] Figure 6H In the example shown, a portion of the doping material forming the doped barrier layer 606 remains on the upper surface of the doped barrier layer 606 (rather than being incorporated into the previously deposited barrier layer when forming the doped barrier layer 606), thereby defining a doping material layer 606C. The subsequently formed metal layer 502 is thus formed on the doping material layer 606C. In an example including a liner layer 608, the liner layer 608 can be formed on the doping material layer 606C, and then the metal layer 502 is formed. As shown in this example, a first interface 652 can be defined between the doping material layer 606C and the doped barrier layer 606, a second interface 654 can be defined between the doped barrier layer 606 and the underlying interlayer dielectric layer 304, and a third interface 660 can be defined between the metal layer 502 and the doping material layer 606C.

[0091] It should be understood that the various structural features shown can exist and be detected in the fabricated device 200. Figures 6E to 6H The above-mentioned various structural features. Specifically, it should be understood that various combinations of structural features and individual interfaces can exist in the same device 200 or in different devices 200 on the same substrate (such as substrate 202). As Figure 6I shown in the exemplary example, which includes Figure 6E and Figure 6F combinations of the above examples shown. Specifically, Figure 6IExamples include regions 680 and 684, where undoped barrier layer portion 606A is sandwiched between doped barrier layer 606 and underlying interlayer dielectric layer 304. Thus, regions 680 and 684 include a first interface 652 between metal layer 502 and doped barrier layer 606, a second interface 654 between undoped barrier layer portion 606A and interlayer dielectric layer 304, and a third interface 656 between doped barrier layer 606 and undoped barrier layer portion 606A. As Figure 6I shown in the example of, region 682 is sandwiched between regions 680 and 684, where region 682 has substantially no doped material mixing with adjacent layers, and the doped material is substantially uniformly distributed throughout the previously deposited barrier layer material in region 682. Thus, region 682 includes a first interface 652 between metal layer 502 and doped barrier layer 606, and a second interface 654 between doped barrier layer 606 and interlayer dielectric layer 304.

[0092] Figure 6I The example of introduces doped material into the previously deposited barrier layer material without completely reaching the bottom of the barrier layer material in regions 680 and 684, and the doped material is uniformly distributed throughout all the barrier layer material in region 682. Although Figure 6I the example of is Figures 6E to 6H an illustrative combination of various structural features and individual interfaces mentioned in the embodiment of, it should be understood that devices 200 fabricated by other examples may have Figures 6E to 6H various other combinations of the various structural features and individual interfaces mentioned in the embodiment of. For example, although the doped material is substantially uniformly dispersed throughout doped barrier layer 606, it may include intermittent regions (similar to regions 680 and 684) of undoped barrier layer portion 606A, doped interlayer dielectric portion 606B, or doped material layer 606C. These structural features present in the intermittent regions or throughout the device help to distinguish devices containing doped barrier layer 606 from devices containing hybrid barrier layer 610.

[0093] Specifically, as Figure 6J shown in the example of, hybrid barrier layer 610 is formed on interlayer dielectric layer 304, and metal layer 502 is formed on hybrid barrier layer 610 (or on cushion layer 608, if cushion layer 608 exists), as described above. As Figure 6J shown, since the method of forming hybrid barrier layer 610 is part of a single process of simultaneously depositing barrier layer material and doped material, hybrid barrier layer 610 includes materials with substantially consistent composition, and thus has substantially clean and consistent interfaces with adjacent material layers. In this way, Figure 6J the example of includes a first interface 672 defined between metal layer 502 and hybrid barrier layer 610, and a second interface 674 defined between hybrid barrier layer 610 and interlayer dielectric layer 304.

[0094] Compared with the individual interfaces present in the device implementing the doping barrier layer 606, implementing the hybrid barrier layer 610 can provide a consistently clean and uniform interface. As described above, this helps to distinguish between devices containing the doping barrier layer 606 and devices containing the hybrid barrier layer 610. It should be understood that the single process of forming the hybrid barrier layer 610 is generally less complex compared to the sequential processes for forming the doping barrier layer 606. For example, the sequential processes for forming the doping barrier layer 606 may employ multiple process chambers of a multi-chamber process system, while the single process for forming the hybrid barrier layer 610 may employ a single multi-functional chamber (which can deposit the barrier layer material and the doping material simultaneously).

[0095] Figure 7 FIG. 6 is an illustrative portion of the multi-layer metal interconnect network 700 of the device 200 formed according to the method 100 described above. As shown, the multi-layer metal interconnect network 700 includes a plurality of interconnect layers 702, 704, 706, and 708. As shown, each of the plurality of interconnect layers 702, 704, 706, and 708 includes a via portion 710 and a metal line portion 712. In some embodiments, the via portion 710 and the metal line portion 712 include a metal layer 716, which may be similar to the metal layers 204 and 502 described above. The plurality of interconnect layers 702, 704, 706, and 708 may include any metallization layer formed on the substrate 202 of the device 200, such as a metallization layer formed as part of the backend process. The etch stop layer 714 may be similar to the etch stop layer 302 described above and is sandwiched between adjacent ones of the plurality of interconnect layers 702, 704, 706, and 708. It should be understood that a surrounding dielectric material such as the above-described interlayer dielectric layer 304 may be provided to surround the via portion 710 and the metal line portion 712 of each of the plurality of interconnect layers 702, 704, 706, and 708.

[0096] In the embodiments described herein, the formation method of each of the plurality of interconnect layers 702, 704, 706, and 708 of the multi-layer metal interconnect network 700 may employ any of a variety of schemes (such as the scheme described above), to implement the barrier layer and the liner layer in the plurality of individual interconnect layers 702, 704, 706, and 708. In the example shown, the interconnect layer 702 includes a doping barrier layer 606 and a liner layer 608 (such as Figures 6A to 6D ) sandwiched between the via portion 710 / metal line portion 712 and the surrounding dielectric layer, the interconnect layer 704 includes a hybrid barrier layer 610 and a liner layer 608 (see Figure 6A ) sandwiched between the via portion 710 / metal line portion 712 and the surrounding dielectric layer, the interconnect layer 706 includes a doping barrier layer 606 but no liner layer 608 (see Figure 6C ) sandwiched between the via portion 710 / metal line portion 712 and the surrounding dielectric layer, and the interconnect layer 708 includes a hybrid barrier layer 610 but no liner layer 608 (see Figure 6B)Interposed between the via portion 710 / metal line portion 712 and the surrounding dielectric layer, and the inner connection layer 708 includes a hybrid barrier layer 610 but no liner layer 608 (see Figure 6D )Interposed between the via portion 710 / metal line portion 712 and the surrounding dielectric layer. Although Figure 7 The specific arrangements of the barrier layer and the liner layer in the plurality of individual inner connection layers 702, 704, 706, and 708 are shown. The examples provided are not intended to limit the embodiments of the present invention. Other embodiments may adopt different arrangements without departing from the scope of the present invention. Specifically, various embodiments may implement any one of a variety of schemes for the barrier layer and the liner layer (see Figures 6A to 6D )In each of the plurality of inner connection layers 702, 704, 706, and 708. In other words, the inner connection layers 702, 704, 706, and 708 may each include any one of four schemes (which may also be regarded as barrier layer arrangements): (i) a doped barrier layer and a liner layer; (ii) a doped barrier layer but no liner layer; (iii) a hybrid barrier layer and a liner layer; or (iv) a hybrid barrier layer but no liner layer.

[0097] As described above, compared with implementing a doped barrier layer 606, implementing a hybrid barrier layer 610 can provide a cleaner and more consistent interface. Thus, in some examples, a hybrid barrier layer 610 needs to be adopted in the more critical lower-side metal layers of the back-end inner connection structure (such as metal layers M0 to M3, whose metal line pitch is less than or equal to about 40 nm), and a hybrid barrier layer 610 or a doped barrier layer 606 is adopted in the upper-side metal layers of the back-end inner connection structure (such as metal layer M4 or higher metal layers, whose metal line pitch is greater than about 40 nm). Of course, in some examples, the doped barrier layer 606 can be used in the lower-side metal layers instead. As for the liner layer 608, it can provide a better gap filling effect, thereby providing a better device yield. In some examples, therefore, the liner layer 608 is usually adopted in the lower-side metal layers of the back-end inner connection structure (such as metal layers M0 to M3) because the metal line pitch of the lower-side metal layers is reduced, and there are more gap filling challenges without the liner layer 608. In the more upper-side metal layers of the back-end inner connection structure (such as metal layer M4 or higher metal layers), the metal line pitch increases, and gap filling is no longer a problem, so the liner layer 608 is not required (although some embodiments may still adopt the liner layer 608). It should still be noted that in some examples, the liner layer 608 may still negatively affect the resistance of the metal layer. Therefore, the decision of whether to adopt the liner layer 608 also depends on the requirements of device performance. Overall, the decision to implement which of the four schemes (such as a doped barrier layer with or without a liner layer, and a hybrid barrier layer with or without a liner layer) depends on the device performance and yield requirements of the given metal layers of the back-end inner connection structure.

[0098] As described above, the semiconductor device formed in the substrate 202 may include devices configured with Figures 8 to 10 the devices described. In addition, although the above embodiments illustrate forming a barrier layer and / or a liner layer in the back-end process, the techniques described herein can be used to form a barrier layer and / or a liner layer in the front-end process of fabricating a device, such as in the front-end process of fabricating a device configured with Figures 8 to 10 the devices described. In this way, Figures 8 to 10 the devices will be described below.

[0099] Figure 8 The metal oxide semiconductor transistor 800 shown in the figure can provide an example of a device type that may include embodiments of the present invention. The transistor 800 can be fabricated on a substrate 802 and includes a gate stack 804. The substrate 802 can be a semiconductor substrate such as a silicon substrate. The substrate 802 can include multiple layers such as conductive layers or insulating layers formed on the substrate 802. The substrate 802 can include various doping settings, depending on the design requirements known in the art. The substrate 802 can also include other semiconductors such as germanium, silicon carbide, silicon germanium, or diamond. The substrate 802 can alternatively include semiconductor compounds and / or semiconductor alloys. In addition, in some embodiments, the substrate 802 can include an epitaxial layer, which can have stress to improve performance, can include a silicon-on-insulator structure, and / or can have other suitable enhancement structures.

[0100] The gate stack 804 includes a gate dielectric layer 806 and a gate 808 located on the gate dielectric layer 806. In some embodiments, the gate dielectric layer 806 can include an interface layer such as a silicon oxide layer or a silicon oxynitride layer, and the interface layer can be formed by chemical oxidation, thermal oxidation, atomic layer deposition, chemical vapor deposition, and / or other suitable methods. In some examples, the gate dielectric layer 806 includes a high-k dielectric layer such as hafnium oxide. The high-k dielectric layer can alternatively include other high-k dielectric layers such as titanium oxide, hafnium zirconium oxide, tantalum trioxide, hafnium silicate, zirconium dioxide, zirconium silicate, lanthanum oxide, aluminum oxide, zirconium oxide, titanium oxide, tantalum pentoxide, yttrium oxide, strontium titanate, barium titanate, barium zirconium oxide, hafnium zirconium oxide, hafnium lanthanum oxide, hafnium silicon oxide, lanthanum silicon oxide, aluminum silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, barium strontium titanate, aluminum oxide, silicon nitride, silicon oxynitride, combinations of the above, or other suitable materials. The high-k gate dielectric layer used and described herein includes dielectric materials having a high dielectric constant, such as greater than the dielectric constant of thermally grown silicon oxide (about 3.9). In other embodiments, the gate dielectric layer 806 can include silicon oxide or other suitable dielectric materials. The gate dielectric layer 806 can be formed by atomic layer deposition, physical vapor deposition, chemical vapor deposition, oxidation, and / or other suitable methods.

[0101] In some embodiments, the gate 808 may be deposited in a gate-first process or a gate-last process (such as replacement gate). In various embodiments, the gate 808 includes a conductive layer such as tungsten, titanium, titanium nitride, titanium aluminum, titanium aluminum nitride, tantalum, tantalum nitride, tungsten nitride, rhenium, iridium, ruthenium, molybdenum, aluminum, copper, cobalt, cobalt silicide, nickel, nickel silicide, combinations of the foregoing, and / or other suitable compositions. In some examples, the gate 808 may include a first metal material for n-type transistors and a second metal material for p-type transistors. Thus, the transistor 800 may include a dual work function metal gate setting. For example, the metal contained in the first metal material (such as for n-type devices) may have a work function that substantially matches the work function of the substrate conduction band, or at least substantially matches the work function of the conduction band of the channel region 814 of the transistor 800. Similarly, the metal contained in the second metal material (such as for p-type devices) may have a work function that substantially matches the public function of the substrate valence band, or at least substantially matches the work function of the valence band of the channel region 814 of the transistor 800. Thus, the gate stack 804 may provide a gate for the transistor 800 including n-type and p-type devices. In some embodiments, the gate 808 may alternatively or additionally include a polysilicon layer. In various examples, the gate 808 may be formed by physical vapor deposition, chemical vapor deposition, electron beam evaporation, and / or other suitable processes. In some embodiments, sidewall spacers are formed on the sidewalls of the gate stack 804. These sidewall spacers may include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or combinations of the foregoing.

[0102] The transistor 800 also includes a source region 810 and a drain region 812 each formed in the semiconductor substrate 802 to be adjacent to and formed on both sides of the gate stack 804. In some embodiments, the source region 810 and the drain region 812 include diffused source / drain regions, ion-implanted source / drain regions, epitaxial growth regions, or combinations thereof. The channel region of the transistor 800 is defined as the region between the source region 810 and the drain region 812 under the gate dielectric layer 806, which is located in the semiconductor substrate 802. The channel region 814 has an associated channel length L and an associated channel width W. When a bias voltage greater than the threshold voltage (i.e., the turn-on voltage) of the transistor 800 is applied to the gate 808 and simultaneously applied between the source region 810 and the drain region 812, current (such as the transistor drive current) will flow through the channel region 814 between the source region 810 and the drain region 812. The amount of drive current generated by a given bias voltage (such as the bias voltage applied to the gate 808 or the bias voltage applied between the source region 810 and the drain region 812) is a function of the mobility of the material used to form the channel region 814. In some examples, the channel region 814 includes silicon and / or a high-mobility material such as germanium (which can be epitaxially grown), and any semiconductor compound or semiconductor alloy known in the art. The mobility of electrons and / or holes in the high-mobility material is greater than that of silicon, and its intrinsic electron mobility at room temperature such as 300K is about 1350 cm 2 / V-s, and its intrinsic hole mobility at room temperature such as 300K is about 480 cm 2 / V-s.

[0103] Such as Figure 9 The fin field-effect transistor device 900 shown provides an example of another device type that may include embodiments of the present invention. For example, the fin field-effect transistor device 900 includes one or more fin-based multi-gate field-effect transistors. The fin field-effect transistor device 900 includes a substrate 952, at least one fin 954 extending from the substrate 952, isolation regions 956, and a gate structure 958 located above and around the fin 954. The substrate 952 can be a semiconductor substrate such as a silicon substrate. In various embodiments, the substrate 952 can be substantially the same as the substrate 802 and can include one or more of the above materials used for the substrate 802.

[0104] The fin 954 is similar to the substrate 952, may include one or more epitaxial growth layers, and may include silicon or another semiconductor element such as germanium, a semiconductor compound (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), a semiconductor alloy (such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, indium gallium arsenide, indium gallium phosphide, and / or gallium arsenide phosphide indium), or a combination of the above. The fin 954 can be fabricated using suitable processes, including photolithography and etching processes. The photolithography process may include forming a photoresist layer on the substrate (such as on a silicon layer), exposing the photoresist to a pattern, performing a post-exposure bake process, and developing the photoresist to form a mask unit containing the photoresist. In some embodiments, the method of patterning the photoresist to form the mask unit may employ electron beam lithography. Then, the mask unit can be used to protect regions of the substrate, and the etching process can form a recess into the silicon layer to leave the extended fin 954. The recess can be etched using dry etching (such as chemical oxide removal), wet etching, and / or other suitable processes. Various other embodiments of the method can also be used to form the fin 954 on the substrate 952.

[0105] Each of the plurality of fins 954 may also include a source region 955 and a drain region 957 formed in, on, and / or around the fin 954. The source region 955 and the drain region 957 can be epitaxially grown on the fin 954. In addition, the channel region of the transistor is located in the fin 954 and under the gate structure 958 in a plane along a cross-section AA' that is substantially parallel to Figure 9 that of the fin. In some examples, the channel region of the fin includes a material with high mobility, as described above.

[0106] The isolation region 956 can be a shallow trench isolation structure. A field oxide, a local oxidation of silicon structure, and / or other suitable isolation structures can be alternatively implemented on and / or in the substrate 952. The isolation region 956 can be composed of silicon oxide, silicon nitride, silicon oxynitride, fluorosilicate glass, a low dielectric constant dielectric layer, a combination of the above, and / or other suitable materials known in the art. In one embodiment, the isolation region 956 is a shallow trench isolation structure, and its formation method can be to etch trenches in the substrate 952. Then, the isolation material can be filled into the trenches, followed by a chemical mechanical polishing process. However, other embodiments are also possible. In some embodiments, the isolation region 956 can include a multi-layer structure, such as having one or more liner layers.

[0107] The gate structure 958 includes a gate stack having an interface layer 960 formed over a channel region of the fin 954, a gate dielectric layer 962 formed over the interface layer 960, and a metal layer 964 formed over the gate dielectric layer 962. In various embodiments, the interface layer 960 is substantially the same as a portion of the gate dielectric layer 806 above, such as the interface layer. In some embodiments, the gate dielectric layer 962 is substantially the same as the gate dielectric layer 806 and includes a high-k dielectric layer that may be similar to the high-k dielectric layer used for the gate dielectric layer 806. Similarly, the metal layer 964 in various embodiments is similar to the gate 808 above. In some embodiments, sidewall spacers are formed on sidewalls of the gate structure 958. The sidewall spacers may include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or a combination of the above.

[0108] As Figure 10 shown, the all-around gate device 1000 provides an example of another type of device that may include embodiments of the present invention. For example, the all-around gate device 1000 includes one or more fin-based multi-gate field effect transistors. Since the overall structure of the all-around gate device 1000 is similar in many aspects to Figure 9 the fin field effect transistor device 900 of Figure 10 the exemplary cross-section of the all-around gate device 1000 of Figure 9 is substantially parallel to the cross-section BB' of

[0109] As described above, the transistor 800, the fin field effect transistor device 900, and the all-around gate device 1000 may each include a barrier layer and / or a liner layer as described above. For example, the transistor 800, the fin field effect transistor device 900, and the all-around gate device 1000 may each include (i) a doped barrier layer and a liner layer; (ii) a doped barrier layer but no liner layer; (iii) a hybrid barrier layer and a liner layer; and / or (iv) a hybrid barrier layer but no liner layer.

[0110] Accordingly, the various embodiments described herein provide more advantages than the prior art. It should be understood that not all advantages need to be described herein, that all embodiments do not necessarily have a particular advantage, and that other embodiments may provide different advantages. In one example, the embodiments described herein include an interconnect structure and related methods that can effectively overcome various disadvantages of the prior methods. Specifically, various solutions are provided to implement a barrier layer and / or a liner layer to effectively reduce the resistance of the interconnect structure, including reducing the resistance of the metal interconnect layer. For example, the barrier layer may include a doped barrier layer, and the method of forming the same may perform an in-situ process and / or a post-process. Before forming the metal interconnect layer, a liner layer may be formed on the doped barrier layer as appropriate. The interconnect structure of some embodiments may alternatively include a hybrid barrier layer, and the method of forming the same may perform a post-process as appropriate. Before forming the metal interconnect layer, a liner layer may be formed on the hybrid barrier layer as appropriate. Therefore, generally when implementing the barrier layer and the liner layer in the interconnect structure described herein, at least four different solutions can be provided: (i) a doped barrier layer and a liner layer; (ii) a doped barrier layer but without a liner layer; (iii) a hybrid barrier layer and a liner layer; and (iv) a hybrid barrier layer but without a liner layer. Regardless of the specific implementation or solution, the embodiments of the present invention can reduce the resistance of the interconnect structure. Those skilled in the art of the present technology who benefit from the embodiments of the present invention will clearly understand additional advantages and / or other advantages.

[0111] Accordingly, an embodiment of the present invention provides a method of fabricating a semiconductor device, including: forming a first metal interconnect layer; depositing a dielectric layer on the first metal interconnect layer; patterning the dielectric layer to form an opening exposing the first metal interconnect layer; forming a doped barrier layer or a hybrid barrier layer along sidewalls and a bottom surface of the opening; and depositing a metal layer on the doped barrier layer or the hybrid barrier layer.

[0112] In some embodiments, the method further includes: before depositing the metal layer, forming a liner layer on the doped barrier layer or the hybrid barrier layer; and depositing the metal layer on the liner layer.

[0113] In some embodiments, the step of forming a doped barrier layer or a hybrid barrier layer includes forming a doped barrier layer along sidewalls and a bottom surface of the opening.

[0114] In some embodiments, the step of forming a doped barrier layer or a hybrid barrier layer includes forming a hybrid barrier layer along sidewalls and a bottom surface of the opening.

[0115] In some embodiments, the doped barrier layer includes a nitride of cobalt, a hydride of cobalt, a carbide of cobalt, a silicide of cobalt, or a metal alloy of cobalt.

[0116] In some embodiments, the doped barrier layer includes a nitride of ruthenium, a hydride of ruthenium, a carbide of ruthenium, a silicide of ruthenium, or a metal alloy of ruthenium.

[0117] In some embodiments, the doped barrier layer comprises a nitride of tantalum, a hydride of tantalum, a carbide of tantalum, a silicide of tantalum, or a metal alloy of tantalum.

[0118] In some embodiments, the doped barrier layer is formed by soaking with a precursor and plasma or heat treatment for in-situ doping during or after the formation of the doped barrier layer.

[0119] In some embodiments, the doped barrier layer is formed by soaking with a precursor and plasma or heat treatment for post-treatment process doping after the barrier layer used for forming the doped barrier layer.

[0120] In some embodiments, after forming the hybrid barrier layer, the hybrid barrier layer is bombarded with a metal, a metal alloy, a carbide, or a nitride.

[0121] In another embodiment, a method of fabricating a semiconductor device includes: forming a first layer of a multi-layer interconnect network. In some embodiments, the first layer of the multi-layer interconnect network includes a first via portion and a first metal line portion. In some examples, the method further includes forming a second layer of the multi-layer interconnect network on the first layer of the multi-layer interconnect network. In some embodiments, the second layer of the multi-layer interconnect network includes a second via portion and a second metal line portion. In various examples, the first layer of the multi-layer interconnect network includes a first barrier layer disposed to at least partially surround the first via portion and the first metal line portion. In some embodiments, the second layer of the multi-layer interconnect network includes a second barrier layer disposed to at least partially surround the second via portion and the second metal line portion. The second barrier layer is disposed differently from the first barrier layer.

[0122] In some embodiments, the first barrier layer includes one of the following: (i) a doped barrier layer and a liner layer on the doped barrier layer; (ii) a doped barrier layer without a liner layer; (iii) a hybrid barrier layer and a liner layer on the hybrid barrier layer; and (iv) a hybrid barrier layer without a liner layer.

[0123] In some embodiments, the second barrier layer includes one of the following: (i) a doped barrier layer and a liner layer on the doped barrier layer; (ii) a doped barrier layer without a liner layer; (iii) a hybrid barrier layer and a liner layer on the hybrid barrier layer; and (iv) a hybrid barrier layer without a liner layer.

[0124] In some embodiments, the doped barrier layer comprises a nitride of cobalt, a hydride of cobalt, a carbide of cobalt, a silicide of cobalt, or a metal alloy of cobalt.

[0125] In some embodiments, the doped barrier layer comprises a nitride of ruthenium, a hydride of ruthenium, a carbide of ruthenium, a silicide of ruthenium, or a metal alloy of ruthenium.

[0126] In some embodiments, the doping barrier layer includes a nitride of tantalum, a hydride of tantalum, a carbide of tantalum, a silicide of tantalum, or a metal alloy of tantalum.

[0127] In some embodiments, the hybrid barrier layer includes a barrier layer bombarded with a metal, a metal alloy, a carbide, or a nitride.

[0128] In yet another embodiment, a semiconductor device includes: a substrate containing one or more semiconductor devices; a first layer of a multi-layer interconnection network formed on the substrate; and a second layer of the multi-layer interconnection network formed on the first layer of the multi-layer interconnection network. In some embodiments, the first layer of the multi-layer interconnection network includes a first barrier layer to at least partially surround a first metal layer of the first layer of the multi-layer interconnection network. In some examples, the second layer of the multi-layer interconnection network includes a second barrier layer to at least partially surround a second metal layer of the second layer of the multi-layer interconnection network, and the second barrier layer is different from the first barrier layer.

[0129] In some embodiments, the first barrier layer includes one of a doping barrier layer and a hybrid barrier layer, and wherein the second barrier layer includes the other of the doping barrier layer and the hybrid barrier layer.

[0130] In some embodiments, the semiconductor device further includes at least one of a first liner layer and a second liner layer, the first liner layer being interposed between the first barrier layer and the first metal layer, and the second liner layer being interposed between the second barrier layer and the second metal layer.

[0131] The features of the above embodiments are beneficial for those skilled in the art of the present technology to understand the present invention. Those skilled in the art of the present technology should understand that the present invention can be used as a basis to design and vary other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art of the present technology should also understand that these equivalent replacements do not depart from the spirit and scope of the present invention, and can be changed, replaced, or modified without departing from the spirit and scope of the present invention.

Claims

1. A method for fabricating a semiconductor device, comprising: Forming a first metal interconnection layer; Depositing a dielectric layer on the first metal interconnection layer; Patterning the dielectric layer to form an opening exposing the first metal interconnection layer; Forming a doping barrier layer or a hybrid barrier layer along sidewalls and a lower surface of the opening; and Depositing a metal layer on the doping barrier layer or the hybrid barrier layer.

2. The method for fabricating a semiconductor device as claimed in claim 1, further comprising: Forming a liner layer on the doping barrier layer or the hybrid barrier layer before depositing the metal layer; And Depositing the metal layer on the liner layer.

3. The method for fabricating a semiconductor device as claimed in claim 1, wherein the step of forming the doping barrier layer or the hybrid barrier layer comprises forming the doping barrier layer along sidewalls and a lower surface of the opening.

4. The method for fabricating a semiconductor device as claimed in claim 1, wherein the step of forming the doping barrier layer or the hybrid barrier layer comprises forming the hybrid barrier layer along sidewalls and a lower surface of the opening.

5. A method for fabricating a semiconductor device, comprising: Forming a first layer of a multi-layer interconnection network, wherein the first layer of the multi-layer interconnection network comprises a first via portion and a first metal line portion; and Forming a second layer of the multi-layer interconnection network on the first layer of the multi-layer interconnection network, wherein the second layer of the multi-layer interconnection network comprises a second via portion and a second metal line portion, Wherein the first layer of the multi-layer interconnection network comprises a first barrier layer disposed to at least partially surround the first via portion and the first metal line portion; and Wherein the second layer of the multi-layer interconnection network comprises a second barrier layer disposed to at least partially surround the second via portion and the second metal line portion, and the second barrier layer is disposed differently from the first barrier layer.

6. The method for fabricating a semiconductor device as claimed in claim 5, wherein the first barrier layer comprises one of the following: (i) a doping barrier layer and a liner layer on the doping barrier layer; (ii) the doping barrier layer without the liner layer; (iii) a hybrid barrier layer and the liner layer on the hybrid barrier layer; and (iv) the hybrid barrier layer without the liner layer.

7. The method for fabricating a semiconductor device as claimed in claim 6, wherein the second barrier layer comprises one of the following: (i) the doping barrier layer and the liner layer on the doping barrier layer; (ii) the doping barrier layer without the liner layer; (iii) the hybrid barrier layer and the liner layer on the hybrid barrier layer; and (iv) the hybrid barrier layer without the liner layer.

8. A semiconductor device, comprising: A substrate containing one or more semiconductor devices; A first layer of a multi-layer interconnection network formed on the substrate; And A second layer of the multi-layer interconnection network formed on the first layer of the multi-layer interconnection network, Wherein the first layer of the multi-layer interconnection network comprises a first barrier layer to at least partially surround a first metal layer of the first layer of the multi-layer interconnection network; and Wherein the second layer of the multi-layer interconnect network includes a second barrier layer to at least partially surround a second metal layer of the second layer of the multi-layer interconnect network, and the second barrier layer is different from the first barrier layer.

9. The semiconductor device as claimed in claim 8, wherein the first barrier layer includes one of a doped barrier layer and a hybrid barrier layer, and wherein the second barrier layer includes the other of the doped barrier layer and the hybrid barrier layer.

10. The semiconductor device as claimed in claim 8, further comprising at least one of a first liner layer and a second liner layer, the first liner layer being interposed between the first barrier layer and the first metal layer, and the second liner layer being interposed between the second barrier layer and the second metal layer.

Images