Package structure

Abstract

The invention provides a packaging structure. The packaging structure comprises a lower substrate, an upper substrate and a chip. The lower substrate defines a lower via. The upper substrate is over the lower substrate and defines an upper via connected to the lower via. A portion of a top surface of the lower substrate is exposed through the upper via. The chip is at least partially received by the upper perforation and supported by the portion of the top surface of the lower substrate.

Description

Technical Field

[0001] The present disclosure generally relates to a packaging structure. Background Art

[0002] Currently, in order to manufacture a packaging structure for a chip or component having input / output (I / O) terminals on opposite sides, a ceramic substrate may be manufactured to provide a specific structure for the chip or component to be disposed therein, such that the I / O terminals on the opposite sides of the chip or component can be exposed through the ceramic substrate for electrical connection. However, the cost and difficulty of manufacturing a ceramic substrate with a specific structure may be relatively high, and the brittle texture of the ceramic substrate may make the ceramic substrate relatively fragile, thus reducing the yield. Summary of the Invention

[0003] In one or more arrangements, a packaging structure includes a lower substrate, an upper substrate, and a chip. The lower substrate defines a lower through-hole. The upper substrate is above the lower substrate and defines an upper through-hole connected to the lower through-hole. A portion of the top surface of the lower substrate is exposed through the upper through-hole. The chip is at least partially received by the upper through-hole and supported by the portion of the top surface of the lower substrate.

[0004] In one or more arrangements, a packaging structure includes a substrate structure and a chip. The substrate structure defines a through-hole that includes a stepped sidewall structure. The chip is disposed in the through-hole and supported by the stepped sidewall structure. In a top perspective view, a central axis of the substrate structure is not parallel to a central axis of the chip.

[0005] In one or more arrangements, a packaging structure includes a first substrate, a second substrate, and a chip. The first substrate defines a first through-hole. The second substrate is above the first substrate and physically spaced apart from the first substrate. The second substrate defines a second through-hole. In a cross-sectional perspective view, a central axis of the first through-hole is not aligned with a central axis of the second through-hole. The chip is disposed in the second through-hole. Brief Description of the Drawings

[0006] Aspects of the present disclosure are better understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that the various features may not be drawn to scale, and the dimensions of the various features may be arbitrarily increased or decreased for the sake of clarity of discussion.

[0007] Figure 1A is a cross-section of a packaging structure according to some arrangements of the present disclosure.

[0008] Figure 1B is a cross-section of a packaging structure according to some arrangements of the present disclosure.

[0009] Figure 1Cis a cross-section of a packaging structure according to some arrangements of the present disclosure.

[0010] Figure 1D is a top view of a packaging structure according to some arrangements of the present disclosure.

[0011] Figure 1E is a top view of a packaging structure according to some arrangements of the present disclosure.

[0012] Figure 1F is a top view of a packaging structure according to some arrangements of the present disclosure.

[0013] Figure 1G is a perspective view of a packaging structure according to some arrangements of the present disclosure.

[0014] Figure 2A 、 Figure 2B 、 Figure 2C 、 Figure 2D 、 Figure 2E 、 Figure 2F 、 Figure 2G 、 Figure 2H and Figure 2I illustrate the various stages of an exemplary method for manufacturing a packaging structure according to some embodiments of the present disclosure.

[0015] Figure 3A and Figure 3B illustrate the various stages of an exemplary method for manufacturing a packaging structure according to some embodiments of the present disclosure.

[0016] Common reference numerals are used throughout the figures and the detailed description to indicate the same or similar elements. The present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Detailed Description

[0017] Figure 1A is a cross-section of a packaging structure 1A according to some arrangements of the present disclosure. The packaging structure 1A may include substrates 10 and 20, an adhesive layer 30, conductive wires 40 and 42, a spacer structure 50, an adhesive element 51, a chip 60, and a connection element 90.

[0018] The substrates 10 and 20 may each include, for example, a printed circuit board, such as a paper copper foil laminate, a composite copper foil laminate, or a polymer impregnated fiberglass-like copper foil laminate. The substrates 10 and 20 may each include an interconnect structure, which may include a plurality of conductive traces and / or conductive vias. The interconnect structure may include a redistribution layer (RDL) and / or a ground element. In some arrangements, the substrates 10 and 20 may each include an organic substrate or a lead frame. In some arrangements, the substrates 10 and 20 may each include a ceramic material or a metal plate. In some arrangements, the substrates 10 and 20 may each include a double-layer substrate, which includes a core layer and conductive materials and / or structures disposed on the upper and lower surfaces of the substrate. The substrates 10 and 20 may each include a semiconductor wafer or an electronic component. The electronic component may be a chip or die that includes a semiconductor substrate, one or more integrated circuit devices, and one or more overlying interconnect structures therein. The integrated circuit devices may include active devices such as transistors and / or passive devices such as resistors, capacitors, inductors, or combinations thereof. In some arrangements, the substrates 10 and 20 may each include one or more conductive elements, surfaces, contacts, or pads.

[0019] In some arrangements, the substrate 10 has a surface 101 (also referred to as the "top surface" or "upper surface") and a surface 102 (also referred to as the "bottom surface" or "lower surface") opposite the surface 101. In some arrangements, the substrate 10 defines a via 10T. In some arrangements, the via 10T extends between the surface 101 (or top surface) and the surface 102 (or bottom surface) of the substrate 10. In some arrangements, in a cross-sectional perspective view, the via 10T includes at least sidewalls 105 and 106. The substrate 10 may be referred to as the first substrate or the lower substrate. The via 10T may be referred to as the lower via.

[0020] In some arrangements, the substrate 10 includes a base layer 100, circuit layers 110 and 130, dielectric layers 120 and 140, and one or more conductive vias 150. In some arrangements, the base layer 100 can be or include a semiconductor substrate or other suitable materials or components included in the substrate 10 as described above. In some arrangements, the circuit layer 110 is adjacent to the surface 101 (or top surface), and the circuit layer 130 is adjacent to the surface 102 (or bottom surface). In some arrangements, the circuit layer 110 can be or include a conductive pad, a conductive layer, a conductive pattern, a conductive portion, etc. In some arrangements, the circuit layer 110 includes portions 110A and 110B. The portions 110A and 110B can be electrically disconnected from each other. In some arrangements, the circuit layer 130 can be or include a conductive pad, a conductive layer, a conductive pattern, a conductive portion, etc. In some arrangements, the circuit layer 130 includes portions 130A and 130B. The portions 130A and 130B can be electrically disconnected from each other. In some arrangements, the circuit layer 130 further includes a protective film 170B on the portion 130B. The protective film can be or include a metal finish layer, such as a NiAu alloy or other suitable materials.

[0021] In some arrangements, the dielectric layers 120 and 140 are disposed on the circuit layers 110 and 130, respectively. In some arrangements, the dielectric layer 120 has one or more openings exposing portions of the circuit layer 110. In some arrangements, the dielectric layer 140 has one or more openings 140T exposing portions of the circuit layer 130. In some arrangements, the protective film 170B is exposed through the opening 140T. In some arrangements, the conductive via 150 electrically connects the surface 101 of the substrate 10 to the surface 102. In some arrangements, the conductive via 150 penetrates the base layer 100. In some arrangements, the conductive via 150 includes a conductive inner liner 151 and an insulating filling layer 153 (e.g., a dielectric layer). In some arrangements, one of the conductive vias in the conductive via 150 electrically connects to the portion 110A of the circuit layer 110 and the portion 130A of the circuit layer 130, and the other conductive via in the conductive via 150 electrically connects to the portion 110B of the circuit layer 110 and the portion 130B of the circuit layer 130.

[0022] Substrate 20 may be disposed above substrate 10. In some arrangements, substrate 20 is physically spaced apart from substrate 10. In some arrangements, substrate 20 has a surface 201 (also referred to as the "top surface" or "upper surface") and a surface 202 (also referred to as the "bottom surface" or "lower surface") opposite to surface 201. In some arrangements, substrate 20 defines a via 20T. In some arrangements, via 20T extends between the surface 201 (or top surface) and the surface 202 (or bottom surface) of substrate 20. In some arrangements, in a cross-sectional perspective view, via 20T includes at least sidewalls 205 and 206. Substrate 20 may be referred to as the second substrate or the upper substrate. Via 20T may be referred to as the upper via. In some arrangements, the thickness 20t of substrate 20 is greater than the thickness 10t of substrate 10. In some arrangements, the ratio of thickness 10t to thickness 20t (10t / 20t) may be less than about 0.5. In some arrangements, the ratio of thickness 10t to thickness 20t (10t / 20t) is from about 0.1 to about 0.5, such as about 0.25. In some arrangements, in a cross-sectional perspective view, the central axis C10T of via 10T is not aligned with the central axis C20T of via 20T.

[0023] In some arrangements, substrate 20 includes a base layer 200, circuit layers 210 and 230, dielectric layers 220 and 240, and one or more conductive vias 250. In some arrangements, base layer 200 may be or include a semiconductor substrate or other suitable materials or components included in substrate 20 as described above. In some arrangements, circuit layer 210 is adjacent to surface 201 (or the top surface), and circuit layer 230 is adjacent to surface 202 (or the bottom surface). In some arrangements, circuit layer 210 may be or include a conductive pad, a conductive layer, a conductive pattern, a conductive portion, etc. In some arrangements, circuit layer 210 includes portions 210A, 210B, and 210C. Portions 210A, 210B, and 210C may be electrically disconnected from each other. In some arrangements, circuit layer 210 further includes protective films 260B and 260C on portions 210B and 210C, respectively. Portions 210A, 210B, and 210C and protective films 260B and 260C may be referred to as pads or conductive pads. The protective film may be or include a metal finish layer, such as a NiAu alloy or other suitable material. In some arrangements, circuit layer 230 may be or include a conductive pad, a conductive layer, a conductive pattern, a conductive portion, etc. In some arrangements, circuit layer 230 includes portions 230A, 230B, and 230C. Portions 230A, 230B, and 230C may be electrically disconnected from each other. In some arrangements, circuit layer 230 further includes a protective film 270B on portion 230B. The protective film may be or include a metal finish layer, such as a NiAu alloy or other suitable material. Portions 230A, 230B, and 230C and protective film 270B may be referred to as pads or conductive pads. In some arrangements, portion 230B and protective film 270B are exposed through via 10T.

[0024] In some arrangements, dielectric layers 220 and 240 are disposed on circuit layers 210 and 230, respectively. In some arrangements, dielectric layer 220 has one or more openings 220T that expose portions of circuit layer 210. In some arrangements, dielectric layer 240 has one or more openings that expose portions of circuit layer 230. In some arrangements, protective films 260B and 260C are exposed through opening 220T. In some arrangements, conductive vias 250 electrically connect surface 201 of substrate 20 to surface 202. In some arrangements, conductive vias 250 penetrate base layer 200. In some arrangements, conductive vias 250 include a conductive lining 251 and an insulating fill layer 253 (e.g., a dielectric layer). In some arrangements, one of the conductive vias 250 electrically connects to portion 210A of circuit layer 210 and portion 230A of circuit layer 230, and another of the conductive vias 150 electrically connects to portion 210B of circuit layer 210 and portion 230C of circuit layer 230. In some arrangements, conductive vias 150 and 250 can be jointly configured to form a conductive via structure that electrically connects substrate 10 to substrate 20.

[0025] Chip 60 can be disposed in via 20T of substrate 20. In some arrangements, chip 60 has a surface 601 (also referred to as the "top surface" or "upper surface"), a surface 602 opposite surface 601 (also referred to as the "bottom surface" or "lower surface"), and at least surfaces 603 and 604 (also referred to as "lateral side surfaces") that extend between surface 601 and surface 602. In some arrangements, surface 601 (or the top surface) of chip 60 protrudes beyond surface 201 (or the top surface) of substrate 20, and surface 602 (or the bottom surface) of chip 60 is generally aligned with surface 101 (or the top surface) of substrate 10. In some arrangements, the height of surface 602 (or the bottom surface) of chip 60 is lower than the height of surface 202 (or the bottom surface) of substrate 20 relative to surface 101 (or the top surface) of substrate 10. In some arrangements, surface 601 of chip 60 and surface 201 of substrate 20 are at different heights. Chip 60 can be or include a sensor. The sensor can be or include a microelectromechanical system (MEMS) sensor, a temperature sensor, a pressure sensor, a humidity sensor, an inertial force sensor, a chemical substance sensor, a magnetic field sensor, or a combination thereof.

[0026] In some arrangements, the surface 603 (or lateral side surface) of the chip 60 is separated from or spaced apart by a gap G1 from the sidewall 205 of the via 20T. In some arrangements, the surface 604 (or lateral side surface) of the chip 60 is separated from or spaced apart by a gap G3 from the sidewall 206 of the via 20T. In some arrangements, the gap G3 can be larger or wider than the first gap G1. In some arrangements, the ratio (G3w / 20t) of the width G3w of the gap G3 to the thickness 20t of the substrate 20 is from about 0.2 to about 0.5, such as about 0.3. In some arrangements, the width G1w of the gap G1 is about 50 μm. In some arrangements, the width G3w of the gap G3 is from about 100 μm to about 500 μm or from about 200 μm to about 300 μm. In some arrangements, the thickness 20t of the substrate 20 is from about 800 μm to about 1200 μm. In some arrangements, the thickness of the chip 60 is greater than the thickness of the substrate 20. In some arrangements, the thickness of the chip 60 is greater than the depth of the via 20T.

[0027] In some arrangements, the chip 60 includes a sensing element 601S adjacent to the surface 601 and a sensing element 602S adjacent to the surface 602. In some arrangements, the sensing element 601S is exposed through the surface 601 of the chip 60, and the sensing element 602S is exposed through the surface 602 of the chip 60. In some arrangements, the sensing elements 601S and 602S are exposed through the substrate 20. In some arrangements, the chip 60 includes a sensing surface 601S1 and a sensing surface 602S1 opposite to the sensing surface 601S1. The sensing element 601S can include the sensing surface 601S1, and the sensing element 602S can include the sensing surface 602S1. In some arrangements, the sensing surface 602S1 of the sensing element 602S is generally aligned with the surface 101 of the substrate 10. The surface 601 and the surface 602 can be referred to as the active surfaces of the chip 60. As used herein, the term "active surface" refers to a surface having one or more pads or terminals that can be connected to one or more external components. For example, the surfaces 601 and 602 having pads 610 and 620 can be the active surfaces of the chip 60. The term "active surface" as used herein also refers to a surface configured to perform an active function such as a sensing function. For example, the surfaces 601 and 602 including the sensing surfaces 601S1 and 602S1 can be the active surfaces of the chip 60. In some arrangements, the surface 602 (or active surface) of the chip 60 is generally aligned with the surface 101 of the substrate 10. In some arrangements, the surface 602 (or bottom surface) of the chip 60 protrudes beyond the surface 202 (or bottom surface) of the substrate 20.

[0028] In some arrangements, the chip 60 includes at least pads 610 and 620 (also referred to as "conductive pads" or "conductive terminals"). In some arrangements, pad 610 is on or adjacent to the surface 601 (or top surface) of chip 60, and pad 620 is on or adjacent to the surface 602 (or bottom surface) of chip 60. In some arrangements, pad 610 projects beyond the surface 601 of chip 60, and pad 620 projects beyond the surface 602 of chip 60. In some arrangements, pad 620 is on the side of chip 60 opposite to pad 610. In some arrangements, pad 610 is electrically connected to the surface 201 of substrate 20, and pad 620 is electrically connected to the surface 202 of substrate 20.

[0029] An adhesive layer 30 may be provided between substrate 10 and substrate 20. In some arrangements, adhesive layer 30 connects substrate 10 and substrate 20. In some arrangements, adhesive layer 30 covers or contacts a portion of one or more lateral side surfaces (e.g., surface 603) of chip 60. In some arrangements, adhesive layer 30 further covers or contacts a portion of the sidewall 205 of via 20T. In some arrangements, adhesive layer 30 further covers or contacts a portion of the sidewall 105 of via 10T. In some arrangements, adhesive layer 30 may be or include an encapsulant or underfill. The encapsulant or underfill may include epoxy resin, molding compound (e.g., epoxy molding compound or other molding compound), polyimide, phenolic compound or material, material containing silicone dispersed therein, or a combination thereof.

[0030] In some arrangements, substrate 10 and substrate 20 together constitute a substrate structure. In some arrangements, the substrate structure defines via T1. In some arrangements, substrate 10 and substrate 20 together define via T1. In some arrangements, via 20T of substrate 20 partially overlaps with via 10T of substrate 10 to define via T1 of the substrate structure.

[0031] In some arrangements, the via T1 of the substrate structure includes a stepped sidewall structure T11 (also referred to as a "stepped structure"). In some arrangements, substrates 10 and 20 jointly define the stepped sidewall structure T11 (or stepped structure). In some arrangements, a portion 101a of the surface 101 of substrate 10 is exposed through the via 20T of substrate 20. In some arrangements, the dielectric layer 120 defines the stepped surface of the stepped sidewall structure T11 (e.g., portion 101a of surface 101). In some arrangements, the stepped sidewall structure T11 includes a first vertical sidewall (e.g., sidewall 205 of via 20T), a second vertical sidewall misaligned with the first vertical sidewall (e.g., sidewall 105 of via 10T), and a horizontal intermediate surface (e.g., portion 101a of surface 101). In some arrangements, the horizontal intermediate surface (e.g., portion 101a of surface 101) is connected to the second vertical sidewall (e.g., sidewall 105), and the first vertical sidewall (e.g., sidewall 205) is spaced apart from the horizontal intermediate surface (e.g., portion 101a of surface 101) by a gap G2. In some arrangements, substrates 10 and 20 are separated by a gap G2. The portion 101a of surface 101 (or the horizontal intermediate surface of the stepped sidewall structure T11) can serve as a support platform for the chip 60 to be disposed thereon. In some arrangements, the ratio (101aw / 20Tw) of the width 101aw of portion 101a to the width 20Tw of via 20T can be equal to or greater than about 0.15, e.g., from about 0.15 to about 0.3 or from about 0.17 to about 0.2. In some arrangements, the width 101aw is from about 300 μm to about 400 μm.

[0032] In some arrangements, the adhesive layer 30 covers a portion of the stepped sidewall structure T11. In some arrangements, the adhesive layer 30 covers a portion of the sidewall 205 (or side face) of the stepped sidewall structure T11. In some arrangements, the adhesive layer 30 connects the chip 60 to the stepped sidewall structure T11. In some arrangements, the adhesive layer 30 contacts the first vertical sidewall (e.g., sidewall 205) and extends into the gap G2. In some arrangements, the adhesive layer 30 at least includes portions 31, 32, and 33. In some arrangements, the portion 31 of the adhesive layer 30 is embedded in the substrate structure. In some arrangements, the portion 31 fills the gap G2 between the substrate 10 and the substrate 20. In some arrangements, the adhesive layer 30 covers a portion of the surface 603 (or side face) of the chip 60. In some arrangements, the portion 31 horizontally overlaps the chip 60. In some arrangements, the portion 32 of the adhesive layer 30 contacts the chip 60. In some arrangements, the portion 32 of the adhesive layer 30 at least partially fills the gap G1 between the sidewall 205 of the via 20T and the surface 603 of the chip 60. In some arrangements, the thickness of the portion 32 may be equal to or less than about half of the depth of the gap G1. In some arrangements, the ratio of the thickness of the portion 32 to the depth of the gap G1 may be equal to or less than about 0.5, e.g., about 0.3 or less. In some arrangements, the portion 33 of the adhesive layer 30 covers or contacts a portion of the sidewall 105 of the via 10T.

[0033] In some arrangements, the chip 60 is disposed in the via T1 and supported by the stepped sidewall structure T11. In some arrangements, the chip 60 is disposed on the stepped sidewall structure T11 in the via T1. In some arrangements, the chip 60 directly contacts the stepped surface (e.g., portion 101a of the surface 101) of the stepped sidewall structure T11. In some arrangements, the chip 60 is at least partially received by the via 20T and supported by the portion 101a of the surface 101 of the substrate 10 (e.g., dielectric layer 120). In some arrangements, the chip 60 is disposed on the portion 101a of the surface 101 of the substrate 10 (e.g., dielectric layer 120). In some arrangements, the chip 60 directly contacts the stepped surface (e.g., portion 101a of the surface 101) of the dielectric layer 120. In some arrangements, the dielectric layer 120 includes a solder mask layer.

[0034] The conductive wire 40 can connect the chip 60 to the substrate 20. In some arrangements, the chip 60 is electrically connected to the substrate 20 through the conductive wire 40. In some arrangements, the conductive wire 40 electrically connects the surface 601 of the chip 60 to the surface 201 of the substrate 20. In some arrangements, the pad 610 of the chip 60 is electrically connected to the surface 201 of the substrate 20 through the conductive wire 40. In some arrangements, the conductive wire 40 electrically connects the pad 610 of the chip 60 to the protective film 260B and the portion 210B of the circuit layer 210 of the substrate 20.

[0035] The conductive wire 42 can connect the chip 60 to the substrate 20. In some arrangements, the chip 60 is electrically connected to the substrate 20 through the conductive wire 42. In some arrangements, the conductive wire 42 electrically connects the surface 602 of the chip 60 to the surface 202 of the substrate 20. In some arrangements, the pad 620 of the chip 60 is electrically connected to the surface 202 of the substrate 20 through the conductive wire 42. In some arrangements, the conductive wire 42 electrically connects the pad 620 of the chip 60 to the protective film 270B and the portion 230B of the circuit layer 230 of the substrate 20. In some arrangements, the conductive wire 42 is received within the via 10T of the substrate 10. In some arrangements, the distance between the substrate 20 and the surface 102 of the substrate 10 is greater than the distance between the substrate 20 and the bottom end (also referred to as the "lower end") 421 of the conductive wire 42. In some arrangements, the curvature of the conductive wire 40 is greater than the curvature of the conductive wire 42. In some arrangements, the change in curvature of the conductive wire 40 is greater than the change in curvature of the conductive wire 42. As used herein, the term "change in curvature" may indicate the change in the height or elevation of the conductive wire within a predetermined horizontal distance. The term "change in curvature" may also reflect the slope of the conductive wire.

[0036] The spacer structure 50 can be disposed around the conductive wire 40. In some arrangements, the height of the top surface 501 of the spacer structure 50 is higher than the height of the top end (also referred to as the "upper end") 401 of the conductive wire 40 relative to the surface 201 of the substrate 20. In some arrangements, the spacer structure 50 is disposed on the surface 201 of the substrate 20 and is configured to protect the chip 60 from damage. In some arrangements, the spacer structure 50 is disposed on the surface 201 of the substrate 20 and defines a space S1 for accommodating the conductive wire 40 and the portion of the chip 60 that protrudes beyond the surface 201 of the substrate 20. In some arrangements, the spacer structure 50 is connected to (or electrically connected to) ground through the conductive via 250. The spacer structure 50 can be referred to as a protective element. The protective element can be disposed on the surface 201 of the substrate 20 and surround the chip 60. The protective element on the surface 202 of the substrate is configured to prevent the chip 60 from being impacted outside the protective element. The spacer structure 50 can act as a shielding element configured to reduce electromagnetic interference (EMI). In some arrangements, the spacer structure 50 can be referred to as or include a spacer, a metal spacer, an interposer, etc. The spacer structure 50 can be or include a metal frame or a metal wall structure. In some embodiments, the spacer structure 50 is made of or includes a conductive material, including, for example, aluminum (Al), copper (Cu), chromium (Cr), tin (Sn), gold (Au), silver (Ag), nickel (Ni), or stainless steel, or a mixture, alloy, or other combination thereof.

[0037] The bonding element 51 can connect the spacer structure 50 to the substrate 20. In some arrangements, the bonding element 51 is at least partially within the opening 220T of the dielectric layer 220. In some arrangements, the bonding element 51 is formed of or includes a conductive material. The bonding element 51 can be or include a conductive adhesive, such as silver paste or silver gel. The bonding element 51 can be or include a soldering material. In some arrangements, the bonding element 51 electrically connects the spacer structure 50 to a portion 210A of the circuit layer 210.

[0038] The connecting element 90 can be between the substrate 10 and the substrate 20. In some arrangements, the connecting element 90 electrically connects the circuit layer 110 of the substrate 10 to the circuit layer 230 of the substrate 20. In some arrangements, a portion 31 of the bonding layer 30 encapsulates the connecting element 90. In some arrangements, the conductive wire 42 horizontally overlaps the connecting element 90. In some arrangements, the connecting element 90 can be or include a conductive bump. The conductive bump can be or include gold (Au), silver (Ag), copper (Cu), another metal, a solder alloy, or a combination of two or more of them.

[0039] The conductive layer, pad, post, portion, via, liner, and / or terminal can each include a conductive material such as a metal or metal alloy. Examples include Au, Ag, Al, Cu, or their alloys. The dielectric layer can each include an organic material, a solder mask, PI, ABF, one or more molding compounds, one or more prepreg composite fibers (e.g., prepreg material), borophosphosilicate glass (BPSG), silicon oxide, silicon nitride, silicon oxynitride, undoped silicate glass (USG), any combination thereof, etc.

[0040] Figure 1B is a cross-section of the encapsulation structure 1B according to some arrangements of the present disclosure. Figure 1B The encapsulation structure 1B illustrated in Figure 1A is similar to the encapsulation structure in

[0041] In some arrangements, the bonding layer 30 does not cover or contact the sidewall 105 of the via 10T of the substrate 10. In some arrangements, the bonding layer 30 does not include a portion that covers or contacts a portion of the sidewall 105 of the via 10T.

[0042] Figure 1C is a cross-section of the encapsulation structure 1C according to some arrangements of the present disclosure. Figure 1C The encapsulation structure 1C illustrated in Figure 1A is similar to the encapsulation structure in

[0043] In some arrangements, the spacer structure 50 is bonded to the dielectric layer 220 of the substrate 20 by a bonding element 51. In some arrangements, the bonding element 51 is or includes an insulating bonding material. In some arrangements, the spacer structure 50 may include a dielectric material, a conductive material, or any suitable spacer material. In some arrangements, the spacer structure 50 is not electrically connected to ground or any conductive structure.

[0044] Figure 1D is a top view of a package structure 1D according to some arrangements of the present disclosure. In some arrangements, Figure 1D shows Figure 1A the package structure 1A described in Figure 1B the package structure 1B described in Figure 1C or the package structure 1C described in Figure 1A , Figure 1B or Figure 1C shows a cross-section along line 1A-1A' in Figure 1D .

[0045] The chip 60 may have surfaces 603, 604, 605, and 606 (also referred to as "lateral side surfaces"). In some arrangements, surfaces 605 and 606 are adjacent to surface 603, and surface 604 is opposite surface 603. In some arrangements, the bonding layer 30 covers at least a portion of surface 603 of the chip 60 and a portion of surface 605 of the chip 60. In some arrangements, the bonding layer 30 covers at least a portion of surface 603 of the chip 60 and a portion of surface 606 of the chip 60. In some arrangements, the bonding layer 30 covers at least a portion of surface 603 of the chip 60, a portion of surface 605 of the chip 60, and a portion of surface 606 of the chip 60. In some arrangements, the bonding layer 30 is spaced apart from surface 604 of the chip 60.

[0046] In some arrangements, portions 321, 322, and 323 of the bonding layer 30 are included in portion 32. Portions 321, 322, and 323 may be referred to as sub-portions or portions of portion 32 of the bonding layer 30. In some arrangements, portion 321 contacts surface 603 (or a lateral side surface) of the chip 60, portion 322 contacts surface 605 (or a lateral side surface) of the chip 60, and portion 323 contacts surface 606 (or a lateral side surface) of the chip 60.

[0047] In some arrangements, at least two or more of portions 321, 322, and 323 of the bonding layer 30 have different widths. For example, the width W1 of portion 321 may be less than the width W2 of portion 322. For example, the width W3 of portion 323 may be less than the width W2 of portion 322. For example, the width W1 of portion 321 may be different from the width W3 of portion 323.

[0048] In some arrangements, at least two or more of the portions 321, 322, and 323 of the adhesive layer 30 have different lengths. For example, the length L1 of portion 321 may be less than the length L2 of portion 322. For example, the length L3 of portion 323 may be less than the length L2 of portion 322. For example, the length L1 of portion 321 may be less than the length L3 of portion 323.

[0049] In some arrangements, a portion 210A of the circuit layer 210 surrounds the chip 60, the adhesive layer 30, and the via T1. In some arrangements, an opening 220T of the dielectric layer 220 surrounds the chip 60, the adhesive layer 30, and the via T1. In some arrangements, the portion 210A is partially exposed through the opening 220T. In some arrangements, the spacer structure 50 surrounds the chip 60, the adhesive layer 30, and the via T1. In some arrangements, the adhesive element 51 surrounds the chip 60, the adhesive layer 30, and the via T1.

[0050] Figure 1E is a top view of the package structure 1E according to some arrangements of the present disclosure. In some arrangements, Figure 1E shows Figure 1A the package structure 1A described in Figure 1B the package structure 1B described in Figure 1C or Figure 1A 、 Figure 1B or Figure 1C shows a cross-section along the line 1A-1A' in Figure 1E . Figure 1E The package structure 1E described in Figure 1D is similar to the package structure in

[0051] In some arrangements, a portion 210A of the circuit layer 210 surrounds the chip 60, the adhesive layer 30, and the via T1. In some arrangements, the dielectric layer 220 has a plurality of openings 220T respectively adjacent to the surfaces 603, 604, 605, and 606 of the chip 60. In some arrangements, the portion 210A includes a plurality of segments that are respectively partially exposed through the plurality of openings 220T. In some arrangements, the spacer structure 50 includes a plurality of segments disposed on the respective exposed segments of the portion 210A. In some arrangements, the adhesive element 51 includes a plurality of segments that connect the segments of the spacer structure 50 to the respective exposed segments of the portion 210A.

[0052] Figure 1F is a top view of the package structure 1F according to some arrangements of the present disclosure. In some arrangements, Figure 1F shows Figure 1A the package structure 1A described inFigure 1B the encapsulation structure 1B described in Figure 1C or a top view of the encapsulation structure 1C described in Figure 1A , Figure 1B or Figure 1C shows a cross-section along the line 1A-1A' in Figure 1F . Figure 1F The encapsulation structure 1F described in Figure 1E is similar to the encapsulation structure in

[0053] In some arrangements, in a top perspective view, the central axis C1 of the substrate structure (e.g., substrates 10 and 20) is not parallel to the central axis C2 of the chip 60.

[0054] In some arrangements, in a top perspective view, the adhesive layer 30 is located between the sidewalls of the substrate structure (e.g., substrates 10 and 20) and the surfaces 603, 605, and 606 (also referred to as side surfaces) of the chip 60. In some arrangements, in a top perspective view, the adhesive layer 30 includes a portion 322 adjacent to the surface 605 and a portion 323 adjacent to the surface 606, and the portions 322 and 323 have different lengths (e.g., lengths L2 and L3). In some arrangements, in a top perspective view, the portion 322 of the adhesive layer 30 has a non-uniform width W2.

[0055] In some arrangements, the conductive wire 40 connects the chip 60 to the substrate structure (e.g., substrates 10 and 20), and in a top perspective view, the extending direction of the conductive wire 40 is not parallel to the central axis C1 of the substrate structure.

[0056] Figure 1G is a perspective view of the encapsulation structure 1G according to some arrangements of the present disclosure. In some arrangements, Figure 1G shows Figure 1A the encapsulation structure 1A described in Figure 1B the encapsulation structure 1B described in Figure 1C or a perspective view of the encapsulation structure 1C described in Figure 1G . Note that some elements are omitted in

[0057] The portion 101a of the surface 101 exposed by the perforation 20T can serve as a support platform for the chip 60 to be disposed thereon. In some arrangements, when viewed from a top perspective, the portion 101a has a U-shaped profile. In some arrangements, the portion 31 of the adhesive layer 30 surrounds the chip 60. In some arrangements, the portion 32 of the adhesive layer 30 has a non-uniform thickness.

[0058] In some arrangements, the height of the top surface of the portion 32 of the adhesive layer 30 is between the top surface of the substrate structure (e.g., the surface 201) and the bottom surface of the substrate structure (e.g., the surface 102). In some arrangements, the height of the top surface of the chip 60 (e.g., the surface 601) is lower than the height of the top surface of the portion 32 of the adhesive layer 30 relative to the bottom surface of the substrate structure (e.g., the surface 102).

[0059] In some arrangements, the height of the top surface 321a of the portion 321, the height of the top surface 322a of the portion 322, and the height of the top surface 323a of the portion 323 can be between the top surface of the substrate structure (e.g., the surface 201) and the bottom surface of the substrate structure (e.g., the surface 102). In some arrangements, the height of the top surface of the chip 60 (e.g., the surface 601) is lower than the height of the top surface 321a of the portion 321, the height of the top surface 322a of the portion 322, and the height of the top surface 323a of the portion 323 relative to the bottom surface of the substrate structure (e.g., the surface 102). In some arrangements, the top surfaces 321a, 322a, and 323a are non-planar surfaces.

[0060] In some arrangements, two or more of the portions 321, 322, and 323 of the adhesive layer 30 have different thicknesses. In some arrangements, the thickness 321t of the portion 321 can be substantially equal to or greater than the thickness 322t of the portion 322. In some arrangements, the thickness 321t of the portion 321 can be substantially equal to or greater than the thickness 323t of the portion 323. In some arrangements, the thickness 322t of the portion 322 decreases in a direction away from the portion 321. In some arrangements, the thickness 323t of the portion 323 decreases in a direction away from the portion 321.

[0061] In some cases, a ceramic substrate is manufactured to provide a specific structure for a chip to be disposed therein such that I / O terminals on opposite sides of the chip can be exposed through the ceramic substrate for electrical connection. However, the cost and difficulty of manufacturing a ceramic substrate with a specific structure may be relatively high, and the brittle texture of the ceramic substrate may make the ceramic substrate relatively fragile, thus reducing the yield. To solve the above problems, a plastic substrate including a specific structure for a chip to be disposed therein can be provided. The plastic substrate can be formed by the following steps: a top cavity and a bottom cavity can be formed from the top surface and the bottom surface of the plastic substrate respectively to connect the top cavity and the bottom cavity, thereby forming a through hole and a platform defined by the cavities in the plastic substrate such that the chip can be disposed on the platform in the through hole of the plastic substrate. However, during the two-step cavity formation process, it is relatively difficult to precisely control the depths of the top cavity and the bottom cavity, and thus variations in the cavity depths may cause the platform so formed to have a non-uniform height or surface profile, which may also reduce the yield.

[0062] According to some arrangements of the present disclosure, two substrates each having a through hole are stacked on each other to form a combined through hole, wherein an exposed portion of the top surface of the lower substrate serves as a platform to support the chip. The process for forming the through holes in the substrates is relatively easy and simplified (e.g., by a single-step drilling operation), the problem of difficultly controlling the depths of multiple cavities can be eliminated, thus the yield can be increased, and the cost can be reduced. In addition, the platform formed by the exposed portion of the top surface of the lower substrate can have a relatively uniform height or a relatively flat surface profile, and thus the chip can be prevented from tilting, and thus the alignment accuracy of connecting conductive wires to the bonding regions (e.g., pads) of the chip can be improved, thereby the position offset error can be reduced, and the yield can be further increased. Additionally, both sides or surfaces of the chip can be exposed through the opposite openings of the combined through hole such that both sides or surfaces of the chip can be electrically connected to conductive elements (e.g., conductive wires).

[0063] In addition, according to some arrangements of the present disclosure, an adhesive layer encapsulates the connecting elements between the substrates and covers a part of the lateral side surfaces of the chip. Thus, the connecting elements that can electrically connect the substrates and are configured to transmit signals between the substrates can be protected by the adhesive layer, and the adhesion between the chip and the side walls of the through holes can be improved. Therefore, the reliability of the packaging structure can be improved, and the yield can also be increased.

[0064] In addition, according to some arrangements of the present disclosure, a spacer structure is higher than the chip and the conductive wires above the top surface of the substrate such that the spacer structure can protect the chip and the conductive wires from damage. Additionally, the spacer structure can be further electrically connected to ground such that the spacer structure can further serve as an EMI shielding element for the chip without setting or installing an additional EMI shielding structure. Therefore, the electrical performance of the packaging structure can be improved without increasing the packaging size.

[0065] In addition, according to some arrangements of the present disclosure, the conductive wire is received in a through-hole of one of the substrates, thereby protecting the conductive wire from damage without encapsulating the conductive wire with a protective element.

[0066] In addition, according to some arrangements of the present disclosure, the gap between the chip and the sidewall of the through-hole is relatively small (for example, the ratio of the width G3w of the gap G3 to the thickness 20t of the substrate 20 (G3w / 20t) is about 0.2 to about 0.5, for example, about 0.3). Thus, the gap with a specific size design is large enough to provide a tolerance space for setting the chip into the through-hole without accidentally hitting or rubbing the sidewall of the through-hole, and the gap is also small enough to prevent impurities or particles from falling into the through-hole. Therefore, the chip can be prevented from being damaged, and impurities or particles can also be avoided.

[0067] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G , Figure 2H and Figure 2I Various stages of an exemplary method for manufacturing a package structure 1A according to some embodiments of the present disclosure are described.

[0068] refer to Figure 2A , a substrate 10 including a base layer 100, circuit layers 110 and 130, dielectric layers 120 and 140, and one or more conductive vias 150 may be provided, and a substrate 20 including a base layer 200, circuit layers 210 and 230, dielectric layers 220 and 240, and one or more conductive vias 250 may be provided.

[0069] refer to Figure 2B and Figure 2C , Figure 2B Instructions along the Figure 2C The through-hole 10T may be formed to penetrate the base layer 100 and the dielectric layers 120 and 140, and the through-hole 20T may be formed to penetrate the base layer 200 and the dielectric layers 220 and 240. The through-holes 10T and 20T may be formed by laser drilling, mechanical drilling, or any suitable technique.

[0070] refer to Figure 2D , the connection element 90 may be formed on the surface 202 (or bottom surface) of the substrate 20. The connection element 90 may be or include a conductive bump.

[0071] refer to Figure 2E, the substrate 20 can be connected or joined to the substrate 10 through the connecting element 90. In some arrangements, the substrate 20 is guided towards the substrate 10 until the connecting element 90 contacts the substrate 10, and then a heat treatment (e.g., a reflow operation) can be performed on the connecting element 90 to connect or join the substrate 20 to the substrate 10 through the connecting element 90. The substrates 10 and 20 jointly construct a substrate structure including a through hole T1 formed by the through holes 10T and 20T. The through hole T1 includes a stepped sidewall structure T11 having a stepped surface (e.g., a portion 101a of the surface 101 of the substrate 10 exposed by the through hole 20T).

[0072] Reference Figure 2F , the chip 60 including the pads 610 and 620 can be disposed in the through hole T1 supported by the stepped sidewall structure T11, and the spacer structure 50 can be adhered or attached to the substrate 20. In some arrangements, the surface 602 of the chip 60 can contact a portion 101a of the top surface (e.g., the surface 101) of the substrate 10. In some arrangements, the surface 101 of the substrate 10 can be substantially aligned with the surface 602 of the chip 60. In some arrangements, the chip 60 can be separated from the sidewall of the through hole 20T by a gap G1. In some arrangements, the spacer structure 50 is adhered to a portion 210A of the circuit layer 210 by an adhesive element 51 exposed by an opening 220T of the dielectric layer 220.

[0073] Reference Figure 2G , Figure 2F The structure illustrated in

[0074] Reference Figure 2H , a conductive wire 42 can be provided or formed above the surface 102 of the substrate 10 to connect the circuit layer 130 to the pad 620 of the chip 60. In some arrangements, the conductive wire 42 is completely received within the through hole 10T of the substrate 10.

[0075] Reference Figure 2I , Figure 2HThe structure described in Figure 1A can be flipped such that the substrate 10 can serve as a support carrier for the structure to undergo subsequent operations, and the conductive wire 42 can be received within the through-hole 10T and protected by the substrate 10. Next, the conductive wire 40 can be provided or formed above the surface 201 of the substrate 20 to connect the circuit layer 210 to the pad 610 of the chip 60, and an adhesive material can be provided to encapsulate the connecting element 90 between the substrate 10 and the substrate 20. In some arrangements, the adhesive material can flow into the gap G2 between the sidewall (e.g., sidewall 205) of the through-hole 20T and the chip 60. In some arrangements, the adhesive material can further flow downward to cover a portion of the sidewall 105 of the through-hole 10T. Next, a curing operation can be performed to cure the adhesive material to form the adhesive layer 30. Thus, the

[0076] Figure 3A and Figure 3B illustrate the various stages of an exemplary method for manufacturing the encapsulation structure 1B according to some embodiments of the present disclosure.

[0077] Referring to Figure 3A , operations similar to those described in Figures 2A to 2H can be performed to form a structure similar to that described in Figure 2H . After the conductive wire 42 is provided or formed on the surface 102 of the substrate 10 to connect the circuit layer 130 to the pad 620 of the chip 60, as described in Figure 3A , an adhesive material can be provided to encapsulate the connecting element 90 between the substrate 10 and the substrate 20. In some arrangements, the adhesive material can flow downward into the gap G2 between the sidewall (e.g., sidewall 205) of the through-hole 20T and the chip 60. Next, a curing operation can be performed to cure the adhesive material to form the adhesive layer 30. Since the curing operation is performed while the substrate 10 is stacked above the adhesive material, the adhesive material does not flow to cover a portion of the sidewall 105 of the through-hole 10T.

[0078] Referring to Figure 3B , Figure 3A the structure described in Figure 1B can be flipped, and the conductive wire 40 can be provided or formed above the surface 201 of the substrate 20 to connect the circuit layer 210 to the pad 610 of the chip 60. Thus, the

[0079] Unless otherwise specified, spatial descriptions such as "above", "below", "upper", "left", "right", "lower", "top", "bottom", "vertical", "horizontal", "side", "higher than", "lower than", "upper part", "upper surface", "lower surface", etc. are indicated relative to the orientation shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and embodiments of the structures described herein can be spatially arranged in any orientation or manner, provided that the advantages of the embodiments of the present disclosure are not deviated due to such arrangements.

[0080] As used herein, the terms "approximately", "substantially", "substantially", "about", and "around" are used to describe and account for minor variations. When used in connection with an event or circumstance, these terms can refer to instances where the event or circumstance occurs precisely as well as instances where the event or circumstance occurs very nearly. For example, when used in connection with a numerical value, these terms can refer to a range of variation of less than or equal to ±10% of the stated numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if a first numerical value is within a range of variation of less than or equal to ±10% of a second numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the first numerical value can be considered to be "substantially" the same as or equal to the second numerical value. For example, "substantially" perpendicular can refer to an angular range of variation of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1%, or less than or equal to ±0.05°.

[0081] If the displacement amount between two surfaces is not greater than 5 μm, not greater than 2 μm, not greater than 1 μm, or not greater than 0.5 μm, then the two surfaces can be considered to be coplanar or substantially coplanar. If the displacement amount between the highest point and the lowest point of a surface does not exceed 5 μm, does not exceed 2 μm, does not exceed 1 μm, or does not exceed 0.5 μm, then the surface can be considered to be substantially flat.

[0082] As used herein, unless the context clearly indicates otherwise, the singular forms "a / an" and "the" can include plural referents.

[0083] As used herein, the terms "conductive", "electrically conductive", and "conductivity" refer to the ability to conduct an electric current. A conductive material is a material that presents little or no resistance to the flow of an electric current. One unit of measure for conductivity is siemens per meter (S / m). Generally, a conductive material is a material having a conductivity greater than about 104 S / m, such as at least 105 S / m or at least 106 S / m. The conductivity of a material sometimes varies with temperature. Unless otherwise specified, the conductivity of a material is measured at room temperature.

[0084] In addition, quantities, ratios, and other numerical values are sometimes presented herein in a range format. It should be understood that such range formats are used for convenience and brevity and should be interpreted flexibly as encompassing not only the explicitly recited values as the limits of the range, but also all individual values or sub-ranges subsumed within that range as if each individual value and sub-range were explicitly recited.

[0085] Although the present disclosure has been described and illustrated with reference to specific embodiments thereof, such description and illustration are not restrictive. Those skilled in the art will understand that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The drawings may not necessarily be drawn to scale. There may be differences between the process reproductions and the actual devices in the present disclosure due to manufacturing processes and tolerances. There may be other embodiments not specifically described herein. The specification and drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objectives, spirit, and scope of the present disclosure. All such modifications are considered to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or re-ordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations of the present disclosure.

Claims

1. An encapsulation structure, comprising: A lower substrate that defines a lower via; An upper substrate that is located above the lower substrate and defines an upper via connected to the lower via, wherein a part of the top surface of the lower substrate is exposed through the upper via; And A chip that is at least partially received by the upper via and supported by the part of the top surface of the lower substrate.

2. The encapsulation structure according to claim 1, wherein the upper substrate includes a first pad located on the bottom surface of the upper substrate, and the first pad is exposed through the lower via.

3. The encapsulation structure according to claim 2, wherein the upper substrate further includes a second pad located on the top surface of the upper substrate, the chip includes an upper pad and a lower pad located at a side of the chip opposite to the upper pad, and the encapsulation structure further includes a first wire connecting the upper pad to the second pad and a second wire connecting the lower pad to the first pad.

4. The encapsulation structure according to claim 3, wherein the distance between the bottom surface of the upper substrate and the bottom surface of the lower substrate is greater than the distance between the bottom surface of the upper substrate and the bottom point of the second wire.

5. The encapsulation structure according to claim 3, wherein the curvature change of the first wire is greater than the curvature change of the second wire.

6. The encapsulation structure according to claim 1, wherein the height of the bottom surface of the chip is lower than the bottom surface of the upper substrate relative to the top surface of the lower substrate.

7. The encapsulation structure according to claim 1, further comprising a protection element that is located on the top surface of the upper substrate and is configured to prevent the chip from being impacted from outside the protection element.

8. The encapsulation structure according to claim 7, further comprising a wire that electrically connects the chip to the upper substrate, wherein the top end of the protection element is higher than the vertex of the wire relative to the top surface of the upper substrate.

9. An encapsulation structure, comprising: A substrate structure that defines a via including a stepped sidewall structure; And A chip that is disposed in the via and supported by the stepped sidewall structure, wherein in a top-down perspective view, the central axis of the substrate structure is not parallel to the central axis of the chip.

10. The encapsulation structure according to claim 9, wherein in the top-down perspective view, the chip has a first side surface, a second side surface adjacent to the first side surface, and a third side surface adjacent to the first side surface, and the encapsulation structure further includes an adhesive layer located between the sidewall of the substrate structure and the first side surface, the second side surface, and the third side surface of the chip.

11. The encapsulation structure according to claim 10, wherein in the top-down perspective view, the adhesive layer includes a first part adjacent to the second side surface and a second part adjacent to the third side surface, and the first part and the second part have different lengths.

12. The encapsulation structure according to claim 11, wherein in the top-down perspective view, the first part of the adhesive layer has a non-uniform width.

13. The encapsulation structure according to claim 11, further comprising a conductive wire connecting the chip to the substrate structure, wherein in the top perspective view, the extending direction of the conductive wire is not parallel to the central axis of the substrate structure.

14. An encapsulation structure, comprising: a first substrate defining a first through hole; a second substrate located above the first substrate and physically spaced apart from the first substrate, wherein the second substrate defines a second through hole, and in a cross-sectional perspective view, the central axis of the first through hole is not aligned with the central axis of the second through hole; and a chip disposed in the second through hole.

15. The encapsulation structure according to claim 14, wherein the first substrate and the second substrate jointly define a stepped structure.

16. The encapsulation structure according to claim 15, further comprising an adhesive layer between the first substrate and the second substrate.

17. The encapsulation structure according to claim 16, wherein the adhesive layer covers a part of the side surface of the chip.

18. The encapsulation structure according to claim 16, wherein the adhesive layer covers a part of the side surface of the stepped structure.

19. The encapsulation structure according to claim 15, further comprising a conductive via structure electrically connecting the first substrate to the second substrate.

20. The encapsulation structure according to claim 19, wherein the thickness of the second substrate is greater than the thickness of the first substrate.

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