Semiconductor device

Abstract

To provide a semiconductor device having a transistor part and a diode part, in which a reverse recovery loss is reduced.SOLUTION: A semiconductor device includes: an interlayer insulating film 38 provided over a semiconductor substrate 10; an emitter electrode 52 being a front surface electrode provided over the semiconductor substrate; contact parts where the front surface electrode and mesa parts 61 to 64 are connected in contact holes 54 of the interlayer insulating film; and a lifetime adjustment region 206 provided on a front surface side of the semiconductor substrate. The contact parts have a first contact part 77 provided in a transistor part, and a second contact part 87 provided in a diode part. The first contact part is disposed over the second contact part.SELECTED DRAWING: Figure 3A

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] In a semiconductor device having a transistor portion and a diode portion, a structure in which an electrode and a semiconductor substrate are connected by a trench-like contact is known (see, for example, Patent Documents 1 and 2). Patent Document 1 WO2018 / 056233 Patent Document 2 Japanese Patent Application Laid-Open No. 2021-150483

Summary of the Invention

Problems to be Solved by the Invention

[0003] In a semiconductor device having a transistor portion and a diode portion, it is preferable to reduce reverse recovery loss.

Means for Solving the Problems

[0004] In a first aspect of the present invention, a semiconductor device includes a transistor section, a diode section, a plurality of trench sections provided on a front surface of a semiconductor substrate, a drift region of a first conductivity type provided in the semiconductor substrate, in the transistor section, a base region of a second conductivity type provided above the drift region, in the transistor section, an emitter region of the first conductivity type provided on the front surface of the semiconductor substrate and having a higher doping concentration than the drift region, a contact region of the second conductivity type having a higher doping concentration than the base region, in the diode section, an anode region of the second conductivity type provided above the drift region, a mesa section of the semiconductor substrate provided between the plurality of trench sections, an interlayer insulating film provided above the semiconductor substrate, a front surface electrode provided above the semiconductor substrate, in a contact hole of the interlayer insulating film, a contact section where the front surface electrode and the mesa section are connected, and a lifetime adjustment region provided on a front surface side of the semiconductor substrate. The contact section has a first contact section provided in the transistor section and a second contact section provided in the diode section, and the first contact section is disposed above the second contact section.

[0005] The semiconductor device may include a second plug region of the second conductivity type provided below the second contact section and having a higher doping concentration than the contact region.

[0006] The second plug region may be provided to extend in a trench extension direction.

[0007] The second plug region may be provided discretely in a trench extension direction.

[0008] The semiconductor device may include a first plug region of the second conductivity type provided below the first contact section and having a higher doping concentration than the contact region.

[0009] The first plug region may be provided discretely in a trench extension direction.

[0010] The first plug region is provided above the contact region and may not be provided above the emitter region.

[0011] The semiconductor device includes a barrier metal portion provided on a side surface of the contact hole, and the barrier metal portion may have a Ti layer.

[0012] In the transistor portion, the semiconductor device may include an accumulation region of a first conductivity type provided above the drift region and having a doping concentration higher than that of the drift region.

[0013] The front surface electrode may include an emitter electrode provided above the interlayer insulating film.

[0014] The front surface electrode may be provided in the contact hole and include a contact plug portion that connects the emitter electrode and the mesa portion.

[0015] The diode portion may have the lifetime adjustment region.

[0016] The transistor portion may have the lifetime adjustment region.

[0017] The lifetime adjustment region of the transistor portion may be formed by irradiation with a particle beam.

[0018] The lifetime adjustment region may be provided to extend over the entire transistor portion and the diode portion in the trench arrangement direction.

[0019] The lifetime adjustment region may be provided to extend from the diode portion to a part of the transistor portion in the trench arrangement direction.

[0020] The doping concentration of the anode region may be lower than the doping concentration of the base region.

[0021] The doping concentration of the anode region may be the same as that of the base region.

[0022] The first contact portion may be in contact with the front surface of the mesa portion.

[0023] The first contact portion may be disposed below the front surface of the mesa portion.

[0024] The semiconductor device may include a boundary region provided between the transistor portion and the diode portion.

[0025] The lifetime adjustment region may extend up to the boundary region in the trench array direction, with respect to the diode portion from

[0026] The width of the boundary region in the trench array direction may be 20 μm or more and 250 μm or less.

[0027] The contact portion of the boundary region is a third contact portion, and the third contact portion may be disposed above the second contact portion and below the first contact portion.

[0028] The contact portion of the boundary region may be the second contact portion.

[0029] Note that the above summary of the invention does not list all the features of the present invention. Also, sub - combinations of these feature groups can also be inventions.

Brief Description of the Drawings

[0030]

Figure 1

Figure 2

Figure 3A

Figure 3B

Figure 4A

Figure 4B

Figure 4C

Figure 4D

Figure 5A

Figure 5B

Figure 6

Figure 7A

Figure 7B

Figure 8

Figure 9A

Figure 9B

Figure 9C

Embodiments for Carrying Out the Invention

[0031] Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention claimed in the claims. Also, not all combinations of features described in the embodiments are essential for the solution of the invention.

[0032] In this specification, one side in the direction parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". Of the two main surfaces of the substrate, layer, or other member, one surface is referred to as the front surface, and the other surface is referred to as the back surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction at the time of mounting the semiconductor device.

[0033] In this specification, technical matters may be described using orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes only specify the relative positions of the components and do not limit a specific direction. For example, the Z-axis does not limit and indicate the height direction with respect to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When described as the Z-axis direction without specifying positive or negative, it means directions parallel to the +Z-axis and -Z-axis.

[0034] In this specification, orthogonal axes parallel to the front surface and the back surface of the semiconductor substrate are defined as the X-axis and Y-axis. Also, an axis perpendicular to the front surface and the back surface of the semiconductor substrate is defined as the Z-axis. In this specification, the direction of the Z-axis may sometimes be referred to as the depth direction. Also, in this specification, directions parallel to the front surface and the back surface of the semiconductor substrate, including the X-axis and Y-axis, may sometimes be referred to as the horizontal direction.

[0035] The region from the center in the depth direction of the semiconductor substrate to the front surface of the semiconductor substrate may sometimes be referred to as the front surface side. Similarly, the region from the center in the depth direction of the semiconductor substrate to the back surface of the semiconductor substrate may sometimes be referred to as the back surface side.

[0036] When referred to as "identical" or "equal" in this specification, it may include cases having errors due to manufacturing variations or the like. The error is, for example, within 10%.

[0037] In this specification, the conductivity type of the doped region doped with impurities is described as P-type or N-type. In this specification, impurities may particularly mean either an N-type donor or a P-type acceptor, and may be referred to as dopants. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to obtain a semiconductor showing an N-type conductivity type or a semiconductor showing a P-type conductivity type.

[0038] In this specification, the doping concentration means the concentration of donors or acceptors in the thermal equilibrium state. In this specification, the net doping concentration means the net concentration obtained by adding the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, including the polarity of the charges. As an example, when the donor concentration is N D and the acceptor concentration is N A , the net net doping concentration at any position is N D - N A . In this specification, the net doping concentration may sometimes be simply referred to as the doping concentration.

[0039] Donors have the function of supplying electrons to a semiconductor. Acceptors have the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to the impurities themselves. For example, VOH defects in which vacancies (V), oxygen (O), and hydrogen (H) existing in a semiconductor are combined function as donors that supply electrons. A hydrogen donor may be at least a donor in which a vacancy (V) and hydrogen (H) are combined. Alternatively, interstitial Si-H in which interstitial silicon (Si-i) and hydrogen in a silicon semiconductor are combined also functions as a donor that supplies electrons. In this specification, VOH defects or interstitial Si-H may sometimes be referred to as hydrogen donors.

[0040] In this specification, in the semiconductor substrate, N-type bulk donors are distributed throughout. The bulk donors are donors by dopants that were contained substantially uniformly in the ingot when the ingot that is the source of the semiconductor substrate was manufactured. The bulk donors in this example are elements other than hydrogen. The dopants of the bulk donors are, for example, phosphorus, antimony, arsenic, selenium, or sulfur, but are not limited thereto. The bulk donor in this example is phosphorus. The bulk donors are also contained in the P-type regions. The semiconductor substrate may be a wafer cut out from a semiconductor ingot, or may be a chip obtained by singulating the wafer. The semiconductor ingot may be manufactured by any one of the Czochralski method (CZ method), the magnetic field applied Czochralski method (MCZ method), and the float zone method (FZ method). The ingot in this example is manufactured by the MCZ method. The oxygen concentration contained in the substrate manufactured by the MCZ method is 1×10 17 ~7×10 17 / cm 3 . The oxygen concentration contained in the substrate manufactured by the FZ method is 1×10 15 ~5×10 16 / cm 3 . A higher oxygen concentration tends to be more likely to generate hydrogen donors. The bulk donor concentration may use the chemical concentration of the bulk donors distributed throughout the semiconductor substrate, and may be a value between 90% and 100% of the chemical concentration. Also, a non-doped substrate that does not contain dopants such as phosphorus may be used as the semiconductor substrate. In that case, the bulk donor concentration (D0) of the non-doping substrate is, for example, 1×10 10 / cm 3 or more and 5×10 12 / cm 3 or less. The bulk donor concentration (D0) of the non-doping substrate is preferably 1×10 11 / cm 3 or more. The bulk donor concentration (D0) of the non-doping substrate is preferably 5×10 12 / cm 3 or less. Incidentally, each concentration in the present invention may be a value at room temperature. As an example, the value at room temperature may use the value at 300 K (Kelvin) (about 26.9 °C).

[0041] When described as P+ type or N+ type in this specification, it means that the doping concentration is higher than that of P type or N type. When described as P- type or N- type, it means that the doping concentration is lower than that of P type or N type. Also, when described as P++ type or N++ type in this specification, it means that the doping concentration is higher than that of P+ type or N+ type. The unit system in this specification is the SI unit system unless otherwise specified. Although the unit of length may be expressed in cm, various calculations may be performed after converting to meters (m).

[0042] In this specification, the chemical concentration refers to the atomic density of impurities measured regardless of the electrical activation state. The chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration described above can be measured by the voltage-capacitance measurement method (CV method). Also, the carrier concentration measured by the spreading resistance measurement method (SR method) may be used as the net doping concentration. The carrier concentration measured by the CV method or the SR method may be taken as the value in the thermal equilibrium state. Also, in the N-type region, since the donor concentration is sufficiently larger than the acceptor concentration, the carrier concentration in the region may be taken as the donor concentration. Similarly, in the P-type region, the carrier concentration in the region may be taken as the acceptor concentration. In this specification, the doping concentration in the N-type region may sometimes be referred to as the donor concentration, and the doping concentration in the P-type region may sometimes be referred to as the acceptor concentration.

[0043] When the concentration distribution of donors, acceptors or net doping has a peak, the peak value may be taken as the concentration of donors, acceptors or net doping in the region. In cases where the concentration of donors, acceptors or net doping is substantially uniform, etc., the average value of the concentration of donors, acceptors or net doping in the region may be taken as the concentration of donors, acceptors or net doping. In this specification, for the concentration per unit volume, the notation is atoms / cm 3 , or, / cm 3It is used. This unit is used for the donor or acceptor concentration, or the chemical concentration, within the semiconductor substrate. The "atoms" notation may be omitted.

[0044] The carrier concentration measured by the SR method may be lower than the concentration of donors or acceptors. In the range where current flows when measuring the spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. The decrease in carrier mobility is caused by the scattering of carriers due to the disorder of the crystal structure (disorder) such as lattice defects.

[0045] The concentration of donors or acceptors calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element indicating the donor or acceptor. As an example, in a silicon semiconductor, the donor concentration of phosphorus or arsenic serving as a donor, or the acceptor concentration of boron (boron) serving as an acceptor, is about 99% of these chemical concentrations. On the other hand, the donor concentration of hydrogen serving as a donor in a silicon semiconductor is about 0.1% to 10% of the chemical concentration of hydrogen.

[0046] FIG. 1 is a plan view showing an example of the semiconductor device 100. In FIG. 1, the positions where each member is projected onto the front surface of the semiconductor substrate 10 are shown. In FIG. 1, only some members of the semiconductor device 100 are shown, and other members are omitted.

[0047] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has an edge 162 in a top view. When simply referred to as a top view in this specification, it means looking from the front surface side of the semiconductor substrate 10. The semiconductor substrate 10 of this example has two pairs of edges 162 facing each other in a top view. In FIG. 1, the X-axis and the Y-axis are parallel to any one of the edges 162. Also, the Z-axis is perpendicular to the front surface of the semiconductor substrate 10.

[0048] An active region 160 is provided on the semiconductor substrate 10. The active region 160 is a region where a main current flows in the depth direction between the front surface and the back surface of the semiconductor substrate 10 when the semiconductor device 100 operates. An emitter electrode is provided above the active region 160, but is omitted in FIG. 1. The active region 160 may refer to a region overlapping with the emitter electrode in a top view. Also, a region sandwiched by the active region 160 in a top view may be included in the active region 160.

[0049] The active region 160 is provided with a transistor portion 70 including transistor elements such as IGBTs (Insulated Gate Bipolar Transistors), and a diode portion 80 including diode elements such as freewheeling diodes (FWDs). In the example of FIG. 1, the transistor portion 70 and the diode portion 80 are alternately arranged along a predetermined first direction (the X-axis direction in this example) on the front surface of the semiconductor substrate 10. The semiconductor device 100 of this example is a reverse-conducting IGBT (RC-IGBT). A boundary region is arranged between the transistor portion 70 and the diode portion 80 in the X-axis direction, but is omitted in FIG. 1.

[0050] In FIG. 1, the region where the transistor portion 70 is arranged is marked with the symbol "I", and the region where the diode portion 80 is arranged is marked with the symbol "F". In this specification, a direction different from the first direction in a top view may be referred to as a second direction (the Y-axis direction in FIG. 1). The second direction may be a direction perpendicular to the first direction. The transistor portion 70 and the diode portion 80 may each have a longitudinal direction in the second direction. That is, the length of the transistor portion 70 in the Y-axis direction is larger than the width in the X-axis direction. Similarly, the length of the diode portion 80 in the Y-axis direction is larger than the width in the X-axis direction. The second direction of the transistor portion 70 and the diode portion 80 may be the same as the longitudinal direction of each trench portion and the longitudinal direction of each mesa portion described later.

[0051] The diode portion 80 has an N+-type cathode region in a region in contact with the back surface of the semiconductor substrate 10. In this specification, the region where the cathode region is provided is referred to as the diode portion 80. That is, the diode portion 80 is a region that overlaps the cathode region in a top view. On the back surface of the semiconductor substrate 10, a P+-type collector region may be provided in a region other than the cathode region. In this specification, the extended region 81 that extends in the Y-axis direction up to the gate wiring described later may also be included in the diode portion 80. A collector region is provided on the back surface of the extended region 81. The diode portion 80 has a P-type anode region on the front surface side of the semiconductor substrate 10.

[0052] The transistor portion 70 has a P+-type collector region in a region in contact with the back surface of the semiconductor substrate 10. Further, in the transistor portion 70, a gate structure including an N-type emitter region, a P+-type contact region, a P-type base region, a gate conductive portion, and a gate insulating film is periodically arranged on the front surface side of the semiconductor substrate 10.

[0053] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 164. The semiconductor device 100 may have pads such as an anode pad, a cathode pad, and a current detection pad of a temperature sensing portion that is a PN junction diode. Each pad is arranged in the vicinity of the end side 162. The vicinity of the end side 162 refers to a region between the end side 162 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via a wiring such as a wire.

[0054] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to the conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes a gate wiring that connects the gate pad 164 and the gate trench portion. In FIG. 1, the gate wiring is hatched with oblique lines.

[0055] The gate wiring in this example has an outer peripheral gate wiring 130. The outer peripheral gate wiring 130 is disposed between the active portion 160 and the edge 162 of the semiconductor substrate 10 in a top view. The outer peripheral gate wiring 130 in this example surrounds the active portion 160 in a top view. The region surrounded by the outer peripheral gate wiring 130 in a top view may be regarded as the active portion 160. Also, a well region is formed below the gate wiring. The well region is a P-type region having a higher concentration than the base region described later, and is formed from the front surface of the semiconductor substrate 10 to a position deeper than the base region. The region surrounded by the well region in a top view may be regarded as the active portion 160.

[0056] The outer peripheral gate wiring 130 is connected to the gate pad 164. The outer peripheral gate wiring 130 is disposed above the semiconductor substrate 10. The outer peripheral gate wiring 130 may be a metal wiring containing aluminum or the like, or a semiconductor such as polysilicon doped with impurities.

[0057] The semiconductor device 100 in this example further includes an active side gate wiring 131. The active side gate wiring 131 is provided in the active portion 160. By providing the active side gate wiring 131 in the active portion 160, the variation in the wiring length from the gate pad 164 can be reduced for each region of the semiconductor substrate 10.

[0058] The outer peripheral gate wiring 130 and the active side gate wiring 131 are connected to the gate trench portion of the active portion 160. The outer peripheral gate wiring 130 and the active side gate wiring 131 are disposed above the semiconductor substrate 10. The outer peripheral gate wiring 130 and the active side gate wiring 131 may be wirings formed of a metal wiring containing aluminum or the like, or a semiconductor such as polysilicon doped with impurities.

[0059] The active-side gate wiring 131 may be connected to the outer peripheral gate wiring 130. The active-side gate wiring 131 in this example extends in the X-axis direction so as to cross the active portion 160 at substantially the center in the Y-axis direction from one outer peripheral gate wiring 130 sandwiching the active portion 160 to the other outer peripheral gate wiring 130. When the active portion 160 is divided by the active-side gate wiring 131, the transistor portions 70 and the diode portions 80 may be alternately arranged in the X-axis direction in each divided region.

[0060] The semiconductor device 100 may include a temperature sensing portion (not shown) which is a PN junction diode formed of polysilicon or the like, and a current detecting portion (not shown) that simulates the operation of the transistor portion provided in the active portion 160. The temperature sensing portion may arrange an anode pad and a cathode pad in the vicinity of the end side 162. Also, the current detecting portion may arrange a current detection pad with in the vicinity of the end side 162.

[0061] The semiconductor device 100 in this example includes an edge termination structure portion 90 between the active portion 160 and the end side 162 in a top view. The edge termination structure portion 90 in this example is arranged between the outer peripheral gate wiring 130 and the end side 162. The edge termination structure portion 90 relaxes the electric field concentration on the front surface side of the semiconductor substrate 10. The edge termination structure portion 90 may include at least one of a guard ring, a field plate, and RESURF provided annularly surrounding the active portion 160.

[0062] FIG. 2 is an enlarged view showing an example of the region D in FIG. 1. The region D is a region including the transistor portion 70, the diode portion 80, and the active-side gate wiring 131. Although omitted in FIG. 1, a boundary region 200 is arranged between the transistor portion 70 and the diode portion 80 in the X-axis direction. The boundary region 200 is a buffer structure for arranging different structures of the transistor portion 70 and the diode portion 80 in parallel. The boundary region 200 is a region having a P+-type collector region in a region in contact with the back surface of the semiconductor substrate 10. The boundary region 200 in this example does not have an emitter region on the front surface of the semiconductor substrate 10.

[0063] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, a well region 11, an emitter region 12, a base region 14, a contact region 15, and an anode region 84 provided inside the front surface side of the semiconductor substrate 10. The gate trench portion 40 and the dummy trench portion 30 are each an example of a trench portion. Further, the semiconductor device 100 of this example includes an emitter electrode 52 and an active side gate wiring 131 provided above the front surface of the semiconductor substrate 10. The emitter electrode 52 and the active side gate wiring 131 are provided separately from each other.

[0064] An interlayer insulating film is provided between the emitter electrode 52 and the active side gate wiring 131 and the front surface of the semiconductor substrate 10, but is omitted in FIG. 2. A contact hole 54 is provided through the interlayer insulating film of this example. In FIG. 2, each contact hole 54 is hatched with oblique lines.

[0065] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, the contact region 15, and the anode region 84. The emitter electrode 52 is in contact with the emitter region 12, the contact region 15, and the base region 14 on the front surface of the semiconductor substrate 10 through the contact hole 54. Further, the emitter electrode 52 is connected to a dummy conductive portion in the dummy trench portion 30 through a contact hole provided in the interlayer insulating film. The emitter electrode 52 may be connected to the dummy conductive portion of the dummy trench portion 30 at the tip of the dummy trench portion 30 in the Y-axis direction. The dummy conductive portion of the dummy trench portion 30 does not have to be connected to the emitter electrode 52 and the gate conductive portion, and may be controlled to a potential different from the potential of the emitter electrode 52 and the potential of the gate conductive portion.

[0066] The active-side gate wiring 131 is connected to the gate trench portion 40 through a contact hole provided in the interlayer insulating film. The active-side gate wiring 131 may be connected to the gate conductive portion of the gate trench portion 40 at the tip portion 41 of the gate trench portion 40 in the Y-axis direction. The active-side gate wiring 131 is not connected to the dummy conductive portion in the dummy trench portion 30.

[0067] The emitter electrode 52 is formed of a material containing metal. The emitter electrode 52 is an example of a front surface electrode. In FIG. 2, the range where the emitter electrode 52 is provided is shown. For example, at least a part of the emitter electrode 52 is formed of aluminum or an alloy mainly composed of aluminum, such as a metal alloy like Al—Si, Al—Si—Cu, etc., or an alloy mainly composed of copper or the like. The front surface electrode may have a barrier metal. Further, the front surface electrode may have a contact plug portion having a barrier metal formed of titanium, titanium compounds, etc. on the side surface of the contact hole in the contact hole, and a plug formed by embedding tungsten, copper, etc. so as to be in contact with the barrier metal and the emitter electrode 52. The contact plug portion connects the emitter electrode 52 and the semiconductor substrate 10. The plug and the emitter electrode 52 may be integrally formed.

[0068] The well region 11 is provided so as to overlap with the active-side gate wiring 131. The well region 11 is also provided to extend with a predetermined width in a range where it does not overlap with the active-side gate wiring 131. The well region 11 in this example is provided away from the active-side gate wiring 131 side from the end of the contact hole 54 in the Y-axis direction. The well region 11 is a region of the second conductivity type having a higher doping concentration than the base region 14. The base region 14 in this example is P-type, and the well region 11 is P+-type.

[0069] Each of the transistor section 70, the diode section 80, and the boundary region 200 has a plurality of trench sections arranged in a first direction. In the transistor section 70 of this example, one or more gate trench sections 40 and one or more dummy trench sections 30 are alternately provided along the first direction. In the diode section 80 of this example, a plurality of dummy trench sections 30 are provided along the first direction. In the diode section 80 of this example, no gate trench section 40 is provided. In the boundary region 200 of this example, a plurality of dummy trench sections 30 are provided along the first direction. In the boundary region 200 of this example, no gate trench section 40 is provided.

[0070] The gate trench section 40 of this example may have two straight portions 39 (portions of the trench that are linear along the second direction) extending along a second direction perpendicular to the first direction, and a tip portion 41 connecting the two straight portions 39. The second direction in FIG. 2 is the Y-axis direction.

[0071] At least a part of the tip portion 41 is preferably provided in a curved shape in a top view. By connecting the ends of the two straight portions 39 in the Y-axis direction with the tip portion 41, the electric field concentration at the ends of the straight portions 39 can be alleviated.

[0072] In the transistor section 70, the dummy trench section 30 is provided between the respective straight portions 39 of the gate trench section 40. One dummy trench section 30 may be provided between the respective straight portions 39, or a plurality of dummy trench sections 30 may be provided. In the transistor section 70 of this example, two dummy trench sections 30 are provided between the respective straight portions 39. The dummy trench section 30 may have a linear shape extending in the second direction, and may have a straight portion 29 and a tip portion 31, similar to the gate trench section 40. The semiconductor device 100 shown in FIG. 2 has only the dummy trench section 30 having the tip portion 31, but may have both a linear dummy trench section 30 having no tip portion 31 and a dummy trench section 30 having the tip portion 31.

[0073] The diffusion depth of the well region 11 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The Y-axis direction ends of the gate trench portion 40 and the dummy trench portion 30 are provided in the well region 11 in a top view. That is, at the Y-axis direction ends of each trench portion, the bottom in the depth direction of each trench portion is covered by the well region 11. Thereby, the electric field concentration at the bottom of each trench portion can be alleviated.

[0074] A mesa portion 60 is provided between trench portions adjacent in the first direction. The mesa portion 60 refers to a region sandwiched by trench portions inside the semiconductor substrate 10. The front surface of the mesa portion 60 in this example is the front surface of the semiconductor substrate 10. The depth position of the lower end of the mesa portion 60 is the same as the depth position of the lower end of the trench portion. The mesa portion 60 in this example is provided to extend in the second direction (Y-axis direction) along the trench on the front surface of the semiconductor substrate 10. The mesa portions 60 of the transistor portion 70, the mesa portions 60 of the diode portion 80, and the mesa portions 60 of the boundary region 200 may have different structures. When simply referred to as the mesa portion 60 in this specification, it refers to each of the mesa portions 60 of the transistor portion 70, the mesa portions 60 of the diode portion 80, and the mesa portions 60 of the boundary region 200.

[0075] A base region 14 is provided in the mesa portions 60 of the transistor portion 70 and the boundary region 200, and a base region 14 and an anode region 84 are provided in the mesa portions 60 of the diode portion 80. In FIG. 2, the base region 14 disposed at one end in the second direction of each mesa portion is shown, but the base region 14 is also disposed at the other end of each mesa portion. In the mesa portion of the transistor portion 70, at least one of an emitter region 12 of the first conductivity type and a contact region 15 of the second conductivity type may be provided in a region sandwiched by the base region 14 in a top view. The emitter region 12 in this example is of N+ type, and the contact region 15 is of P+ type. The emitter region 12 and the contact region 15 may be provided between the base region 14 and the front surface of the semiconductor substrate 10 in the depth direction.

[0076] The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the front surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 60 in contact with the gate trench portion 40 may be provided with a contact region 15 exposed on the front surface of the semiconductor substrate 10.

[0077] Each of the contact region 15 and the emitter region 12 in the mesa portion 60 is provided from one trench portion in the X-axis direction to the other trench portion. As an example, the contact region 15 and the emitter region 12 of the mesa portion 60 are alternately arranged along the second direction (Y-axis direction) of the trench portion.

[0078] In another example, the contact region 15 and the emitter region 12 of the mesa portion 60 may be provided in a stripe shape along the second direction (Y-axis direction) of the trench portion. For example, the emitter region 12 is provided in a region in contact with the trench portion, and the contact region 15 is provided in a region sandwiched between the emitter regions 12. The emitter region 12 is not provided in the mesa portion 60 of the diode portion 80 and the boundary region 200 in this example.

[0079] A contact region 15 and an anode region 84 may be provided on the front surface of the mesa portion 60 of the diode portion 80 in this example. The anode region 84 of the diode portion 80 may be provided between the base regions 14 in the second direction (Y-axis direction), and the contact region 15 of the diode portion 80 may be provided between the base region 14 and the anode region 84 in the second direction (Y-axis direction). The doping concentration of the anode region 84 may be the same as or different from the doping concentration of the base region 14. The doping concentration of the anode region 84 in this example is the same as the doping concentration of the base region 14. The base region 14 and the anode region 84 in this example are P-type. The base region 14 and the anode region 84 can be formed in the same process, which facilitates manufacturing.

[0080] On the front surface of the mesa portion 60 of the boundary region 200 in this example, a contact region 15 may be provided. The contact region 15 of the boundary region 200 may be sandwiched by the base region 14 in the second direction (Y-axis direction). Alternatively, on the front surface of the mesa portion 60 of the boundary region 200, the same anode region 84 as that of the mesa portion 60 of the diode portion 80 may be provided. Alternatively, in the mesa portion 60 of the boundary region 200, an N-type impurity region having a doping concentration lower than that of the emitter region 12 or the emitter region 12 may be provided. However, in that case, no gate trench portion 40 is provided in the boundary region 200. Also, the trench portion at the boundary position between the transistor portion 70 and the boundary region 200 is a dummy trench portion 30. In the mesa portion 60 of the boundary region 200, since the N-type impurity region does not contact the gate trench portion 40, an inversion layer is not formed and conduction does not occur. the same doping concentration Or an N-type impurity region having a lower doping concentration than the emitter region 12 may be provided. However, in that case, no gate trench portion 40 is provided in the boundary region 200. Also, the trench portion at the boundary position between the transistor portion 70 and the boundary region 200 is a dummy trench portion 30. In the mesa portion 60 of the boundary region 200, since the N-type impurity region does not contact the gate trench portion 40, an inversion layer is not formed and conduction does not occur.

[0081] The area ratio of the contact region 15 in the mesa portion 60 of the boundary region 200 may be larger than the area ratio of the contact region 15 in the mesa portion 60 of the diode portion 80. In this case, holes in the semiconductor substrate 10 can be easily drawn out to the emitter electrode 52 through the mesa portion 60 of the boundary region 200.

[0082] Above each mesa portion 60, a contact hole 54 is provided. The contact hole 54 is disposed in a region sandwiched by the base region 14 or the anode region. The contact hole 54 in this example is provided above each of the contact region 15, the base region 14, and the emitter region 12. The contact hole 54 is not provided in the base region 14 and the well region 11. The contact hole 54 may be disposed at the center in the first direction (X-axis direction) of the mesa portion 60.

[0083] In the diode section 80, an N+-type cathode region 82 is provided in a region adjacent to the back surface of the semiconductor substrate 10. A P+-type collector region 22 may be provided in a region on the back surface of the semiconductor substrate 10 where the cathode region 82 is not provided. The cathode region 82 and the collector region 22 are provided between the back surface 23 of the semiconductor substrate 10 and the buffer region 20. In FIG. 2, the boundary between the cathode region 82 and the collector region 22 is indicated by a dotted line.

[0084] The cathode region 82 is arranged away from the well region 11 in the Y-axis direction. Thereby, the distance between the P-type region (well region 11) with a relatively high doping concentration and formed to a deep position and the cathode region 82 is ensured, and the breakdown voltage can be improved. The end portion of the cathode region 82 in the Y-axis direction in this example is arranged farther from the well region 11 than the end portion of the contact hole 54 in the Y-axis direction. In other examples, the end portion of the cathode region 82 in the Y-axis direction may be arranged between the well region 11 and the contact hole 54.

[0085] FIG. 3A is a diagram showing an example of the a-a cross section in FIG. 2. The a-a cross section is an XZ plane passing through the emitter region 12 and the cathode region 82. The semiconductor device 100 in this example has, in this cross section, the semiconductor substrate 10, the interlayer insulating film 38, the emitter electrode 52, and the collector electrode 24.

[0086] The interlayer insulating film 38 is provided on the front surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film including at least one layer of an insulating film such as a silicate glass to which impurities such as boron or phosphorus are added, a thermal oxide film, and other insulating films. The contact hole 54 described in FIG. 2 is provided in the interlayer insulating film 38.

[0087] The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 is an example of a front surface electrode. The emitter electrode 52 may be in contact with the semiconductor substrate 10 through the contact hole 54 of the interlayer insulating film 38. Alternatively, a contact plug portion may be provided in the contact hole 54 to connect the emitter electrode 52 and the semiconductor substrate 10. The contact plug portion may include a plug formed of tungsten or the like and a barrier metal containing titanium provided at a portion in contact with the semiconductor substrate 10. The barrier metal may have a titanium nitride layer and may have a laminated structure of a titanium nitride layer and a titanium layer.

[0088] The collector electrode 24 is provided on the back surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum. In this specification, the direction (Z-axis direction) connecting the emitter electrode 52 and the collector electrode 24 is referred to as the depth direction.

[0089] The semiconductor substrate 10 has an N-type drift region 18. The drift region 18 is provided in each of the transistor portion 70, the diode portion 80, and the boundary region 200.

[0090] In this example, the plurality of mesa portions 60 include a first mesa portion 61, a third mesa portion 63, and a fourth mesa portion 64. The first mesa portion 61 is provided in the transistor portion 70, the third mesa portion 63 is provided in the diode portion 80, and the fourth mesa portion 64 is provided in the boundary region 200.

[0091] In the first mesa portion 61 of the transistor portion 70, an N+-type emitter region 12 and a P-type base region 14 are provided in order from the front surface 21 side of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An N+-type accumulation region 16 may be provided in the first mesa portion 61. The accumulation region 16 is disposed between the base region 14 and the drift region 18.

[0092] The emitter region 12 is exposed on the front surface 21 of the semiconductor substrate 10 and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The emitter region 12 has a higher doping concentration than the drift region 18.

[0093] The base region 14 is provided below the emitter region 12. In this example, the base region 14 is provided in contact with the emitter region 12. The base region 14 may be in contact with the trench portions on both sides of the first mesa portion 61.

[0094] The accumulation region 16 is provided below the base region 14. The accumulation region 16 is an N+ type region having a higher doping concentration than the drift region 18. That is, the donor concentration of the accumulation region 16 is higher than that of the drift region 18. By providing the high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection promotion effect (IE effect) can be enhanced and the on-voltage can be reduced. The accumulation region 16 may be provided so as to cover the entire back surface of the base region 14 in the first mesa portion 61.

[0095] On the third mesa portion 63 of the diode portion 80, an anode region 84 is provided in contact with the front surface 21 of the semiconductor substrate 10. The doping concentration of the anode region 84 may be the same as that of the base region 14 or may be lower than that of the base region 14. In this example, the doping concentration of the anode region 84 is the same as that of the base region 14. The base region 14 and the anode region 84 in this example are P-type. Below the anode region 84, a drift region 18 is provided. An accumulation region 16 may be provided below the anode region 84.

[0096] In the fourth mesa portion 64 of the boundary region 200 of this example, a base region 14 is provided, and a contact region 15 is provided on the front surface side of the base region 14. The contact region 15 is sandwiched by the base region 14 in the second direction (Y-axis direction). Thereby, holes in the semiconductor substrate 10 are easily drawn out to the emitter electrode 52 through the fourth mesa portion 64 of the boundary region 200 during the turn-off operation. A drift region 18 is provided below the base region 14. In the fourth mesa portion 64, an accumulation region 16 may be provided below the base region 14.

[0097] Note that in FIG. 3A, the boundary region 200 is shown as having one fourth mesa portion 64, but it is not limited thereto. The boundary region 200 may be provided over one or several mesa portions 60 (fourth mesa portion 64).

[0098] In each of the transistor portion 70, the diode portion 80, and the boundary region 200, an N+-type buffer region 20 may be provided below the drift region 18. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may have a concentration peak with a higher doping concentration than the drift region 18. The doping concentration of the concentration peak refers to the doping concentration at the apex of the concentration peak. Also, the doping concentration of the drift region 18 may be the average value of the doping concentration in a region where the doping concentration distribution is substantially flat.

[0099] The buffer region 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The concentration peaks of the buffer region 20 may be provided at the same depth position as, for example, the chemical concentration peaks of hydrogen (proton) or phosphorus. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower end of the base region 14 from reaching the P+-type collector region 22 and the N+-type cathode region 82.

[0100] In the transistor section 70, a P+-type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than that of the base region 14. The collector region 22 may contain the same acceptor as the base region 14 or may contain a different acceptor. The acceptor of the collector region 22 is, for example, boron or aluminum.

[0101] In the diode section 80, an N+-type cathode region 82 is provided below the buffer region 20. The donor concentration of the cathode region 82 is higher than that of the drift region 18. The donor of the cathode region 82 is, for example, hydrogen or phosphorus. Note that the elements serving as donors and acceptors in each region are not limited to the above examples.

[0102] In the boundary region 200, a P+-type collector region 22 is provided below the buffer region 20. That is, the boundary region 200 may be regarded as a part of the transistor section 70. The collector region 22 of the boundary region 200 may have the same doping concentration as the boundary region 200 of the transistor section 70. The boundary position in the X-axis direction between the cathode region 82 and the collector region 22 may be the boundary position in the X-axis direction between the diode section 80 and the boundary region 200.

[0103] In another example, in the boundary region 200, part or all of the collector region 22 may be replaced with the cathode region 82. When the cathode region 82 is provided on the back surface of the boundary region 200, the region where the contact region 15 and the anode region 84 are alternately arranged in the region sandwiched by the anode region 84 may be regarded as the diode section 80, and the region where the contact region 15 is arranged over the entire region sandwiched by the anode region 84 may be regarded as the boundary region 200. When the cathode region 82 is provided on the back surface of the boundary region 200, the boundary region 200 may be regarded as a part of the diode section 80.

[0104] Of the two trench portions in contact with the emitter region 12 disposed closest to the diode portion 80 in the X-axis direction, the trench portion on the diode portion 80 side may be the dummy trench portion 30. The dummy trench portion 30 in this case may be used as the boundary position in the X-axis direction between the transistor portion 70 and the boundary region 200 (or the diode portion 80). The central position of the dummy trench portion 30 in the X-axis direction may be used as the boundary position in the X-axis direction between the transistor portion 70 and the boundary region 200 (or the diode portion 80).

[0105] The emitter region 12 may be provided in the boundary region 200. However, in that case, the gate trench portion 40 is not provided in the boundary region 200. Also, the trench portion at the boundary position between the transistor portion 70 and the boundary region 200 is the dummy trench portion 30. That is, no transistor operation occurs in the boundary region 200. The gate trench portion 40 may be provided in the boundary region 200. However, in that case, the emitter region 12 is not provided in the boundary region 200. That is, no transistor operation occurs in the boundary region 200.

[0106] The collector region 22 and the cathode region 82 are exposed on the back surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire back surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum.

[0107] The semiconductor device 100 of this example includes a lifetime adjustment region 206 that includes a lifetime killer for adjusting the carrier lifetime. The lifetime adjustment region 206 of this example is a region where the lifetime of charge carriers is locally short. The charge carriers are electrons or holes. The charge carriers may simply be referred to as carriers. The lifetime adjustment region 206 of this example is formed by irradiating a particle beam. Here, when simply referring to a particle beam, it includes a particle beam composed of charged particles such as helium ions and protons and an electron beam. The lifetime adjustment region 206 of this example is formed by injecting a particle beam from the front surface 21 side of the semiconductor substrate 10. The particle beam may be injected from the back surface 23 side of the semiconductor substrate 10.

[0108] In this example, the concentration distribution of helium or the like in the depth direction of the semiconductor substrate 10 may have a shape that trails from the lifetime adjustment region 206 to the front surface 21 of the semiconductor substrate 10. That is, from the lifetime adjustment region 206 to the front surface 21, the concentration of helium or the like ( / cm 3 ) may monotonically decrease. The concentration of helium or the like on the front surface 21 may be greater than 0. On the other hand, also in the direction from the lifetime adjustment region 206 toward the back surface 23, the concentration of helium or the like may have a shape that trails. However, the trail toward the back surface 23 has a steeper decrease in the concentration of helium or the like than the trail toward the front surface 21. The concentration of helium or the like on the back surface 23 is lower than the concentration of helium or the like on the front surface 21. The concentration of helium or the like on the front surface 21 may be below the measurement limit or may be 0.

[0109] By irradiating a semiconductor substrate 10 with a particle beam to inject charged particles, lattice defects 204 such as vacancies are formed in the vicinity of the injection position. The lattice defects 204 generate recombination centers. The lattice defects 204 may mainly be vacancies such as single-atom vacancies (V), multi-atom vacancies (VV), etc., may be dislocations, may be interstitial atoms, or may be transition metals, etc. For example, an atom adjacent to a vacancy has a dangling bond. In a broad sense, donors and acceptors may also be included in the lattice defects 204, but in this specification, the lattice defects 204 mainly composed of vacancies may be referred to as vacancy-type lattice defects, vacancy-type defects, or simply lattice defects. In this specification, the lattice defects 204 may be simply referred to as recombination centers or lifetime killers as recombination centers contributing to carrier recombination. The lifetime killer may be formed by injecting helium ions into the semiconductor substrate 10. The helium chemical concentration may be used as the density of the lattice defects 204. Note that since the lifetime killer formed by injecting helium ions may be terminated by hydrogen present in the buffer region 20, the depth position of the density peak of the lifetime killer and the depth position of the peak of the helium chemical concentration may not match. In addition, the lifetime killer may be formed in the passage region of hydrogen ions on the injection surface side rather than the range of travel when hydrogen ions are injected into the semiconductor substrate 10. of hydrogen ions It may be formed in the passage region of hydrogen ions on the injection surface side rather than the range of travel.

[0110] The lattice defects 204 are an example of a lifetime killer. In FIG. 3A, the lattice defects 204 at the injection position of the charged particles are schematically shown by crosses. In a region where many lattice defects 204 remain, carriers are captured by the lattice defects 204, so the lifetime of the carriers becomes short. By adjusting the lifetime of the carriers, characteristics such as the reverse recovery time and reverse recovery loss of the diode portion 80 can be adjusted. In the depth direction of the semiconductor substrate 10, the position where the carrier lifetime shows a minimum value may be used as the depth position of the lifetime adjustment region 206.

[0111] When an electron beam, a particle beam, or the like for forming the lifetime adjustment region 206 passes through the gate trench portion 40, defects may occur in the vicinity of the interface between the gate insulating film 42 and the semiconductor substrate 10. When a metal such as Ti having a hydrogen storage effect exists in the vicinity of the gate trench portion 40, the diffusing hydrogen is stored, inhibiting the hydrogen termination of the dangling bonds in the gate trench portion 40 and causing the threshold voltage to fluctuate.

[0112] The lifetime adjustment region 206 of this example is disposed on the front surface 21 side of the semiconductor substrate 10. Here, the front surface 21 side of the semiconductor substrate 10 is the region from the central position in the depth direction of the semiconductor substrate 10 to the front surface 21 of the semiconductor substrate 10. The lifetime adjustment region 206 of this example is disposed below the lower end of the trench portion. Also, when the lifetime adjustment region 206 is formed by irradiating a particle beam with high transmissive power such as an electron beam, lattice defects are formed substantially uniformly from the front surface 21 to the back surface 23 of the semiconductor substrate 10. In this case as well, the depth position of the lifetime adjustment region 206 may be regarded as being disposed on the front surface 21 side of the semiconductor substrate 10.

[0113] The lifetime adjustment region 206 may be provided in at least one of the transistor portion 70 and the diode portion 80. When the semiconductor device 100 has the boundary region 200, the lifetime adjustment region 206 may also be provided in the boundary region 200. The lifetime adjustment region 206 may be provided so as to extend to at least a part or the whole of the diode portion 80 in the first direction (X-axis direction). The lifetime adjustment region 206 may be provided so as to extend to at least a part or the whole of the transistor portion 70 in the first direction (X-axis direction). The lifetime adjustment region 206 may also be provided in the whole of the boundary region 200. In another example, the lifetime adjustment region 206 may be provided in a part of the boundary region 200.

[0114] In this example, the lifetime adjustment region 206 extends across the entire transistor portion 70 and diode portion 80 in the first direction (X-axis direction). That is, in this example, the lifetime adjustment region 206 extends across the entire boundary region 200 in the first direction (X-axis direction).

[0115] As described above, the doping concentration of the anode region 84 in this example is the same as that of the base region 14. Since the semiconductor device 100 in this example includes the lifetime adjustment region 206, the reverse recovery loss of the diode portion 80 is reduced, so that the doping concentration of the anode region 84 can be increased to the same level as that of the base region 14. Therefore, the base region 14 and the anode region 84 can be formed in the same process, and the manufacturing becomes easy.

[0116] Also, since the lifetime adjustment region 206 in this example extends across the entire transistor portion 70 in the first direction (X-axis direction), hole injection from the contact region 15 of the transistor portion 70 can be suppressed. Therefore, in the first direction (X-axis direction), it is not necessary to extend across the plurality of mesa portions 60 of the boundary region 200, and the area of the inactive region where the transistor does not operate can be reduced.

[0117] On the front surface 21 side of the semiconductor substrate 10, one or more gate trench portions 40 and one or more dummy trench portions 30 are provided. Each trench portion is provided from the front surface 21 of the semiconductor substrate 10 through the base region 14 or the anode region 84 to below the base region 14 and the anode region 84. In a region where at least one of the emitter region 12, the contact region 15, and the accumulation region 16 is provided, each trench portion also penetrates these doping regions. The fact that the trench portion penetrates the doping region is not limited to the case where the trench portion is formed after the doping region is formed. Those in which the doping region is formed between the trench portions after the trench portions are formed are also included in those in which the trench portion penetrates the doping region.

[0118] As described above, the transistor portion 70 is provided with the gate trench portion 40 and the dummy trench portion 30. The diode portion 80 and the boundary region 200 of this example are provided with the dummy trench portion 30 and are not provided with the gate trench portion 40. However, the gate trench portion 40 may be disposed at the boundary between the boundary region 200 and the transistor portion 70, or the dummy trench portion 30 may be disposed there.

[0119] The gate trench portion 40 includes a gate trench provided on the front surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate insulating film 42 inside the gate trench. That is, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0120] The gate conductive portion 44 may be provided longer than the base region 14 in the depth direction. The gate trench portion 40 in the cross section is covered by the interlayer insulating film 38 on the front surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel due to an inversion layer of electrons is formed in the surface layer of the interface of the base region 14 in contact with the gate trench portion 40.

[0121] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross-section. The dummy trench portion 30 includes a dummy trench provided on the front surface 21 of the semiconductor substrate 10, a dummy insulating film 32, and a dummy conductive portion 34. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 is provided to cover the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction.

[0122] In this example, the gate trench portion 40 and the dummy trench portion 30 are covered by the interlayer insulating film 38 on the front surface 21 of the semiconductor substrate 10. Note that the bottoms of the dummy trench portion 30 and the gate trench portion 40 may be curved surfaces convex downward (curved in cross-section).

[0123] In the first mesa portion 61 of this example, a first contact portion 77 is provided. In the first mesa portion 61, the region where the first contact portion 77 connects the first mesa portion 61 and the front surface electrode corresponds to the contact portion.

[0124] In the third mesa portion 63 of this example, a second contact portion 87 where the front surface electrode is in contact with the front surface of the third mesa portion 63 is provided. The second contact portion 87 is a portion where the front surface electrode (i.e., the emitter electrode 52 or the contact plug portion) is provided inside the mesa portion 60. By forming a groove in the front surface 21 of the semiconductor substrate 10 exposed by the contact hole 54 and filling the groove with the front surface electrode, the second contact portion 87 can be formed. In the second contact portion 87, the region where the third mesa portion 63 and the front surface electrode are connected corresponds to the contact portion. The first contact portion 77 is disposed above the second contact portion 87.

[0125] In the fourth mesa portion 64 of this example, a second contact portion 87 is provided. Alternatively, a first contact portion 77 may be provided in some of the fourth mesa portions 64, and a second contact portion 87 may be provided in the other fourth mesa portions 64.

[0126] In this example, each contact portion refers to the interface where the front surface electrode and the mesa portion 60 are in contact. The contact portion may include the surface of the front surface electrode and the surface of the mesa portion 60. Here, the surface of the mesa portion 60 the first contact portion 77 in the case of, refers to the front surface of the mesa portion 60, that is, the front surface 21 of the semiconductor substrate 10. In the case of the second contact portion 87, the surface of the mesa portion 60 refers to the bottom surface of the contact hole 54 provided inside the mesa portion 60.

[0127] In addition, when a metal silicide layer is formed at the interface between the front surface electrode and the mesa portion 60, the metal silicide layer may be included in the front surface electrode. That is, the interface between the metal silicide layer and the mesa portion 60 may be used as the contact portion.

[0128] In this example, by providing the second contact portion 87 in the diode portion 80, a region with a high doping concentration near the front surface 21 of the semiconductor substrate 10 is removed, so the second contact portion 87 is in contact with a region with a low doping concentration in the anode region 84. Thereby, the reverse recovery loss of the diode portion 80 can be reduced.

[0129] FIG. 3B is an enlarged view of the vicinity of the contact hole 54 provided in the first mesa portion 61, the third mesa portion 63, and the fourth mesa portion 64 shown in FIG. 3A. FIG. 3B shows one each of the first mesa portion 61, the third mesa portion 63, and the fourth mesa portion 64, and omits the regions between the respective mesa portions.

[0130] The emitter electrode 52 in this example is provided on the front surface of the interlayer insulating film 38. The contact plug portion 250 includes a plug 251 and a barrier metal portion 252. The plug 251 in this example contains tungsten. The barrier metal portion 252 is provided above the front surface 21 of the semiconductor substrate 10. The barrier metal portion 252 is provided at least on the bottom surface of the contact hole 54. The barrier metal portion 252 may be provided at each contact portion. The barrier metal portion 252 may be in contact with the semiconductor substrate 10. The barrier metal portion 252 may also be provided on the side surface of the contact hole 54. The plug 251 is embedded in the contact hole 54 via the barrier metal portion 252. The plug 251 and the barrier metal portion 252 may or may not be provided on the front surface of the interlayer insulating film 38.

[0131] The barrier metal portion 252 suppresses the intrusion of metal elements of the plug 251 into the semiconductor substrate 10 and ions contained in the external environment. The barrier metal portion 252 may contain at least one metal element of titanium (Ti), cobalt (Co), nickel (Ni), tantalum (Ta), magnesium (Mg), vanadium (V), lanthanum (La), palladium (Pd), or zirconium (Zr). The barrier metal portion 252 may be a metal having a hydrogen storage effect. The barrier metal portion 252 in this example has a titanium (Ti) layer. The barrier metal portion 252 may include a titanium nitride layer. The barrier metal portion 252 may be a laminated film of a titanium layer and a titanium nitride layer.

[0132] The emitter electrode 52 is provided above the barrier metal portion 252. The emitter electrode 52 is also provided above the interlayer insulating film 38. The emitter electrode 52 is formed of a material different from that of the barrier metal portion 252. As an example, the emitter electrode 52 contains aluminum. The emitter electrode 52 may be an alloy of aluminum and silicon.

[0133] FIG. 3B shows the depth Z1 of the first contact portion 77 and the depth Z2 of the second contact portion 87 in the depth direction (Z-axis direction) of the semiconductor substrate 10. In this example, the first contact portion 77 is provided in the first mesa portion 61, and the second contact portion 87 is provided in the third mesa portion 63 and the fourth mesa portion 64.

[0134] Here, the depths of the first contact portion 77 and the second contact portion 87 are the distances from the front surface 21 of the semiconductor substrate 10 to the deepest position at the interface where the semiconductor substrate 10 and the front surface electrode are in contact at the bottom surface of the contact hole 54. The depth Z2 of the second contact portion 87 is greater than the depth Z1 of the first contact portion 77.

[0135] The first contact portion 77 in this example is in contact with the front surface 21 of the semiconductor substrate 10. Therefore, the depth Z1 of the first contact portion 77 is zero. The first contact portion 77 may be disposed at a position deeper than the front surface 21 of the semiconductor substrate 10. Also, the depth Z2 of the second contact portion 87 in this example is greater than the depth Z1 of the first contact portion 77. That is, the second contact portion 87 is disposed at a position farther from the front surface 21 of the semiconductor substrate 10 than the first contact portion 77.

[0136] In this example, by providing the first contact portion 77 in the transistor portion 70, the surface area (total area of the side surface and the bottom surface) of the contact hole 54 provided in the transistor portion 70 becomes smaller than the surface area of the contact hole 54 provided in the diode portion 80. Therefore, in the contact hole 54 provided in the transistor portion 70, the area of the barrier metal portion 252 is relatively small, and the amount of the Ti layer in the barrier metal portion 252 is also relatively small. Thereby, the fluctuation of the threshold voltage due to the Ti layer having a hydrogen storage effect can be suppressed.

[0137] FIG. 4A is a view showing an example of the b-b cross section in FIG. 2. The b-b cross section is an XZ plane passing through the contact region 15 and the cathode region 82. In the b-b cross section of FIG. 4A, the contact region 15 is arranged instead of the emitter region 12 in the a-a cross section shown in FIG. 3A. Also, a plug region of the second conductivity type is provided below the contact hole 54. Since other structures are the same as those in the a-a cross section, the description thereof is omitted here.

[0138] The first mesa portion 61 in this example is provided below the first contact portion 77 and has a P++-type first plug region 221 having a higher doping concentration than the contact region 15. The first plug region 221 may be provided in contact with the first contact portion 77. At least a part of the first plug region 221 is provided so as to overlap the contact region 15 in a top view. The entire first plug region 221 may be provided so as to overlap the contact region 15. That is, the first plug region 221 is provided in any XZ cross section passing through the contact region 15. The first plug region 221 may be provided in an XZ cross section passing through the center of the contact region 15 in the Z-axis direction.

[0139] In this example, as can be seen from FIG. 3A, the first plug region 221 is not provided in the XZ cross section passing through the emitter region 12. That is, the first plug region 221 is provided below the contact region 15 and may not be provided below the emitter region 12. For example, the first plug region 221 is not provided in the XZ cross section passing through the center of the emitter region 12 in the Z-axis direction. That is, the first plug region 221 does not overlap the emitter region 12 in a top view, and the first plug region 221 is discretely provided in the second direction (Y-axis direction). By providing each plug region, it becomes easier to extract holes in each mesa portion. Therefore, a decrease in breakdown voltage can be suppressed. In other examples, the first plug region 221 may be provided below the emitter region 12 and may be provided extending in the second direction (Y-axis direction) as long as it does not completely prevent the connection between the emitter region 12 and the first contact portion 77.

[0140] The third mesa portion 63 may be provided below the second contact portion 87 and may have a P++ type second plug region 222 with a doping concentration higher than that of the contact region 15. The second plug region 222 may be provided in contact with the second contact portion 87.

[0141] Alternatively, similar to the first plug region 221 described above, the second plug region 222 may not be provided in the XZ cross-section passing through the emitter region 12 and may be discretely provided below the contact region 15 in the second direction (Y-axis direction). Similar to the first plug region 221, the second plug region 222 in this example is discretely provided in the second direction (Y-axis direction) and is not provided in the XZ cross-section passing through the center of the emitter region 12 in the Z-axis direction. Thereby, the injection of holes from the third mesa portion 63 into the drift region 18 can be suppressed, and the reverse recovery loss can be reduced.

[0142] In another example, the second plug region 222 of the third mesa portion 63 is discretely provided in the second direction (Y-axis direction) spacing, width, position may be provided to be different from the interval, width, and position of the emitter region 12 of the first mesa portion 61. The second plug region 222 of each third mesa portion 63 may be provided to be different from the interval, width, and position of the second plug region 222 of another third mesa portion 63. The second plug region 222 may be provided to extend in the second direction (Y-axis direction).

[0143] The fourth mesa portion 64 may have a second plug region 222 below the second contact portion 87. Since the configuration of the second plug region 222 in the fourth mesa portion 64 is the same as that of the second plug region 222 in the third mesa portion 63, the description thereof is omitted.

[0144] FIG. 4B is an enlarged view of the vicinity of the contact hole 54 provided in the first mesa portion 61, the third mesa portion 63, and the fourth mesa portion 64 shown in FIG. 4A. In this example, a first plug region 221 is provided below the first contact portion 77, and a second plug region 222 is provided below the second contact portion 87. Since other points are common to FIG. 3B, the description thereof is omitted. By providing each plug region, it becomes easier to extract holes in each mesa portion. Therefore, a reduction in withstand voltage can be suppressed.

[0145] FIG. 4C is a view showing another example of the b-b cross section in FIG. 2. FIG. 4D is an enlarged view of the vicinity of the contact hole 54 provided in the first mesa portion 61, the third mesa portion 63, and the fourth mesa portion 64 shown in FIG. 4C. In this example, the first plug region 221 and the second plug region 222 are not provided below the contact region 15 and the anode region 84. That is, the semiconductor device 100 of this example is not provided with a plug region. Thereby, injection of holes can be suppressed, and reverse recovery loss can be reduced.

[0146] Note that when the plug region is not provided, neither the first contact portion 77 nor the second contact portion 87 is provided with the contact plug portion 250, that is, the plug 251 and the barrier metal portion 252, and the plug 251 and the barrier metal portion 252 are not provided at the location where the first contact portion 77 contacts the emitter region 12 either.

[0147] FIG. 5A is a view showing another example of the a-a cross section in FIG. 2. FIG. 5B is a view showing another example of the b-b cross section in FIG. 2. In this example, it is different from the above-described example in that the first contact portion 77 is provided in the fourth mesa portion 64 of the boundary region 200 instead of the second contact portion 87. Therefore, a first plug region 221 is provided below the first contact portion 77 in the fourth mesa portion 64 of the boundary region 200.

[0148] The first plug region 221 of the fourth mesa portion 64 in this example may be provided in the same arrangement as the second plug region 222 of the fourth mesa portion 64 described with reference to FIG. 4A. Even with such a configuration, the same effects as the above-described configuration can be obtained.

[0149] FIG. 6 is an enlarged view showing another example of region D in FIG. 1. FIG. 7A is a view showing an example of a c-c cross section in FIG. 6. FIG. 7B is a view showing an example of a d-d cross section in FIG. 6. This example is different from the above-described example in that no boundary region 200 is provided between the transistor portion 70 and the diode portion 80.

[0150] Also, the lifetime adjustment region 206 of this example is provided so as to extend from the diode portion 80 over a part of the transistor portion 70 in the second direction (Y-axis direction). In the semiconductor device 100 of this example, at least a part of the transistor portion 70 includes the lifetime adjustment region 206, so that a wide boundary region 200 is not provided, and the area of the inactive region where the transistor does not operate can be reduced. An example of providing a wide boundary region 200 will be described later. In the transistor portion 70, the region where the lifetime adjustment region 206 is provided is defined as an adjustment region 201, and the region where the lifetime adjustment region 206 is not provided is defined as a non-adjustment region 202. Since the configuration of the diode portion 80 is the same as that of the above-described example, the description thereof is omitted.

[0151] The adjustment region 201 of this example has the first contact portion 77 provided on the first mesa portion 61. The first contact portion 77 may be provided for some of the first mesa portions 61, or may be provided for all of the first mesa portions 61. Alternatively, the second contact portion 87 may be provided for all of the first mesa portions 61. Since the first mesa portion 61 of the adjustment region 201 has the same structure as the above-described first mesa portion 61, the description thereof is omitted.

[0152] The non-adjustment region 202 of this example has a first contact portion 77 provided in the second mesa portion 62. The non-adjustment region 202 is a region where the carrier lifetime at the same depth position as the lifetime adjustment region 206 is longer than the carrier lifetime of the lifetime adjustment region 206 of the diode portion 80. The non-adjustment region 202 may be a region into which charged particles such as helium for forming a lifetime killer such as a lattice defect 204 are not implanted. The chemical concentration ( / cm 3 ) of charged particles such as helium in the non-adjustment region 202 may be the same as the chemical concentration of the charged particles at the center in the Z-axis direction of the drift region 18.

[0153] The first contact portion 77 of this example is disposed below the front surfaces of the first mesa portion 61 and the second mesa portion 62. The depth of the first contact portion 77 may be 1 / 2 or less of the depth of the second contact portion 87, and may be 1 / 4 or less of the depth. The first contact portion 77 may be in contact with the front surface 21 of the semiconductor substrate 10, and the depth Z1 of the first contact portion 77 may be zero.

[0154] The doping concentration of the anode region 84 of this example may be the same as the doping concentration of the base region 14. Since the semiconductor device 100 of this example includes the lifetime adjustment region 206, the reverse recovery loss of the diode portion 80 is reduced, so the doping concentration of the anode region 84 can be increased to the same level as the base region 14. Therefore, the base region 14 and the anode region 84 can be formed in the same process, and the manufacturing becomes easy. In other examples, the doping concentration of the anode region 84 may be lower than the doping concentration of the base region 14, and the reverse recovery loss can be further reduced.

[0155] Also, the second plug region 222 of this example is provided to extend in the second direction (Y-axis direction). Since the semiconductor device 100 of this example includes the lifetime adjustment region 206, the reverse recovery loss of the diode portion 80 is reduced, so the second plug region 222 can be provided to extend, promoting the extraction of holes and suppressing the reduction of the withstand current.

[0156] In other examples, the plug regions may be provided discretely as described in FIGS. 3A, 3B, 4A, and 4B, or may not be provided as described in FIGS. 4C and 4D.

[0157] FIG. 8 is an enlarged view showing another example of region D in FIG. 1. FIG. 9A is a view showing an example of an e-e cross section in FIG. 8. FIG. 9B is an enlarged view of the vicinity of the second mesa portion 62, the third mesa portion 63, and the fourth mesa portion 64 shown in FIG. 9A. FIG. 9C is a view showing an example of an f-f cross section in FIG. 8.

[0158] The width of the boundary region 200 in this example is larger than the width of the boundary region 200 shown in FIG. 2. The width W of the boundary region 200 in the first direction (X-axis direction) in this example may be 20 μm or more and 250 μm or less, preferably 30 μm or more and 200 μm or less is more desirably, 50 μm or more and 100 μm or less.

[0159] The lifetime adjustment region 206 in this example is provided to extend from the diode portion 80 to the boundary region 200 in the first direction (X-axis direction). That is, the lifetime adjustment region 206 in this example is not provided in the transistor portion 70. Alternatively, the semiconductor device 100 may not have the lifetime adjustment region 206.

[0160] In this example, since the boundary region 200 is widely provided over a plurality of fourth mesa portions 64, the influence of the transistor portion 70 on the characteristics of the diode portion 80, for example, the operation of the gate trench portion 40, the discharge or injection of holes in the contact region 15 on the forward voltage and reverse recovery characteristics can be suppressed. Therefore, the lifetime adjustment region 206 in this example does not need to be provided in the transistor portion 70.

[0161] In the boundary region 200 of this example, a third contact portion 207 is provided on the fourth mesa portion 64. As shown in FIG. 9B, the third contact portion 207 is disposed above the second contact portion 87 and below the first contact portion 77. That is, the depth Z3 of the third contact portion 207 is greater than the depth of the first contact portion 77 and less than the depth Z2 of the second contact portion 87. The depth Z3 of the third contact portion 207 may be 1 / 2 or less of the depth Z2 of the second contact portion 87, or may be 1 / 4 or less of the depth. Thus, in this example, by providing the shallow third contact portion 207 in the boundary region 200, it is possible to reduce the amount of the Ti layer of the barrier metal portion 252 while promoting the extraction of holes to prevent latch-up.

[0162] In other examples, as described with reference to FIGS. 3A, 3B, 4A, and 4B, the boundary region 200 may be provided with the first contact portion 77 or the second contact portion 87. Further, in the examples described with reference to FIGS. 2 to 5B, the third contact portion 207 of this example may be provided in the boundary region 200.

[0163] In the boundary region 200 of this example, an anode region 84 is provided on the front surface of the fourth mesa portion 64, and the contact region 15 is not provided. That is, the structure of the front surface of the fourth mesa portion 64 is the same as the structure of the front surface of the third mesa portion 63. Further, the doping concentration of the anode region 84 in this example is lower than the doping concentration of the base region 14. In other examples, the doping concentration of the anode region 84 may be the same as the doping concentration of the base region 14.

[0164] Also, in FIGS. 9A and 9C, the first plug region 221 and the second plug region 222 are provided in the XZ cross-section passing through the contact region 15 and are not provided in the XZ cross-section passing through the emitter region 12. Therefore, the first plug region 221 and the second plug region 222 in this example are discretely provided in the second direction (Y-axis direction). Thereby, the injection of holes is suppressed, and even if the width W of the lifetime adjustment region 206 is small, the reverse recovery loss can be reduced. In other examples, the plug regions may be provided discretely or continuously as described in FIGS. 3A, 3B, 4A, and 4B, and may not be provided as described in FIGS. 4C and 4D.

[0165] As described above, the present invention has been described using the embodiments. However, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clear from the description of the claims that embodiments with such changes or improvements can also be included in the technical scope of the present invention.

[0166] It should be noted that the execution order of each process such as operations, procedures, steps, and stages in the devices, systems, programs, and methods shown in the claims, the specification, and the drawings is not explicitly indicated as "earlier" or "preceding" etc., and can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flows in the claims, the specification, and the drawings, even if "first," "next," etc. are used for convenience of explanation, it does not mean that it is essential to implement in this order.

Description of Reference Numerals

[0167] 10 ··· semiconductor substrate, 11 ··· well region, 12 ··· emitter region, 14 ··· base region, 15 ··· contact region, 16 ··· accumulation region, 18 ··· drift region, 20 ··· buffer region, 21 ··· front surface, 22 ··· collector region, 23 ··· back surface, 24 ··· collector electrode, 29 ··· straight portion, 30 ··· dummy trench portion, 31 ··· tip portion, 32 ··· dummy insulating film, 34 ··· dummy conductive portion, 38 ··· interlayer insulating film, 39 ··· straight portion, 40 ··· gate trench portion, 41 ··· tip portion, 42 ··· gate insulating film, 44 ··· gate conductive portion, 52 ··· emitter electrode, 54 ··· contact hole, 60 ··· mesa portion, 61 ··· first mesa portion, 62 ··· second mesa portion, 63 ··· third mesa portion, 64 ··· fourth mesa portion, 70 ··· transistor portion, 77 ··· first contact portion, 80 ··· diode portion, 81 ··· extension region, 82 ··· cathode region, 84 ··· anode region, 87 ··· second contact portion, 90 ··· edge termination structure portion, 100 ··· semiconductor device, 130 ··· outer peripheral gate wiring, 131 ··· active side gate wiring, 160 ··· active portion, 162 ··· side edge, 164 ··· gate pad, 200 ··· boundary region, 201 ··· adjustment region, 202 ··· non-adjustment region, 204 ··· lattice defect, 206 ··· lifetime adjustment region, 207 ··· third contact portion, 221 ··· first plug region, 222 ··· second plug region, 250 ··· contact plug portion, 251 ··· plug, 252 ··· barrier metal portion

Claims

1. A transistor section, a diode section, a plurality of trench sections provided on the front surface of a semiconductor substrate, a drift region of a first conductivity type provided in the semiconductor substrate, in the transistor section, a base region of a second conductivity type provided above the drift region, in the transistor section, a first conductivity type emitter region provided on the front surface of the semiconductor substrate and having a doping concentration higher than that of the drift region, and a second conductivity type contact region having a doping concentration higher than that of the base region, in the diode section, a second conductivity type anode region provided above the drift region, a mesa section of the semiconductor substrate provided between the plurality of trench sections, an interlayer insulating film provided above the semiconductor substrate, a front surface electrode provided above the semiconductor substrate, in a contact hole of the interlayer insulating film, a contact section where the front surface electrode and the mesa section are connected, a lifetime adjustment region provided on the front surface side of the semiconductor substrate, comprising: the contact section has a first contact section provided in the transistor section and a second contact section provided in the diode section, the first contact section is disposed above the second contact section a semiconductor device.

2. A second conductivity type second plug region provided below the second contact section and having a doping concentration higher than that of the contact region is provided. The semiconductor device according to claim 1.

3. The second plug region is provided to extend in the trench extension direction. The semiconductor device according to claim 2.

4. The second plug region is provided discretely in the trench extension direction. The semiconductor device according to claim 2.

5. A second conductivity type first plug region provided below the first contact section and having a doping concentration higher than that of the contact region is provided. The semiconductor device according to claim 1.

6. The first plug region is provided discretely in the trench extension direction. The semiconductor device according to claim 5.

7. The first plug region is provided above the contact region and not above the emitter region. The semiconductor device according to claim 5.

8. A barrier metal section provided on the side surface of the contact hole is provided, the barrier metal section has a Ti layer The semiconductor device according to claim 1.

9. In the transistor portion, a first conductivity type accumulation region provided above the drift region and having a doping concentration higher than that of the drift region is provided. The semiconductor device according to claim 1.

10. The front surface electrode includes an emitter electrode provided above the interlayer insulating film. The semiconductor device according to claim 1.

11. The front surface electrode includes a contact plug portion provided in the contact hole and connecting the emitter electrode and the mesa portion. The semiconductor device according to claim 10.

12. The diode portion has the lifetime adjustment region. The semiconductor device according to claim 1.

13. The transistor portion has the lifetime adjustment region. The semiconductor device according to claim 1.

14. The lifetime adjustment region of the transistor portion is formed by irradiation with a particle beam. The semiconductor device according to claim 13.

15. The lifetime adjustment region is provided so as to extend over the entire transistor portion and the diode portion in the trench arrangement direction. The semiconductor device according to claim 13.

16. The lifetime adjustment region is provided so as to extend from the diode portion to a part of the transistor portion in the trench arrangement direction. The semiconductor device according to claim 13.

17. The doping concentration of the anode region is lower than the doping concentration of the base region. The semiconductor device according to claim 1.

18. The doping concentration of the anode region is the same as the doping concentration of the base region. The semiconductor device according to claim 1.

19. The first contact portion is in contact with the front surface of the mesa portion. The semiconductor device according to claim 1.

20. The first contact portion is disposed below the front surface of the mesa portion. The semiconductor device according to claim 1.

21. A boundary region provided between the transistor portion and the diode portion is provided. The semiconductor device according to claim 1.

22. The lifetime adjustment region is provided so as to extend to the diode portion and the boundary region in the trench arrangement direction. The semiconductor device according to claim 21.

23. The width of the boundary region in the trench arrangement direction is 20 μm or more and 250 μm or less. The semiconductor device according to claim 21.

24. The contact portion of the boundary region is a third contact portion, The third contact portion is disposed above the second contact portion and below the first contact portion. The semiconductor device according to claim 21.

25. The contact portion of the boundary region is the second contact portion. The semiconductor device according to claim 21.

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