Surge protection circuit for a power converter and power converter

Abstract

The application discloses a surge protection circuit of a converter and a power converter, and belongs to the technical field of converters. The surge protection circuit comprises a sampling circuit, an detection circuit, a logic circuit and a protection circuit. The sampling circuit is connected with an AC bus and is configured to obtain a sampling voltage of the AC bus. The detection circuit is connected with the sampling circuit and is configured to generate a first signal based on the sampling voltage. The logic circuit is connected with the detection circuit and is configured to input a second signal and generate a third signal when the polarities represented by the first signal and the second signal are inconsistent. The protection circuit is connected with the logic circuit and the cycle conversion circuit and is configured to perform cycle control on at least one pair of reverse switching tubes in the cycle conversion circuit when the third signal is received. The surge voltage impact can be detected at the first time and the cycle control can be performed, the positive and negative buses on the power grid side are isolated, the short circuit risk is reduced, and the switching tubes are not prone to over-stress damage.

Description

Technical Field

[0001] This application belongs to the field of converter technology, and particularly relates to a surge protection circuit for a converter and a power converter. Background Technology

[0002] In new energy photovoltaic, energy storage, or charging scenarios, high-efficiency conversion circuits are needed to convert the DC power from solar panels into AC power for grid connection, or to bidirectionally convert the DC power from energy storage batteries or automotive power batteries to AC power from the grid. Among various conversion circuit topologies, the isolated single-stage topology using a cycloconverter circuit on the AC side has attracted widespread attention in the industry due to its advantages of fewer circuit components, high conversion efficiency, and input-output electrical isolation. However, when the cycloconverter circuit encounters surge impacts on the grid side, the reverse AC voltage can form a short-circuit loop through the internal switching transistors, causing overstress or even damage to the switching transistors. Summary of the Invention

[0003] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a surge protection circuit and power converter that can detect and block surge voltage impacts at the first moment, isolate the positive and negative buses on the grid side, reduce the risk of short circuits, and prevent the switching transistors from being damaged by overstress.

[0004] In a first aspect, this application provides a surge protection circuit for a converter. The converter includes a frequency conversion circuit, and the output side of the frequency conversion circuit is provided with an AC bus. The surge protection circuit includes:

[0005] A sampling circuit is connected to the AC bus and configured to acquire the sampling voltage of the AC bus.

[0006] The detection circuit is connected to the sampling circuit and configured to generate a first signal based on the sampling voltage, the first signal representing the current polarity state of the AC bus;

[0007] A logic circuit is connected to a detection circuit and configured to receive a second signal, and generate a third signal when the polarity states represented by the first and second signals are inconsistent. The second signal represents the desired polarity state of the AC bus under the drive of the cycle conversion circuit.

[0008] A protection circuit, connected to a logic circuit and a frequency converter circuit, is configured to perform wave blocking control on at least one pair of inverting switches in the frequency converter circuit when a third signal is received.

[0009] According to one embodiment of this application, the detection circuit includes:

[0010] The first comparator has its non-inverting input connected to the sampling circuit to receive the sampling voltage, its inverting input connected to the first reference voltage, and its output used to provide the first signal.

[0011] The first reference voltage is the bias voltage corresponding to the AC bus voltage being zero.

[0012] According to one embodiment of this application, the logic circuit includes:

[0013] An XOR gate is used to connect the first input of a first comparator to the output of a first comparator to receive a first signal, the second input of the XOR gate to receive a second signal, and the output of the XOR gate to provide a third signal.

[0014] According to one embodiment of this application, the first signal includes a first detection signal and a second detection signal. The first detection signal characterizes whether the AC bus is in a current polarity state that is less than the negative half-cycle voltage threshold, and the second detection signal characterizes whether the AC bus is in a current polarity state that is greater than the positive half-cycle voltage threshold.

[0015] The detection circuit includes:

[0016] The second comparator has an inverting input terminal connected to the sampling voltage, an inverting input terminal connected to the second reference voltage, and an output terminal used to provide the first detection signal.

[0017] The third comparator has a sampling voltage connected to its non-inverting input and a third reference voltage connected to its inverting input. Its output is used to provide a second detection signal.

[0018] The second reference voltage is the bias voltage corresponding to the condition that the voltage of the AC bus is less than zero, and the third reference voltage is the bias voltage corresponding to the condition that the voltage of the AC bus is greater than zero.

[0019] According to one embodiment of this application, the second signal includes a first expected signal and a second expected signal, wherein the first expected signal characterizes the current expected polarity state of whether the AC bus is greater than zero, and the second expected signal characterizes the current expected polarity state of whether the AC bus is less than zero.

[0020] The logic circuit includes:

[0021] The first AND gate has a first detection signal connected to its first input terminal and a first desired signal connected to its second input terminal.

[0022] The second AND gate has a first input terminal connected to a second detection signal and a second input terminal connected to a second desired signal.

[0023] The OR gate has its first input connected to the output of the first AND gate, and its second input connected to the output of the second AND gate. The output of the OR gate is used to provide a third signal.

[0024] According to one embodiment of this application, the converter includes a driving unit connected to a frequency conversion circuit and a logic circuit, and configured to drive the frequency conversion circuit to operate and form a protection circuit.

[0025] According to one embodiment of this application, the converter includes a main control chip connected to a sampling circuit, a driving unit, and a logic circuit, and is configured to control the driving unit based on the sampled voltage to drive the Hz conversion circuit and generate a second signal based on the current control strategy.

[0026] According to one embodiment of this application, the converter includes a transformer connected to a frequency conversion circuit and has a first coupling node and a second coupling node.

[0027] The protection circuit is also configured to perform wave blocking control on the switching transistors in the frequency conversion circuit, except for those connected between the first coupling node and the second coupling node, when a third signal is received.

[0028] According to one embodiment of this application, the frequency conversion circuit includes a first switch, a second switch, a third switch, and a fourth switch connected in series. One end of the first switch and one end of the fourth switch are connected to an AC bus. A first coupling node is located between the first switch and the second switch, and a second coupling node is located between the third switch and the fourth switch.

[0029] The protection circuit is also configured to perform wave blocking control on the first and fourth switching transistors when a third signal is received.

[0030] Secondly, this application provides a power converter, which includes a transformer, a primary-side conversion circuit connected to the primary side of the transformer, a secondary-side conversion circuit connected to the secondary side of the transformer, a main control chip, a drive unit, and a surge protection circuit according to the aforementioned. The main control chip is connected to the primary-side conversion circuit, the secondary-side conversion circuit, the drive unit, and the surge protection circuit, respectively. The secondary-side conversion circuit includes a peripheral conversion circuit.

[0031] According to the surge protection circuit and power converter of the present application, surge detection and protection are realized through analog and logic circuits. Surge voltage impact can be detected and blocked at the first time. When blocking, the positive and negative buses on the grid side can be isolated by turning off at least one pair of reverse switching transistors, reducing the risk of short circuit and making the switching transistors less prone to overstress damage.

[0032] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0033] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0034] Figure 1 This is a schematic diagram of the power converter provided in the embodiments of this application;

[0035] Figure 2 This is a schematic diagram of the operating mode of the frequency converter provided in the embodiments of this application;

[0036] Figure 3 This is one of the structural schematic diagrams of the surge protection circuit provided in the embodiments of this application;

[0037] Figure 4 This is a waveform diagram of the switching transistor of the surge protection circuit provided in the embodiment of this application;

[0038] Figure 5 This is a second schematic diagram of the surge protection circuit provided in the embodiments of this application;

[0039] Figure 6 This is one of the signal waveform diagrams of the surge protection circuit provided in the embodiments of this application;

[0040] Figure 7 This is the third schematic diagram of the surge protection circuit provided in the embodiments of this application;

[0041] Figure 8 This is the second signal waveform diagram of the surge protection circuit provided in the embodiments of this application.

[0042] Figure label:

[0043] Primary-side conversion circuit 100, sampling circuit 10, detection circuit 20, logic circuit 30, protection circuit 40, main control chip 50, drive unit 60, first to fourth switching transistors S1~S4, transformer T, resonant capacitor Lr, resonant inductor Cr, first to fourth resistors R1~R4, amplifier Amp, first to third comparators Cmp1~Cmp3. Detailed Implementation

[0044] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0045] In the following description, a "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by an electrical or electromagnetic link. When an element or circuit is said to be "coupled to" or "connected to" another element, or when an element / circuit is said to be "coupled at" or "connected at" two nodes, it can be directly coupled to or connected to the other element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between them.

[0046] In the description, the terms "first," "second," etc., are used to distinguish similar objects, not to describe a specific order or sequence. It should be understood that such numerical descriptors can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class, not limited in number; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0047] Furthermore, the use of terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicates that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0048] During operation, the switching transistors within the frequency converter need to switch between high-frequency and low-frequency roles based on the polarity of the grid voltage. Specifically, during the half-cycle when the grid voltage is positive, some transistors remain on as low-frequency transistors, while others act as high-frequency transistors, switching on and off at high frequencies. During the half-cycle when the grid voltage is negative, the aforementioned low-frequency transistors switch to high-frequency transistors for high-frequency switching, and vice versa. The high-frequency transistors control the changes in inductor current and the instantaneous value of the grid-connected current; the low-frequency transistors ensure the freewheeling path of the inductor current within the dead zone of the high-frequency transistors and implement soft switching.

[0049] However, when the converter encounters a surge on the grid side, the AC voltage at the output of the aforementioned frequency converter may undergo a sudden change in polarity. Although the duration may only be tens of microseconds, if the converter fails to detect the abnormality in time and adjust the switching transistor timing, the reverse AC voltage will form a short circuit loop through the body diode of the high-frequency transistor and the turned-on low-frequency transistor, causing the switching transistor to be overstressed or even damaged.

[0050] In related technologies, the surge absorption capability of the varistor in the AC side of the converter is typically increased to bypass surge energy and reduce its impact on the converter bridge arm. Alternatively, the inductance of the differential-mode inductor in the EMI circuit is increased to increase its equivalent impedance and distribute more surge voltage, thus reducing the voltage surge amplitude of the converter bridge arm. However, this significantly increases the component size on the AC side of the converter, and the cost also increases accordingly.

[0051] This application proposes a surge protection circuit and power converter for a converter. Surge detection and protection are achieved through analog and logic circuits. It can detect surge voltage impacts and block them at the first time. During the blocking, the positive and negative buses on the grid side can be isolated by turning off at least one pair of reverse switching transistors, reducing the risk of short circuits. The switching transistors are also less prone to overstress damage.

[0052] Reference Figure 1 , Figure 1 The structure of a power converter is shown. The power converter includes a primary-side conversion circuit 100, a transformer T, and a frequency converter. The primary-side conversion circuit 100 can be a full-bridge or half-bridge. The frequency converter includes a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4 connected in series. The common-source connection node between the first switch S1 and the second switch S2 is connected through a resonant capacitor L. r and resonant inductance C r The common-source connection node between the third switch S3 and the fourth switch S4 is connected to the second terminal of the secondary winding of transformer T. The output side of the frequency converter also includes an output capacitor C0 and a differential-mode inductor L. f And the first varistor VR1 and the second varistor VR2.

[0053] The topology of the frequency converter can also take other forms, and the surge protection circuit proposed later can also be applied. Other frequency converter topologies will not be elaborated here.

[0054] Reference Figure 2 , Figure 2The operating mode of a frequency converter is illustrated. During the positive half-cycle of the grid voltage, the second switch S2 and the fourth switch S4 are always on as power frequency transistors, while the first switch S1 and the third switch S3 are on and off at high frequencies. During the negative half-cycle of the grid voltage, the first switch S1 and the third switch S3 are always on as power frequency transistors, while the second switch S2 and the fourth switch S4 are on and off at high frequencies.

[0055] During surge testing, there may be certain situations that cause u g Voltage polarity abrupt changes, such as a 90° "-" differential-mode surge and a 270° "+" differential-mode surge in the mains phase. Although the output side of the frequency converter has a differential-mode inductance L... f Along with varistors VR1 and VR2, they can perform voltage division and bypass absorption during surge impacts, reducing u g The voltage fluctuation amplitude is small, but the surge energy is relatively large, u g The voltage may still change polarity abruptly, eventually forming a short circuit loop through the body diode of the power frequency transistor and the high frequency transistor, causing damage to the switching transistor.

[0056] Reference Figure 3 , Figure 3 The structure of a surge protection circuit for a converter is shown. One embodiment of this application provides a surge protection circuit for a converter. This surge protection circuit is applied to... Figure 1 Taking the power converter shown as an example, in this embodiment, the surge protection circuit includes a sampling circuit 10, a detection circuit 20, a logic circuit 30, and a protection circuit 40. The sampling circuit 10 is connected to the AC bus and configured to acquire the sampling voltage of the AC bus. The detection circuit 20 is connected to the sampling circuit 10 and configured to generate a first signal based on the sampling voltage. The first signal represents the current polarity state of the AC bus. The logic circuit 30 is connected to the detection circuit 20 and configured to receive a second signal. When the polarity states represented by the first signal and the second signal are inconsistent, a third signal is generated. The second signal represents the desired polarity state of the AC bus under the drive of the frequency conversion circuit. The protection circuit 40 is connected to the logic circuit 30 and the frequency conversion circuit and configured to perform wave blocking control on at least one pair of reverse switching transistors in the frequency conversion circuit when the third signal is received.

[0057] The AC bus is located on the output side of the frequency converter circuit. One side of the AC bus is connected to one end of the first switch S1, and the other side is connected to one end of the fourth switch S4. As an example, the first sampling node of the sampling circuit 10 is connected to one end of the first switch S1, and the second sampling node is connected to one end of the fourth switch S4 to obtain the sampled voltage of the AC bus. This sampled voltage can characterize the actual bus voltage of the AC bus.

[0058] As an example, when one end of the first switch S1 is connected to a positive bus and one end of the fourth switch S4 is connected to a negative bus, the polarity of the AC bus is positive; when one end of the first switch S1 is connected to a positive bus and one end of the fourth switch S4 is connected to a negative bus, the polarity of the AC bus is negative.

[0059] The detection circuit 20 can determine the current polarity state of the AC bus based on the actual bus voltage. In the example above, if the detected actual bus voltage is positive, the current polarity state of the AC bus is determined to be positive; if the detected actual bus voltage is negative, the current polarity state of the AC bus is determined to be negative.

[0060] In some embodiments, the detection circuit 20 can also simultaneously determine the voltage threshold and polarity. In the example above, if the actual bus voltage is detected to be positive and greater than the threshold, the current polarity of the AC bus is determined to be positive; if the actual bus voltage is detected to be negative and less than the threshold, the current polarity of the AC bus is determined to be negative. This avoids misjudgments near the zero-crossing point of the grid voltage.

[0061] As an example, when driven by a frequency converter circuit, the desired polarity of the AC bus is positive when the output voltage is in the positive half-cycle; when driven by a frequency converter circuit, the desired polarity of the AC bus is negative when the output voltage is in the negative half-cycle.

[0062] Logic circuit 30 is used to determine whether the polarity of the AC bus has reversed. Combined with... Figure 2 It can be seen that when the current polarity state of the AC bus is inconsistent with the desired polarity state, the polarity reversal of the power grid is determined; when the current polarity state of the AC bus is consistent with the desired polarity state, the polarity reversal of the power grid is determined.

[0063] When the protection circuit 40 receives the third signal, it indicates that the AC bus has experienced polarity reversal and poses a short-circuit risk. At this time, it can perform wave blocking control on at least one pair of reverse switching transistors in the frequency conversion circuit to isolate the AC bus. The at least one pair of reverse switching transistors under wave blocking control can include at least one of the power frequency transistors and at least one of the high frequency transistors.

[0064] In some embodiments, the transformer and the frequency conversion circuit have a first coupling node and a second coupling node; the protection circuit 40 is further configured to perform wave blocking control on the switching transistors in the frequency conversion circuit other than the switching transistors connected between the first coupling node and the second coupling node when a third signal is received.

[0065] In this embodiment, the protection circuit 40 shuts off all switching transistors except those between the first and second coupling nodes, while maintaining the switching transistors between the first and second coupling nodes in operation. This preserves a freewheeling path for the inductance on the secondary side of transformer T.

[0066] by Figure 1 Taking the circuit structure shown as an example, the first coupling node is located between the first switch S1 and the second switch S2, and the second coupling node is located between the third switch S3 and the fourth switch S4. When the protection circuit 40 receives the third signal, it performs wave blocking control on the first switch S1 and the fourth switch S4.

[0067] Reference Figure 4 , Figure 4 A waveform diagram of a switching transistor is shown. As an example, after a surge occurs, the output of the logic circuit's blocking signal changes to a high level (i.e., the third signal) and remains high for a short period of time. The protection circuit 400 outputs a low-level signal to the first switching transistor S1 and the fourth switching transistor S4, turning off the first switching transistor S1 and the fourth switching transistor S4; at the same time, it outputs a high-level signal to the second switching transistor S2 and the third switching transistor S3, turning them on to form an internal freewheeling loop.

[0068] Reference Figure 5 , Figure 5 The structure of a surge protection circuit for a converter is shown. In some embodiments, the detection circuit 20 includes a first comparator Cmp1, the non-inverting input of the first comparator Cmp1 is connected to the sampling circuit 10 to receive a sampling voltage, the inverting input of the first comparator Cmp1 is connected to a first reference voltage, and the output of the first comparator Cmp1 is used to provide a first signal; wherein, the first reference voltage is the bias voltage corresponding to the AC bus voltage being zero.

[0069] In this embodiment, the sampling circuit 10 is a differential circuit, which includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and an amplifier Amp. The non-inverting input terminal of the amplifier Amp is connected to one end of the first switching transistor S1 through the first resistor R1, and the non-inverting input terminal of the amplifier Amp is also connected to the bias voltage V through the third resistor R3. offset1 The inverting input of amplifier Amp is connected to one end of the fourth switch S4 through the second resistor R2, and feedback is formed between the inverting input of amplifier Amp and the output of amplifier Amp through the fourth resistor R4.

[0070] Sampling circuit 10 samples the output voltage u of the frequency converter. g This refers to the mains voltage, and it outputs a sampling signal u1. The sampling signal u1 is sent to the first comparator Cmp1. The first comparator Cmp1 compares u1 with V.offset1 The hardware signal HW_GRID_POL (i.e., the first signal) is used to obtain the polarity of the mains voltage. u1 is greater than or equal to V. offset1 When HW_GRID_POL is high, it indicates that the current polarity of the mains voltage is positive; u1 is less than V. offset1 When HW_GRID_POL is low, it indicates that the current polarity of the mains voltage is negative.

[0071] In this embodiment, the logic circuit 30 includes an XOR gate. The first input of the XOR gate is connected to the output of the first comparator Cmp1 to receive a first signal. The second input of the XOR gate is connected to a second signal. The output of the XOR gate is used to provide a third signal.

[0072] Based on the principle of the XOR gate, the same polarity state is represented by the same level state in both the second and third signals. For example, both the second and third signals use a high level to represent positive polarity and a low level to represent negative polarity. Based on the above example, when the desired polarity state of the AC bus is positive, the second signal is high; when the desired polarity state of the AC bus is negative, the second signal is low.

[0073] The XOR gate outputs a high level when the levels of the first and second signals are different, indicating that the current polarity of the AC bus is inconsistent with the desired polarity, and thus the polarity of the power grid is determined to be reversed. When the levels of the first and second signals are the same, it outputs a high level, indicating that the current polarity of the AC bus is consistent with the desired polarity, and thus the polarity of the power grid is determined not to be reversed.

[0074] As an example, the converter also includes a main control chip 50 and a drive unit 60. The main control chip 50 is connected to the sampling circuit 10, the drive unit 60, and the logic circuit 30. The drive unit 60 is connected to the frequency conversion circuit and the logic circuit 30. The main control chip 50 and the drive unit 60 are the original circuit units of the converter.

[0075] In this example, the second signal is the firmware signal FW_GRID_POL provided by the main control chip 50. In the converter control, the main control chip 50 receives the sampled voltage u1 from the sampling circuit 10 and sends control signals to the drive unit 60 according to the established control strategy to control the drive unit 60. The main control chip 50 can generate the firmware signal FW_GRID_POL based on the current control strategy.

[0076] The drive unit 60 sends corresponding drive signals to the frequency converter circuit according to the control signal to drive the frequency converter circuit. The drive unit 60 can also act as a protection circuit 40, performing wave blocking control on at least one pair of inverting switches in the frequency converter circuit when it receives a high-level signal from the XOR gate output. Therefore, by utilizing the original circuit structure of the converter, hardware costs can be reduced.

[0077] Reference Figure 6 , Figure 6 A signal waveform diagram is shown. As can be seen from the diagram, during the positive half-cycle of the mains voltage, if polarity reversal occurs, the signal HW_GRID_POL is low and the signal FW_GRID_POL is high; during the negative half-cycle of the mains voltage, if polarity reversal occurs, the signal HW_GRID_POL is high and the signal FW_GRID_POL is low. In both cases, the XOR gate will output a high level. When the driver unit 60 receives the high-level signal output by the XOR gate, it performs waveform blocking control.

[0078] Reference Figure 7 , Figure 7 The structure of a surge protection circuit for a converter is shown. In some embodiments, the first signal includes a first detection signal and a second detection signal. The first detection signal characterizes whether the AC bus voltage is below the current polarity state of the negative half-cycle threshold, and the second detection signal characterizes whether the AC bus voltage is above the current polarity state of the positive half-cycle threshold. The detection circuit 20 includes a second comparator Cmp2 and a third comparator Cmp3. The inverting input of the second comparator Cmp2 is connected to a sampling voltage, and the non-inverting input of the second comparator Cmp2 is connected to a second reference voltage. The output of the second comparator Cmp2 is used to provide the first detection signal. The non-inverting input of the third comparator Cmp3 is connected to the sampling voltage, and the inverting input of the third comparator Cmp3 is connected to a third reference voltage. The output of the third comparator Cmp3 is used to provide the second detection signal. The second reference voltage is less than the bias voltage corresponding to the zero voltage of the AC bus, and the third reference voltage is greater than the bias voltage corresponding to the zero voltage of the AC bus.

[0079] The sampling circuit 10 can also be a differential circuit, which includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and an amplifier Amp. Specific details can be found in the aforementioned embodiments, and will not be repeated here.

[0080] In this embodiment, the reference voltages connected to the second comparator Cmp2 and the third comparator Cmp3 are different, V offset1 The bias voltage corresponding to the AC bus voltage being zero is given by the second reference voltage, which is denoted as V. offset2 The third reference voltage is represented as V. offset3 Voffset2 You can subtract the sampling voltage corresponding to the threshold from the grid voltage, V offset3 You can add the sampling voltage corresponding to the threshold to the grid voltage.

[0081] The second comparator Cmp2 is used when the actual voltage of the power grid is negative and less than V. offset2 At that time, the HW_GRID_NEG signal (i.e., the first detection signal) is high, and the actual voltage of the third comparator Cmp3 on the power grid is positive and greater than V. offset3 At this time, the HW_GRID_POS (i.e., the first detection signal) signal is high. Therefore, the detection circuit 20 uses two comparators to judge the sampling signal u1 output by the amplifier Amp, forming a detection hysteresis window to prevent accidental triggering of the blocking wave at the normal zero crossing point of the power grid.

[0082] As an example, V offset2 and V offset3 About V offset1 Symmetry, i.e., V offset1 =( V offset2 + V offset3 The value is 1 / 2, which makes the detection threshold voltage of the hysteresis window symmetrical at both ends of the voltage zero point, such as -10V and +10V. If the AC voltage is sampled and converted into an ADC voltage of 0~3.3V, assuming Voffset1 is 1.65V, then Voffset2 can be 1.60V, which corresponds to the mains voltage minus the 10V threshold; Voffset3 can be 1.70V, which corresponds to the mains voltage plus the 10V threshold.

[0083] In some embodiments, the second signal also includes a first expected signal and a second expected signal. The first expected signal represents the current expected polarity state of whether the AC bus is greater than zero, and the second expected signal represents the current expected polarity state of whether the AC bus is less than zero. The logic circuit 30 includes a first AND gate AND1, a second AND gate AND2, and an OR gate OR. The first input terminal of the first AND gate AND1 is connected to the first detection signal, and the second input terminal of the first AND gate AND1 is connected to the first expected signal. The first input terminal of the second AND gate AND2 is connected to the second detection signal, and the second input terminal of the second AND gate AND2 is connected to the second expected signal. The first input terminal of the OR gate OR is connected to the output terminal of the first AND gate AND1, the second input terminal of the OR gate OR is connected to the output terminal of the second AND gate AND2, and the output terminal of the OR gate OR is used to provide a third signal.

[0084] When the current desired polarity of the AC bus is positive, the first desired signal is high and the second desired signal is low. When the current desired polarity of the AC bus is negative, the first desired signal is low and the second desired signal is high. Therefore, when the grid voltage reverses polarity during the positive half-cycle, the first AND gate AND1 outputs a high level and the second AND gate AND2 outputs a low level; when the grid voltage reverses polarity during the positive half-cycle, the first AND gate AND1 outputs a low level and the second AND gate AND2 outputs a high level. In both cases, the OR gate outputs a high level.

[0085] In this embodiment, the converter may also include a main control chip 50 and a drive unit 60. The main control chip 50 can generate firmware signals FW_GRID_POS and FW_GRID_NEG based on the current control strategy. The drive unit 60 can act as a protection circuit 40, which performs wave blocking control on at least one pair of inverting switches in the frequency conversion circuit when it receives a high-level signal from the OR gate output. By utilizing the original circuit structure of the converter, hardware costs can be reduced.

[0086] Reference Figure 8 , Figure 8 A signal waveform diagram is shown. As can be seen from the diagram, during the positive half-cycle of the mains voltage, if polarity reversal occurs, signals HW_GRID_POS are low, HW_GRID_NEG are high, FW_GRID_POS is high, and FW_GRID_NEG is low. The first AND gate AND1 outputs a high level, and the second AND gate AND outputs a low level. During the negative half-cycle of the mains voltage, if polarity reversal occurs, signals HW_GRID_POS are high, HW_GRID_NEG are low, FW_GRID_POS is low, and FW_GRID_NEG is high. The first AND gate AND1 outputs a low level, and the second AND gate AND outputs a high level. In both cases, the OR gate will output a high level. When the drive unit 60 receives the high-level signal output by the OR gate, it performs waveform blocking control.

[0087] One embodiment of this application also provides a power converter, which includes a transformer, a primary-side conversion circuit 100 connected to the primary side of the transformer, a secondary-side conversion circuit connected to the secondary side of the transformer, a main control chip 50, a drive unit 60, and a surge protection circuit according to the aforementioned. The main control chip 50 is connected to the primary-side conversion circuit 100, the secondary-side conversion circuit, the drive unit 60, and the surge protection circuit, respectively. The secondary-side conversion circuit includes a peripheral conversion circuit.

[0088] The specific structure and principle of the surge protection circuit can be referred to in the aforementioned embodiments, which also have corresponding technical effects. The power converter realizes surge detection and protection through analog and logic circuits. It can detect surge voltage impacts and block them at the first time. When blocking, the positive and negative buses on the grid side can be isolated by turning off at least one pair of reverse switching transistors, reducing the risk of short circuits, and the switching transistors are not easily damaged by overstress.

[0089] In this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0090] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A surge protection circuit for a converter, characterized in that, The converter includes a frequency conversion circuit, and the output side of the frequency conversion circuit is provided with an AC bus. The surge protection circuit includes: A sampling circuit is connected to the AC bus and configured to acquire the sampling voltage of the AC bus; A detection circuit is connected to the sampling circuit and configured to generate a first signal based on the sampling voltage, the first signal representing the current polarity state of the AC bus. A logic circuit, connected to the detection circuit, is configured to receive a second signal and generate a third signal when the polarity states represented by the first signal and the second signal are inconsistent, wherein the second signal represents the desired polarity state of the AC bus under the drive of the cycle conversion circuit. A protection circuit, connected to the logic circuit and the frequency conversion circuit, is configured to perform wave blocking control on at least one pair of inverting switches in the frequency conversion circuit when the third signal is received. Wherein, the first signal and the second signal are both logic signals, and the first signal and the second signal are both based on logic level to represent the corresponding polarity state; The detection circuit is configured to compare the sampled voltage and the reference voltage, and generate the first signal based on the comparison result. The reference voltage is determined based on the bias voltage corresponding to when the voltage of the AC bus is zero. The logic circuit is configured to compare the actual logic levels of the first signal and the second signal, and generate a third signal when the polarity states corresponding to the actual logic levels are inconsistent.

2. The surge protection circuit according to claim 1, characterized in that, The detection circuit includes: A first comparator has its non-inverting input connected to the sampling circuit to receive the sampling voltage, its inverting input connected to a first reference voltage, and its output used to provide the first signal. Wherein, the first reference voltage is the bias voltage corresponding to the AC bus voltage being zero.

3. The surge protection circuit according to claim 2, characterized in that, The logic circuit includes: An XOR gate is used, wherein the first input of the XOR gate is connected to the output of the first comparator to receive the first signal, the second input of the XOR gate is connected to the second signal, and the output of the XOR gate is used to provide the third signal.

4. The surge protection circuit according to claim 1, characterized in that, The first signal includes a first detection signal and a second detection signal. The first detection signal indicates whether the AC bus is in a current polarity state that is less than the negative half-cycle voltage threshold, and the second detection signal indicates whether the AC bus is in a current polarity state that is greater than the positive half-cycle voltage threshold. The detection circuit includes: The second comparator has its inverting input connected to the sampling voltage, its non-inverting input connected to a second reference voltage, and its output used to provide the first detection signal. A third comparator is configured such that its non-inverting input is connected to the sampling voltage, its inverting input is connected to a third reference voltage, and its output is used to provide the second detection signal. Wherein, the second reference voltage is less than the bias voltage corresponding to the zero voltage of the AC bus, and the third reference voltage is greater than the bias voltage corresponding to the zero voltage of the AC bus.

5. The surge protection circuit according to claim 4, characterized in that, The second signal includes a first expected signal and a second expected signal. The first expected signal represents the current expected polarity state of whether the AC bus is greater than zero, and the second expected signal represents the current expected polarity state of whether the AC bus is less than zero. The logic circuit includes: A first AND gate, wherein the first input terminal of the first AND gate is connected to the first detection signal, and the second input terminal of the first AND gate is connected to the first desired signal; The second AND gate has its first input terminal connected to the second detection signal and its second input terminal connected to the second desired signal. The OR gate has its first input connected to the output of the first AND gate, its second input connected to the output of the second AND gate, and its output used to provide the third signal.

6. The surge protection circuit according to any one of claims 1-5, characterized in that, The converter includes a driving unit connected to the frequency conversion circuit and the logic circuit, and is configured to drive the frequency conversion circuit to work and constitute the protection circuit.

7. The surge protection circuit according to claim 6, characterized in that, The converter includes a main control chip, which is connected to the sampling circuit, the driving unit, and the logic circuit. The main control chip is configured to control the driving unit based on the sampled voltage to drive the cycle conversion circuit and generate the second signal based on the current control strategy.

8. The surge protection circuit according to any one of claims 1-5, characterized in that, The converter includes a transformer, which is connected to the frequency conversion circuit and has a first coupling node and a second coupling node. The protection circuit is further configured to perform wave blocking control on the switching transistors in the frequency conversion circuit, excluding the switching transistors connected between the first coupling node and the second coupling node, when the third signal is received.

9. The surge protection circuit according to claim 8, characterized in that, The frequency conversion circuit includes a first switch, a second switch, a third switch, and a fourth switch connected in series. One end of the first switch and one end of the fourth switch are connected to the AC bus. The first coupling node is located between the first switch and the second switch, and the second coupling node is located between the third switch and the fourth switch. The protection circuit is further configured to perform wave blocking control on the first switch and the fourth switch when the third signal is received.

10. A power converter, characterized in that, The power converter includes a transformer, a primary-side conversion circuit connected to the primary side of the transformer, a secondary-side conversion circuit connected to the secondary side of the transformer, a main control chip, a drive unit, and a surge protection circuit according to any one of claims 1-9. The main control chip is connected to the primary-side conversion circuit, the secondary-side conversion circuit, the drive unit, and the surge protection circuit, respectively. The secondary-side conversion circuit includes a peripheral conversion circuit.

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