Buck converter, method of operating same, and electronic device including same

Abstract

The invention provides a buck converter, an operation method thereof and an electronic device. The buck converter includes: a power switching circuit that alternately delivers an input voltage and a ground voltage to an output terminal in response to a pulse switching signal; an LC filter having one end connected to the output terminal; a sensing voltage generator that generates a voltage corresponding to a change in inductor current between the output terminal and the second end of the inductor; and an overshoot detector that generates an off signal in response to the voltage and the first reference voltage.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application Nos. 10 - 2024 - 0009447, filed on January 22, 2024, and 10 - 2024 - 0034867, filed on March 13, 2024, with the Korean Intellectual Property Office (KIPO), the disclosures of which are hereby incorporated by reference in their entireties. Technical field

[0003] Example embodiments generally relate to voltage converters, and more particularly, to a buck converter configured to generate an accurate and stable output voltage, a method of operating the buck converter, and an electronic device including the buck converter. Background art

[0004] An electronic device may include various semiconductor devices, and each of the semiconductor devices may require an appropriate direct current (DC) voltage. In addition, the electronic device may include a semiconductor device, referred to as a power management integrated circuit (PMIC), for generating the DC voltage required for each semiconductor device. The PMIC may include at least one DC - DC converter that generates an output DC voltage required for at least one semiconductor device based on an input DC voltage. A buck converter (e.g., a switching regulator) is a type of DC - DC converter that can generate an output voltage having a voltage level lower than the voltage level of the input voltage. Research has been conducted to improve the accuracy of the output voltage regardless of the load current and to improve the transient response characteristics when the load current changes. Summary of the invention

[0005] At least one example embodiment of the present disclosure provides a buck converter capable of reducing or minimizing overshoot on an output voltage when a load current changes from a relatively large load current to a relatively small load current.

[0006] At least one example embodiment of the present disclosure provides a method of operating a buck converter.

[0007] At least one example embodiment of the present disclosure provides an electronic device including a buck converter.

[0008] According to an exemplary embodiment, a buck converter includes a power switching circuit, an inductor, a sense voltage generator, and an overshoot detector. The power switching circuit includes a high-side (HS) switch and a low-side (LS) switch, and in response to a pulse switching signal, alternately transfers an input voltage and a ground voltage to an output terminal through the HS switch and the LS switch. The inductor has a first end connected to the output terminal and a second end connected to a load capacitor, and generates an output voltage at the second end. The sense voltage generator generates a first voltage and a second voltage, includes a first resistor and a first capacitor connected in series between the output terminal and the second end of the inductor, and includes a second resistor and a second capacitor connected in series between a first common node and the second end of the inductor. The first voltage is a voltage at the first common node between the first resistor and the first capacitor. The second voltage is a voltage at the second common node between the second resistor and the second capacitor. The overshoot detector generates a switching cut-off signal in response to a first reference voltage, the first voltage, and the second voltage. The overshoot detector is configured to generate the first reference voltage based on replicating a current flowing through the first common node during half of a conduction time interval of the HS switch. The power switching circuit is further configured to, based on the switching cut-off signal being in a first state, the HS switch and the LS switch alternately conduct in response to the pulse switching signal, and based on the switching cut-off signal being in a second state, the LS switch is cut off.

[0009] According to an exemplary embodiment, in a method of operating a buck converter, a reference voltage corresponding to half of a change amount of an inductor current in a steady state is generated. A first voltage corresponding to a change amount of the inductor current caused by a change in a load current is generated. A first state in which the first voltage is higher than the reference voltage is sensed. The low-side (LS) switch is cut off in response to the first state, regardless of the pulse switching signal. The LS switch is included in the power switching circuit, and the power switching circuit is included in the buck converter.

[0010] According to an exemplary embodiment, an electronic device includes a first semiconductor chip, an inductor, a load capacitor, and a second semiconductor chip. The first semiconductor chip includes a power switching circuit that includes a high-side (HS) switch and a low-side (LS) switch. The inductor and the load capacitor are connected to an output terminal of the power switching circuit and generate an output voltage. The second semiconductor chip receives the output voltage as a power supply voltage and consumes a load current. The first semiconductor chip is configured to generate a reference voltage corresponding to a change amount of an inductor current flowing through the inductor during half of a conduction time interval of the HS switch, generate a first voltage corresponding to a change amount of the inductor current caused by a change in the load current, and adjust a slope of a decrease in the inductor current based on the reference voltage and the first voltage.

[0011] In a buck converter according to an exemplary embodiment, a stable output voltage can be generated regardless of the load current. For example, even when the operating state changes from consuming a relatively large load current to consuming a relatively small load current, the overshoot of the output voltage can be minimized or reduced quickly and stably. Therefore, the overall performance can be improved or enhanced. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The illustrative, non-limiting exemplary embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

[0013] Figure 1 is a diagram for describing the overshoot of the output voltage of a DC-DC converter.

[0014] Figure 2 is a block diagram showing a buck converter according to an exemplary embodiment.

[0015] Figure 3 is a diagram showing Figure 2 an example of a power switching circuit, an LC filter, a sense voltage generator, an overshoot detector, and a driver circuit in

[0016] Figure 4 is a diagram showing Figure 2 an example of a pulse switching signal generator in

[0017] Figure 5 is a diagram showing Figure 4 an example of signals associated with the pulse switching signal generator of

[0018] Figure 6 is a diagram showing Figure 3 an example of signals associated with the overshoot detector in

[0019] Figure 7 is a diagram showing an example of a parasitic diode in a MOSFET included in an LS switch.

[0020] Figure 8A is a timing diagram showing the operation of a buck converter according to an exemplary embodiment due to a change in the load current.

[0021] Figure 8B is Figure 8A an enlarged view of a region where the absolute value of the slope of the inductor current decrease increases in the case of overshoot in

[0022] Figure 9 is a timing diagram showing the overshoot of a conventional buck converter and the overshoot of a buck converter according to an exemplary embodiment.

[0023] Figure 10 is Figure 2Circuit diagram of an example of the sensing voltage generator in

[0024] Figure 11 It is a flowchart showing a method of operating a buck converter according to an example embodiment.

[0025] Figure 12 It is a block diagram showing an electronic device including a buck converter according to an example embodiment. Detailed Description

[0026] Various example embodiments will be described more fully with reference to the accompanying drawings in which embodiments are shown. However, the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In the present application, like reference numerals denote like elements.

[0027] Figure 1 It is a diagram for describing the overshoot of the output voltage of a DC-DC converter.

[0028] Referring to Figure 1 , in order to supply a load current I to a load device (not shown) LOAD , the DC-DC converter 1 can generate an output voltage Vout to the load capacitor C by flowing an inductor current I L through the inductor L in response to a pulse switching signal PWM. For example, the DC-DC converter 1 can be a buck converter. The DC-DC converter 1 can repeatedly increase and decrease the inductor current I L in response to a pulse switching signal PWM to generate an output voltage Vout having a constant (or fixed) voltage level. L

[0029] In a transition state where the load current I of the load device LOAD changes from a relatively strong (or large) load current to a relatively weak (or small) load current, the inductor current I L may become greater than the load current I LOAD , and then an overshoot may occur, resulting in an increase in the output voltage Vout. In Figure 1 , the current ΔI in the shaded area can accumulate in the load capacitor C L , and a change amount ΔVout of the overshoot output voltage Vout may appear on the output voltage Vout. The change amount ΔVout of the output voltage Vout (for example, the overshoot on the output voltage Vout) can be represented by Equation 1.

[0030] [Equation 1]

[0031]

[0032] In Equation 1, ΔVout represents the change in the output voltage Vout, and ΔI represents the difference between the load current I LOAD and the inductor current I L , and C L represents the capacitance of the load capacitor C L . Since the value C is determined during the manufacturing process of the DC-DC converter 1 L , the value ΔI should be reduced to minimize (or reduce) the overshoot on the output voltage Vout (e.g., to reduce the value ΔVout).

[0033] Figure 2 is a block diagram showing a buck converter according to an exemplary embodiment.

[0034] Referring to Figure 2 , the buck converter 100 may include a semiconductor chip 101 and an LC filter (or low-pass filter) 20. The semiconductor chip 101 may include an output terminal TO, a feedback terminal TF, a power switching circuit 10, a sense voltage generator 30, a pulse switching signal generator 40, an overshoot detector 50, and a driver circuit 60. For example, the semiconductor chip 101 and the LC filter 20 may be mounted together on a printed circuit board (PCB) (not shown).

[0035] The buck converter 100 may be an example of a DC-DC converter according to an exemplary embodiment. In other words, a DC-DC converter according to an exemplary embodiment may be or may include a buck converter. The buck converter 100 may be electrically connected to a load device (not shown) that consumes the load current I LOAD , and may supply the load current I LOAD to the load device. For example, the buck converter 100 may generate an output voltage Vout by reducing the input voltage Vin using the semiconductor chip 101 and the LC filter 20, and the voltage level of the output voltage Vout may be lower than the voltage level of the input voltage Vin.

[0036] The power switching circuit 10 may include a high-side (HS) switch and a low-side (LS) switch, and may alternately transfer (or send) the input voltage Vin and the ground voltage Vss to the output terminal TO in response to a pulse switching signal PWM. For example, both the HS switch and the LS switch may be implemented using metal-oxide semiconductor field effect transistors (MOSFETs). Although Figure 2 not shown in, the semiconductor chip 101 may also include input terminals for receiving the input voltage Vin and the ground voltage Vss.

[0037] The LC filter 20 may include an inductor having a first end (or one end) connected to the output terminal TO and a second end connected to the load capacitor C Lan inductor L at the second end (or the other end), and an output voltage Vout can be generated at the second end of the inductor L.

[0038] The sense voltage generator 30 can generate a first voltage Va obtained by reflecting the output voltage Vout and the inductor current I flowing through the inductor L L and can generate a second voltage Vb obtained by reflecting only the direct current (DC) component of the output voltage Vout and the inductor current I. For example, the inductor current I L can include a DC component corresponding to the load current I L and an alternating current (AC) component corresponding to the switching operation of the power switching circuit 10. For example, the sense voltage generator 30 can include an RC filter including a resistor and a capacitor, and can generate the first voltage Va and the second voltage Vb using the RC filter. The detailed configuration of the sense voltage generator 30 will be described with reference to LOAD Figure 3 the detailed configuration of the sense voltage generator 30.

[0039] The pulse switching signal generator 40 can generate a pulse switching signal PWM in response to the output voltage Vout, the first voltage Va, the second voltage Vb, and the first reference voltage Vref1. The pulse switching signal PWM can be activated, can be maintained in an activated state within a predetermined (or, alternatively, desired or selected) time interval Ton, and then can be deactivated. For example, the first reference voltage Vref1 can be or can correspond to the target voltage of the buck converter 100. During a predetermined (or, alternatively, desired or selected) time interval Ton when the pulse switching signal PWM is activated, the HS switch included in the power switching circuit 10 can be turned on, and the inductor current I flowing through the inductor L L can increase. In other words, the activation time interval Ton of the pulse switching signal PWM can be equal to or substantially equal to the conduction time interval of the HS switch. During the deactivation time interval of the pulse switching signal PWM (or when the pulse switching signal PWM is deactivated), the LS switch included in the power switching circuit 10 can be turned on, and the inductor current I flowing through the inductor L L can decrease.

[0040] The overshoot detector 50 can generate a switching cutoff signal S_OFF in response to the first voltage Va, the second voltage Vb, and the second reference voltage Vs. For example, the second reference voltage Vs can be a voltage generated by replicating or simulating the current flowing through the inductor L (e.g., the inductor current I L ) during half of the conduction time interval of the HS switch (e.g., during half of the activation time interval Ton of the pulse switching signal PWM). For example, the second reference voltage Vs can be the same as the inductor current I in the steady state LThe voltage (Vb-Va) obtained by subtracting the first voltage Va from the second voltage Vb can be calculated according to the inductor current I L The voltage may vary with the increase and decrease of or may be changed relative to approximately 0V (or around 0V) or exactly 0V.

[0041] At load current I LOAD In a constant or fixed steady state, the voltage (Vb-Va) may be lower than or equal to the second reference voltage Vs. LOAD When the load current changes from a relatively large load current to a relatively small load current, and when the inductor current I L When the voltage (Vb-Va) increases, the voltage (Vb-Va) may become higher than the second reference voltage Vs. The overshoot detector 50 may detect when the voltage (Vb-Va) becomes higher than the second reference voltage Vs, and may determine that an overshoot has occurred on the output voltage Vout at the time point when the voltage (Vb-Va) becomes higher than the second reference voltage Vs. In other words, when the voltage formed by the change in the current flowing through the inductor L is higher than the inductor current I flowing within half of the on-time interval (e.g., Ton / 2) of the HS switch in the steady state, the overshoot detector 50 may detect when the voltage (Vb-Va) becomes higher than the second reference voltage Vs, and may determine that an overshoot has occurred on the output voltage Vout at the time point when the voltage (Vb-Va) becomes higher than the second reference voltage Vs. L When the copied voltage (e.g., higher than the second reference voltage Vs) is higher than the second reference voltage Vs, it can be determined that an overshoot has occurred on the output voltage Vout. The overshoot detector 50 can detect when the voltage (Vb-Va) becomes higher than the second reference voltage Vs, and can change the state of the switching cutoff signal S_OFF from a first state to a second state in response to such detection. For example, the first state can represent or indicate that the switching cutoff signal S_OFF has a logic high level and the buck converter 100 operates in a stable state. For example, the second state can represent or indicate that the switching cutoff signal S_OFF has a logic low level and an overshoot has occurred on the output voltage Vout of the buck converter 100. Figure 3 The detailed configuration of the overshoot detector 50 is described.

[0042] The driver circuit 60 can receive a pulse switching signal PWM and a switching off signal S_OFF, and can drive the power switching circuit 10. For example, when the switching off signal S_OFF is in a first state (e.g., when it indicates that the buck converter 100 is in a stable state), the driver circuit 60 can drive the power switching circuit 10 in response to the pulse switching signal PWM. For example, when the switching off signal S_OFF is in a second state (e.g., when it indicates that the buck converter 100 is in an overshoot state), the driver circuit 60 can turn off the HS switch and the LS switch included in the power switching circuit 10 regardless of the pulse switching signal PWM (e.g., independent of or not relying on the conditions of the pulse switching signal PWM). For example, when the MOSFET included in the LS switch is turned off, the parasitic diode in the MOSFET can conduct. When the parasitic diode conducts, the voltage difference between the output terminal TO and the second end of the inductor L can increase by as much as the built-in voltage of the parasitic diode, and thus the current flowing through the inductor L can decrease faster than when the MOSFET is conducting. When the current flowing through the inductor L decreases faster, Figure 1 the current ΔI in the shaded area of

[0043] In other words, Figure 2 the buck converter 100 of L can use the change in the inductor current I L to detect overshoot, and can turn off the LS switch included in the power switching circuit 10 to decrease the inductor current I Figure 1 faster, thereby reducing Figure 2 the ΔI in L and minimizing or reducing overshoot. In addition, Figure 2 the buck converter 100 of L can use the change in the inductor current I

[0044] Figure 3 is a circuit diagram showing an example of the power switching circuit 10, the LC filter 20, the sense voltage generator 30, the overshoot detector 50, and the driver circuit 60 in Figure 2 . Figure 4 is a circuit diagram showing an example of the pulse switching signal generator 40 in Figure 2 . Figure 5 is a timing diagram showing an example of the signals associated with the pulse switching signal generator 40 of Figure 4 . Figure 6 is a timing diagram showing an example of the signals associated with the overshoot detector 50 in Figure 3 . Hereinafter, the configuration and operation of the buck converter of Figures 3 to 6 will be described in detail with reference to Figure 2 .

[0045] Refer to Figure 3 , the power switching circuit 10 may include an HS switch HSS and an LS switch LSS, and may alternately transmit or output the input voltage Vin and the ground voltage Vss to the output terminal TO in response to the switching signals HS_ON and LS_ON. In Figure 3 and the subsequent drawings, three parallel straight lines with different lengths connected to the LS switch LSS may represent the ground voltage Vss. For example, each of the HS switch HSS and the LS switch LSS may include a MOSFET. For example, the MOSFET included in the LS switch LSS may include a parasitic diode formed by commonly connecting the source and the body between the source and the drain. Refer to Figure 7 to describe the LS switch LSS.

[0046] The LC filter 20 may include an inductor L and a load capacitor C L . For example, the inductor L may be modeled as including a DC resistor (DCR) R connected in series with the inductor L DCR , and the load capacitor C L may be modeled as including an equivalent series resistor (ESR) R connected in series with the load capacitor C L . The DC resistor R ESR and the equivalent series resistor R DCR may not be included in the actual product (for example, the DC resistor R ESR and the equivalent series resistor R DCR may be parasitic elements). Hereinafter, when describing the physical connection of the inductor L in the buck converter 100, the DC resistor R ESR will be described as non-existent. DCR will be described as non-existent.

[0047] The sense voltage generator 30 may include a first resistor R1, a first capacitor C1, a second resistor R2, and a second capacitor C2. The first resistor R1 and the first capacitor C1 may be connected in series between the output terminal TO and the second end of the inductor L, and the first common node CN1 may be the node connected to and located between the first resistor R1 and the first capacitor C1. The second resistor R2 and the second capacitor C2 may be connected in series between the first common node CN1 and the second end of the inductor L, and the second common node CN2 may be the node connected to and located between the second resistor R2 and the second capacitor C2. The first voltage Va may be the voltage at the first common node CN1, and may be the sum of the output voltage Vout and the voltage Vc1 reflecting the DC component and the AC component of the inductor current I L . The second voltage Vb may be the voltage at the second common node CN2, and may be the output voltage Vout and only reflect the inductor current IL The sum of the voltages Vc2 of the DC components. For example, the inductor current I L The DC component of can correspond to the load current I LOAD The inductor current I L The AC component of can correspond to the ripple component, which is the change in the inductor current I caused by the switching of the power switching circuit 10 L The amount of change.

[0048] Referring to Figure 4 FIG., the pulse switching signal generator 40 may include a set generator 41, a reset generator 43, and a latch L1.

[0049] The set generator 41 may include a comparator CP1 and an inverter INV1. The set generator 41 may operate in response to the voltage Va at the first common node CN1, the voltage Vb at the second common node CN2, the output voltage Vout, and the first reference voltage Vref1. The inverter INV1 may operate in response to the output of the comparator CP1. The comparator CP1 and the inverter INV1 may generate a first signal S1. When (Va - Vb)+Vout is less than or equal to Vref1, the first signal S1 may be activated to a logic high level, and when (Va - Vb)+Vout is higher than Vref1, the first signal S1 may be deactivated to a logic low level. In other words, when the output voltage Vout and the sum of the voltages caused by the ripple component of the inductor current I L is equal to or lower than the first reference voltage Vref1, the first signal S1 may be activated, otherwise it is deactivated. In Figure 5 the timing diagram of FIG., it can be seen that in response to the voltage obtained by subtracting the voltage Vb at the second common node CN2 from the voltage Va at the first common node CN1, the output voltage Vout, and the first reference voltage Vref1, the first signal S1 can be activated and deactivated.

[0050] The latch L1 may receive the first signal S1 as a set signal at the set node, and may activate the pulse switching signal PWM to a logic high level when the first signal S1 is activated. In Figure 5 the timing diagram of FIG., it can be seen that when the first signal S1 is activated, the pulse switching signal PWM is activated.

[0051] The reset generator 43 may include a flip - flop FF, a current source I1, a capacitor C3, a comparator CP2, a latch L2, and a delay circuit D1. The configuration and operation of the reset generator 43 will be described with reference to Figure 4 and Figure 5 FIG.

[0052] The flip-flop FF can generate a second signal S2 that is activated when the pulse switching signal PWM is activated. The current source I1 can generate a current (A×Vin) / R that is proportional to the input voltage Vin. The capacitor C3 can generate a ramp voltage Vramp by accumulating the current from the current source I1 during the activation time interval of the second signal S2. The switches SW1 and SW2 can be set between the current source I1 and the capacitor C3. For example, the connection and / or disconnection of the current source I1 and the capacitor C3 can be controlled by the switches SW1 and SW2 such that the current from the current source I1 is accumulated in the capacitor C3 during the activation time interval of the second signal S2, and the capacitor C3 is discharged during the deactivation time interval of the second signal S2.

[0053] The comparator CP2 can generate a third signal S3 in response to the ramp voltage Vramp and the third reference voltage Vref3. For example, the third reference voltage Vref3 can be A×Vt that is proportional to the target voltage Vt of the buck converter. For example, the proportionality coefficient (e.g., A) of the current source I1 to the input voltage Vin and the proportionality coefficient (e.g., A) of the third reference voltage Vref3 to the target voltage Vt can be equal to each other. For example, the target voltage Vt can be equal to or substantially equal to the first reference voltage Vref1. For example, the target voltage Vt can be equal to or substantially equal to the output voltage Vout. When the ramp voltage Vramp becomes equal to the third reference voltage Vref3, the comparator CP2 can activate the third signal S3 to a logic high level. The latch L2 can receive the third signal S3 as a set signal at the set node, and when the third signal S3 is activated, can activate the fourth signal S4 to a logic high level.

[0054] The latch L1 can receive the fourth signal S4 as a reset signal at the reset node, and can deactivate the pulse switching signal PWM when the fourth signal S4 is activated.

[0055] The flip-flop FF can deactivate the second signal S2 in response to the activation of the fourth signal S4. The delay circuit D1 can generate a fifth signal S5 based on the second signal S2. To delay the deactivation transmission of the second signal S2, the delay circuit D1 can include inverters, each of which includes a capacitor Cd, a resistor Rd, and transistors TR1 and TR2. For example, the fifth signal S5 can have a phase substantially opposite to that of the second signal S2, the length of the deactivation time interval of the fifth signal S5 can be increased by a time interval Ta compared to the length of the activation time interval of the second signal S2, and the time interval Ta can be determined by the delay components of the capacitor Cd and the resistor Rd included in the delay circuit D1. The latch L2 can receive the fifth signal S5 as a reset signal at the reset node, and can deactivate the fourth signal S4 when the fifth signal S5 is activated. The delay components of the capacitor Cd and the resistor Rd included in the delay circuit D1 can ensure a minimum activation time interval Ta of the fourth signal S4. For example, the minimum activation time interval Ta of the fourth signal S4 can be used to ensure a minimum deactivation time interval of the pulse switching signal PWM and a minimum conduction time interval of the LS switch LSS included in the power switching circuit 10.

[0056] Based on Equation 2, the activation time interval Ton of the logic high level of the pulse switching signal PWM generated by the pulse switching signal generator 40 having Figure 4 can be obtained.

[0057] [Equation 2]

[0058] Ton = (Vout / Vin) × RC3

[0059] In Equation 2, Ton represents the activation time interval of the pulse switching signal PWM, Vout represents the output voltage, Vin represents the input voltage, R represents the resistance of the current source I1, and C3 represents the capacitance of the capacitor C3. When the buck converter 100 operates, the activation time interval Ton of the pulse switching signal PWM can be changed at least according to the voltage level of the input voltage Vin. The control scheme for controlling, adjusting, and / or changing the activation time interval Ton of the pulse switching signal PWM when the buck converter 100 operates can be referred to as an adaptive on-time (AOT) scheme.

[0060] However, the example embodiments are not limited thereto. For example, included in Figure 4The current source I1 in the reset generator 43 can generate a constant current, independent of the input voltage Vin (e.g., independent of or unconditional on the input voltage Vin), and the active time interval Ton of the pulse switching signal PWM can be fixed and independent of changes in the input voltage Vin (e.g., independent of or unconditional on the input voltage Vin). The control scheme for fixing the active time interval Ton of the pulse switching signal PWM can be referred to as the constant on-time (COT) scheme. The exemplary embodiments can be applied or used for both the AOT scheme and the COT scheme.

[0061] Referring again to Figure 3 , the overshoot detector 50 can include a half-signal generator 51, a first reference voltage generator 53, and a logic circuit 55. The half-signal generator 51 can generate a half-signal P2 having pulses with half of the active time interval Ton of the pulse switching signal PWM. The first reference voltage generator 53 can generate a voltage by replicating the inductor current I L during half of the active time interval Ton. The logic circuit 55 can include a comparator CP4 and other components.

[0062] The half-signal generator 51 can include a comparator CP5 and latches L3 and L4. The comparator CP5 can respond to a fourth reference voltage Vref4 (which is half of the third reference voltage Vref3) and generate a sixth signal S6 in response to a ramp voltage Vramp (which is generated by Figure 4 the pulse switching signal generator 40). The latch L3 can receive the sixth signal S6 as a set signal at the set node and can generate a seventh signal S7 in response to the sixth signal S6. The latch L4 can receive the first signal S1 as a set signal at the set node, can activate the half-signal P2 when the first signal S1 is activated, and can deactivate the half-signal P2 in response to the seventh signal S7. As Figure 5 shown, the active time interval of the half-signal P2 can be half of the active time interval Ton of the pulse switching signal PWM.

[0063] The first reference voltage generator 53 can include a current source I2 and a capacitor C4. The current source I2 can generate a current corresponding to (Vin - Vout) / R1. For example, the Vout of the current source I2 can be equal to or substantially equal to the target voltage Vt. During the active time interval of the half-signal P2, the capacitor C4 can generate a half-voltage Vs as the second reference voltage through the current of the current source I2. Switches SW3 and SW4 can be disposed between the current source I2 and the capacitor C4. For example, the connection and / or disconnection of the current source I2 and the capacitor C4 can be controlled by the switches SW3 and SW4 such that as Figure 6The half voltage Vs is generated as shown. To generate the half voltage Vs by copying the current flowing through the inductor L during half of the activation time interval Ton (during which the HS switch HSS is turned on), for example, to generate a half voltage Vs equal to half of the voltage corresponding to the change in the inductor current flowing through the inductor L during the activation time interval Ton, the resistance of the current source I2 can be equal to the resistance of the first resistor R1 in the sense voltage generator 30, and the capacitance of the capacitor C4 can be equal to the capacitance of the capacitor C1. Thus, even if the input voltage Vin, the output voltage Vout, and / or the switching frequency change, the second reference voltage, such as the half voltage Vs, can be accurately generated.

[0064] Referring to Figure 6 , the half voltage Vs, which is the second reference voltage, generated in the capacitor C4 during the activation time interval of the half signal P2 is shown. When the half signal P2 is activated, the half voltage Vs can be reset to approximately 0V, can increase during Ton / 2, which is the activation time interval of the half signal P2, and then can hold the increased voltage level until the half signal P2 is activated again.

[0065] Referring again to Figure 3 , the comparator CP4 can generate an eighth signal S8 in response to the voltage Va at the first common node CN1, the voltage Vb at the second common node CN2, and the half voltage Vs as the second reference voltage. The comparator CP4 can compare the voltage (Vb - Va) obtained by subtracting the voltage Va from the voltage Vb with the half voltage Vs, can activate the eighth signal S8 to a logic high level when the voltage (Vb - Va) becomes higher than the half voltage Vs, and can deactivate the eighth signal S8 to a logic low level when the voltage (Vb - Va) is less than the half voltage Vs. For example, the voltage (Vb - Va) can be calculated as (Vout + Vc2) - (Vout + Vc1), for example, (Vc2 - Vc1), which is obtained by subtracting the voltage of the DC component of the inductor current I L from the voltage of the DC and AC components of the inductor current I L and which represents the AC component. In other words, Figure 6 the voltage (Vb - Va) in

[0066] The NAND gate ND1 can receive the ninth signal S9 (wherein, the eighth signal S8 is delayed by the delay circuit D2), can receive the signal P2B (wherein, the half signal P2 is inverted by the inverter INV2), and can generate a switching cut-off signal S_OFF in response to the ninth signal S9 and the signal P2B. When the half signal P2 has a logic high level, the switching cut-off signal S_OFF can be in a first state (e.g., logic high level) representing a stable state. When the half signal P2 has a logic low level, according to the ninth signal S9, the switching cut-off signal S_OFF can be in the first state (e.g., logic high level) or the second state (e.g., logic low level).

[0067] The delay circuit D2 can help prevent or reduce the occurrence of the switching cut-off signal S_OFF switching from the first state to the second state due to the logic high level of the eighth signal S8 and the logic high level of the signal P2B. In some example embodiments, the delay circuit D2 can be omitted. If the delay circuit D2 is omitted, the NAND gate ND1 can receive the eighth signal S8, can receive the signal P2B in which the half signal P2 is inverted by the inverter INV2, and can generate the switching cut-off signal S_OFF in response to the eighth signal S8 and the signal P2B.

[0068] Referring to Figure 6 , the overshoot detector 50 can set the switching cut-off signal S_OFF to the first state of logic high level in a stable state where the voltage (Vb - Va) is lower than the half voltage Vs, and can set the switching cut-off signal S_OFF to the second state of logic low level in an overshoot situation where the voltage (Vb - Va) becomes higher than the half voltage Vs.

[0069] The driver circuit 60 can receive a pulse switching signal PWM and a switching cut-off signal S_OFF, and can generate switching signals HS_ON and LS_ON in response to the pulse switching signal PWM and the switching cut-off signal S_OFF. For example, the driver circuit 60 can include AND gates AND1 and AND2 and an inverter INV3. When the switching cut-off signal S_OFF is in a first state of logic high level (e.g., before the time point tov), the driver circuit 60 can generate the switching signals HS_ON and LS_ON such that during the activation time interval Ton of the switching pulse signal PWM, the HS switch HSS is turned on and the LS switch LSS is turned off. When the switching cut-off signal S_OFF is in a second state of logic low level (e.g., after the time point tov), the driver circuit 60 can generate the switching signals HS_ON and LS_ON such that the HS switch HSS and the LS switch LSS are turned off. When the MOSFET included in the LS switch LSS is turned off, the parasitic diode of the MOSFET can be turned on to maintain the current flowing through the inductor L, and then the voltage across the inductor L can become higher compared with when the MOSFET is turned on. Therefore, as Figure 6 shown, when the switching cut-off signal S_OFF is in the second state of logic low level (e.g., in the ovs state after the time point tov), the absolute value of the slope of the decreasing inductor current I L can increase, thereby minimizing or reducing the overshoot. In Figure 6 , after the time point tov, the I L with a relatively small absolute value of the slope of the decreasing inductor current I L _CASE1 can represent the inductor current of a conventional buck converter, and the IL_CASE2 with a relatively large absolute value of the slope of the decreasing inductor current I L shown by a solid line after the time point tov can represent the inductor current of the buck converter according to the exemplary embodiment.

[0070] Figure 7 is a diagram showing an example of the parasitic diode in the MOSFET included in the LS switch.

[0071] Referring to Figure 7 , in the substrate, the structure of an n-type MOSFET is shown, where the voltages of the source S and the body B are commonly connected, and the parasitic diode Dp can be formed between the source S and the drain D. Even when a cut-off voltage is applied to the gate G, the parasitic diode Dp can be turned on by the voltages of the source S and the drain D.

[0072] Figure 8A is a timing diagram showing the operation of the buck converter according to the exemplary embodiment due to the change in the load current I LOAD .Figure 8B is Figure 8A wherein the inductor current I L An enlarged view of a region where the absolute value of the decreasing slope of the inductor current I increases in an overshoot situation.

[0073] Referring to Figure 8A and Figure 8B the load current I LOAD can transition or change from a relatively large load current to a relatively small load current. At time point t0, when the signal P2B is logic high and the voltage (Vb - Va) becomes higher than the half voltage Vs, the signal S8 can be activated to logic high, and when the signal S9 is activated to logic high, the switching off signal S_OFF can transition from logic high to logic low. In response to the switching off signal S_OFF, the LS switch LSS included in the power switching circuit 10 can be turned off, such that the inductor current I L has an increasing absolute value of the decreasing slope. At time point t1, when the voltage (Vb - Va) becomes lower than the half voltage Vs, the switching off signal S_OFF can switch back to logic high, and the buck converter can enter a steady state with a relatively light load current. As Figure 8B shown, when (Vb - Va)>Vs at time point t0, the LS switch LSS can be turned off, and the inductor current I L has a more significantly changing decreasing slope.

[0074] Figure 9 is a timing diagram showing the overshoot of a conventional buck converter and the overshoot of a buck converter according to an exemplary embodiment.

[0075] Referring to Figure 9 I L _CASE1 and Vout_CASE1 respectively represent the inductor current and the output voltage of a conventional buck converter. I L _CASE2 and Vout_CASE2 respectively represent the inductor current and the output voltage of a buck converter according to an exemplary embodiment. At time point t0, when the switching off signal S_OFF transitions to logic low, the absolute value of the decreasing slope of the inductor current of the buck converter according to the exemplary embodiment can be greater than the absolute value of the decreasing slope of the inductor current of the conventional buck converter. In other words, the decreasing slope of the inductor current of the buck converter according to the exemplary embodiment can be steeper than the decreasing slope of the inductor current of the conventional buck converter. As the absolute value of the decreasing slope of the inductor current of the buck converter according to the exemplary embodiment increases, the output voltage of the buck converter according to the exemplary embodiment can be approximately or precisely 3.3 mV lower than the overshoot voltage (e.g., approximately or precisely 23 mV) of the conventional buck converter.

[0076] Figure 10 isFigure 2 Circuit diagram of an example of a sense voltage generator.

[0077] Refer to Figure 10 Except that the sense voltage generator 30' further includes resistors R5, R6, R7, and R8, Figure 10 the sense voltage generator 30' in Figure 3 may be the same as or substantially the same as the sense voltage generator 30 in . Resistors R5 and R6 may be connected in series between the output terminal TO and the ground voltage Vss, and resistors R7 and R8 may be connected in series between the second end of the inductor L and the ground voltage Vss. One end of resistor R1 may be connected to the common node CN3 of resistors R5 and R6, and one end of capacitor C1 may be connected to the common node CN4 of resistors R7 and R8. The sense voltage generator 30' may not be directly connected between the output terminal TO and the second end of the inductor L (e.g., the feedback terminal TF), and may be connected at an intermediate node (e.g., common nodes CN3 and CN4) of a resistor divider (e.g., resistors R5, R6, R7, and R8). In applications where the input voltage Vin is relatively high, the resistor divider can be used to improve the withstand voltage characteristics of the capacitor C1 connected in parallel with resistors R5, R6, R7, and R8.

[0078] Figure 11 is a flowchart showing a method of operating a buck converter according to an example embodiment.

[0079] Refer to Figure 3 and Figure 11 the buck converter 100 may generate a reference voltage Vs (operation S1) corresponding to half of the change amount of the inductor current I L in the steady state. For example, the current source I2 and the capacitor C4 included in the first reference voltage generator 53 of the buck converter 100 may be used to generate the reference voltage Vs during the active time interval of the half signal P2.

[0080] The buck converter 100 may generate a voltage (Vb - Va) (operation S2) corresponding to the change amount of the inductor current I LOAD due to the change in the load current I L . For example, the sense voltage generator 30 of the buck converter 100 may generate the voltage Va at the first common node CN1 and the voltage Vb at the second common node CN2, and the comparator CP4 of the buck converter 100 may generate the voltage (Vb - Va) by subtracting the voltage Va at the first common node CN1 from the voltage Vb at the second common node CN2.

[0081] Comparator CP4 of the buck converter 100 can determine whether the voltage (Vb - Va) is higher than the reference voltage Vs (operation S3). When the voltage (Vb - Va) is lower than the reference voltage Vs, the overshoot detector 50 of the buck converter 100 can generate a switching cut-off signal S_OFF indicating a steady state, and the driver circuit 60 can drive the HS switch HSS and the LS switch LSS included in the power switching circuit 10 in response to the pulse switching signal PWM, such that the HS switch HSS and the LS switch LSS are alternately turned on (operation S4). When the voltage (Vb - Va) is higher than the reference voltage Vs, the overshoot detector 50 of the buck converter 100 can generate a switching cut-off signal S_OFF indicating an overshoot, and the driver circuit 60 can turn off the LS switch LSS included in the power switching circuit 10 regardless of the pulse switching signal PWM (e.g., independent of the pulse switching signal PWM or under a condition not dependent on the pulse switching signal PWM) (operation S5). When the LS switch LSS is turned off, the absolute value of the slope of the decreasing inductor current can increase. Thus, the inductor current I L accumulated in the load capacitor C L can be reduced, thereby minimizing or reducing the overshoot on the output voltage Vout. For example, operations S3, S4, and S5 can be repeatedly executed.

[0082] For example, when the LS switch LSS is turned off in operation S5, the absolute value of the slope of the decreasing inductor current can be greater than the absolute value of the slope of the decreasing inductor current when the LS switch LSS is turned on in operation S4. For example, operation S1 can be executed during the active time interval of the half-signal P2, and the half-signal P2 is activated only within half of the active time interval Ton of the pulse switching signal PWM. For example, the conduction time interval of the HS switch HSS can be equal to the active time interval Ton of the pulse switching signal PWM.

[0083] Figure 12 is a block diagram showing an electronic device including a buck converter according to an exemplary embodiment.

[0084] Referring to Figure 12 , the electronic device 1000 can include a first semiconductor chip 101, a second semiconductor chip 300, and an LC filter 20, and can also include a printed circuit board (PCB) 500 on which the first semiconductor chip 101, the second semiconductor chip 300, and the LC filter 20 are mounted.

[0085] The first semiconductor chip 101 and the LC filter 20 can form Figure 2 and / or Figure 10Buck converter 100. For example, the first semiconductor chip 101 may include a power switching circuit 10, a sensed voltage generator 30, a pulse switching signal generator 40, an overshoot detector 50, and a driver circuit 60. The power switching circuit 10 may receive an input voltage Vin from a battery (not shown) and may alternately transfer the input voltage Vin and the ground voltage Vss to the output terminal TO in response to a pulse switching signal PWM having an active time interval and a deactivated time interval. The LC filter 20 may generate an output voltage Vout by low-pass filtering the voltage at the output terminal TO. The second semiconductor chip 300 may receive the output voltage Vout as a power supply voltage and may consume a load current I LOAD . For example, the second semiconductor chip 300 may be or may include one of a memory and a central processing unit (CPU) having computing capabilities.

[0086] In some example embodiments, the first semiconductor chip 101 included in the electronic device 1000 may further include one of a linear regulator (e.g., a low dropout (LDO) regulator) and a DC-DC converter of a different type than the buck converter.

[0087] In the electronic device 1000 according to the example embodiments, even if the operating state of the second semiconductor chip 300 changes, the buck converter 100 may provide a stable output voltage Vout to the second semiconductor chip 300 (e.g., a load device), and thus stable performance may be achieved. For example, even if the operation of the second semiconductor chip 300 changes from consuming a relatively large load current to consuming a relatively small load current, the buck converter 100 including the first semiconductor chip 101 and the LC filter 20 may detect an overshoot, may increase the inductor current I L decrease the absolute value of the slope, and may minimize or reduce the change in the output voltage Vout. Accordingly, stable performance of the electronic device 1000 may be ensured.

[0088] The example embodiments may be applied to various electronic devices and systems including a buck converter. For example, the example embodiments may be applied to systems such as a personal computer (PC), a server computer, a data center, a workstation, a mobile phone, a smartphone, a tablet computer, a laptop computer, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a portable game console, a music player, a video camera, a video player, a navigation device, a wearable device, an Internet of Things (IoT) device, an Internet of Everything (IoE) device, an e-book reader, a virtual reality (VR) device, an augmented reality (AR) device, a robotic device, a drone, an automobile, etc.

[0089] When the terms "about" or "substantially" are used in conjunction with a numerical value in this specification, it is intended that the associated numerical value include manufacturing or operational tolerances (e.g., ±10%) around the stated numerical value. Further, when the words "substantially" and "about" are used in conjunction with a geometric shape, it is intended that the precision of the geometric shape is not required, but that the degree of freedom of the shape is within the scope of the present disclosure. Further, whether a numerical value or shape is modified with "about" or "substantially", it will be understood that these values and shapes should be interpreted as including manufacturing or operational tolerances (e.g., ±10%) around the stated numerical value or shape.

[0090] As described herein, any electronic device and / or portion thereof according to any example embodiment may include one or more instances of a processing circuit, may be included in one or more instances of a processing circuit, and / or may be implemented by one or more instances of a processing circuit, such as hardware including logic circuits, a hardware / software combination (such as a processor executing software), or any combination thereof. For example, the processing circuit may more particularly include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a graphics processing unit (GPU), an application processor (AP), a digital signal processor (DSP), a microcomputer, a field programmable gate array (FPGA), and a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), a neural network processing unit (NPU), an electronic control unit (ECU), an image signal processor (ISP), and the like. In some example embodiments, the processing circuit may include a non-transitory computer-readable storage device (e.g., a memory), such as a DRAM device storing a program of instructions; and a processor (e.g., a CPU) configured to execute the program of instructions to implement functions and / or methods performed by some or all of and / or any part of any device, system, module, unit, controller, circuit, architecture, and / or portion thereof according to any example embodiment.

[0091] The foregoing are illustrative of example embodiments and should not be construed as limiting thereof. Although some example embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made in the example embodiments without materially departing from the novel teachings and advantages of the example embodiments. Accordingly, all such modifications are intended to be included within the scope of the example embodiments as defined in the claims. Accordingly, it will be understood that the foregoing are illustrative of various example embodiments and should not be construed as limited to the specific example embodiments disclosed, and modifications to the disclosed example embodiments as well as other example embodiments are intended to be included within the scope of the appended claims.

Claims

1. A buck converter, comprising: A power switching circuit including a high-side switch and a low-side switch, the power switching circuit being configured to alternately transfer an input voltage and a ground voltage to an output terminal through the high-side switch and the low-side switch in response to a pulse switching signal; An inductor having a first end connected to the output terminal and a second end connected to a load capacitor, the inductor being configured to generate an output voltage at the second end; A sense voltage generator configured to generate a first voltage and a second voltage, the sense voltage generator including: A first resistor and a first capacitor connected in series between the output terminal and the second end of the inductor, the first voltage being the voltage at a first common node between the first resistor and the first capacitor, and A second resistor and a second capacitor connected in series between the first common node and the second end of the inductor, the second voltage being the voltage at a second common node between the second resistor and the second capacitor; And An overshoot detector configured to generate a switching cut-off signal in response to a first reference voltage, the first voltage, and the second voltage, and to generate the first reference voltage based on replicating the current flowing through the first common node during half of the conduction time interval of the high-side switch, The power switching circuit is further configured to: Based on the switching cut-off signal being in a first state, the high-side switch and the low-side switch alternately conduct in response to the pulse switching signal, and Based on the switching cut-off signal being in a second state, the low-side switch is turned off.

2. The buck converter according to claim 1, wherein The low-side switch is a metal-oxide semiconductor field-effect transistor having a parasitic diode between the source and the drain, and The power switching circuit is configured to turn on the parasitic diode based on the switching cut-off signal being in the second state.

3. The buck converter according to claim 2, further comprising: A pulse switching signal generator configured to generate the pulse switching signal having an active time interval equal to the conduction time interval.

4. The buck converter according to claim 3, wherein, The pulse switching signal generator includes: A set generator including a first comparator configured to generate a first signal in response to the first voltage, the second voltage, the output voltage, and a second reference voltage; A reset generator configured to generate a second signal in response to a ramp signal and a third reference voltage, the ramp signal being generated from the active time point of the pulse switching signal; and A first latch configured to activate the pulse switching signal in response to the first signal and deactivate the pulse switching signal in response to the second signal.

5. The buck converter according to claim 4, wherein, Each of the second reference voltage and the third reference voltage is associated with a target voltage of the buck converter or the output voltage of the buck converter.

6. The buck converter according to claim 4, wherein The overshoot detector includes: A half-signal generator configured to activate a half-signal in response to the first signal and deactivate the half-signal in response to a ramp voltage and a fourth reference voltage; A first reference voltage generator configured to generate the first reference voltage during an activation time interval of the half-signal; and A second comparator configured to generate a first internal signal in response to the first voltage, the second voltage, and the first reference voltage, The first internal signal is activated in response to a voltage obtained by subtracting the first voltage from the second voltage being higher than the first reference voltage, and The first internal signal is deactivated in response to a voltage obtained by subtracting the first voltage from the second voltage being lower than or equal to the first reference voltage.

7. The buck converter according to claim 6, wherein, The fourth reference voltage is half of the third reference voltage.

8. The buck converter according to claim 7, wherein, The voltage obtained by subtracting the first voltage from the second voltage changes with respect to 0V.

9. The step-down converter according to claim 8, wherein, The first reference voltage is equal to a voltage corresponding to half of a change amount of an inductor current flowing through the inductor during the on-time interval.

10. The buck converter according to claim 8, wherein, The first reference voltage generator includes: A first current source configured to generate a current, the amount of the current generated from the first current source being obtained by (Vin - Vout) / R1, where R1 represents a resistance equal to a resistance of the first resistor, Vin represents the input voltage, and Vout represents the output voltage; and A second capacitor having a capacitance equal to a capacitance of the first capacitor.

11. The buck converter according to claim 10, wherein, The overshoot detector further includes: A logic circuit configured to receive the first internal signal and an inverted signal of the half-signal to generate the switching cut-off signal having the first state in response to the first internal signal being deactivated or the half-signal being activated, and generate the switching cut-off signal having the second state in response to the first internal signal being activated and the half-signal being deactivated.

12. The buck converter according to claim 10, wherein, The overshoot detector further includes: A delay circuit configured to generate a second internal signal by delaying the first internal signal; and A logic circuit configured to receive the second internal signal and an inverted signal of the half-signal to generate the switching cut-off signal having the first state in response to the second internal signal being deactivated or the half-signal being activated, and generate the switching cut-off signal having the second state in response to the second internal signal being activated and the half-signal being deactivated.

13. The buck converter according to claim 12, further comprising: A driver circuit configured to drive the power switching circuit in response to the pulse switching signal when the switching cut-off signal is in the first state, and turn off a low-side switch included in the power switching circuit based on the switching cut-off signal being in the second state regardless of the pulse switching signal.

14. A method of operating a buck converter, the method comprising: Generating a reference voltage corresponding to half of a change amount of an inductor current in a steady state; Generate a first voltage corresponding to a change in inductor current caused by a change in load current; Sense a first state in which the first voltage is higher than the reference voltage; and In response to the first state, turn off the low-side switch regardless of the pulse switching signal, the low-side switch being included in a power switching circuit included in the buck converter.

15. The method according to claim 14, further comprising: Sense a second state in which the first voltage is lower than the reference voltage; And In response to the second state and the pulse switching signal, alternately turn on the high-side switch and the low-side switch, the high-side switch being included in the power switching circuit.

16. The method according to claim 15, wherein, The absolute value of the slope of decrease of the inductor current when the low-side switch is turned off in response to the first state is greater than the absolute value of the slope of decrease of the inductor current when the low-side switch is turned on in response to the second state.

17. The method according to claim 16, wherein, Generate the reference voltage during an active time interval of a half-signal, the half-signal being active during half of the active time interval of the pulse switching signal.

18. The method according to claim 17, wherein, The conduction time interval of the high-side switch is equal to the active time interval of the pulse switching signal.

19. An electronic device, comprising: A first semiconductor chip including a power switching circuit, the power switching circuit including a high-side switch and a low-side switch; An inductor and a load capacitor, the inductor and the load capacitor being connected to an output terminal of the power switching circuit and configured to generate an output voltage; And A second semiconductor chip configured to receive the output voltage as a supply voltage and consume a load current, The first semiconductor chip is configured to: Generate a reference voltage corresponding to a change in inductor current flowing through the inductor during half of the conduction time interval of the high-side switch, Generate a first voltage corresponding to a change in inductor current caused by a change in load current, and Adjust the slope of decrease of the inductor current according to the reference voltage and the first voltage.

20. The electronic device according to claim 19, wherein, The absolute value of the slope of decrease of the inductor current based on the first voltage being higher than the reference voltage is greater than the absolute value of the slope of decrease of the inductor current based on the first voltage being lower than the reference voltage.

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