Current adjusting method, current adjusting circuit and electronic equipment

Abstract

The invention discloses a current adjusting method, a current adjusting circuit and electronic equipment. The current adjusting method comprises the following steps: acquiring an output current of an adjusting output sub-circuit; an adjustment output value is obtained by using an error value between the reference pulse current and the output current; in response to the condition that the adjustment output value is lower than the first threshold range, adjusting the adjustment output value to be within the first threshold range; generating a drive control signal using the adjusted output value; in response to the fact that the reference pulse current is zero, a driving control signal is sent to any preset number of power switch sub-circuits, so that the output current is adjusted to be within a second threshold range; wherein the preset number is smaller than the total number of the power switch sub-circuits. Through the above mode, the current adjusting method provided by the invention can meet the power supply demand in time when the multi-phase interlaced conversion circuit is loaded again, can effectively avoid the working error caused by the fact that the load circuit is still maintained in the working state when the load circuit is unloaded, and avoids unnecessary element loss.

Description

Technical Field

[0001] This application relates to the technical field of circuit control, and in particular, to a current regulation method, a current regulation circuit, and an electronic device. Background Art

[0002] Nowadays, with the increasing richness of electronic devices, the requirements for power supply are also becoming more diverse. Especially when there are non-linear elements and / or energy storage elements in the load circuit, in order to ensure good power supply quality and power supply stability, the power supply usually still needs to maintain a certain output current when it is no-load, and it is also necessary to ensure that the output current does not exceed a specific threshold. However, in the related art, the current regulation method for power supply usually cannot ensure that there is still an output current when it is no-load, or cannot adjust the output current to a specific threshold range, so that the load circuit remains in the working state when it is no-load, resulting in working errors and unnecessary component losses. Summary of the Invention

[0003] The main technical problem to be solved by this application is to provide a current regulation method, a current regulation circuit, and an electronic device, which can solve the problem that the current regulation method in the related art cannot adjust the output current to a specific threshold range when it is no-load, so that the load circuit remains in the working state when it is no-load, resulting in working errors and unnecessary component losses.

[0004] To solve the above technical problem, a technical solution adopted by this application is: to provide a current regulation method, which is applied to the current regulation of a multi-phase interleaved conversion circuit. The multi-phase interleaved conversion circuit includes a power switch sub-circuit and an adjustment output sub-circuit that are phase-coupled. The number of power switch sub-circuits is at least two. Among them, the current regulation method includes: obtaining the output current of the adjustment output sub-circuit; obtaining an adjustment output value by using the error value between the reference pulse current and the output current; in response to the adjustment output value being lower than the first threshold range, adjusting the adjustment output value to within the first threshold range; generating a drive control signal by using the adjustment output value; in response to the reference pulse current being zero, sending the drive control signal to any preset number of power switch sub-circuits to adjust the output current to within the second threshold range; where the preset number is less than the total number of power switch sub-circuits.

[0005] Among them, before the step of obtaining the adjustment output value by using the error value between the reference pulse current and the output current, it further includes: receiving a power supply adjustment signal sent by the host computer; adjusting the signal frequency of the reference pulse current in response to the power supply adjustment signal.

[0006] Among them, before the step of adjusting the adjustment output value to within the first threshold range in response to the adjustment output value being lower than the first threshold range, it further includes: setting the first threshold range by using the preset number and the second threshold range.

[0007] Among them, the step of adjusting the adjusted output value to within the first threshold range in response to the adjusted output value being lower than the first threshold range includes: obtaining the falling edge of the reference pulse current; starting timing in response to the falling edge, and when the accumulated timing reaches the preset minimum duration, adjusting the error value to 0; using the adjusted error value to adjust the adjusted output value to within the first threshold range.

[0008] Among them, the step of sending the drive control signal to any preset number of power switch sub-circuits in response to the reference pulse current being zero includes: sending the drive control signal to any preset number of power switch sub-circuits in response to the falling edge.

[0009] Among them, after the step of sending the drive control signal to any one of any preset number of power switch sub-circuits in response to the falling edge, it further includes: obtaining the rising edge of the reference pulse current; sending the drive control signal to each power switch sub-circuit in response to the rising edge.

[0010] Among them, the preset minimum duration is greater than or equal to the time interval between the falling edge and the starting moment when the error value is within the third threshold range, and less than the minimum period of the reference pulse current.

[0011] Among them, the step of adjusting the adjusted output value to within the first threshold range in response to the adjusted output value being lower than the first threshold range includes: obtaining the falling edge and the rising edge of the reference pulse current; starting timing in response to the falling edge, and when the accumulated timing reaches the preset minimum duration, keeping the current adjusted output value unchanged until the rising edge to adjust the adjusted output value to within the first threshold range; where the reference pulse current has different signal frequencies.

[0012] Among them, the step of starting timing in response to the falling edge and keeping the current adjusted output value unchanged until the rising edge when the accumulated timing reaches the preset minimum duration includes: starting timing in response to the falling edge, and when the accumulated timing reaches the preset minimum duration, setting the adjustment flag bit low; keeping the current adjusted output value unchanged; setting the adjustment flag bit high in response to the rising edge, and obtaining the adjusted output value using the error value.

[0013] Among them, obtaining the adjusted output value using the error value between the reference pulse current and the output current includes: subtracting the output current from the reference pulse current to obtain the error value; performing proportional-integral adjustment on the error value to obtain the adjusted output value.

[0014] To solve the above technical problems, another technical solution adopted by this application is: providing a current adjustment circuit, where the current adjustment circuit is coupled to a multi-phase interleaved conversion circuit; where the current adjustment circuit adjusts the current of the multi-phase interleaved conversion circuit by using the current adjustment method described in any one of the above.

[0015] To solve the above technical problems, another technical solution adopted by this application is: to provide an electronic device, wherein the electronic device includes a housing and a current regulation circuit connected to the housing; wherein, the current regulation circuit is the current regulation circuit as described above.

[0016] The beneficial effects of this application are as follows: Different from the prior art, the current regulation method provided by this application obtains the output current of the regulation output sub-circuit, uses the error value between the reference pulse current and the output current to obtain the regulation output value, and in response to the regulation output value being lower than the first threshold range, adjusts the regulation output value to within the first threshold range, uses the regulation output value to generate a drive control signal, and in response to the reference pulse current being zero, sends the drive control signal to any preset number of power switch sub-circuits. Therefore, when the reference pulse current is zero, by restricting the regulation output value and the controlled number of power switch sub-circuits, the output current can be effectively regulated to within the second threshold range, so as to ensure that the multi-phase interleaved conversion circuit can meet the power supply requirements in a timely manner when reloading, and at the same time, it can effectively avoid the load circuit from remaining in the working state when the load is empty, resulting in work errors, and avoid unnecessary component losses; and when the reference pulse current has different frequencies, by restricting the regulation output value within the first threshold range, it also effectively ensures the consistency and stability of the output current during the rising stage when the multi-phase interleaved conversion circuit reloads, thus ensuring good power supply quality and power supply stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of this application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings, where: Figure 1 is a schematic flowchart of the first embodiment of the current regulation method of this application; Figure 2 is a schematic structural diagram of the first embodiment of the current regulation circuit of this application; Figure 3 is Figure 1 a schematic flowchart of an embodiment of S12 in Figure 4 is Figure 1 a schematic flowchart of an embodiment of S13 in Figure 5 is Figure 4 a waveform diagram of an embodiment of the reference pulse current, error value, and regulation output value in Figure 6 is Figure 4 a schematic flowchart of an embodiment of S132 in Figure 7 It is a schematic flowchart of the second embodiment of the current regulation method of the present application; Figure 8 It is a schematic flowchart of the third embodiment of the current regulation method of the present application; Figure 9 It is a schematic structural diagram of the second embodiment of the current regulation circuit of the present application; Figure 10 It is a schematic structural diagram of an embodiment of an electronic device of the present application. Specific Embodiments

[0018] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present application.

[0019] The terms "first", "second", and "third" in the present application are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, features defined with "first", "second", and "third" may explicitly or implicitly include at least one of such features. In the description of the present application, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically and clearly defined. All directional indications (such as up, down, left, right, front, back...) in the embodiments of the present application are only used to explain the relative positional relationship and movement conditions between components in a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications will also change accordingly. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products, or devices.

[0020] Referring to "embodiments" herein means that the specific features, structures, or characteristics described in connection with the embodiments can be included in at least one embodiment of the present application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0021] Next, the present application will be described in detail in conjunction with the accompanying drawings and embodiments.

[0022] Please refer to Figure 1 and Figure 2 , wherein, Figure 1 is a schematic flow chart of the first embodiment of the current regulation method of the present application, Figure 2 is a schematic structural diagram of the first embodiment of the current regulation circuit of the present application. Specifically, the following steps may be included: S11: Obtain the output current of the regulation output sub-circuit.

[0023] It can be understood that the current regulation method in this embodiment is specifically applied to the current regulation of the first multi-phase interleaved conversion circuit 200 as shown in Figure 2 . The first multi-phase interleaved conversion circuit 200 includes a first power switch sub-circuit 201 and a first regulation output sub-circuit 202 that are phase-coupled; wherein, the first current regulation circuit 100 uses the current regulation method described in any item herein to implement current regulation on the first multi-phase interleaved conversion circuit 200.

[0024] It should be noted that the first multi-phase interleaved conversion circuit 200 may specifically be a multi-phase interleaved BUCK circuit (step-down conversion circuit), or a multi-phase interleaved BOOST circuit (step-up conversion circuit), or other forms of circuit topologies, and this embodiment does not limit this.

[0025] Wherein, the number of the first power switch sub-circuits 201 is specifically at least two, such as the first power switch sub-circuit 1, the first power switch sub-circuit 2,..., the first power switch sub-circuit n (n is an integer greater than 1). And the first power switch sub-circuit 1, the first power switch sub-circuit 2,..., the first power switch sub-circuit n are all coupled to the first current regulation circuit 100 and the first regulation output sub-circuit 202, and the first regulation output sub-circuit 202 is further used to be coupled to the load circuit 301.

[0026] In some embodiments, the first current regulation circuit 100 may specifically include a control chip, a DSP (Digital Signal Processing) chip, an MCU (Micro Controller Unit) circuit, a CPU (Central Processing Unit), a single-chip microcomputer, a field programmable gate array, a programmable logic device, discrete gates or transistor logic devices, discrete hardware, or any other reasonable circuit unit with signal processing functions, and the present application does not limit this.

[0027] In addition, "coupled" in this text refers to including any direct and indirect connection means. Therefore, if it is described in the text that the first circuit is coupled to the second circuit, it means that the first circuit can be directly connected to the second circuit through electrical connection, wireless transmission, optical transmission and other signal connection methods, or indirectly electrically connected or signal-connected to the second circuit through other circuits or connection means.

[0028] Specifically, the first current regulation circuit 100 monitors the output current of the first regulation output sub-circuit 202 in real time, and samples the output current output to the load circuit 301 in the first regulation output sub-circuit 202.

[0029] S12: Obtain the regulated output value by using the error value between the reference pulse current and the output current.

[0030] The first current regulation circuit 100 sets a reference pulse current, or receives the reference pulse current sent by the host computer, subtracts the output current from the reference pulse current to obtain the error value, and uses a PID (Proportional Integral Derivative) controller, a PI controller or any other reasonable feedback control algorithm for the error value to obtain the regulated output value. This application does not make any limitations on this.

[0031] Among them, the reference pulse current can specifically be a periodic pulse waveform or other forms of reference signals.

[0032] It is worth noting that the host computer usually refers to a computer system with powerful computing power and data processing capabilities. It is responsible for the monitoring, instruction issuing, data acquisition, processing and analysis, and user interaction of the entire control system. As the "brain" of the system, the host computer can process complex algorithms, perform long-term data storage, and provide a graphical interface for users to operate.

[0033] The slave computer refers to a device or controller directly connected to hardware such as sensors and actuators in the control system. It is responsible for executing the specific control instructions issued by the host computer, such as the output of switch signals, the adjustment of analog quantities, the acquisition of data, etc. The slave computer usually executes simple logical judgments and real-time control tasks.

[0034] S13: In response to the regulated output value being lower than the first threshold range, adjust the regulated output value to within the first threshold range.

[0035] Set a first threshold range according to specific control requirements. If the regulated output value is lower than the first threshold range, adjust it to the first threshold range; or it can be understood that when the regulated output value decreases to the first threshold range, keep the regulated output value from decreasing further.

[0036] S14: Generate a drive control signal by using the regulated output value.

[0037] Generate corresponding drive control signals according to the adjusted output value. These drive control signals are used to trigger the switching elements of each first power switch sub-circuit 201 to control their on and off states.

[0038] In some embodiments, the drive control signal may specifically be one or more of any reasonable control signals such as PWM (Pulse Width Modulation) signal or PFM (Pulse Frequency Modulation) signal, etc., and the present application does not limit this.

[0039] S15: Send the drive control signal to any preset number of first power switch sub-circuits in response to the reference pulse current being zero, so as to adjust the output current to within the second threshold range.

[0040] When the reference pulse current is detected to be zero, select any preset number of first power switch sub-circuits 201, and this preset number is less than the total number of first power switch sub-circuits 201.

[0041] Send the currently generated drive control signal to these selected partial first power switch sub-circuits 201 to adjust the output current to the second threshold range, so that the controlled number of first power switch sub-circuits 201 can be reduced by limiting, and at the same time, the adjusted output value is limited not to exceed the first threshold range, so as to effectively limit the output current of the multi-phase interleaved conversion circuit when it is no-load to within the second threshold range, so that while ensuring that the power supply demand can be met in time when reloading, it can also effectively avoid the load circuit from remaining in the working state when it is no-load, causing work errors, and avoid unnecessary component losses.

[0042] It can be understood that the second threshold range can specifically be understood as a specific current threshold interval reasonably set so that when the first multi-phase interleaved conversion circuit 200 is no-load, that is, when the reference pulse current is zero, the load circuit 301 can exit the working state and maintain a specific standby state to cooperate with the first adjustment output sub-circuit 202 to wait for the first multi-phase interleaved conversion circuit 200 to quickly enter the working state again when reloading.

[0043] In addition, the first threshold range can also specifically be understood as a specific threshold interval reasonably set to ensure that the output current can be adjusted to within the second threshold range when it is no-load.

[0044] Moreover, since the first threshold range is set to ensure that the output current is limited within the second threshold range under no-load conditions, the actual corresponding adjusted output value of the first threshold range is negative. Limiting the adjusted output value within the first threshold range means that the adjusted output value is not lower than the lower limit value of the first threshold range, and this lower limit value is negative.

[0045] In some embodiments, the second threshold range is less than the rated output current of the first multi-phase interleaved conversion circuit 200 in a normal operating state. For example, the second threshold range can specifically be any reasonable proportional range such as 5% - 25%, 5% - 15%, or 10% - 30% of the rated output current. When under no-load conditions, it can maintain a certain output current to ensure that the output voltage is not lower than a specific voltage drop, such as the voltage drop to maintain the conduction of the diode in the load circuit or the voltage drop to maintain a certain level of energy storage, etc., any reasonable voltage drop. And at the same time, it does not cause the load circuit to be in a working state, thus avoiding working errors and unnecessary component losses. Specifically, it can be determined by the actual application scenario, and the present application does not make any limitations in this regard.

[0046] In the above solution, when the reference pulse current is zero, by limiting the adjusted output value and the controlled quantity of the first power switch sub-circuit 201, the output current is effectively adjusted within the second threshold range. This can not only meet the power supply demand in a timely manner when the first multi-phase interleaved conversion circuit 200 resumes loading, but also effectively avoid working errors caused by the load circuit 301 still remaining in the working state under no-load conditions, and avoid unnecessary component losses. And when there are different frequencies of the reference pulse current, by limiting the adjusted output value within the first threshold range, it also effectively ensures the consistency and stability of the output current during the rising stage when the first multi-phase interleaved conversion circuit 200 resumes loading, thus ensuring good power supply quality and power supply stability.

[0047] By real-time monitoring the output current and comparing it with the reference pulse current, it can quickly respond to load changes and keep the output current stable. The staggered operation among multiple first power switch sub-circuits 201 can effectively reduce the input / output ripple and improve the efficiency and stability of the system. By setting the first threshold range and the second threshold range, it ensures that the adjusted output value and the output current are always within a reasonable working range, avoiding problems such as overload or undervoltage. In a multi-phase Buck converter, multiple parallel Buck converters operate in a staggered manner to jointly share the load current. Through the above current adjustment method, efficient energy transfer can be achieved under different load conditions, and electromagnetic interference can be reduced. This method not only improves the control accuracy and stability of the first multi-phase interleaved conversion circuit 200, but also enhances the flexibility and adaptability of the system, and is applicable to various power electronics application fields.

[0048] Further, in one embodiment, before the above S13, it specifically further includes: setting a first threshold range by using a preset number and a second threshold range.

[0049] It can be understood that the feedback regulation of the output current is actually achieved by adjusting the switching states of the first power switch sub-circuits 201. Different controlled numbers of the first power switch sub-circuits 201 correspond to different adjustment amplitudes of the output current; and the drive control signal is generated from the adjusted output value, and the limit value of the adjusted output value will also directly affect the limit range of the output current. Therefore, in order to adjust the output current to within the second threshold range, it is also necessary to comprehensively consider the different limit ranges of the adjusted output value under the premise that different controlled numbers, that is, the preset number of the first power switch sub-circuits 201 are controlled by the drive control signal, so as to set the first threshold range by using the preset number and the second threshold range.

[0050] Please continue to refer to Figure 3 , Figure 3 is Figure 1 a schematic flowchart of an embodiment of S12 in S121: Subtract the output current from the reference pulse current to obtain an error value.

[0051] Specifically, the first current regulation circuit 100 subtracts the currently obtained output current from the reference pulse current to obtain an error value.

[0052] S122: Perform proportional-integral regulation on the error value to obtain an adjusted output value.

[0053] Further, a PID controller, a PI controller or any other reasonable feedback control algorithm is used to perform arithmetic processing on the error value to obtain an adjusted output value. The adjusted output signal reflects the energy level or direction that needs to be adjusted so that the output current approaches the reference pulse current.

[0054] Please refer to Figure 4 , Figure 4 is Figure 1 a schematic flowchart of an embodiment of S13 in S131: Obtain the falling edge and rising edge of the reference pulse current.

[0055] Please continue to refer to Figure 5 , Figure 5 is Figure 4Waveform diagram of a reference pulse current, an error value, and an adjusted output value in an embodiment.

[0056] It can be understood that since the reference pulse current is a pulse signal, there are transitions from a low level to a high level, i.e., rising edges, and from a high level to a low level, i.e., falling edges. Taking the high and low level transition moments of the reference pulse current, i.e., the falling edges and rising edges as boundaries, error values that are positive or negative will be obtained respectively, thus affecting subsequent adjustment control.

[0057] Specifically, the first current adjustment circuit 100 identifies and detects the falling edges and rising edges of the reference pulse current. For example, this goal can be achieved by any reasonable means such as a hardware circuit (such as an edge trigger), a software algorithm (for example, writing corresponding code in an embedded system), or a controller counter. The present application does not limit this.

[0058] S132: Start timing in response to the falling edge, and when the accumulated timing reaches a preset minimum duration, keep the current adjusted output value unchanged until the rising edge, so as to adjust the adjusted output value within the first threshold range.

[0059] Furthermore, when the falling edge of the reference pulse current is detected, start timing from the falling edge until the accumulated timing reaches the preset minimum duration t1, and maintain the adjusted output value at the current moment constant until the next rising edge of the reference pulse current arrives. That is, before the next rising edge arrives, ensure that the current adjusted output value does not increase negatively, so as not to exceed the first threshold range.

[0060] It can be understood that by setting to start timing at the falling edge of the reference pulse current, and when the accumulated timing reaches the preset minimum duration t1, keeping the current adjusted output value unchanged and not increasing negatively in cumulative integration until the next rising edge arrives, it is ensured that the adjusted output value has the same initial value when the next rising edge arrives, regardless of the different frequencies of the reference pulse current, that is, the duration from the current falling edge of the reference pulse current to the next rising edge, or the duration when the reference pulse current is zero current. Based on this same initial value, in response to the next rising edge, the error value between the current reference pulse current and the output current is again subjected to real-time proportional-integral adjustment to increase the adjusted output value. The sameness of the initial value effectively ensures the consistency and stability of the rising stage of the adjusted output value after the next rising edge arrives, and further ensures the consistency and stability of the adjustment of the output current by the drive control signal generated by this adjusted output value. That is, it ensures the consistency and stability of the rising stage of the output current in response to the arrival of the next rising edge of the reference pulse current.

[0061] In some embodiments, the preset minimum duration t1 is greater than or equal to the interval time between the falling edge of the reference pulse current and the starting moment when the error value changes to the third threshold range, and less than the minimum period time of the reference pulse current. This application does not make any limitations in this regard.

[0062] It should be noted that the third threshold range can be understood as the threshold interval when the error value enters the stable state when the reference pulse current is zero.

[0063] In addition, the minimum period time is determined by the power supply requirements of the load circuit 301. For example, the range of the output power requirement of the load circuit 301 determines the frequency range and the maximum frequency of the reference pulse current, and the minimum period time is obtained from the maximum frequency.

[0064] It can be understood that as Figure 5 shown, when the frequencies of the reference pulse currents are different, the durations when the reference pulse currents are zero are different, and the initial values of the regulated output values obtained from the error values when the rising edge of the reference pulse current arrives are different. As a result, the drive control signals obtained from the regulated output values are also different. Therefore, at low frequencies of the reference pulse current, the rising time of the regulated output value at the rising edge becomes longer, and there is a risk of causing the output current to drop and become unstable.

[0065] Therefore, by limiting that the regulated output value remains unchanged from the falling edge to the preset minimum duration t1, it is effectively ensured that the regulated output value has a constant initial value when the rising edge arrives at different frequencies of the reference pulse current, thereby effectively ensuring that the output current is regulated within the second threshold range and avoiding the situations of dropping and instability.

[0066] Please refer to Figure 6 , Figure 6 is Figure 4 a schematic flowchart of an embodiment of S132 in . In one embodiment, in addition to the above S131 - S132, the current regulation method of this application further includes some more specific steps. Specifically, the above S132 may further include the following steps: S1321: Start timing in response to the falling edge, and set the regulation flag bit low when the cumulative timing reaches the preset minimum duration.

[0067] It can be understood that to ensure that the regulated output value is not lower than the first threshold range at different frequencies of the reference pulse current, the first current regulation circuit 100 may specifically set a regulation flag bit to implement the control for restricting the regulated output value.

[0068] Specifically, the first current regulation circuit 100 starts timing when detecting the falling edge of the reference pulse current, and sets the regulation flag bit low when the accumulated timing reaches a preset minimum duration t1.

[0069] Wherein, the regulated output value specifically remains unchanged when the regulation flag bit is low, and is unrestricted when the regulation flag bit is high and follows the change of the error value.

[0070] S1322: Keep the current regulated output value unchanged.

[0071] When detecting that the regulation flag bit is low, keep the current regulated output value unchanged.

[0072] S1323: Set the regulation flag bit high in response to the rising edge, and obtain the regulated output value using the error value.

[0073] When detecting the rising edge of the reference pulse current, set the regulation flag bit high to recalculate the regulated output value using the currently obtained error value.

[0074] Please refer to Figure 7 , Figure 7 is a schematic flowchart of the second embodiment of the current regulation method of the present application. The current regulation method of this embodiment is Figure 1 a schematic flowchart of a refined embodiment of the current regulation method in S21: Obtain the output current of the regulated output sub-circuit.

[0075] Among them, S21 is the same as Figure 1 S11 in

[0076] Please refer to S11 and its related text description for details, which will not be elaborated here.

[0077] S22: Receive the power supply regulation signal sent by the host computer.

[0078] It should be noted that the host computer can be specifically understood as a system processor that monitors and controls the working state and application scenario of the load circuit 301 to determine the current power supply demand of the load circuit 301, such as the demand for output power of the load circuit 301, and then sets the current power supply regulation signal.

[0079] S23: Regulate the signal frequency of the reference pulse current in response to the power supply regulation signal.

[0080] Further, in response to the currently obtained power supply regulation signal, the signal frequency of the reference pulse current is adjusted to adjust the drive control signal obtained using the reference pulse current, thereby adjusting the output current to meet the power supply requirements of the load circuit 301.

[0081] S24: Obtain an adjustment output value using the error value between the reference pulse current and the output current.

[0082] S25: In response to the adjustment output value being lower than the first threshold range, adjust the adjustment output value to within the first threshold range.

[0083] S26: Generate a drive control signal using the adjustment output value.

[0084] S27: In response to the reference pulse current being zero, send the drive control signal to any preset number of power switch sub - circuits to adjust the output current to within the second threshold range.

[0085] Among them, S24, S25, S26, and S27 are the same as Figure 1 S12, S13, S14, and S15 in, and for specific details, please refer to S12, S13, S14, and S15 and their related textual descriptions, which will not be elaborated here.

[0086] Please refer to Figure 8 and Figure 9 , where Figure 8 is a schematic flowchart of the third implementation manner of the current regulation method of this application, Figure 9 is a schematic structural diagram of the second implementation manner of the current regulation circuit of this application. The current regulation method of this implementation manner is Figure 1 a schematic flowchart of a refined implementation manner of the current regulation method in, and specifically includes the following steps: S31: Obtain the output current of the adjustment output sub - circuit.

[0087] It can be understood that the current regulation method in this implementation manner can specifically perform current regulation on the second multi - phase interleaved conversion circuit 400 as shown in Figure 9 . Among them, the second multi - phase interleaved conversion circuit 400 includes a second power switch sub - circuit 401 and a second adjustment output sub - circuit 402 that are phase - coupled. The second power switch sub - circuit 401 specifically includes switching transistors Q1, Q2,..., Qn and diodes D1, D2,..., Dn, and the second adjustment output sub - circuit 402 includes inductors L1, L2,..., Ln and an output capacitor C.

[0088] In some embodiments, the second regulated output sub-circuit 402 is further configured to be coupled to the load circuit 301, and the load circuit 301 may specifically include equivalent diodes DF1, DF2, ..., DFn and a resistor Ro, or may include a circuit topology of a diode and any reasonable circuit elements such as a resistor, a capacitor, or an inductor. The present application does not limit this.

[0089] Among them, the first ends of the switching transistors Q1, Q2, ..., Qn are all configured to be coupled to the first end of the DC power supply DC. The second ends of the switching transistors Q1, Q2, ..., Qn are respectively coupled to the second ends of the diodes D1, D2, ..., Dn, and are respectively coupled to the first ends of the inductors L1, L2, ..., Ln. The third ends of the switching transistors Q1, Q2, ..., Qn are all coupled to a second current regulation circuit (not shown in the figure). The first ends of the diodes D1, D2, ..., Dn are all configured to be coupled to the second end of the DC power supply DC and the second end of the resistor Ro, and are coupled to the second end of the output capacitor C. The second ends of the inductors L1, L2, ..., Ln are all coupled to the first end of the output capacitor C and the first end of the equivalent diode DF1. The equivalent diodes DF1, DF2, ..., DFn are connected in series in sequence, and the second end of the equivalent diode DFn is coupled to the first end of the resistor Ro.

[0090] In some embodiments, the switching transistors Q1, Q2, ..., Qn may specifically be one of MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a bipolar transistor, a thin-film transistor, a field-effect transistor, or any other reasonable switching transistor. The present application does not limit this.

[0091] For convenience of description, taking the second multi-phase interleaved conversion circuit 400 specifically applied to a switched laser power supply as an example, that is, the load circuit 301 can be specifically understood as an equivalent circuit of a laser pumping circuit. Since the laser pumping circuit usually needs to obtain lasers with different wavelength frequencies in actual applications, the requirements for the output power of the second multi-phase interleaved conversion circuit 400 are also different. Correspondingly, in the feedback regulation of its output current Io, the frequency of the reference signal also needs to be adjusted according to different power supply requirements and is a pulse signal, that is, a reference pulse current.

[0092] It should be noted that due to the characteristics of the laser pumping circuit itself, which is a load similar to multiple diodes in series, when the reference pulse current is zero, the second multi-phase interleaved conversion circuit 400 needs to maintain a certain output current Io to ensure that the output voltage is not lower than the conduction voltage drop of each diode, and the output current Io cannot be higher than a specific threshold, otherwise the laser will emit light under no-load conditions. In this case, since the actual output current Io is greater than zero while the reference output current Io is zero, the error value between the two is always less than zero. After entering the PI feedback regulation loop, the anti-integration operation will be continuously performed. Since the anti-integration time is different at different frequencies of the reference pulse current, the lower the frequency, the greater the change in anti-integration and the smaller the integration. When the output current Io rises again, it will lead to different initial integration values, thereby resulting in different waveforms of the drive control signal, and causing the integration, that is, the pulse rise time of the regulated output value, to become longer at low frequencies, and situations such as the regulated output value and the output current Io dropping may occur.

[0093] Therefore, to address the problem that the output current Io cannot be higher than a specific threshold, some phases in the multi-phase can be made to work under no-load conditions to reduce the no-load output current Io. To solve the problem of different current rise times at different frequencies, it can be achieved by ensuring that the initial integration values are the same when the rising edges of the reference pulse current arrive at different frequencies.

[0094] Specifically, the second current regulation circuit samples and obtains the output current Io flowing through the resistor Ro.

[0095] S32: Obtain the regulated output value using the error value between the reference pulse current and the output current.

[0096] In some embodiments, the second current regulation circuit may specifically receive the set program instructions of the user, or the power supply regulation signal sent by the host computer according to its monitoring of the power supply demand of the laser pumping circuit, so as to set and adjust the reference pulse current, or directly receive the reference pulse current set and adjusted according to the corresponding power supply demand sent by the host computer. This application does not make any limitations on this.

[0097] The second current regulation circuit subtracts the output current Io from the currently obtained reference pulse current to obtain the error value, and uses a PID controller, a PI controller, or any other reasonable feedback control algorithm to perform arithmetic processing on the error value to obtain the regulated output value. This regulated output signal reflects the energy level or direction that needs to be adjusted to make the output current Io close to the reference pulse current.

[0098] S33: Obtain the falling edge of the reference pulse current.

[0099] Such as Figure 5As shown, the falling edge of the reference pulse current is detected in real time. For example, this can be achieved by any reasonable means such as a hardware circuit (e.g., an edge trigger), a software algorithm (e.g., writing corresponding code in an embedded system), or a controller counter. This application does not limit this.

[0100] S34: Start timing in response to the falling edge, so that when the accumulated timing reaches the preset minimum duration, the error value is adjusted to 0.

[0101] When the falling edge of the reference pulse current is detected, start timing from the falling edge as the starting moment. Until the accumulated timing reaches the preset minimum duration t1, the error value is adjusted to 0.

[0102] S35: Adjust the adjusted output value to within the first threshold range using the adjusted error value.

[0103] Obtain the adjusted output value using the adjusted error value. Since the error value is adjusted to 0 at this time, the adjusted output value remains constant at the value corresponding to the preset minimum duration t1, so as to maintain it within the first threshold range.

[0104] S36: Generate a drive control signal using the adjusted output value.

[0105] Generate a corresponding drive control signal according to the current adjusted output value.

[0106] It should be noted that when there are multiple controlled switching tubes, the drive control signal is actually also multiple, and the duty cycles of each drive control signal are the same, but the phases will correspond to switching tube Q1, switching tube Q2,..., switching tube Qn in turn, with a delay of 360 / n degrees.

[0107] S37: Send the drive control signal to any preset number of power switch sub - circuits in response to the falling edge, so as to adjust the output current to within the second threshold range.

[0108] When the falling edge of the reference pulse current is detected, specifically, this second current adjustment circuit sends the drive control signal to any preset number of switching tubes among switching tube Q1, switching tube Q2,..., switching tube Qn. For example, switching tube Q1, or switching tube Q2, or switching tube Q1 and switching tube Q2, or switching tube Q2 and switching tube Qn, etc., and block the wave for other switching tubes to reduce the output current Io and maintain it within the second threshold range.

[0109] S38: Obtain the rising edge of the reference pulse current.

[0110] Obtain the rising edge of the reference pulse current in real time.

[0111] S39: Send the drive control signal to each power switch sub - circuit in response to the rising edge.

[0112] When the rising edge of the reference pulse current is detected, that is, when the load circuit 301 needs to re - enter the working state to obtain the output current Io, the drive control signals are respectively sent to the switching transistor Q1, the switching transistor Q2,..., the switching transistor Qn. After the input of the DC power supply is regulated by the first multi - phase interleaved conversion circuit 200, the output current Io is provided to the load circuit 301.

[0113] This application also provides an electronic device. Please refer to Figure 10 , Figure 10 FIG. is a schematic structural diagram of an embodiment of the electronic device of this application. In this embodiment, the electronic device 40 includes a housing 41 and a third current regulation circuit 42 connected to the housing 41.

[0114] It should be noted that the third current regulation circuit 42 described in this embodiment is the first current regulation circuit 100 or the second current regulation circuit described in any one of the above - mentioned embodiments. For details, please refer to Figures 1 - 9 and the relevant text content, which will not be elaborated here.

[0115] The beneficial effects of this application are as follows: Different from the prior art, the current regulation method provided by this application obtains the output current of the regulated output sub - circuit, uses the error value between the reference pulse current and the output current to obtain the regulated output value, and in response to the regulated output value being lower than the first threshold range, adjusts the regulated output value to within the first threshold range. Then, the regulated output value is used to generate the drive control signal, and in response to the reference pulse current being zero, the drive control signal is sent to any preset number of power switch sub - circuits. Thus, when the reference pulse current is zero, by restricting the regulated output value and the controlled number of power switch sub - circuits, the output current can be effectively adjusted to within the second threshold range, which can not only meet the power supply requirements in a timely manner when the multi - phase interleaved conversion circuit re - loads, but also effectively avoid the working errors caused by the load circuit remaining in the working state when it is unloaded, and avoid unnecessary component losses. Moreover, when the reference pulse current has different frequencies, by restricting the regulated output value within the first threshold range, the consistency and stability of the output current during the rising stage when the multi - phase interleaved conversion circuit re - loads are effectively ensured, thus ensuring good power supply quality and power supply stability.

[0116] The above are only the embodiments of this application, and do not limit the patent scope of this application accordingly. Any equivalent structural or equivalent process transformation made by using the content of the specification and drawings of this application, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of this application.

Claims

1. A current regulation method is applied to the current regulation of a multi-phase interleaved conversion circuit. The multi-phase interleaved conversion circuit includes a power switch sub-circuit and a regulated output sub-circuit that are phase-coupled. The number of the power switch sub-circuits is at least two, and it is characterized in that, The described current regulation method includes: Obtaining the output current of the regulation output sub - circuit; Obtaining a regulation output value using the error value between the reference pulse current and the output current; In response to the regulation output value being lower than the first threshold range, adjusting the regulation output value to within the first threshold range; the step of in response to the regulation output value being lower than the first threshold range and adjusting the regulation output value to within the first threshold range includes: obtaining the falling edge and rising edge of the reference pulse current; starting to time in response to the falling edge, and when the cumulative timing reaches a preset minimum duration, keeping the current regulation output value unchanged until the rising edge to adjust the regulation output value to within the first threshold range; wherein, the reference pulse current has different signal frequencies; Generating a drive control signal using the regulation output value; In response to the reference pulse current being zero, sending the drive control signal to any preset number of the power switch sub - circuits to adjust the output current to within a second threshold range; wherein, the preset number is less than the total number of the power switch sub - circuits.

2. The current regulation method according to claim 1, characterized in that Before the step of obtaining a regulation output value using the error value between the reference pulse current and the output current, it further includes: Receiving a power supply regulation signal sent by the host computer; Adjusting the signal frequency of the reference pulse current in response to the power supply regulation signal.

3. The current regulation method according to claim 1, characterized in that Before the step of in response to the regulation output value being lower than the first threshold range and adjusting the regulation output value to within the first threshold range, it further includes: Setting the first threshold range using the preset number and the second threshold range.

4. The current regulation method according to claim 1, wherein The step of in response to the regulation output value being lower than the first threshold range and adjusting the regulation output value to within the first threshold range includes: Obtaining the falling edge of the reference pulse current; Starting to time in response to the falling edge, and when the cumulative timing reaches a preset minimum duration, adjusting the error value to 0; Adjusting the regulation output value to within the first threshold range using the adjusted error value.

5. The current regulation method according to claim 4, wherein The step of in response to the reference pulse current being zero and sending the drive control signal to any preset number of the power switch sub - circuits includes: Sending the drive control signal to any of the preset number of the power switch sub - circuits in response to the falling edge.

6. The current regulation method according to claim 5, wherein After the step of in response to the falling edge and sending the drive control signal to any one of the preset number of the power switch sub - circuits, it further includes: Obtaining the rising edge of the reference pulse current; Sending the drive control signal to each of the power switch sub - circuits in response to the rising edge.

7. According to the current regulation method described in claim 4, characterized in that, The preset minimum duration is greater than or equal to the interval time between the falling edge and the starting moment when the error value is within the third threshold range, and less than the minimum period time of the reference pulse current.

8. The current regulation method according to claim 1, wherein The step of starting to time in response to the falling edge, and when the cumulative timing reaches a preset minimum duration, keeping the current regulation output value unchanged until the rising edge includes: Start timing in response to the falling edge, and when the accumulated timing reaches the preset minimum duration, set the adjustment flag bit low; Keep the current adjustment output value unchanged; Set the adjustment flag bit high in response to the rising edge, and obtain the adjustment output value by using the error value.

9. The current regulation method according to any one of claims 1-8, characterized in that, The obtaining of the adjustment output value by using the error value between the reference pulse current and the output current includes: Subtract the output current from the reference pulse current to obtain the error value; Perform proportional-integral adjustment on the error value to obtain the adjustment output value.

10. A current regulation circuit, characterized in that, The current adjustment circuit is coupled to the multi-phase interleaved conversion circuit; Wherein, the current adjustment circuit adjusts the current of the multi-phase interleaved conversion circuit by using the current adjustment method described in any one of claims 1-9.

11. An electronic device, characterized in that, The electronic device includes a housing and a current adjustment circuit connected to the housing; Wherein, the current adjustment circuit is the current adjustment circuit described in claim 10.

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