Pulse width compensation method, electronic equipment and storage medium
By obtaining the ripple voltage during the transformer excitation, the magnetic saturation problem caused by the transformer bias is solved in the bridge circuit, and simple and effective bias suppression is achieved, which improves the reliability of the circuit.
Patent Information
- Application Number
- CN202410225862.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-29
- Publication Date
- 2025-07-22
AI Technical Summary
The bias of the transformer in the bridge circuit causes the transformer to enter the magnetic saturation area, causing damage to the switch tube. The prior art increases the circuit complexity and cost by connecting series isolation capacitors.
By obtaining the ripple voltage when the transformer is excitated in the positive and negative directions, the bias magnetic compensation amount is calculated, and the duty cycle signal is compensated to suppress the bias magnetic of the transformer.
Effectively suppress the transformer's bias, avoiding the size and cost problems caused by increasing the device, and maintaining the biased bias suppression effect when the input voltage is stable or transient, improving reliability.
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Figure CN120357754A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of power electronics technology, and in particular, to a method for pulse width compensation, an electronic device, and a storage medium. Background Art
[0002] In the field of power electronics technology, a bridge circuit is a common conversion circuit, which can be applied to a power converter, for example. During the operation of the bridge circuit, due to the fact that the PWM (Pulse-width modulation) signal and the circuit hardware parameters cannot be exactly the same, it may lead to an imbalance in the magnetizing volt-second product of the positive and negative half-cycles of the transformer. This imbalance in the magneto-volt-second product will cause the phenomenon of transformer bias magnetization. When the bias magnetization is severe, the transformer will enter the magnetic saturation region, and the magnetic saturation of the transformer is equivalent to a short circuit of the winding, resulting in a sharp increase in the current flowing through the switching tube, causing overcurrent or short circuit protection, and even may cause damage to the switching tube.
[0003] In the related art, usually a DC-blocking capacitor is connected in series with the primary transformer winding of the bridge circuit. Although it has a certain anti-bias magnetization effect, it increases the complexity of the circuit, and at the same time increases the volume and cost of the converter. Summary of the Invention
[0004] The purpose of the embodiments of the present disclosure is to provide a method for pulse width compensation, an electronic device, and a storage medium.
[0005] To solve the above technical problems, the embodiments of the present disclosure are achieved through the following aspects.
[0006] According to a first aspect of the embodiments of the present disclosure, a method for pulse width compensation is provided. A first ripple voltage during positive excitation of the transformer and a second ripple voltage during negative excitation of the transformer are obtained; a first bias magnetization compensation amount during positive excitation of the transformer and a second bias magnetization compensation amount during negative excitation of the transformer are determined according to the first ripple voltage and the second ripple voltage; and the duty cycle signal amount of the loop output of the transformer is compensated according to the first bias magnetization compensation amount and the second bias magnetization compensation amount to suppress the bias magnetization of the transformer.
[0007] According to a second aspect of the embodiments of the present disclosure, an electronic device is provided, including: a processor; a memory for storing executable instructions of the processor; a sampling module for sampling the bus voltage according to the control of the processor; a driving module for exciting and driving a switching tube according to the control of the processor; wherein, the processor is configured to perform the following operations: obtaining a first ripple voltage during positive excitation of a transformer in a power converter and a second ripple voltage during negative excitation of the transformer; determining a first bias magnetic compensation amount during positive excitation of the transformer and a second bias magnetic compensation amount during negative excitation of the transformer according to the first ripple voltage and the second ripple voltage; compensating a duty cycle signal amount output by a loop of the transformer according to the first bias magnetic compensation amount and the second bias magnetic compensation amount to suppress the bias magnetic of the transformer.
[0008] According to a third aspect of the embodiments of the present disclosure, a computer-readable storage medium is provided, where the computer-readable storage medium stores one or more programs, and when the one or more programs are executed by an electronic device including a plurality of application programs, the electronic device is caused to execute the steps of the pulse width compensation method described in the first aspect.
[0009] One of the above technical solutions has the following advantages or beneficial effects: it can effectively suppress the bias magnetic of the transformer with a simple solution. On the one hand, no additional devices need to be added, overcoming the problem of increased volume and cost of the converter caused by series isolation capacitors in the related art. On the other hand, it can be applied to occasions where the input voltage is stable or there are input voltage transients, so that the effect of bias magnetic suppression is not affected by the input voltage, further improving reliability.
[0010] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure.
[0011] Other features and advantages of the present disclosure will be described in detail in the following specific implementation section. BRIEF DESCRIPTION OF THE DRAWINGS
[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.
[0013] Figure 1 A schematic flowchart showing a method for pulse width compensation provided by an embodiment of the present disclosure;
[0014] Figure 2Schematic diagram of input capacitor voltage without bias magnetic field provided by an embodiment of the present disclosure;
[0015] Figure 3 Schematic diagram of input capacitor voltage with bias magnetic field provided by an embodiment of the present disclosure;
[0016] Figure 4 Another schematic flow diagram of the pulse width compensation method provided by an embodiment of the present disclosure;
[0017] Figure 5 Another schematic flow diagram of the pulse width compensation method provided by an embodiment of the present disclosure;
[0018] Figure 6 Implementation block diagram of the pulse width compensation method provided by an embodiment of the present disclosure;
[0019] Figure 7 Another schematic flow diagram of the pulse width compensation method provided by an embodiment of the present disclosure;
[0020] Figure 8 Another schematic flow diagram of the pulse width compensation method provided by an embodiment of the present disclosure;
[0021] Figure 9 Another schematic flow diagram of the pulse width compensation method provided by an embodiment of the present disclosure;
[0022] Figure 10 Another schematic flow diagram of the pulse width compensation method provided by an embodiment of the present disclosure;
[0023] Figure 11 Circuit diagram of an isolated bridge circuit provided by an embodiment of the present disclosure;
[0024] Figure 12 Circuit diagram of a non-isolated bridge circuit provided by an embodiment of the present disclosure;
[0025] Figure 13 Hardware structure schematic diagram of an electronic device for executing the pulse width compensation method provided by an embodiment of the present disclosure. Detailed implementation manners
[0026] In order to enable those skilled in the art to better understand the technical solutions in the present disclosure, the following will clearly and completely describe the technical solutions in the embodiments of the present disclosure with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present disclosure.
[0027] Figure 1A schematic flowchart of a method for pulse width compensation provided by an embodiment of the present disclosure is shown. As Figure 1 shown, the method may include the following steps:
[0028] In step S101, a first ripple voltage during the positive excitation of the transformer and a second ripple voltage during the negative excitation of the transformer are obtained.
[0029] Wherein, the first ripple voltage is used to measure the voltage fluctuation during the positive excitation of the transformer, and the second ripple voltage is used to measure the voltage fluctuation during the negative excitation of the transformer.
[0030] In some possible implementation manners, the difference between the input capacitor voltages during the positive excitation and the negative excitation may be used to characterize the first ripple voltage and the second ripple voltage.
[0031] Figure 2 A schematic diagram of the input capacitor voltage without bias magnetic is shown. As Figure 2 shown, when there is no bias magnetic, the amplitude of the primary current of the voltage transformer is balanced in the positive and negative half-cycles. Since the discharge currents of the input capacitor in the positive and negative half-cycles are the same, the input capacitor voltage 1 is substantially equivalent during the positive half-cycle excitation drive and the negative half-cycle excitation drive. The first ripple voltage may be characterized as the voltage difference between the first moment 21 and the second moment 22 during the positive half-cycle excitation drive, and the second ripple voltage may be characterized as the voltage difference between the third moment 23 and the fourth moment 24 during the negative half-cycle excitation drive. When there is no bias magnetic, the first ripple voltage and the second ripple voltage are substantially balanced.
[0032] Figure 3 A schematic diagram of the input capacitor voltage with bias magnetic is shown. As Figure 3 shown, when there is bias magnetic, the amplitude of the primary current of the transformer is unbalanced in the positive and negative half-cycles. Therefore, the discharge currents of the input capacitor in the positive and negative half-cycles are different, resulting in different ripple voltages of the input capacitor. When there is bias magnetic, the first ripple voltage and the second ripple voltage are unbalanced.
[0033] Figure 4 Another schematic flowchart of the method for pulse width compensation provided by an embodiment of the present disclosure is shown. As Figure 4 shown, the first ripple voltage and the second ripple voltage can be obtained through the following steps:
[0034] In step S1011, a first positive excitation voltage and a second positive excitation voltage are respectively obtained at a preset first moment and a second moment during the positive excitation of the transformer.
[0035] In some possible implementation manners, any one of the methods shown in Table 1 may be adopted to select the first moment and the second moment, where T1 is the moment when the positive excitation drive is turned on, and T is the period of the full bridge.
[0036] The first moment The second moment Method 1 T1 + 0.05T T1 + 0.3T Method 2 T1 + 0.01T T1 + 0.35T Method 3 T1 + 0.03T T1 + 0.25T Method 4 T1 + 0.08T T1 + 0.45T
[0037] It can be understood that those skilled in the art can also flexibly adopt other methods to determine the above-mentioned first moment and second moment with reference to the examples in Table 1, and the present application does not limit this.
[0038] After determining the above-mentioned first moment and second moment, the input capacitor voltage corresponding to the first moment can be used as the first positive excitation voltage, and the input capacitor voltage corresponding to the second moment can be used as the second positive excitation voltage.
[0039] In step S1012, the difference between the first positive excitation voltage and the second positive excitation voltage is used as the first ripple voltage.
[0040] In some possible implementation manners, the first ripple voltage can be determined by the following formula (1).
[0041] V pp1 = U1 - U2 (formula (1))
[0042] Wherein, V pp1 is the first ripple voltage, U1 is the first positive excitation voltage, and U2 is the second positive excitation voltage.
[0043] In step S1013, a first negative excitation voltage and a second negative excitation voltage are respectively obtained at a preset third moment and a fourth moment during the negative excitation of the transformer.
[0044] Wherein, the deviation of the third moment relative to the negative excitation start moment is equal to the deviation of the first moment relative to the positive excitation start moment, and the deviation of the fourth moment relative to the negative excitation start moment is equal to the deviation of the second moment relative to the positive excitation start moment. The corresponding first moment, second moment, third moment, and fourth moment can be determined by the corresponding manner in Table 1 and Table 2. For example, the first moment and the second moment are determined by the first method in Table 1, and the corresponding third moment and fourth moment are determined by the corresponding first method in Table 2.
[0045] In some possible implementation manners, multiple methods shown in Table 2 can be adopted to select the third moment and the fourth moment, wherein, T2 is the moment when the negative excitation drive is turned on, and T is the period of the full bridge.
[0046] The third moment The fourth moment Method 1 T2 + 0.05T T2 + 0.3T Method 2 T2 + 0.01T T2 + 0.35T Method 3 T2 + 0.03T T2 + 0.25T Method 4 T2 + 0.08T T2 + 0.45T
[0047] In step S1014, the difference between the first negative excitation voltage and the second negative excitation voltage is used as the second ripple voltage.
[0048] In some possible implementation manners, the second ripple voltage can be determined by the following formula (2).
[0049] V pp2 = U3 - U4 (Equation 2)
[0050] where V pp2 is the second ripple voltage, U3 is the first negative exciting voltage, and U4 is the second negative exciting voltage.
[0051] In step S102, the first magnetic bias compensation amount during the positive excitation of the transformer and the second magnetic bias compensation amount during the negative excitation of the transformer are determined according to the first ripple voltage and the second ripple voltage.
[0052] In some embodiments, the input capacitance discharge characteristic can be utilized to determine the first magnetic bias compensation amount during the positive excitation of the transformer and the second magnetic bias compensation amount during the negative excitation of the transformer based on the difference between the input first ripple voltage and the second ripple voltage, so as to achieve pulse width compensation to suppress the magnetic bias of the transformer.
[0053] Figure 5 Another schematic flowchart of the pulse width compensation method provided by the embodiments of the present disclosure is shown. As Figure 5 shown, step S102 may include the following steps:
[0054] In step S1021, the ripple voltage difference is obtained according to the first ripple voltage and the second ripple voltage.
[0055] In some embodiments, the following Equation 3 can be used to determine the ripple voltage difference.
[0056] ΔV1 = V pp1 - V pp2 (Equation 3)
[0057] where ΔV1 is the ripple voltage difference, V pp1 is the first ripple voltage, and V pp2 is the second ripple voltage.
[0058] In step S1022, the ripple voltage difference is processed to obtain the compensation information amount.
[0059] In some embodiments, the ripple voltage difference is processed by at least one of amplification, filtering, and limiting to obtain the compensation information amount.
[0060] Exemplarily, the amplification can be multiplying the ripple voltage difference ΔV1 by a preset coefficient K to obtain ΔV2. The coefficient K is usually greater than or equal to 1 and can be selected according to the calculation and measurement accuracy.
[0061] The filtering may include: filtering with a preset filtering coefficient to obtain ΔV3. For example, any filtering algorithm such as sliding mode filtering can be used for filtering. The present disclosure does not limit the filtering algorithm.
[0062] The clipping may include, for example, limiting the maximum or minimum value of ΔV3 to obtain the final compensated information amount ΔV3.
[0063] In step S1023, a first bias magnetic compensation amount and a second bias magnetic compensation amount are determined according to the compensated information amount.
[0064] In step S103, the duty ratio signal amount of the loop output of the transformer is compensated according to the first bias magnetic compensation amount and the second bias magnetic compensation amount to suppress the bias magnetic of the transformer.
[0065] Figure 6 The implementation block diagram showing the pulse width compensation method provided by the embodiments of the present disclosure is as Figure 6 shown. After obtaining the first bias magnetic compensation amount and the second bias magnetic compensation amount, the following technical solution can be adopted to compensate the duty ratio signal amount of the loop output of the transformer to suppress the bias magnetic of the transformer.
[0066] Exemplarily, the first bias magnetic compensation amount Δd1 can be superimposed on the duty ratio signal amount D and output to the switching tube for positive excitation, and the second bias magnetic compensation amount Δd2 can be superimposed on the duty ratio signal amount D and output to the switching tube for negative excitation.
[0067] One of the above technical solutions has the following advantages or beneficial effects. It can effectively suppress the bias magnetic of the transformer with a simple solution. On the one hand, no additional devices need to be added, overcoming the problem of increased volume and cost of the converter caused by the series isolation capacitor in the related technology. On the other hand, it can be applied to the occasions where the input voltage is stable or there are transient changes in the input voltage, so that the effect of bias magnetic suppression is not affected by the input voltage, further improving the reliability.
[0068] Figure 7 The flow diagram showing another process of the pulse width compensation method provided by the embodiments of the present disclosure is as Figure 7 shown. Step S1023 may include the following steps:
[0069] Step 100: When the absolute value of the compensated information amount is greater than the first threshold, set the first bias magnetic compensation amount to the first preset value and set the second bias magnetic compensation amount to the second preset value.
[0070] Exemplarily, the first threshold may be 16 mV, the first preset value may be 0 ns, and the second preset value may be 0 ns. In some possible implementation manners, when the absolute value of the compensated information amount is greater than the first threshold, it indicates that the difference between the first ripple voltage and the second ripple voltage is too large, and an alarm of power supply abnormality can be displayed to the user.
[0071] Step 101: When the absolute value of the compensation information amount is less than or equal to the second threshold, keep the first bias magnetic compensation amount and the second bias magnetic compensation amount unchanged.
[0072] Wherein, the first threshold is greater than the second threshold.
[0073] Exemplarily, the second threshold may be 2 mV. When the absolute value of the compensation information amount is less than or equal to the second threshold, it indicates that the difference between the first ripple voltage and the second ripple voltage is small, the primary current of the transformer has balanced amplitudes in the positive and negative half-cycles, the power supply operates in a magnetic flux balance state, and there is no need to suppress the bias magnetic field for the drive of positive and negative excitation. In some possible implementation manners, the magnetic flux balance flag bit may also be set, and / or a prompt message of magnetic flux balance may be displayed to the user.
[0074] Step 102: When the compensation information amount is less than or equal to the first threshold and greater than the second threshold, reduce the second bias magnetic compensation amount or increase the first bias magnetic compensation amount.
[0075] Specifically, Figure 8 Another flowchart showing the pulse width compensation method provided by the embodiments of the present disclosure is as Figure 8 shown. In step 102, the second bias magnetic compensation amount can be reduced or the first bias magnetic compensation amount can be increased through the following steps:
[0076] Step 1021: When the second bias magnetic compensation amount is greater than the first compensation threshold, update the second bias magnetic compensation amount with the difference between the second bias magnetic compensation amount and the first preset compensation adjustment amount, and update the first bias magnetic compensation amount with the first preset compensation value.
[0077] Exemplarily, the first compensation threshold may be 0 ns, the first preset compensation adjustment amount may be 0.25 ns, and the first preset compensation value may be 0 ns. The above update process can be expressed by the following formula four:
[0078]
[0079] Step 1022: When the second bias magnetic compensation amount is less than or equal to the first compensation threshold and the first bias magnetic compensation amount is less than the second compensation threshold, update the first bias magnetic compensation amount with the sum of the first bias magnetic compensation amount and the second preset compensation adjustment amount, and update the second bias magnetic compensation amount with the second preset compensation value.
[0080] Wherein, the second compensation threshold is greater than the first compensation threshold.
[0081] Exemplarily, the second compensation threshold may be 50 ns, the second preset compensation adjustment amount may be 0.25 ns, and the second preset compensation value may be 0 ns. The above update process can be expressed by the following formula five:
[0082]
[0083] Step 1023: When the second bias compensation amount is less than or equal to the first compensation threshold and the first bias compensation amount is greater than or equal to the second compensation threshold, update the second bias compensation amount with the first compensation threshold and update the first bias compensation amount with the second compensation threshold. The above update process can be represented by the following Formula 6:
[0084]
[0085] In some possible implementation manners, when the second bias compensation amount is less than or equal to the first compensation threshold and the first bias compensation amount is greater than or equal to the second compensation threshold, since the magnetic flux balance function has reached the limit and no longer compensates for the magnetic flux balance, the bias function saturation flag bit can be set and / or a prompt message indicating the saturation of the bias function can be displayed to the user.
[0086] Step 103: When the compensation information amount is greater than or equal to the third threshold and less than the fourth threshold, decrease the first bias compensation amount or increase the second bias compensation amount.
[0087] Wherein, the third threshold is the opposite number of the first threshold, and the fourth threshold is the opposite number of the second threshold. For example, when the first threshold is 16 mV, the third threshold can be -16 mV, and when the second threshold is 2 mV, the fourth threshold can be -2 mV.
[0088] Specifically, Figure 9 Another flow schematic diagram showing the pulse width compensation method provided by the embodiments of the present disclosure is shown as Figure 9 shown. In Step 103, the first bias compensation amount can be decreased or the second bias compensation amount can be increased through the following steps:
[0089] Step 1031: When the first bias compensation amount is greater than the third compensation threshold, update the first bias compensation amount with the difference between the first bias compensation amount and the third preset compensation adjustment amount, and update the second bias compensation amount with the third preset compensation value.
[0090] For example, the third compensation threshold can be 0 ns, the third preset compensation adjustment amount can be 0.25 ns, and the third preset compensation value can be 0 ns. The above update process can be represented by the following Formula 7:
[0091]
[0092] Step 1032: When the first bias magnetic compensation amount is less than or equal to the third compensation threshold and the second bias magnetic compensation amount is less than the fourth compensation threshold, update the second bias magnetic compensation amount with the sum of the second bias magnetic compensation amount and the fourth preset compensation adjustment amount, and update the first bias magnetic compensation amount with the fourth preset compensation value.
[0093] Among them, the fourth compensation threshold is greater than the third compensation threshold.
[0094] Exemplarily, the fourth compensation threshold can be 50 ns, the fourth preset compensation adjustment amount can be 0.25 ns, and the fourth preset compensation value can be 0 ns. The above update process can be expressed by the following formula eight:
[0095]
[0096] Step 1033: When the first bias magnetic compensation amount is less than or equal to the third compensation threshold and the second bias magnetic compensation amount is greater than or equal to the fourth compensation threshold, update the first bias magnetic compensation amount with the third compensation threshold and update the second bias magnetic compensation amount with the fourth compensation threshold.
[0097] The above update process can be expressed by the following formula nine:
[0098]
[0099] In some possible implementation manners, when the first bias magnetic compensation amount is less than or equal to the third compensation threshold and the second bias magnetic compensation amount is greater than or equal to the fourth compensation threshold, since the magnetic flux balance function has reached the limit and the compensation of the magnetic flux balance is no longer performed, the bias magnetic function saturation flag bit can be set and / or a prompt message indicating the saturation of the bias magnetic function can be displayed to the user.
[0100] It can be understood that the above first compensation threshold, second compensation threshold, third compensation threshold, fourth compensation threshold, first preset compensation value, second preset compensation value, third preset compensation value, fourth preset compensation value, first preset compensation adjustment amount, second preset compensation adjustment amount, third preset compensation adjustment amount, fourth preset compensation adjustment amount, first threshold, second threshold, third threshold, and fourth threshold can all be flexibly adjusted according to the needs of the actual circuit design.
[0101] It can be understood that when the transformer is powered on, the first bias magnetic compensation amount and the second bias magnetic compensation amount can be set to preset initial values, such as 0 ns.
[0102] Another technical solution in the above technical solutions has the following advantages or beneficial effects. The first bias magnetic compensation amount and the second bias magnetic compensation amount are obtained through iterative calculation, and the duty cycle signal amount of the loop output of the transformer is compensated according to the first bias magnetic compensation amount and the second bias magnetic compensation amount, which can effectively suppress the bias magnetic of the transformer with a simple solution. On the one hand, no additional devices need to be added, overcoming the problem of increased volume and cost of the converter caused by the series isolation capacitor in the related technology. On the other hand, it can be applied to the occasions where the input voltage is stable or there are transients in the input voltage, so that the effect of bias magnetic suppression is not affected by the input voltage, further improving the reliability.
[0103] Figure 10 Another schematic flowchart showing the pulse width compensation method provided by the embodiments of the present disclosure is as follows Figure 10 shown, in combination with Figures 7 - 9 . The method specifically includes the following steps:
[0104] In step 201, a first ripple voltage and a second ripple voltage are obtained.
[0105] In step 202, a ripple voltage difference ΔV1 is obtained.
[0106] Exemplarily, the ripple voltage difference ΔV1 can be obtained according to the first ripple voltage and the second ripple voltage through Formula 3.
[0107] In step 203, a compensation information amount ΔV3 is obtained.
[0108] Exemplarily, the compensation information amount ΔV3 can be obtained through at least one of amplification, filtering, and limiting.
[0109] In step 204, when the absolute value of the compensation information amount is greater than 16 mV, the first bias magnetic compensation amount is set to 0 ns, and the second bias magnetic compensation amount is set to 0 ns.
[0110] In step 205, when the absolute value of the compensation information amount is greater than 16 mV, a power supply abnormality alarm is displayed.
[0111] Since the difference between the first ripple voltage and the second ripple voltage is too large, an alarm of power supply abnormality can be displayed to the user.
[0112] In step 206, when the absolute value of the compensation information amount is less than or equal to 2 mV, the first bias magnetic compensation amount and the second bias magnetic compensation amount are kept unchanged.
[0113] In step 207, a magnetic flux balance flag bit is set.
[0114] Since the difference between the first ripple voltage and the second ripple voltage is small, the magnitude of the primary current of the transformer is balanced in the positive and negative half-cycles, and no bias magnetic suppression is required. In some possible implementation manners, a prompt message of flux balance can also be displayed to the user.
[0115] In step 208, when the compensation information amount is greater than 2 mV and less than or equal to 16 mV, and the second bias magnetic compensation amount is greater than 0 ns, set the updated first bias magnetic compensation amount Δd1 to 0 ns, and use the difference between the current second bias magnetic compensation amount Δd2 and 0.25 ns as the updated second bias magnetic compensation amount Δd2.
[0116] In step 209, when the compensation information amount is greater than 2 mV and less than or equal to 16 mV, the second bias magnetic compensation amount Δd2 is less than or equal to 0 ns, and the first bias magnetic compensation amount Δd1 is less than 50 ns, use the sum of the current first bias magnetic compensation amount Δd1 and 0.25 ns as the updated first bias magnetic compensation amount Δd1, and set the updated second bias magnetic compensation amount Δd2 to 0.
[0117] In step 210, when the compensation information amount is greater than 2 mV and less than or equal to 16 mV, the second bias magnetic compensation amount is less than or equal to 0 ns, and the first bias magnetic compensation amount is greater than or equal to 50 ns, set the first bias magnetic compensation amount Δd1 to 50 ns, and set the second bias magnetic compensation amount Δd2 to 0 ns.
[0118] In step 211, since the flux balance function has reached its limit and no longer performs flux balance compensation, the bias magnetic function saturation flag bit can be set.
[0119] In step 212, when the compensation information amount is greater than -16 mV and less than or equal to -2 mV, and the first bias magnetic compensation amount is greater than 0 ns, use the difference between the current first bias magnetic compensation amount Δd1 and 0.25 ns as the updated first bias magnetic compensation amount Δd1, and set the updated second bias magnetic compensation amount Δd2 to 0.
[0120] In step 213, when the compensation information amount is greater than -16 mV and less than or equal to -2 mV, the first bias magnetic compensation amount is less than or equal to 0 ns, and the second bias magnetic compensation amount is less than 50 ns, set the updated first bias magnetic compensation amount Δd1 to 0, and use the sum of the current second bias magnetic compensation amount Δd2 and 0.25 ns as the updated second bias magnetic compensation amount Δd2.
[0121] In step 214, when the compensated information amount is -16 mV and less than or equal to -2 mV, the first bias magnetic compensation amount Δd1 is less than or equal to 0 ns, and the second bias magnetic compensation amount Δd2 is greater than or equal to 50 ns, set the first bias magnetic compensation amount Δd1 to 0 ns and set the second bias magnetic compensation amount Δd2 to 50 ns.
[0122] In step 215, since the flux balance function has reached its limit and no further flux balance compensation is performed, the bias magnetic function saturation flag bit can be set to end the process.
[0123] Another technical solution in the above technical solutions has the following advantages or beneficial effects. It can effectively suppress the bias magnetism of the transformer with a simple solution. On the one hand, no additional devices need to be added, overcoming the problem of increased volume and cost of the converter caused by the series isolation capacitor in the related technology. On the other hand, it can be applied to occasions where the input voltage is stable or there are input voltage transients, so that the effect of bias magnetism suppression is not affected by the input voltage, further improving the reliability.
[0124] According to the differences of specific bridge circuits, various methods can be adopted to obtain the first positive excitation voltage, the second positive excitation voltage, the first negative excitation voltage, and the second negative excitation voltage. Figure 11 The circuit diagram of an isolated bridge circuit provided by an embodiment of the present disclosure is shown as Figure 11 shown. In some embodiments, the first positive excitation voltage, the second positive excitation voltage, the first negative excitation voltage, and the second negative excitation voltage can be obtained through the first sampling point 11 set at the positive end of the input capacitor of the isolated bridge circuit.
[0125] In another embodiment, the first positive excitation voltage and the second positive excitation voltage can be obtained through the second sampling point 12 set on the primary full-bridge arm of the isolated bridge circuit, and the first negative excitation voltage and the second negative excitation voltage can be obtained through the third sampling point 13 set on the primary full-bridge arm of the isolated bridge circuit.
[0126] In another embodiment, the first positive excitation voltage and the second positive excitation voltage can be obtained through the fourth sampling point 14 set on the secondary full-bridge arm of the isolated bridge circuit, and the first negative excitation voltage and the second negative excitation voltage can be obtained through the fifth sampling point 14 set on the secondary full-bridge arm of the isolated bridge circuit.
[0127] In another embodiment, the first positive excitation voltage, the second positive excitation voltage, the first negative excitation voltage, and the second negative excitation voltage are obtained through the sixth sampling point 16 after rectification of the secondary bridge arm of the isolated bridge circuit.
[0128] Figure 12The circuit diagram of a non-isolated bridge circuit provided by an embodiment of the present disclosure is shown. As Figure 12 shown, the first positive excitation voltage, the second positive excitation voltage, the first negative excitation voltage, and the second negative excitation voltage can be obtained through the seventh sampling point 17 after rectification of the secondary bridge arm of the non-isolated bridge circuit.
[0129] Another technical solution in the above technical solutions has the following advantages or beneficial effects. It can effectively suppress the bias magnetism of the transformer with a simple solution. On the one hand, no additional devices need to be added, overcoming the problem of increased volume and cost of the converter caused by the series isolation capacitor in the related technology. On the other hand, it can be applied to the occasions where the input voltage is stable or there are transient changes in the input voltage, so that the effect of bias magnetism suppression is not affected by the input voltage, further improving the reliability.
[0130] Figure 13 The schematic diagram of the hardware structure of an electronic device provided by an embodiment of the present disclosure is shown. As Figure 13 shown, at the hardware level, the electronic device includes at least one processor. Optionally, it includes an internal bus, a network interface, and a memory. Among them, the memory may include internal memory, such as high-speed random access memory (RAM), and may also include non-volatile memory, such as at least one disk memory, etc. Of course, the electronic device may also include other hardware required for other services.
[0131] The processor, the network interface, and the memory can be interconnected through the internal bus. The internal bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of simplicity, only a bidirectional arrow is used in this figure to represent it, but it does not mean that there is only one bus or one type of bus.
[0132] The memory stores the program. Specifically, the program may include program code, and the program code includes at least one computer operation instruction. The memory can include internal memory and non-volatile memory, and provide instructions and data to the processor.
[0133] At least one processor reads the corresponding computer program from the non-volatile memory into the memory and then runs it, forming a device for locating the target user at the logical level. At least one processor executes the program stored in the memory and specifically executes: the method disclosed in the embodiments shown in the first aspect and realizes the functions and beneficial effects of the various methods described in the foregoing method embodiments, which will not be elaborated herein.
[0134] The method disclosed in the embodiments shown in the first aspect of the present disclosure can be applied to or implemented by at least one processor. The processor may be an integrated circuit chip with signal processing capabilities. In the implementation process, the steps of the foregoing method can be completed by the integrated logic circuit in the hardware of at least one processor or instructions in software form. The foregoing processor may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. It can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present disclosure. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in combination with the embodiments of the present disclosure can be directly embodied as being executed and completed by a hardware decoding processor, or executed and completed by a combination of hardware and software modules in the decoding processor. The software module may be located in a mature storage medium in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. This storage medium is located in the memory, and the processor reads the information in the memory and combines its hardware to complete the steps of the foregoing method.
[0135] The electronic device can also execute the various methods described in the foregoing method embodiments and realize the functions and beneficial effects of the various methods described in the foregoing method embodiments, which will not be elaborated herein.
[0136] Of course, in addition to the software implementation, the electronic device of the present disclosure does not exclude other implementation manners, such as a logic device or a combination of software and hardware, etc. That is to say, the execution subject of the following processing flow is not limited to each logic unit, and may also be hardware or a logic device.
[0137] Embodiments of the present disclosure also propose a computer-readable storage medium storing one or more programs which, when executed by at least one processor, implement the methods disclosed in the embodiments shown in the first aspect and achieve the functions and beneficial effects of the various methods described in the foregoing method embodiments, which will not be elaborated herein.
[0138] The computer-readable storage medium includes, for example, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disc.
[0139] Furthermore, embodiments of the present disclosure also provide a computer program product including a computer program stored on a non-transitory computer-readable storage medium. The computer program includes program instructions which, when executed by a computer, implement the following process: the methods disclosed in the embodiments shown in the first aspect and achieve the functions and beneficial effects of the various methods described in the foregoing method embodiments, which will not be elaborated herein.
[0140] In summary, the foregoing are only preferred embodiments of the present disclosure and do not limit the protection scope of the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included within the protection scope of the present disclosure.
[0141] The systems, modules, or units illustrated in the above embodiments may be specifically implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or any combination of these devices.
[0142] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.
[0143] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.
[0144] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.
Claims
1. A method for pulse width compensation, the method comprising: Obtaining a first ripple voltage during the positive excitation of the transformer and a second ripple voltage during the negative excitation of the transformer; Determining a first bias magnetic compensation amount during the positive excitation of the transformer and a second bias magnetic compensation amount during the negative excitation of the transformer according to the first ripple voltage and the second ripple voltage; Compensating the duty cycle signal amount output by the loop of the transformer according to the first bias magnetic compensation amount and the second bias magnetic compensation amount to suppress the bias magnetic of the transformer.
2. The method according to claim 1, wherein the obtaining the first ripple voltage during the positive excitation of the transformer and the second ripple voltage during the negative excitation of the transformer comprises: Obtaining a first positive excitation voltage and a second positive excitation voltage at a preset first moment and a second moment during the positive excitation of the transformer respectively; Taking the difference between the first positive excitation voltage and the second positive excitation voltage as the first ripple voltage; Obtaining a first negative excitation voltage and a second negative excitation voltage at a preset third moment and a fourth moment during the negative excitation of the transformer, wherein the deviation of the third moment relative to the start moment of the negative excitation is equal to the deviation of the first moment relative to the start moment of the positive excitation, and the deviation of the fourth moment relative to the start moment of the negative excitation is equal to the deviation of the second moment relative to the start moment of the positive excitation; Taking the difference between the first negative excitation voltage and the second negative excitation voltage as the second ripple voltage.
3. The method according to claim 2, wherein the obtaining the first positive excitation voltage, the second positive excitation voltage, the first negative excitation voltage and the second negative excitation voltage comprises: Obtaining the first positive excitation voltage, the second positive excitation voltage, the first negative excitation voltage and the second negative excitation voltage through a first sampling point arranged at the positive end of the input capacitor of the isolated bridge circuit; or, Obtaining the first positive excitation voltage and the second positive excitation voltage through a second sampling point arranged at the primary full-bridge arm of the isolated bridge circuit, and obtaining the first negative excitation voltage and the second negative excitation voltage through a third sampling point arranged at the primary full-bridge arm of the isolated bridge circuit; or, Obtaining the first positive excitation voltage and the second positive excitation voltage through a fourth sampling point arranged at the secondary full-bridge arm of the isolated bridge circuit, and obtaining the first negative excitation voltage and the second negative excitation voltage through a fifth sampling point arranged at the secondary full-bridge arm of the isolated bridge circuit; or, Obtaining the first positive excitation voltage, the second positive excitation voltage, the first negative excitation voltage and the second negative excitation voltage through a sixth sampling point after rectification of the secondary arm of the isolated bridge circuit; or, Obtaining the first positive excitation voltage, the second positive excitation voltage, the first negative excitation voltage and the second negative excitation voltage through a seventh sampling point after rectification of the secondary arm of the non-isolated bridge circuit.
4. The method according to claim 1, wherein determining the first bias magnetic compensation amount during the positive excitation of the transformer and the second bias magnetic compensation amount during the negative excitation of the transformer based on the first ripple voltage and the second ripple voltage includes: Obtaining a ripple voltage difference based on the first ripple voltage and the second ripple voltage; Processing the ripple voltage difference to obtain a compensation information amount; Determining the first bias magnetic compensation amount and the second bias magnetic compensation amount based on the compensation information amount.
5. The method according to claim 4, wherein processing the ripple voltage difference to obtain a compensation information amount includes: Performing at least one of amplification, filtering, and limiting on the ripple voltage difference to obtain the compensation information amount.
6. The method according to claim 4, wherein determining the first bias magnetic compensation amount and the second bias magnetic compensation amount based on the compensation information amount includes: When the compensation information amount is less than or equal to a first threshold and greater than a second threshold, reducing the second bias magnetic compensation amount or increasing the first bias magnetic compensation amount, where the first threshold is greater than the second threshold; When the compensation information amount is greater than or equal to a third threshold and less than a fourth threshold, reducing the first bias magnetic compensation amount or increasing the second bias magnetic compensation amount, where the third threshold is the opposite of the first threshold and the fourth threshold is the opposite of the second threshold; When the absolute value of the compensation information amount is less than or equal to the second threshold, keeping the first bias magnetic compensation amount and the second bias magnetic compensation amount unchanged; When the absolute value of the compensation information amount is greater than the first threshold, setting the first bias magnetic compensation amount to a first preset value and setting the second bias magnetic compensation amount to a second preset value.
7. The method according to claim 6, wherein reducing the second bias magnetic compensation amount or increasing the first bias magnetic compensation amount includes: When the second bias magnetic compensation amount is greater than a first compensation threshold, updating the second bias magnetic compensation amount with the difference between the second bias magnetic compensation amount and a first preset compensation adjustment amount, and updating the first bias magnetic compensation amount with a first preset compensation value; or, When the second bias magnetic compensation amount is less than or equal to the first compensation threshold and the first bias magnetic compensation amount is less than a second compensation threshold, updating the first bias magnetic compensation amount with the sum of the first bias magnetic compensation amount and a second preset compensation adjustment amount, and updating the second bias magnetic compensation amount with a second preset compensation value, where the second compensation threshold is greater than the first compensation threshold; or, When the second bias magnetic compensation amount is less than or equal to the first compensation threshold and the first bias magnetic compensation amount is greater than or equal to the second compensation threshold, updating the second bias magnetic compensation amount with the first compensation threshold and updating the first bias magnetic compensation amount with the second compensation threshold.
8. The method according to claim 6, wherein reducing the first bias magnetic compensation amount or increasing the second bias magnetic compensation amount includes: When the first bias magnetic compensation amount is greater than the third compensation threshold, update the first bias magnetic compensation amount with the difference between the first bias magnetic compensation amount and the third preset compensation adjustment amount, and update the second bias magnetic compensation amount with the third preset compensation value; or, When the first bias magnetic compensation amount is less than or equal to the third compensation threshold and the second bias magnetic compensation amount is less than the fourth compensation threshold, update the second bias magnetic compensation amount with the sum of the second bias magnetic compensation amount and the fourth preset compensation adjustment amount, and update the first bias magnetic compensation amount with the fourth preset compensation value, where the fourth compensation threshold is greater than the third compensation threshold; or, When the first bias magnetic compensation amount is less than or equal to the third compensation threshold and the second bias magnetic compensation amount is greater than or equal to the fourth compensation threshold, update the first bias magnetic compensation amount with the third compensation threshold, and update the second bias magnetic compensation amount with the fourth compensation threshold.
9. The method according to any one of claims 1 to 8, wherein compensating the duty cycle signal amount of the loop output of the transformer according to the first bias magnetic compensation amount and the second bias magnetic compensation amount comprises: Superimpose the first bias magnetic compensation amount on the duty cycle signal amount and output it to the switching tube for positive excitation, and superimpose the second bias magnetic compensation amount on the duty cycle signal amount and output it to the switching tube for negative excitation.
10. An electronic device, comprising: A processor; A memory for storing instructions executable by the processor; A sampling module for sampling the bus voltage according to the control of the processor; A driving module for exciting and driving the switching tube according to the control of the processor; Wherein, the processor is configured to perform the following operations: Obtain a first ripple voltage during positive excitation of the transformer in the power converter and a second ripple voltage during negative excitation of the transformer; Determine a first bias magnetic compensation amount during positive excitation of the transformer and a second bias magnetic compensation amount during negative excitation of the transformer according to the first ripple voltage and the second ripple voltage; Compensate the duty cycle signal amount of the loop output of the transformer according to the first bias magnetic compensation amount and the second bias magnetic compensation amount to suppress the bias magnetism of the transformer.
11. A computer-readable storage medium, the computer-readable storage medium stores one or more programs, and when the one or more programs are executed by an electronic device including a plurality of application programs, the electronic device is caused to execute the steps of the pulse width compensation method according to any one of claims 1-9.