On-off control method and device of alternating current solid state power controller

Abstract

The invention discloses an on-off control method and device of an alternating-current solid-state power controller, and belongs to the technical field of power electronics and electricians. According to the control method, alternating current power supply voltage and current limiting branch current are sampled and processed to obtain alternating current power supply voltage positive / negative half-cycle judgment signals, current limiting branch current positive / negative half-cycle judgment signals and alternating current power supply voltage frequency doubled frequency signals; the signals and external switching signals are logically combined to obtain a control signal of a current-limiting branch power tube, a control signal of a main power branch power tube is further obtained, the current-limiting branch power tube can achieve zero-voltage turn-on and zero-current turn-off, and the main power branch power tube can achieve zero-current turn-on. The switch control method can efficiently suppress the impact current generated in the process of switching on the capacitive load, and has the advantages of high reliability and low complexity.

Description

Technical Field

[0001] The present invention relates to a switching control method and device for an AC solid-state power controller, belonging to the fields of power electronics technology and electrical engineering technology. Background Art

[0002] A solid-state power controller (SSPC) uses power semiconductor devices as switches, integrating the switching control function of a relay and the protection function of a circuit breaker. It has advantages such as fast response, no arc, no mechanical contacts, low conduction power consumption, strong load adaptability, and high reliability, and is the key core of an advanced solid-state power distribution system.

[0003] To reduce the current impact during the turn-on of capacitive loads, DC SSPC mainly adopts a soft turn-on control strategy or a current-limiting branch scheme. For AC SSPC, the current stress problem at the moment of turn-on can theoretically also be solved by adding a current-limiting branch. However, since AC SSPC adopts a control method of "switching the upper and lower power tubes in a certain order without relying on zero-crossing detection", its switching process itself is already relatively complex. If a current-limiting branch is added on this basis, new technical challenges such as control timing coordination and branch switching will be faced, and a mature solution has not been formed yet.

[0004] Therefore, for an AC SSPC with a parallel current-limiting branch, an innovative control method is urgently needed, which can not only effectively suppress the inrush current during the turn-on of capacitive loads, but also significantly improve the reliability of the system, thereby further enhancing the performance and application scope of AC SSPC. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a switching control method and device for an AC solid-state power controller adapted to a parallel current-limiting branch, which can not only effectively suppress the inrush current during the turn-on process of capacitive loads, but also accurately coordinate the switching timing of the main power branch and the current-limiting branch, improving the stability and reliability of the system.

[0006] To solve the above technical problems, the present invention specifically adopts the following technical solutions: A switching control method for an AC solid-state power controller, the AC solid-state power controller including a main power branch and a current-limiting branch connected in parallel, characterized by comprising: Sampling and processing the AC power supply voltage and the current of the current-limiting branch to obtain an AC power supply voltage positive / negative half-cycle judgment signal, a current-limiting branch current positive / negative half-cycle judgment signal, and a double-frequency signal of the AC power supply voltage frequency; Logically combine the above signals and the external switch signal to obtain the control signal for the power transistor in the current-limiting branch; logically combine the control signal for the power transistor in the current-limiting branch, the voltage across the detection resistor in the current-limiting branch, the threshold voltage corresponding to the rated steady-state current peak value, the positive / negative half-cycle judgment signal of the current in the current-limiting branch, and the external switch signal to obtain the control signal for the power transistor in the main power branch, so as to achieve that when the AC solid-state power controller is turned on, the current-limiting branch is first turned on with zero voltage, and when it is detected that the current peak value is lower than the rated current peak value, the main power branch is turned on at the current zero-crossing point; when the AC solid-state power controller is turned off, the main power branch is first turned off, and the current-limiting branch is turned off after the current zero-crossing point.

[0007] Preferably, the current-limiting branch includes a current-limiting resistor, a power transistor in the current-limiting branch, a first detection resistor, a second detection resistor, and a lower power transistor in the current-limiting branch connected in series in sequence, and the gates of the upper power transistor and the lower power transistor in the current-limiting branch are connected to different control signals.

[0008] Further preferably, the switching control method of the above AC solid-state power controller is characterized by including: When turning on the current-limiting branch, when the power supply voltage is in the positive half-cycle, first turn on the lower power transistor in the current-limiting branch, and then turn on the upper power transistor in the current-limiting branch after the voltage zero-crossing point; when the power supply voltage is in the negative half-cycle, first turn on the upper power transistor in the current-limiting branch, and then turn on the lower power transistor in the current-limiting branch after the voltage zero-crossing point; When turning off the current-limiting branch, when the current in the current-limiting branch is in the positive half-cycle, first turn off the lower power transistor in the current-limiting branch, and then turn off the upper power transistor in the current-limiting branch after the current zero-crossing point; when the current in the current-limiting branch is in the negative half-cycle, first turn off the upper power transistor in the current-limiting branch, and then turn off the lower power transistor in the current-limiting branch after the current zero-crossing point.

[0009] The present invention also provides an electronic device, including a processor and a memory, the memory stores a program that can run on the processor, and is characterized in that when the program is executed by the processor, the steps of the above switching control method of the AC solid-state power controller are realized.

[0010] The beneficial effects brought by adopting the technical solution of the present invention are as follows: 1) The power transistor in the current-limiting branch can achieve "zero-voltage turn-on and zero-current turn-off", and the power transistor in the main power branch can achieve "zero-current turn-on", and the loss generated by the power transistor during the turn-on and turn-off processes is relatively low; 2) Effectively suppress the inrush current generated during the process of turning on the capacitive load; 3) Can accurately coordinate the switching timing of the main power branch and the current-limiting branch, and has the advantages of high reliability and high stability. Description of the Drawings

[0011] Figure 1 is the circuit diagram of an AC solid-state power controller with a parallel current-limiting branch; Figure 2 It is the power supply voltage detection circuit, positive and negative half-cycle judgment circuit, and the corresponding working timing diagram; Figure 3 It is the current-limiting branch current detection and positive and negative half-cycle judgment circuit, and the corresponding working timing diagram; Figure 4 It is the power supply voltage frequency doubling detection circuit and the corresponding working timing diagram; Figure 5 It is the current-limiting branch control logic combination circuit diagram; Figure 6 It is the working timing diagram of the current-limiting branch control logic combination circuit under capacitive load; Figure 7 It is the main power branch control logic combination circuit diagram; Figure 8 It is the overall working timing diagram of the AC solid-state power controller. Specific implementation manners

[0012] The following details some key technologies involved in the present invention with reference to the accompanying drawings to support the claims; for making the purpose, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0013] Embodiment 1 This embodiment provides a switching control method for an AC solid-state power controller. The above AC solid-state power controller includes a main power branch and a current-limiting branch connected in parallel. The above switching control method includes: When turning on the AC solid-state power controller, first turn on the current-limiting branch at zero voltage. When it is detected that the current peak value is lower than the rated current peak value, turn on the main power branch at the current zero crossing point; When turning off the AC solid-state power controller, first turn off the main power branch, and then turn off the current-limiting branch after the current zero crossing point.

[0014] Figure 1 It is the circuit diagram of the AC solid-state power controller in this embodiment. As Figure 1 shown, the AC solid-state power controller is connected between the AC power supply V s and the load. The AC power supply is a 115V AC source, Figure 1 where PGND is the power ground terminal. The AC SSPC includes a main power branch, a current-limiting branch, a power supply voltage detection circuit, a power supply voltage positive and negative half-cycle judgment circuit, a power supply voltage frequency doubling detection circuit, a current-limiting branch current detection circuit, a current-limiting branch current positive and negative half-cycle judgment circuit, a current-limiting branch control logic combination circuit, and a main power branch control logic combination circuit.

[0015] The main power branch of the AC SSPC consists of two identical N-channel enhancement-mode Si MOSFETs (the first power transistor S upp and the second power transistor S low ) connected in anti-series. The gates of the two power transistors are connected to the same control signal CMD m , and CMD m comes from the control logic combinational circuit of the main power branch. The current-limiting branch of the AC SSPC consists of a current-limiting resistor R lim、 two identical N-channel enhancement-mode Si MOSFETs (the upper power transistor S u on the current-limiting branch and the lower power transistor S l on the current-limiting branch), a first detection resistor R sense1 , and a second detection resistor R sense2 connected in series. The connection terminals of the first detection resistor R sense1 and the second detection resistor R sense2 are connected to the analog ground terminal AGND1. U sense+ is the voltage across the first detection resistor R sense1 , and U sense- is the voltage across the second detection resistor R sense2 . The gate of the upper power transistor S u on the current-limiting branch is connected to the control signal CMD u for the upper power transistor on the current-limiting branch, and the gate of the lower power transistor S l on the current-limiting branch is connected to the control signal CMD l for the lower power transistor on the current-limiting branch. The control signal CMD u for the upper power transistor on the current-limiting branch and the control signal CMD l for the lower power transistor on the current-limiting branch come from the control logic combinational circuit of the current-limiting branch.

[0016] Specifically, the switching control method of the AC solid-state power controller in this embodiment includes: When turning on the current-limiting branch, when the power supply voltage is in the positive half-cycle, first turn on the lower power transistor S l on the current-limiting branch, and then turn on the upper power transistor S u on the current-limiting branch after the voltage passes through the zero-crossing point; when the power supply voltage is in the negative half-cycle, first turn on the upper power transistor S u on the current-limiting branch, and then turn on the lower power transistor S l on the current-limiting branch after the voltage passes through the zero-crossing point; When turning off the current-limiting branch, when the current in the current-limiting branch is in the positive half-cycle, first turn off the lower power transistor S l, turn off the power transistor S on the current limiting branch after the current passes through the zero crossing point u ; when the current on the current limiting branch is in the negative half cycle, first turn off the power transistor S on the current limiting branch u , and turn off the power transistor S on the lower current limiting branch after the current passes through the zero crossing point l .

[0017] Such as Figure 2 , in which (a) shows the power supply voltage detection circuit and the positive and negative half cycle judgment circuit, and (b) shows the working timing of the power supply voltage detection circuit and the positive and negative half cycle judgment circuit. The power supply voltage detection circuit is implemented by a differential proportional operation circuit. The voltages at both ends of the AC power supply are input into the differential proportional operation circuit, and the output signal u op , with a value of U S * R 2 / R 1. The power supply voltage positive and negative half cycle judgment circuit includes an RC low-pass filter circuit and two comparators. The signal u op is input into the power supply voltage positive and negative half cycle judgment circuit. After being processed by the RC low-pass filter circuit, it is compared with the high threshold voltage U TH + and the low threshold voltage U TH - through two comparators respectively, and the power supply voltage positive / negative half cycle judgment signal U + / U - signal is obtained.

[0018] Such as Figure 3 , in which (a) shows the current limiting branch current detection circuit and the positive and negative half cycle judgment circuit, and (b) shows the working timing of the current limiting branch current detection circuit and the positive and negative half cycle judgment circuit. The current limiting branch current detection circuit is implemented by a differential proportional operation circuit. The voltages at both ends of the first and second detection resistors R sense1 , R sense2 are input into the differential proportional operation circuit, and the output signal i op . The current limiting branch current positive and negative half cycle judgment circuit includes an RC low-pass filter and two comparators. The signal i op is input into the current limiting branch current positive and negative half cycle judgment circuit. After being processed by the RC low-pass filter circuit, it is compared with the high threshold voltage I TH + and the low threshold voltage I TH - through two comparators respectively, and the current limiting branch current positive / negative half cycle judgment signal I + / I - signal is obtained.

[0019] As shown in Figure 4 , where (a) shows the double-frequency detection circuit of the power supply voltage frequency, and (b) shows the working timing of the double-frequency detection circuit of the power supply voltage frequency. The double-frequency detection circuit of the power supply voltage frequency is implemented by an OR gate, and the positive / negative half-cycle judgment signals U + and U - of the power supply voltage are subjected to OR logic operation. Since U + and U - are the positive and negative half-cycle signals of the power supply voltage and have a phase difference of 180°, the OR logic operation result of them will generate a signal with a frequency twice that of the power supply voltage frequency, that is, the double-frequency signal Fre of the AC power supply voltage frequency.

[0020] Figure 5 is the combined circuit diagram of the current-limiting branch control logic. Among them, I + / I - are the positive / negative half-cycle judgment signals of the current-limiting branch current, U + / U - are the positive / negative half-cycle judgment signals of the power supply voltage, CMD is the external switch signal, CMD u is the control signal of the power transistor on the current-limiting branch, CMD l is the control signal of the power transistor under the current-limiting branch, Fre is the double-frequency signal of the AC power supply voltage frequency, After1 is the auxiliary turn-off signal of the power transistor under the current-limiting branch, and After2 is the auxiliary turn-off signal of the power transistor on the current-limiting branch. I + / I -, U + / U -, CMD, and Fre are processed by this logic circuit to obtain CMD u and CMD l .

[0021] As shown in Figure 5 , the combined circuit of the current-limiting branch control logic includes the first NOR gate NOR1, the second NOR gate NOR2, the third NOR gate NOR3, the fourth NOR gate NOR4, the first OR gate OR1, the second OR gate OR2, the first NAND gate NAND1, the second NAND gate NAND2, the first D flip-flop D1, the second D flip-flop D2, the first RS flip-flop RS1, and the second RS flip-flop RS2. Among them, the first and second NOR gates NOR1 and NOR2, the first D flip-flop D1, the first OR gate OR1, the first NAND gate NAND1, and the first RS flip-flop RS1 constitute the control logic circuit of the power transistor on the current-limiting branch; the third and fourth NOR gates NOR3 and NOR4, the second D flip-flop D2, the second OR gate OR2, the second NAND gate NAND2, and the second RS flip-flop RS2 constitute the control logic circuit of the power transistor under the current-limiting branch.

[0022] The input terminals of the first NOR gate NOR1 are connected to the external switch signal CMD, the power transistor control signal CMD on the current limiting branch u and the current negative half-cycle judgment signal of the current limiting branch I -. The input terminals of the second NOR gate NOR2 are connected to the output signal After2 of the Q terminal of the second D flip-flop D2 and the current negative half-cycle judgment signal of the current limiting branch I -. The signal After2 is the auxiliary turn-off signal of the power transistor on the current limiting branch. The D terminal of the first D flip-flop D1 is connected to the output terminal of the first NOR gate NOR1, and the CLK terminal is connected to the double-frequency signal Fre of the AC power supply voltage frequency. The input terminals of the first OR gate OR1 are connected to the output signal of the second NOR gate NOR2 and the external switch signal CMD. The input terminals of the first NAND gate NAND1 are connected to the power supply voltage negative half-cycle judgment signal U - and the external switch signal CMD; the input terminals of the second NAND gate NAND2 are connected to the power supply voltage positive half-cycle judgment signal U + and the external switch signal CMD. The R terminal of the first RS flip-flop RS1 is connected to the output terminal of the first OR gate OR1, the S terminal is connected to the output terminal of the first NAND gate NAND1, and the Q terminal outputs the power transistor control signal CMD on the current limiting branch u . The input terminals of the third NOR gate NOR3 are connected to the output signal After1 of the Q terminal of the first D flip-flop D1 and the current positive half-cycle judgment signal of the current limiting branch I +, and the signal After1 is the auxiliary turn-off signal of the power transistor under the current limiting branch. The input terminals of the second OR gate OR2 are connected to the output signal of the third NOR gate NOR3 and the external switch signal CMD. The input terminals of the fourth NOR gate NOR4 are connected to the power transistor control signal CMD1 under the current limiting branch, the current positive half-cycle judgment signal I + and the external switch signal CMD. The D terminal of the second D flip-flop D2 is connected to the output terminal of the fourth NOR gate NOR4, and the CLK terminal is connected to the double-frequency signal Fre of the AC power supply voltage frequency; the R terminal of the second RS flip-flop RS2 is connected to the output terminal of the second NAND gate NAND2, the S terminal is connected to the output terminal of the second OR gate OR2, and the Q terminal outputs the power transistor control signal CMD under the current limiting branch l .

[0023] Figure 7 is the combined circuit diagram of the main power branch control logic. Among them, U sense are the first and second current detection resistors R sense1 , R sense2 the voltages at both ends, U sense = U sense+ - Usense- . U TH is the threshold voltage corresponding to the rated steady-state current peak, CMD u is the control signal of the power transistor on the current-limiting branch, CMD l is the control signal of the power transistor under the current-limiting branch, I + / I - is the positive / negative half-cycle judgment signal of the current-limiting branch current, CMD is the external switch signal, CMD m is the control signal of the power transistor in the main power branch (S upp 、S low ).

[0024] As Figure 7 shown, the main power branch control logic combinational circuit includes: a conditioning and amplifying circuit, a full-wave rectifying and filtering circuit, a peak detection circuit, a comparator CMP, a first AND gate AND1, a second AND gate AND2, a third AND gate AND3, a fifth NOR gate NOR5, and a third D flip-flop D3. The input end of the conditioning and amplifying circuit is connected to the voltage across the current-limiting branch detection resistor U sense , after conditioning, it is input into the peak detection circuit through the full-wave rectifying and filtering circuit, where the conditioning and amplification multiple is set to K 1, the output end of the peak detection circuit is connected to the negative-phase input end of the comparator CMP, and the positive-phase input end of the comparator CMP is connected to the threshold voltage corresponding to the rated steady-state current peak U TH , U TH = KI p , K is K 1*( R sense1 + R sense2 ), I p is the rated current peak; its output end is connected to one input end of the second AND gate AND2; the two input ends of the first AND gate are respectively connected to the upper and lower power transistor control signals, and its output end is connected to the other input end of the second AND gate AND2; the output end of the second AND gate AND2 is connected to the D end of the third D flip-flop D3; the two input ends of the fifth NOR gate NOR5 are respectively connected to the positive and negative half-cycle judgment signals of the current-limiting branch current I + and I -, its output end is connected to the CLK end of the third D flip-flop D3, the Q end of the third D flip-flop D3 is connected to one input end of the third AND gate AND3, the other input end of the third AND gate AND3 is connected to the external switch signal CMD, and its output end outputs the control signal CMD of the power transistor in the main power branch m .

[0025] Figure 6 It is the working timing diagram of the current-limiting branch control logic combinational circuit under capacitive load. In the control timing, when the power supply voltage u s is in the negative half cycle, the current-limiting branch receives the turn-on instruction, and the current in the current-limiting branch i limit is in the positive half cycle when the current-limiting branch receives the turn-off instruction, where t 0~ t 2 corresponds to the turn-on process of the current-limiting branch, t 3~ t 5 corresponds to the turn-off process of the current-limiting branch.

[0026] (1) Turn-on process t 0: The current-limiting branch receives the turn-on instruction (CMD is set to high level), and it is detected that the power supply voltage u s is in the negative half cycle at this time. CMD u is set to high level, and the power transistor on the current-limiting branch S u is immediately turned on, and the lower power transistor S l remains in the cut-off state (CMD l remains low level), and the current-limiting branch is in the reverse cut-off state; t 1: The power supply voltage u s passes through the zero crossing point, and the current in the current-limiting branch starts to rise slowly from zero; t 2: CMD l is set to high level, and the lower power transistor of the current-limiting branch S l is turned on, and the current-limiting branch is fully conducted; (2) Turn-off process t 3: The current-limiting branch receives the turn-off instruction (CMD is set to low level), and it is detected that the current in the current-limiting branch i limit is in the positive half cycle at this time. CMD l is set to low level, and the lower power transistor of the current-limiting branch S l is immediately turned off, and the upper power transistor S u remains in the conducting state (CMD u remains high level). At this time, the current path is: the conducting channel of the lower power transistor - the body diode of the upper power transistor; t 4: The current in the current-limiting branch passes through the zero crossing point. Since the lower power transistor of the current-limiting branch Sl Turn off, so the current in the current-limiting branch is 0 subsequently; t 5: Set the signal After2 to high level, and set CMD u to low level, and the current-limiting branch switches to the bidirectional cut-off state.

[0027] Summarize the control logic of the current-limiting branch as shown in Table 1 below: Table 1 Control Logic of the Current-Limiting Branch Zero-Crossing Switch

[0028] Figure 8 is the overall working timing diagram of the AC solid-state power controller. In the control timing, when the power supply voltage u s is in the negative half-cycle, the AC SSPC receives the turn-on command, and the load current i L is in the positive half-cycle when the AC SSPC receives the turn-off command, where t 0~ t 4 corresponds to the turn-on process of the main power branch of the AC SSPC, t 5~ t 7 corresponds to the turn-off process of the main power branch of the AC SSPC. Among them, u s is the power supply voltage, U + / U - is the positive / negative half-cycle judgment signal of the power supply voltage, CMD is the external switch signal, i L is the load current, I + / I - is the positive / negative half-cycle judgment signal of the current-limiting branch current, i limit is the current-limiting branch current, i main is the main power branch current, CMD u is the control signal of the power transistor on the current-limiting branch, CMD l is the control signal of the power transistor under the current-limiting branch, After2 is the auxiliary turn-off signal of the power transistor on the current-limiting branch, CMD m is the control signal of the power transistor of the main power branch.

[0029] (1) Turn-on process t 0: The AC SSPC receives the turn-on command (CMD is set to 1), and judges that the power supply voltage u s is in the negative half-cycle, and the power transistor on the current-limiting branch S u is immediately turned on (CMD u is set to 1), and the lower power transistorS l Still in the cut-off state (CMD l keeps 0), the AC SSPC is in the reverse cut-off state; t 1: At the zero-crossing point of the power supply voltage, the SSPC current starts to rise slowly from zero; t 2: Turn on the power transistor in the current-limiting branch S l (CMD l sets to 1), the current-limiting branch is fully conducting; t 3: Detect that the current peak value in the current-limiting branch is close to the rated current peak value; t 4: At the current zero-crossing point, turn on the power transistor in the main power branch (CMD m sets to 1), so that the current is smoothly commutated to the main power branch.

[0030] (2) Turn-off process t 5: The AC SSPC receives a turn-off command (CMD sets to 0), and the power transistor in the main power branch turns off slowly (CMD m sets to 0), so that the current is smoothly commutated to the current-limiting branch; t 6: Judge that the current in the current-limiting branch is in the positive half-cycle at this time, and the power transistor in the current-limiting branch S l turns off immediately (CMD l sets to 0), and the upper power transistor in the current-limiting branch S u still remains in the conducting state (CMD u keeps 1), and at this time the SSPC current flows through the conducting channel of the upper power transistor - the body diode of the lower power transistor; t 7: Set the auxiliary turn-off signal After2 of the upper power transistor to high level to turn off the upper power transistor in the current-limiting branch S u (CMD u sets to 0), and the AC SSPC switches to the bidirectional cut-off state.

[0031] The switching control logic of the AC SSPC with a current-limiting branch is summarized in Table 2 below: Table 2 Switching Control Logic of AC SSPC with Current-Limiting Branch

[0032] Example 2 This embodiment provides an electronic device, including a processor and a memory communicatively connected to the processor. A program that can run on the processor is stored on the memory. When the program is executed by the processor, it implements the steps of the switching control method of the AC solid-state power controller provided in the above embodiment.

[0033] The above program can be written in one or more programming languages or combinations thereof, including object-oriented programming languages such as Java, Smalltalk, C++, and also including conventional procedural programming languages such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, executed as an independent software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server.

[0034] In the switching control method of the AC solid-state power controller of the present invention, by sampling and processing the AC power supply voltage and the current of the current-limiting branch, an AC power supply voltage positive / negative half-cycle judgment signal, a current-limiting branch current positive / negative half-cycle judgment signal, and an AC power supply voltage frequency double-frequency signal are obtained. The above signals and an external switch signal are logically combined to obtain a control signal for the power tube of the current-limiting branch; the control signal for the power tube of the current-limiting branch, the voltage across both ends of the current-limiting branch detection resistor, the threshold voltage corresponding to the rated steady-state current peak value, the current-limiting branch current positive / negative half-cycle judgment signal, and the external switch signal are logically combined to obtain a control signal for the power tube of the main power branch; the power tube of the current-limiting branch can achieve "zero-voltage turn-on and zero-current turn-off", and the power tube of the main power branch can achieve "zero-current turn-on". This switching control method can effectively suppress the inrush current generated during the process of turning on the capacitive load, and has the advantages of high reliability and low complexity.

[0035] The above embodiments are only used to illustrate the technical idea of the present invention, and the protection scope of the present invention cannot be limited thereby. Any modification made on the basis of the technical solution according to the technical idea proposed by the present invention falls within the protection scope of the present invention.

Claims

1. A switching control method for an AC solid-state power controller, the AC solid-state power controller comprising a main power branch and a current-limiting branch connected in parallel, characterized in that, Including: Sampling and processing the AC power supply voltage and the current of the current-limiting branch to obtain an AC power supply voltage positive / negative half-cycle judgment signal, a current-limiting branch current positive / negative half-cycle judgment signal, and an AC power supply voltage frequency double-frequency signal; Logically combining the above signals and an external switch signal to obtain a control signal for the power tube of the current-limiting branch; logically combining the control signal for the power tube of the current-limiting branch, the voltage across the detection resistor of the current-limiting branch, the threshold voltage corresponding to the rated steady-state current peak value, the current-limiting branch current positive / negative half-cycle judgment signal, and the external switch signal to obtain a control signal for the power tube of the main power branch, so as to achieve that when the AC solid-state power controller is turned on, the current-limiting branch is first turned on with zero voltage, and when it is detected that the current peak value is lower than the rated current peak value, the main power branch is turned on at the current zero-crossing point; when the AC solid-state power controller is turned off, the main power branch is first turned off, and the current-limiting branch is turned off after the current zero-crossing point.

2. The switching control method of the AC solid-state power controller according to claim 1, wherein: The main power branch is composed of two power tubes connected in reverse series, and the gates of the two power tubes are connected to the same control signal.

3. The switching control method of the AC solid-state power controller according to claim 1, wherein: The current-limiting branch includes a current-limiting resistor, a power tube on the current-limiting branch, a first detection resistor, a second detection resistor, and a power tube under the current-limiting branch connected in series in sequence, and the gates of the power tube on the current-limiting branch and the power tube under the current-limiting branch are connected to different control signals.

4. The switching control method of the AC solid-state power controller according to claim 3, characterized in that Including: When turning on the current-limiting branch, when the power supply voltage is in the positive half-cycle, first turn on the power tube under the current-limiting branch, and then turn on the power tube on the current-limiting branch after the voltage zero-crossing point; when the power supply voltage is in the negative half-cycle, first turn on the power tube on the current-limiting branch, and then turn on the power tube under the current-limiting branch after the voltage zero-crossing point; When turning off the current-limiting branch, when the current-limiting branch current is in the positive half-cycle, first turn off the power tube under the current-limiting branch, and then turn off the power tube on the current-limiting branch after the current zero-crossing point; when the current-limiting branch current is in the negative half-cycle, first turn off the power tube on the current-limiting branch, and then turn off the power tube under the current-limiting branch after the current zero-crossing point.

5. The switching control method of the AC solid-state power controller according to claim 3, wherein: The AC solid-state power controller includes a current-limiting branch control logic combination circuit, and the current-limiting branch control logic combination circuit includes a first NOR gate, a second NOR gate, a third NOR gate, a fourth NOR gate, a first OR gate, a second OR gate, a first NAND gate, a second NAND gate, a first D flip-flop, a second D flip-flop, a first RS flip-flop, and a second RS flip-flop; the input end of the first NOR gate is connected to an external switch signal, a power transistor control signal on the current-limiting branch, and a current-negative half-cycle judgment signal of the current-limiting branch; the input end of the second NOR gate is connected to the Q-end output signal of the second D flip-flop and the current-negative half-cycle judgment signal of the current-limiting branch; the D end of the first D flip-flop is connected to the output end of the first NOR gate, and the CLK end is connected to a double-frequency signal of the AC power supply voltage frequency; the input end of the first OR gate is connected to the output end signal of the second NOR gate and the external switch signal; the input end of the first NAND gate is connected to a power-voltage negative half-cycle judgment signal and the external switch signal; the input end of the second NAND gate is connected to a power-voltage positive half-cycle judgment signal and the external switch signal; the R end of the first RS flip-flop is connected to the output end of the first OR gate, the S end is connected to the output end of the first NAND gate, and the Q end outputs a power transistor control signal on the current-limiting branch; the input end of the third NOR gate is connected to the Q-end output signal of the first D flip-flop and a current-positive half-cycle judgment signal of the current-limiting branch; the input end of the second OR gate is connected to the output end signal of the third NOR gate and the external switch signal; the input end of the fourth NOR gate is connected to a lower power transistor control signal on the current-limiting branch, a current-positive half-cycle judgment signal of the current-limiting branch, and the external switch signal; the D end of the second D flip-flop is connected to the output end of the fourth NOR gate, and the CLK end is connected to a double-frequency signal of the AC power supply voltage frequency; the R end of the second RS flip-flop is connected to the output end of the second NAND gate, the S end is connected to the output end of the second OR gate, and the Q end outputs a lower power transistor control signal on the current-limiting branch.

6. The switching control method of the AC solid-state power controller according to claim 3, characterized in that: The AC solid-state power controller includes a main power branch control logic combination circuit, and the main power branch control logic combination circuit includes: a conditioning and amplification circuit, a full-wave rectification and filtering circuit, a peak detection circuit, a comparator, a first AND gate, a second AND gate, a third AND gate, a fifth NOR gate, and a third D flip-flop; The input end of the conditioning amplifier circuit is connected to both ends of the current-limiting branch detection resistor, and the output end is connected to the input end of the peak detection circuit through the full-wave rectification and filtering circuit. The output end of the peak detection circuit is connected to the negative-phase input end of the comparator. The positive-phase input end of the comparator is connected to the threshold voltage corresponding to the rated steady-state current peak value, and its output end is connected to one of the input ends of the second AND gate; the two input ends of the first AND gate are respectively connected to the control signals of the upper and lower power tubes on the current-limiting branch, and its output end is connected to the other input end of the second AND gate; the output end of the second AND gate is connected to the D end of the third D flip-flop; the two input ends of the fifth NOR gate are respectively connected to the positive and negative half-cycle judgment signals of the current-limiting branch current, and its output end is connected to the CLK end of the third D flip-flop. The Q end is connected to one of the input ends of the third AND gate. The other input end of the third AND gate is connected to the external switch signal, and its output end outputs the control signal of the power tube of the main power branch.

7. An electronic device, comprising a processor and a memory, the memory storing a program that can run on the processor, characterized in that, When the program is executed by the processor, it implements the steps of the switching control method of the AC solid-state power controller according to any one of claims 1-6.

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