A multi-frequency digital phase-locked amplification method and device based on coherent sampling

Abstract

The present invention discloses a multi-frequency digital phase-locked amplification method and device based on coherent sampling. The method includes applying a multi-frequency sinusoidal reference signal excitation containing K reference frequencies to the object under test to obtain the impedance response signal of the object under test; coherently sampling the impedance response signal; and synchronously digitally phase-locking the discrete impedance response signal sequence at the K reference frequencies to obtain the amplitude and phase at the K reference frequencies. The device includes a front-end unit and a back-end unit. The front-end unit includes a positive and negative current source and a current amplifier, and the back-end unit includes a control processing module, a DA conversion and low-pass filtering module, and a low-pass filtering and AD conversion module. The present invention aims to improve the digital phase-locked amplifier so that it can synchronously process multi-frequency signals, reduce the design difficulty and resource consumption of the low-pass filter, and improve the accuracy and speed of the phase-locked amplifier, so that the digital phase-locked amplifier is stable, reliable, and has a wide range of adaptability.

Description

Technical Field

[0001] The present invention belongs to the technical field of weak signal detection, and in particular relates to a multi-frequency digital phase-locked amplification method and device based on coherent sampling. Background Art

[0002] Effective detection of weak signals in noisy environments is a major interdisciplinary issue, long constraining the development of numerous disciplines, including biomedicine and precision measurement. The lock-in amplifier (LIA), a key tool for addressing this problem, achieves stable extraction of weak signals in strong noise through a coherent demodulation mechanism combining quadrature mixing of a reference signal with narrowband filtering. Since the advent of the first LIA in the mid-20th century, the LIA has evolved from analog to digital architecture, gradually establishing its core position in weak signal detection. This has also driven its irreplaceable role in critical scenarios across multiple fields, finding widespread application in fields such as bioelectrical impedance analysis, spectroscopy, and industrial sensing.

[0003] Lock-in amplifiers can be divided into analog lock-in amplifiers (ALIAs) and digital lock-in amplifiers (DLIAs). Early analog lock-in amplifiers achieved signal demodulation through analog multipliers and low-pass filters. Although simple in structure and fast in response, their performance was limited by operational amplifier noise, temperature drift, and the nonlinear distortion of the analog filter, resulting in a limited dynamic range and insufficient harmonic suppression. Furthermore, the temperature drift characteristics of the analog multiplier can introduce significant phase errors, while the cutoff frequency drift of traditional low-pass filters exacerbates the volatility of signal demodulation, limiting their application in high-precision phase information detection applications such as bioelectrical impedance analysis. With advances in digital signal processing technology, digital lock-in amplifiers have gradually replaced analog solutions, using programmable logic devices to implement orthogonal mixing and digital filtering, significantly improving the system's anti-interference capabilities and flexibility. However, current research on digital lock-in amplifiers (DLIAs) primarily focuses on optimizing and validating single-frequency scenarios, such as automatic frequency tracking and high-frequency, high-precision design. These amplifiers can only demodulate the amplitude and phase of a single frequency in real time at any given moment, failing to meet the demands of dynamic detection scenarios such as physiological trait monitoring and spectral analysis, which require multi-frequency response characteristics. Furthermore, traditional DLIAs still rely on low-pass filters (LPFs) to suppress high-frequency noise during demodulation, which consumes significant hardware resources and often produces poor results. Furthermore, spectral leakage and accumulated phase errors caused by non-integer-cycle sampling significantly impact DLIA measurement accuracy. Summary of the Invention

[0004] Technical problem to be solved by the present invention: In response to the above-mentioned problems of the prior art, a multi-frequency digital phase-locked amplifier method and device based on coherent sampling are provided. The present invention aims to improve the digital phase-locked amplifier so that it can synchronously process multi-frequency signals, reduce the design difficulty and resource consumption of the pass filter, and improve the accuracy and speed of the phase-locked amplifier, so that the digital phase-locked amplifier is stable, reliable and has a wide adaptability.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0006] A multi-frequency digital phase-locked amplification method based on coherent sampling comprises the following steps:

[0007] S101, applying a multi-frequency sinusoidal reference signal excitation including K reference frequencies to the object under test, and obtaining an impedance response signal of the object under test under the excitation of the multi-frequency sinusoidal reference signal;

[0008] S102, coherently sampling the impedance response signal to obtain a discrete impedance response signal sequence;

[0009] S103 , performing synchronous digital phase locking of K reference frequencies on the discrete impedance response signal sequence to obtain amplitudes and phases at the K reference frequencies.

[0010] Optionally, when performing synchronous digital phase locking of the discrete impedance response signal sequence with K reference frequencies in step S103 to obtain amplitudes and phases at the K reference frequencies, the synchronous digital phase locking at any reference frequency includes: generating two orthogonal reference sequences at the reference frequency, the two orthogonal reference sequences including a sine reference sequence and a cosine reference sequence, multiplying the discrete impedance response signal sequence with the sine reference sequence and the cosine reference sequence, respectively, to obtain an in-phase component and a quadrature component; and calculating the amplitude and phase at the corresponding reference frequency using the in-phase component and the quadrature component.

[0011] Optionally, in step S101, a multi-frequency sinusoidal reference signal excitation including K reference frequencies is applied to the object under test, and when the impedance response signal of the object under test is obtained under the multi-frequency sinusoidal reference signal excitation, the multi-frequency sinusoidal reference signal excitation adopts a pair of current excitation electrodes. and The output is injected into the object under test, and the impedance response signal is passed through a pair of voltage detection electrodes and It is detected that the object to be measured is a human body, and the current excitation electrode and voltage detection electrodes The gap is placed on the skin of the neck of the subject, and the current excitation electrode and voltage detection electrodes The gaps are arranged at the heart and skin of the subject.

[0012] Optionally, step S103 also includes: after normalizing the amplitude and phase at K reference frequencies, using a pre-trained first machine learning model to predict the amount of blood output by the heart per unit time and the amount of blood output per heartbeat, the first machine learning model is pre-trained to establish a mapping relationship between the normalized amplitude and phase at K reference frequencies, the amount of blood output by the heart per unit time, and the amount of blood output per heartbeat.

[0013] Optionally, step S103 also includes: after normalizing the amplitude and phase at K reference frequencies, using a pre-trained second machine learning model to predict the percentage of blood volume ejected by the ventricles during each heartbeat to the end-diastolic volume of the ventricles, the second machine learning model is pre-trained to establish a mapping relationship between the normalized amplitude and phase at K reference frequencies and the percentage of blood volume ejected by the ventricles during each heartbeat to the end-diastolic volume of the ventricles.

[0014] Optionally, step S103 also includes: after normalizing the amplitude and phase at K reference frequencies, using a pre-trained third machine learning model to predict the preload state and afterload state of the heart, the third machine learning model is pre-trained to establish a mapping relationship between the normalized amplitude and phase at K reference frequencies, and the preload state and afterload state of the heart.

[0015] Optionally, step S103 also includes: after normalizing the amplitude and phase at K reference frequencies, using a pre-trained fourth machine learning model to predict myocardial contractility, the fourth machine learning model is pre-trained to establish a mapping relationship between the normalized amplitude and phase at K reference frequencies and myocardial contractility.

[0016] In addition, the present invention also provides a multi-frequency digital lock-in amplifier device for applying the multi-frequency digital lock-in amplifier method based on coherent sampling, comprising a front-end unit and a back-end unit, wherein the front-end unit comprises a positive current source, a negative current source and a current amplifier, wherein the positive current source and the negative current source respectively have current excitation electrodes. and For outputting a multi-frequency sinusoidal reference signal containing K reference frequencies, the current amplifier has a pair of voltage detection electrodes and For collecting impedance response signals, the back-end unit includes a control processing module, a DA conversion and low-pass filtering module, and a low-pass filtering and AD conversion module. The output end of the control processing module is connected to the control ends of the positive current source and the negative current source respectively through the DA conversion and low-pass filtering module. The input end of the control processing module is connected to the output end of the current amplifier through the low-pass filtering and AD conversion module. The control processing module is used to control the positive current source and the negative current source to generate a multi-frequency sinusoidal reference signal, and process the impedance response signal output by the current amplifier to obtain the amplitude and phase at K reference frequencies.

[0017] Optionally, the control processing module includes an FPGA module and an ARM processor interconnected by a bus, the FPGA module includes a clock and reset management module, an AD conversion drive module, a reference frequency generation module, a synchronous digital phase-locked unit, a coordinate rotation digital calculation module, a FIFO storage queue, a FIFO read-write controller, a multi-frequency sine reference signal generator and a DA conversion drive module, the clock and reset management module respectively provide clock and reset signals to the AD conversion drive module, the reference frequency generation module, the coordinate rotation digital calculation module, the FIFO storage queue, the FIFO read-write controller, the multi-frequency sine reference signal generator and the DA conversion drive module, the AD conversion drive module is connected to the drive signal end of the low-pass filter and AD conversion module, the number of the synchronous digital phase-locked units is K and the input ends are all connected to the output ends of the low-pass filter and AD conversion module, the synchronous digital phase-locked unit, the coordinate rotation digital calculation module, and the FIFO storage queue are connected in sequence, and the synchronous digital phase-locked unit is used to respectively compare the discrete impedance response signal sequence with the corresponding reference frequency output by the reference frequency generation module. The two orthogonal reference sequences, the sine reference sequence and the cosine reference sequence, are multiplied to obtain an in-phase component and a quadrature component. The coordinate rotation digital calculation module is used to calculate the amplitude and phase at the corresponding reference frequency based on the in-phase component and the quadrature component. The coordinate rotation digital calculation module is connected to the FIFO read-write controller to write the amplitude and phase at each reference frequency into the FIFO storage queue. The ARM processor is connected to the FIFO storage queue and the FIFO read-write controller through a bus to read the amplitude and phase at each reference frequency stored in the FIFO storage queue and perform moving average filtering, format conversion, and data packet encapsulation in sequence before outputting the data through its data communication interface. The reference frequency generation module includes an address accumulator AA and a ROM memory for storing K reference frequencies. The address accumulator AA repeatedly counts from 0 to K-1 according to the clock signal generated by the clock and reset management module, and repeatedly addresses the K reference frequencies stored in the ROM memory from 0 to K-1 based on the count value, and finds the kth reference frequency f stored in the ROM memory by addressing when any count value is k. k, output K kinds of reference frequencies to the multi-frequency sine reference signal generator, and respectively calculate the two orthogonal reference sequences of the sine reference sequence and the cosine reference sequence under the k-th reference frequency and output them to the synchronous digital phase-locked unit corresponding to the k-th reference frequency. The multi-frequency sine reference signal generator is used to generate sine signals of K kinds of reference frequencies, and add the sine signals of the K kinds of reference frequencies to obtain a multi-frequency sine reference signal and output it to the DA conversion and low-pass filtering module through the DA conversion drive module.

[0018] Optionally, the synchronous digital phase-locked unit includes a data extraction module, a multiplier, an adder, a shift module, and an FIR filter connected in sequence. The data extraction module is used to extract impedance response signal sampling values ​​from the discrete impedance response signal sequence and input them into the multiplier. The multiplier is used to multiply the impedance response signal sampling values ​​with the sampling values ​​of two orthogonal reference sequences, namely, a sine reference sequence and a cosine reference sequence, at corresponding reference frequencies output by the reference frequency generation module to obtain an in-phase component and a quadrature component. The adder is used to accumulate the in-phase component and the quadrature component within a sampling period to obtain the in-phase component and the quadrature component of the entire discrete impedance response signal sequence. The shift module is used to perform a shift operation on the in-phase component and the quadrature component to replace the divider in the mean filter so that the calculation result is a fixed multiple relationship with the true value. The FIR filter is used to perform FIR low-pass filtering on the in-phase component and the quadrature component with a sampling frequency of 5 kHz and a cutoff frequency of 100 Hz to obtain the final in-phase component and the quadrature component.

[0019] Compared with the prior art, the present invention primarily achieves the following beneficial effects: the method of the present invention includes applying a multi-frequency sinusoidal reference signal excitation comprising K reference frequencies to a measured object to obtain an impedance response signal of the measured object; coherently sampling the impedance response signal; and synchronously digitally phase-locking a discrete impedance response signal sequence at each of the K reference frequencies to obtain amplitudes and phases at the K reference frequencies. By using the multi-frequency sinusoidal reference signal excitation at the K reference frequencies and synchronously digitally phase-locking the discrete impedance response signal sequence at each of the K reference frequencies to obtain amplitudes and phases at the K reference frequencies, multiple synchronous phase-locked amplification units are established and innovatively integrated with the multi-frequency sinusoidal reference signal excitation, enabling synchronous real-time demodulation of multi-frequency signals. System measurement results demonstrate that the method outperforms other DLIA systems in phase resolution and signal-to-noise ratio, and is one of the few DLIA systems currently supporting multi-frequency synchronous demodulation. The present invention improves the digital lock-in amplifier to enable synchronous processing of multi-frequency signals, reduces the design difficulty and resource consumption of the pass filter, and improves the accuracy and speed of the lock-in amplifier, making the digital lock-in amplifier stable, reliable, and widely adaptable. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1Schematic diagram of the basic process of the method of the embodiment of the present invention.

[0021] Figure 2 FIG. 4 is a time domain waveform diagram of a multi-frequency sinusoidal reference signal generated in an embodiment of the present invention.

[0022] Figure 3 FIG. 4 is a frequency domain waveform diagram of a multi-frequency sinusoidal reference signal generated in an embodiment of the present invention.

[0023] Figure 4 Schematic diagram of the structure of the device in an embodiment of the present invention.

[0024] Figure 5 Schematic diagram of the structure of the back-end unit in an embodiment of the present invention.

[0025] Figure 6 Schematic diagram of the structure of the reference frequency generation module in an embodiment of the present invention.

[0026] Figure 7 Schematic diagram of the structure of a synchronous digital phase-locked unit in an embodiment of the present invention.

[0027] Figure 8 : is the relative error distribution surface of the amplitude demodulation results under different amplitude and frequency signals in the embodiment of the present invention.

[0028] Figure 9 : is the measurement error distribution surface of the phase demodulation result under different phase and frequency signals in the embodiment of the present invention.

[0029] Figure 10 is a signal-to-noise ratio curve in an embodiment of the present invention.

[0030] Figure 11 The demodulation waveform comparison results of the two instruments at frequencies of 10 kHz and 25 kHz in the embodiment of the present invention are shown, where (a) is the amplitude comparison at a frequency of 25 kHz, (b) is the phase comparison at a frequency of 25 kHz, (c) is the amplitude comparison at a frequency of 10 kHz, and (d) is the phase comparison at a frequency of 10 kHz.

[0031] Legend: 1. Positive current source; 2. Negative current source; 3. Current amplifier; 4. Control processing module; 41. Reset management module; 42. AD conversion drive module; 43. Reference frequency generation module; 44. Synchronous digital phase-locked unit; 441. Data extraction module; 442. Multiplier; 443. Adder; 444. Shift module; 445. FIR filter; 45. Coordinate rotation digital calculation module; 46. FIFO storage queue; 47. FIFO read / write controller; 48. Multi-frequency sinusoidal reference signal generator; 49. DA conversion drive module; 5. DA conversion and low-pass filtering module; 6. Low-pass filtering and AD conversion module. DETAILED DESCRIPTION

[0032] In order to enable those skilled in the art to better understand the technical solution of the present invention, the technical solution of the present invention will be further described in detail below with reference to the accompanying drawings in the embodiments of the present invention.

[0033] like Figure 1 As shown, the multi-frequency digital phase-locked amplification method based on coherent sampling in this embodiment includes the following steps:

[0034] S101, applying a multi-frequency sinusoidal reference signal excitation including K reference frequencies to the object under test, and obtaining an impedance response signal of the object under test under the excitation of the multi-frequency sinusoidal reference signal;

[0035] S102, coherently sampling the impedance response signal to obtain a discrete impedance response signal sequence;

[0036] S103 , performing synchronous digital phase locking of K reference frequencies on the discrete impedance response signal sequence to obtain amplitudes and phases at the K reference frequencies.

[0037] In step S101 of this embodiment, a multi-frequency sinusoidal reference signal excitation including K reference frequencies is applied to the object under test, and when the impedance response signal of the object under test is obtained under the multi-frequency sinusoidal reference signal excitation, the multi-frequency sinusoidal reference signal excitation adopts a pair of current excitation electrodes. and The output is injected into the object under test, and the impedance response signal is passed through a pair of voltage detection electrodes and It should be noted that the method of this embodiment can be used with any object to be measured that contains impedance, which can be a human body or other objects such as cables, equipment, and the ground.

[0038] As an optional implementation, in this embodiment, the object to be measured is a human body, and the current excitation electrode and voltage detection electrodes The gap is placed on the skin of the neck of the subject, and the current excitation electrode and voltage detection electrodes The gaps are arranged at the heart skin of the subject under test. In this way, the cardiac impedance signal of the subject under test can be collected and used to predict multiple cardiac-related indicators of the subject under test. When a multi-frequency sinusoidal reference signal containing K reference frequencies is applied to the subject under test, the applied multi-frequency sinusoidal reference signal containing K reference frequencies can be expressed as:

[0039] ,

[0040] in, is a multi-frequency sinusoidal reference signal, ~ They are the sinusoidal reference signal components of the 1st to Kth reference frequencies. The sinusoidal reference signal components are all standard sinusoidal signals. The parameters of any kth sinusoidal reference signal component include its amplitude ,frequency and phase In this embodiment, the multi-frequency sinusoidal reference signal generation process combines signal synthesis and hardware implementation for collaborative optimization. In this embodiment, the base frequency is first determined according to the target frequency band. , and choose a series of prime numbers , generating the reference frequency To avoid harmonic interference in the demodulation result. In this embodiment, the base frequency is selected , They are 2, 3, 5, 7, 11, and 13 respectively. The generated multi-frequency sinusoidal reference signal time domain waveform is as follows Figure 2 As shown in the frequency domain waveform Figure 3 As shown, the K reference frequencies are 10 kHz , 15 kHz , 25 kHz , 35 kHz , 55 kHz , 65 kHz , with amplitudes of 0.167. Furthermore, to reduce the crest factor (CF) of the multi-frequency sinusoidal reference signal and improve the signal-to-noise ratio (SNR) of the measurement system, this embodiment utilizes a pre-trained phase prediction model to obtain the initial phases of the K reference frequencies. The pre-trained phase prediction model establishes a mapping relationship between the reference frequencies and their initial phases. The phase prediction model is trained to ensure that the crest factor (CF) of the multi-frequency sinusoidal reference signal is less than a preset threshold.

[0041] In step S102 of this embodiment, when coherent sampling is performed on the impedance response signal to obtain a discrete impedance response signal sequence, the frequency of the coherent sampling satisfies:

[0042] ,

[0043] in, is the kth reference frequency, is the sampling frequency, is a positive integer ( ), which indicates the integer multiple relationship between the signal period and the sampling interval (indicates that Among the sampling points, the signal The frequency components include complete cycle), is the number of sampling points, is the reference frequency number.

[0044] In step S102 of this embodiment, after coherent sampling is performed on the impedance response signal to obtain a discrete impedance response signal sequence, the obtained discrete impedance response signal can be expressed as:

[0045] ,

[0046] in, is the impedance response signal sampling value containing K reference frequencies, ~ They are the impedance response signal sampling values ​​of the 1st to Kth reference frequencies respectively.

[0047] In step S103 of this embodiment, when the discrete impedance response signal sequence is subjected to synchronous digital phase locking at K reference frequencies to obtain amplitudes and phases at the K reference frequencies, the synchronous digital phase locking at any reference frequency includes: generating two orthogonal reference sequences at the reference frequency, the two orthogonal reference sequences including a sine reference sequence and a cosine reference sequence, which can be expressed as:

[0048] ,

[0049] ,

[0050] in, and are the sine reference signal and cosine reference signal in the sine reference sequence and cosine reference sequence respectively, is the reference frequency, is the sampling frequency for coherent sampling of the impedance response signal, , is the number of sampling points; the discrete impedance response signal sequence is multiplied by the sine reference sequence and the cosine reference sequence to obtain the in-phase component and the quadrature component, which can be expressed as:

[0051] ,

[0052] ,

[0053] in, is the in-phase component at the kth reference frequency, is the orthogonal component at the kth reference frequency; the amplitude and phase at the corresponding reference frequency are calculated using the in-phase component and the orthogonal component, which can be expressed as:

[0054] ,

[0055] ,

[0056] in, is the amplitude at the kth reference frequency, is the phase at the kth reference frequency.

[0057] When the discrete impedance response signal sequence is multiplied by the sine reference sequence and the cosine reference sequence to obtain the in-phase component and the quadrature component, the function expressions of the discrete impedance response signal and the sine reference signal and the cosine reference signal are substituted into the function expressions, and the Euler formula is used to simplify to obtain:

[0058] ,

[0059] ,

[0060] ,

[0061] ,

[0062] in, 、 、 and is an intermediate variable, is the amplitude of the kth sinusoidal reference signal component, is the frequency of the kth sinusoidal reference signal component, is the phase of the kth sinusoidal reference signal component, is the imaginary unit, is the reference frequency. Since the coherent sampling condition is met:

[0063] ,

[0064] Then we can easily prove that the cumulative sum of non-zero frequency components is zero through geometric progression, that is:

[0065] ,

[0066] Therefore, the function expressions of the in-phase component and the orthogonal component can be further simplified as follows:

[0067] , ,

[0068] Therefore, according to the coherent sampling condition, the accumulated sum of non-zero frequency components can be ignored, and the amplitude and phase at the corresponding reference frequency can be directly calculated by the following formula:

[0069] ,

[0070] ,

[0071] in, is the amplitude at the kth reference frequency, is the phase at the kth reference frequency. Compared to traditional digital lock-in amplifiers based on I / Q demodulation, digital lock-in amplifiers based on multi-frequency sinusoidal coherent sampling achieve zero cumulative sum of demodulated high-frequency components when signal-correlated sampling conditions are met. Therefore, high-frequency interference components can theoretically be completely eliminated. However, in practical applications, due to factors such as quantization error, signal period fluctuations, and environmental noise, trace residual high-frequency components may still remain in the demodulation result. Therefore, a finite impulse response (FIR) low-pass filter is typically placed after the digital IQ demodulation module to suppress residual high-frequency noise and ensure high-precision signal amplitude and phase demodulation.

[0072] By analyzing the cardiac impedance signal, the amount of blood pumped by the heart per unit time, i.e., cardiac output, and the amount of blood pumped per heartbeat, i.e., stroke volume, can be calculated, thereby understanding the heart's pumping function. As an optional embodiment, step S103 further includes: normalizing the amplitude and phase at the K reference frequencies, and then using a pre-trained first machine learning model to predict the amount of blood pumped per unit time and the amount of blood pumped per heartbeat. The first machine learning model is pre-trained to establish a mapping relationship between the normalized amplitude and phase at the K reference frequencies, the amount of blood pumped per unit time, and the amount of blood pumped per heartbeat. The first machine learning model can be any desired machine learning model, for example, comprising an input layer, a hidden layer, and an output layer. The input layer has 2K neurons for inputting the normalized amplitude and phase at the K reference frequencies, and the output layer has 2 neurons for outputting the amount of blood pumped per unit time and the amount of blood pumped per heartbeat, respectively. The characteristic of this method is that it utilizes the amplitude and phase information at K reference frequencies, and improves the accuracy of the prediction of the amount of blood output by the heart per unit time and the amount of blood output per heartbeat by using the amplitude and phase information at multiple reference frequencies.

[0073] Cardiac impedance signals can help determine ejection fraction (EF), which is the percentage of ventricular end-diastolic volume (EDV) ejected during each heartbeat. This is an important indicator of cardiac function. As an optional implementation, step S103 may further include normalizing the amplitude and phase at K reference frequencies and then using a pre-trained second machine learning model to predict the percentage of ventricular end-diastolic volume (EDV) ejected during each heartbeat. The second machine learning model is pre-trained to establish a mapping relationship between the normalized amplitude and phase at K reference frequencies and the percentage of ventricular end-diastolic volume (EDV) ejected during each heartbeat. The second machine learning model can be any desired machine learning model, for example, including an input layer, a hidden layer, and an output layer. The input layer may have 2K neurons for inputting the normalized amplitude and phase at K reference frequencies, and the output layer may have 1 neuron for outputting the percentage of ventricular end-diastolic volume (EDV) ejected during each heartbeat. The characteristic of this method is that it utilizes the amplitude and phase information at K reference frequencies, and improves the accuracy of predicting the percentage of ventricular end-diastolic volume of blood ejected by the ventricle during each heartbeat by using the amplitude and phase information at multiple reference frequencies.

[0074] The cardiac impedance signal can reflect the heart's preload and afterload. Preload represents the volumetric load on the ventricles before contraction and is related to venous return; afterload is primarily related to arterial blood pressure and peripheral vascular resistance. By analyzing the cardiac impedance signal, the heart's load state can be assessed. As an optional embodiment, step S103 further includes: normalizing the amplitude and phase at K reference frequencies, and then using a pre-trained third machine learning model to predict the heart's preload and afterload states. The third machine learning model is pre-trained to establish a mapping relationship between the normalized amplitude and phase at the K reference frequencies and the heart's preload and afterload states. The third machine learning model can be any desired machine learning model, for example, comprising an input layer, a hidden layer, and an output layer. The input layer has 2K neurons for inputting the normalized amplitude and phase at the K reference frequencies, and the output layer has 2 neurons for outputting the heart's preload and afterload states. The characteristic of this method is that it utilizes the amplitude and phase information at K reference frequencies, and improves the accuracy of predicting the preload state and afterload state of the heart by using the amplitude and phase information at multiple reference frequencies.

[0075] The characteristic points and waveform changes of the cardiac impedance signal can indirectly reflect myocardial contractility. For example, the amplitude of the C wave in the cardiac impedance differential signal is primarily used to determine stroke volume and cardiac output. Its magnitude is correlated with myocardial contractility, and an increased C wave amplitude generally indicates increased myocardial contractility. As an optional embodiment, after step S103, the method further includes: normalizing the amplitude and phase at K reference frequencies, and then predicting myocardial contractility using a pre-trained fourth machine learning model. The pre-trained fourth machine learning model establishes a mapping relationship between the normalized amplitude and phase at the K reference frequencies and myocardial contractility. The fourth machine learning model can be any desired machine learning model, for example, comprising an input layer, a hidden layer, and an output layer. The input layer has 2K neurons for inputting the normalized amplitude and phase at the K reference frequencies, and the output layer has 1 neuron for outputting myocardial contractility. This method is characterized by utilizing information about the amplitude and phase at K reference frequencies, improving the accuracy of myocardial contractility prediction by leveraging information about the amplitude and phase at multiple reference frequencies.

[0076] like Figure 4 As shown, this embodiment also provides a multi-frequency digital lock-in amplifier device for applying a multi-frequency digital lock-in amplifier method based on coherent sampling, including a front-end unit and a back-end unit, wherein the front-end unit includes a positive current source 1, a negative current source 2 and a current amplifier 3, wherein the positive current source 1 and the negative current source 2 respectively have current excitation electrodes and To output a multi-frequency sinusoidal reference signal containing K reference frequencies, the current amplifier 3 has a pair of voltage detection electrodes and For collecting impedance response signals, the back-end unit includes a control processing module 4, a DA conversion and low-pass filtering module 5, and a low-pass filtering and AD conversion module 6. The output end of the control processing module 4 is connected to the control end of the positive current source 1 and the negative current source 2 respectively through the DA conversion and low-pass filtering module 5, and the input end of the control processing module 4 is connected to the output end of the current amplifier 3 through the low-pass filtering and AD conversion module 6. The control processing module 4 is used to control the positive current source 1 and the negative current source 2 to generate a multi-frequency sinusoidal reference signal, and to process the impedance response signal output by the current amplifier 3 to obtain the amplitude and phase at K reference frequencies.

[0077] like Figure 5As shown, the control processing module 4 includes an FPGA module and an ARM processor interconnected by a bus. The FPGA module includes a clock and reset management module 41, an AD conversion drive module 42, a reference frequency generation module 43, a synchronous digital phase-locked unit 44, a coordinate rotation digital calculation module 45, a FIFO storage queue 46, a FIFO read-write controller 47, a multi-frequency sinusoidal reference signal generator 48 and a DA conversion drive module 49. The clock and reset management module 41 provides clock and reset signals to the AD conversion drive module 42, the reference frequency generation module 43, the coordinate rotation digital calculation module 45, the FIFO storage queue 46, the FIFO read-write controller 47, the multi-frequency sinusoidal reference signal generator 48 and the DA conversion drive module 49 respectively. The AD conversion drive module 42 is connected to the drive signal end of the low-pass filter and AD conversion module 6. The number of the synchronous digital phase-locked units 44 is K, and the input ends are all connected to the output end of the low-pass filter and AD conversion module 6. The synchronous digital phase-locked unit 44, the coordinate rotation digital calculation module 45, and the FIFO storage queue 46 are connected in sequence. The synchronous digital phase-locked unit 44 is used to multiply the discrete impedance response signal sequence with the two orthogonal reference sequences of the sine reference sequence and the cosine reference sequence at the corresponding reference frequency output by the reference frequency generation module 43 to obtain the in-phase component and the quadrature component. The coordinate rotation digital calculation module 45 is used to calculate the amplitude and phase at the corresponding reference frequency based on the in-phase component and the quadrature component. The coordinate rotation digital calculation module 45 is connected to the FIFO read-write controller 47 to write the amplitude and phase at each reference frequency into the FIFO storage queue 46. The ARM processor is connected to the FIFO storage queue 46 and the FIFO read-write controller 47 through the bus to read the amplitude and phase at each reference frequency stored in the FIFO storage queue 46 and perform moving average filtering, format conversion, and data packet encapsulation in sequence, and then output through its data communication interface, as shown in FIG. Figure 6 As shown, the reference frequency generation module 43 includes an address accumulator AA and a ROM memory for storing K reference frequencies. The address accumulator AA repeatedly counts from 0 to K-1 according to the clock signal generated by the clock and reset management module 41, and repeatedly addresses the K reference frequencies stored in the ROM memory from 0 to K-1 based on the count value, and finds the kth reference frequency f stored in the ROM memory by addressing when any count value is k. k, output K reference frequencies to the multi-frequency sine reference signal generator 48, and respectively calculate the two orthogonal reference sequences of the sine reference sequence and the cosine reference sequence under the k-th reference frequency and output them to the synchronous digital phase-locked unit 44 corresponding to the k-th reference frequency. The multi-frequency sine reference signal generator 48 is used to generate sine signals of K reference frequencies, and add the sine signals of the K reference frequencies to obtain a multi-frequency sine reference signal and output it to the DA conversion and low-pass filtering module 5 through the DA conversion drive module 49, as shown. Figure 4 shown.

[0078] like Figure 5 As shown, in this embodiment, the clock and reset management module 41 generates the clock and reset signals required for the normal operation of each module through a phase-locked loop (PLL). The clock signal of each address accumulator AA output by the phase-locked loop is calculated by the following formula:

[0079] ,

[0080] in, is the clock signal output to the address accumulator AA in the k-th synchronous digital phase-locked unit 44, is the kth reference frequency, The number of sampling points is 5000 per cycle in this embodiment to achieve a higher phase resolution and take into account the frequency division capability of the phase-locked loop. The sine sequences under the frequency components are shifted, superimposed and normalized, and the synthesized multi-frequency sine reference signal sequence is transmitted to the DA conversion and low-pass filtering module 5 for digital-to-analog conversion. In the DA conversion and low-pass filtering module 5, the high-frequency quantization noise is filtered out by a 6th-order Butterworth low-pass filter, and finally the multi-frequency sine reference signal in the form of a corresponding analog signal is output.

[0081] like Figure 7As shown, the synchronous digital phase-locked unit 44 includes a data extraction module 441, a multiplier 442, an adder 443, a shift module 444, and an FIR filter 445 connected in sequence. The data extraction module 441 is used to extract impedance response signal sampling values ​​from the discrete impedance response signal sequence and send them to the multiplier 442. The multiplier 442 is used to multiply the impedance response signal sampling values ​​with the sampling values ​​of the two orthogonal reference sequences of the sine reference sequence and the cosine reference sequence at the corresponding reference frequency output by the reference frequency generation module 43 to obtain the same phase. The adder 443 is used to accumulate the in-phase component and the quadrature component within a sampling period to obtain the in-phase component and the quadrature component of the entire discrete impedance response signal sequence. The shift module 444 is used to perform a shift operation on the in-phase component and the quadrature component to replace the divider in the mean filter so that the calculation result is a fixed multiple relationship with the true value. The FIR filter 445 is used to perform FIR low-pass filtering with a sampling frequency of 5 kHz and a cutoff frequency of 100 Hz on the in-phase component and the quadrature component to obtain the final in-phase component and quadrature component.

[0082] The core of the multi-frequency digital coherent sampling and demodulation is to realize the multi-frequency digital coherent sampling and demodulation based on the FPGA high-speed parallel architecture. The core of the multi-frequency digital coherent sampling and demodulation is to ensure that the frequency components of the signal to be measured strictly meet the constraints of coherent sampling, that is, the sampling frequency of the signal to be demodulated is The signal to be measured Reference frequency Satisfy integer multiples N In order to reduce the ADC sampling frequency in the low-pass filter and AD conversion module 6 To achieve this goal, the phase-locked amplifier units corresponding to different frequency components must have independent parameter configurations to ensure that all frequency components are demodulated in a unified time window. ( m is an integer, Specifically, each phase-locked amplifier unit needs to complete coherent sampling according to different reference frequencies. Set data extraction frequency and the total number of sampling points In this embodiment , , the parameter configuration of each synchronous digital phase-locked unit 44 is shown in Table 1.

[0083] Table 1 Parameter configuration table of each synchronous digital phase-locked unit 44

[0084]

[0085] When the data extraction frequency Exceeds the ADC sampling frequency in the low-pass filter and AD conversion module 6 When the system adopts the upsampling strategy, the ADC sampling frequency is increased to the data extraction frequency by repeating the current sampling value. Although this method will introduce high-frequency image harmonics, their energy is mainly distributed in the stop band of the FIR filter at the rear stage of the synchronous digital phase-locked unit 44, and will not have much impact on the demodulation accuracy. The device of this embodiment performs the above-mentioned coherent sampling and low-pass filtering (LPF) on the demodulated signal through the low-pass filtering and AD conversion module 6 to suppress high-frequency noise, and then inputs multiple parallel phase-locked amplifier units to perform multi-frequency synchronous demodulation on each frequency component. Each phase-locked amplifier unit is in the fundamental frequency period. The orthogonal mixing operation is triggered based on the rising edge of the sampling clock to complete the multiplication and accumulation operation of the demodulated sequence and the reference sequence of each frequency component, and the average operation without a divider is realized through the shift operation. The amplitude ratio error is compensated in real time by the pre-stored calibration coefficient, and the phase measurement accuracy is not affected. The in-phase component and the orthogonal component of the demodulated output are filtered out by the FIR low-pass filter to remove the residual high-frequency component and then the in-phase component corresponding to each frequency component is output. and orthogonal components , where the filter sampling frequency is set to 5kHz and the cutoff frequency is set to 100Hz. The in-phase component output by the lock-in amplifier unit and orthogonal components The coordinate rotation digital calculation module 45 is converted into the corresponding 28-bit high-precision fixed-point amplitude and phase information, and the output amplitude and phase information is stored in the FIFO queue 46 (write clock 5) of the dual clock domain. kHz , read clock 1 kHz ) After buffering, the data is transferred to the ARM processor for calibration (moving average filtering and format conversion) according to the AXI-Lite protocol. It is then encapsulated into a data packet containing 32-bit floating-point amplitude and phase information and uploaded to the host computer via the serial port at a baud rate of 921600bps. In this embodiment, a GUI interface was built on the host computer based on MATLAB. This interface integrates four parts: serial port configuration, measurement, storage, and display. The serial port configuration module is mainly used to set the serial port number and baud rate, as well as start and stop the serial port; the measurement module is mainly used to select single-frequency demodulation or multi-frequency (up to six frequencies) synchronous demodulation mode; and the display module can synchronously plot the amplitude-phase dynamic characteristics of the corresponding frequency demodulated within 10 seconds within a time domain window. To meet the measurement requirements in different noise environments, the demodulated waveform data shown here has undergone time-domain MAF (Moving Average Filtering) with a window length of 99. In addition, the data storage module has built-in multiple file export formats, supporting the synchronous output of amplitude, phase, and other data demodulated at different frequencies, providing a standardized data source for subsequent offline analysis.

[0086] To evaluate the amplitude demodulation accuracy of the multi-frequency digital lock-in amplifier (MSCS-DLIA) of this embodiment, an external signal generator (SDG6052X-E, SIGLENT, 2mVpp-20Vpp) was used to generate a sinusoidal signal with a frequency of 5kHz-100kHz and an amplitude of 1-1000mV for demodulation. The average demodulated amplitude within 1s was calculated as the demodulation result. Figure 8 is the relative error distribution surface of the amplitude demodulation results under different amplitude and frequency signals in this embodiment. Figure 8 As can be seen from the amplitude axis, the amplitude demodulation error gradually increases as the signal amplitude decreases. For signals above 5mV, the system amplitude demodulation error remains below 0.5%. However, for signals of 1mV, the error increases significantly, reaching 1.04%-2.22%. This is primarily due to the signal approaching the system noise floor, which increases the quantization error. From the frequency axis, the amplitude demodulation error is relatively small as the frequency increases. The error increases slightly with increasing signal frequency, presumably due to sampling uncertainty caused by clock jitter, but the overall impact is weaker than the amplitude factor. Table 2 shows typical demodulation data for various amplitude signals at a base frequency of 5kHz using the multi-frequency digital lock-in amplifier (MSCS-DLIA) of this embodiment.

[0087] Table 2: Typical demodulated data of various amplitude signals at a base frequency of 5 kHz

[0088]

[0089] The errors of the multi-frequency digital lock-in amplifier (MSCS-DLIA) of this embodiment mainly come from calibration errors caused by amplitude compensation, ADC quantization errors, and clock jitter. The amplitude measurement accuracy can be improved by adopting more reliable data fitting methods to calibrate the amplitude data, increasing the number of ADC bits, or amplifying the signal to be measured.

[0090] To quantitatively evaluate the phase measurement accuracy of the multi-frequency digital lock-in amplifier (MSCS-DLIA) of this embodiment, a synchronous sinusoidal test signal with a frequency of 5 kHz to 100 kHz and an initial phase of 0° to 90° was generated using the Redpitaya platform, and the 1-s measurement average was taken as the system demodulation result. Figure 9 This is the measurement error distribution curve of the phase demodulation results under different phase and frequency signals in this embodiment. Figure 9As can be seen from the phase axis, when the phase difference between the reference signal and the measured signal is close to quadrature (0° or 90°), the phase measurement error is less than 0.002°. When the phase difference deviates from quadrature to 50°, the error peaks at 0.014°. These test results are consistent with previous research findings, indicating that the phase error of the lock-in amplifier is related to the phase difference between the reference signal and the measured signal. When the phase difference is 0° or 90°, the system is in the optimal detection state, with the highest signal-to-noise ratio and the lowest error. When the phase difference deviates from these angles, the signal-to-noise ratio decreases and the error increases. From the frequency axis, frequency changes have little effect on phase error. Therefore, this article uses typical data at a fundamental frequency of 5 kHz as an example to demonstrate the phase demodulation accuracy in detail, as shown in Table 3.

[0091] Table 3: 5kHz phase demodulation error

[0092]

[0093] To quantitatively evaluate the signal-to-noise ratio (SNR) of the multi-frequency digital lock-in amplifier (MSCS-DLIA) of this embodiment, this embodiment uses a direct measurement method. By repeatedly measuring the amplitude fluctuations of a stable signal, the signal power and noise power are separated to quantify the system performance. The specific experimental method is as follows: A low-distortion signal generator is used to output a sine wave signal with a frequency of 5 kHz and an amplitude range of 1 mV to 1 V. The MSCS-DLIA demodulates the signal to obtain its instantaneous amplitude. ,in is the number of measurements, Take 10000. Based on statistical characteristics, assuming that the signal amplitude is stable in multiple measurements, its power Estimated by the following formula:

[0094] ;

[0095] Noise is characterized by the variance of the measured value, and the fluctuation of the amplitude can be calculated according to the following formula :

[0096] ;

[0097] The system signal-to-noise ratio can be obtained as follows:

[0098] ,

[0099] Figure 10 is the signal-to-noise ratio curve in the embodiment of the present invention. Figure 10 It can be seen that the multi-frequency digital lock-in amplifier (MSCS-DLIA) of this embodiment has a signal-to-noise ratio (SNR) of 81.21 dB when the input signal amplitude is 1 V, which is close to the theoretical limit of 14-bit ADC ( ), demonstrating that the system noise floor and quantization noise are effectively suppressed. When the signal amplitude drops to 1 mV, the signal-to-noise ratio (SNR) remains at 45.3 dB, validating its reliability in weak signal detection. The deviation between the theoretical and measured values ​​is primarily caused by ADC quantization error and clock jitter. Increasing the number of ADC bits can significantly improve the system's SNR.

[0100] In addition, for the measurement scenario of cardiac impedance signals, due to the limitations of FPGA hardware resources and phase-locked loop (PLL) frequency division capabilities, two reference frequency components of 10kHz and 25kHz are selected in this embodiment to construct a multi-frequency sinusoidal reference signal for demodulation. In order to verify the reliability of the multi-frequency digital phase-locked amplifier (MSCS-DLIA) of this embodiment, the commercial impedance analyzer MFIA of Zurich Instruments of Switzerland was selected as a reference to conduct an independent demodulation experiment on the cardiac impedance signal of the same subject. It should be noted that the demodulation experiments of the two instruments are based on the acquisition of impedance signals by the same subject under the same physiological state, but a time-sharing independent test mode is used to avoid the influence of reference signal interference between systems on the measurement results. Figure 11 Comparisons of demodulated waveforms at 10 kHz and 25 kHz are shown for the multi-frequency digital lock-in amplifier (MSCS-DLIA) and the MFIA of this embodiment. (a) shows the amplitude comparison at 25 kHz, (b) the phase comparison at 25 kHz, (c) the amplitude comparison at 10 kHz, and (d) the phase comparison at 10 kHz. The experimental data demonstrates that the amplitude and phase waveforms demodulated by the MSCS-DLIA are distinct and stable, and highly consistent with the MFIA demodulation results in the time domain. This demonstrates that the MSCS-DLIA possesses comparable stability and feature extraction capabilities to commercial instruments for multi-frequency synchronous demodulation.

[0101] A comparison of the core performance indicators of the multi-frequency digital lock-in amplifier (MSCS-DLIA) of this embodiment with those of a commercial impedance analyzer (MFIA) and other typical homemade digital lock-in amplifiers (DLIAs) shows that, using only a 14-bit ADC, the multi-frequency digital lock-in amplifier (MSCS-DLIA) of this embodiment achieves a phase resolution of 0.002°, significantly outperforming the other compared solutions. Its signal-to-noise ratio (SNR) reaches 81.21 dB, approaching the theoretical limit of 86dB for systems using a 14-bit ADC, validating the effectiveness of its noise suppression mechanism. Compared to existing DLIA systems, the core advantage of the multi-frequency digital lock-in amplifier (MSCS-DLIA) of this embodiment lies in its use of a multi-frequency sinusoidal reference signal to capture the amplitude and phase characteristics of the multi-frequency response in real time, while also supporting multi-frequency synchronous demodulation by establishing multiple synchronized lock-in amplifier units. Existing digital lock-in amplifiers, such as MFIAs, can demodulate multiple frequencies, but they typically rely on deploying multiple complete lock-in amplifiers. Their reference signals are typically output via multiple channels or simply summed sine waves of different frequencies. This not only affects the accuracy of multi-frequency measurements but also significantly increases costs.

[0102] In terms of frequency range, the PLL module of the XC7Z010CLG-1 series FPGA selected by the multi-frequency digital lock-in amplifier (MSCS-DLIA) of this embodiment is limited by the device speed grade. Its theoretical maximum output frequency is 800MHz. Experimental verification shows that the system can maintain stable operation at an operating frequency of 600MHz. Based on the above parameter configuration in this embodiment, the maximum operating frequency of the multi-frequency digital lock-in amplifier (MSCS-DLIA) of this embodiment is Theoretical deduction can be made through the following formula:

[0103] KHz,

[0104] in, It is the stable output clock of the phase-locked loop PLL. Although it is lower than some comparison solutions, it can be improved by reducing the number of sampling points. N, its maximum operating frequency can be expanded to meet the measurement requirements of high-frequency weak signals. For example, when N is reduced to 100, the maximum operating frequency is increased to 12 MHz. At this point, the multi-frequency digital lock-in amplifier (MSCS-DLIA) of this embodiment, while sacrificing some phase accuracy, still maintains good performance. Regarding the amplitude measurement range, the system defaults to a dynamic range of 60 dB, specifically designed for bioimpedance signals. For sub-millivolt weak signals, a pre-low-noise amplifier can effectively detect them. Furthermore, the multi-frequency digital lock-in amplifier (MSCS-DLIA) of this embodiment features a compact hardware design (105 mm × 65 mm × 25 mm) and costs only 5% of an MFIA system (approximately $550), offering significant cost-effectiveness in portable medical devices and industrial embedded systems. In summary, the multi-frequency digital lock-in amplifier (MSCS-DLIA) of this embodiment, through its multi-frequency synchronous detection design, overcomes the bottlenecks of traditional solutions in multi-frequency real-time detection, accuracy, and cost, providing a new option for weak signal analysis in complex scenarios. In summary, this embodiment constructs a multi-frequency digital phase-locked amplifier (MSCS-DLIA) based on the traditional DLIA system. By establishing multiple synchronous phase-locked amplifier units and innovatively integrating multi-frequency sinusoidal reference signal excitation, it achieves synchronous real-time demodulation of multi-frequency signals. System measurement results show that it outperforms other DLIA systems in phase resolution and signal-to-noise ratio, and is one of the few DLIA systems currently supporting multi-frequency synchronous demodulation. In addition, the results of cardiac impedance blood flow graph measurements show that the system successfully extracts the multi-frequency amplitude and phase characteristics of human cardiac impedance signals, demonstrating its engineering value in multi-frequency synchronous measurement. It can provide a highly reliable, low-latency detection solution for scenarios such as cardiac index detection and real-time hemodynamic index monitoring.

[0105] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiment. All technical solutions based on the concept of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, various improvements and modifications that do not depart from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A multi-frequency digital phase-locked amplification method based on coherent sampling, characterized in that: The steps include: S101, applying a multi-frequency sinusoidal reference signal excitation including K reference frequencies to the object under test, and obtaining an impedance response signal of the object under test under the excitation of the multi-frequency sinusoidal reference signal; S102, coherently sampling the impedance response signal to obtain a discrete impedance response signal sequence; the frequency of the coherent sampling satisfies: ； in, is the kth reference frequency, is the sampling frequency; is a positive integer, indicating the integer multiple relationship between the period of the impedance response signal and the sampling interval. Among the sampling points, the impedance response signal The frequency components include A complete cycle; is the number of sampling points, , is the reference frequency number; S103, performing synchronous digital phase locking of K reference frequencies on the discrete impedance response signal sequence to obtain amplitudes and phases at the K reference frequencies; When the discrete impedance response signal sequence is subjected to synchronous digital phase locking at K reference frequencies in step S103 to obtain amplitudes and phases at the K reference frequencies, the synchronous digital phase locking at any reference frequency includes: generating two orthogonal reference sequences at the reference frequency, the two orthogonal reference sequences including a sine reference sequence and a cosine reference sequence; multiplying the discrete impedance response signal sequence by the sine reference sequence and the cosine reference sequence respectively to obtain an in-phase component and a quadrature component; and calculating the amplitude and phase at the corresponding reference frequency using the in-phase component and the quadrature component.

2. The multi-frequency digital phase-locked amplification method based on coherent sampling according to claim 1, characterized in that: In step S101, a multi-frequency sinusoidal reference signal excitation including K reference frequencies is applied to the object under test to obtain the impedance response signal of the object under test under the multi-frequency sinusoidal reference signal excitation. The multi-frequency sinusoidal reference signal excitation adopts a pair of current excitation electrodes. and The output is injected into the object under test, and the impedance response signal is passed through a pair of voltage detection electrodes and It is detected that the object to be measured is a human body, and the current excitation electrode and voltage detection electrodes The gap is placed on the skin of the neck of the subject, and the current excitation electrode and voltage detection electrodes The gaps are arranged at the heart and skin of the subject.

3. The multi-frequency digital phase-locked amplification method based on coherent sampling according to claim 2, characterized in that: Step S103 also includes: after normalizing the amplitude and phase at K kinds of reference frequencies, using a pre-trained first machine learning model to predict the amount of blood output by the heart per unit time and the amount of blood output per heartbeat, the first machine learning model is pre-trained to establish a mapping relationship between the normalized amplitude and phase at K kinds of reference frequencies, the amount of blood output by the heart per unit time, and the amount of blood output per heartbeat.

4. The multi-frequency digital lock-in amplification method based on coherent sampling according to claim 2, characterized in that: Step S103 also includes: after normalizing the amplitude and phase at K kinds of reference frequencies, using a pre-trained second machine learning model to predict the percentage of blood volume ejected by the ventricles during each heartbeat to the end-diastolic volume of the ventricles, the second machine learning model is pre-trained to establish a mapping relationship between the normalized amplitude and phase at K kinds of reference frequencies and the percentage of blood volume ejected by the ventricles during each heartbeat to the end-diastolic volume of the ventricles.

5. The multi-frequency digital lock-in amplification method based on coherent sampling according to claim 2, characterized in that: Step S103 also includes: after normalizing the amplitude and phase at K kinds of reference frequencies, using a pre-trained third machine learning model to predict the preload state and afterload state of the heart, the third machine learning model is pre-trained to establish a mapping relationship between the normalized amplitude and phase at K kinds of reference frequencies, and the preload state and afterload state of the heart.

6. The multi-frequency digital lock-in amplification method based on coherent sampling according to claim 2, characterized in that: Step S103 also includes: after normalizing the amplitude and phase at K reference frequencies, using a pre-trained fourth machine learning model to predict myocardial contractility, the fourth machine learning model is pre-trained to establish a mapping relationship between the normalized amplitude and phase at K reference frequencies and myocardial contractility.

7. A multi-frequency digital lock-in amplifier device for applying the multi-frequency digital lock-in amplifier method based on coherent sampling according to any one of claims 1 to 6, characterized in that: The invention comprises a front-end unit and a back-end unit, wherein the front-end unit comprises a positive current source (1), a negative current source (2) and a current amplifier (3), wherein the positive current source (1) and the negative current source (2) respectively have current excitation electrodes. and For outputting a multi-frequency sinusoidal reference signal containing K reference frequencies, the current amplifier (3) has a pair of voltage detection electrodes and The invention is used for collecting impedance response signals. The back-end unit comprises a control processing module (4), a DA conversion and low-pass filtering module (5) and a low-pass filtering and AD conversion module (6). The output end of the control processing module (4) is respectively connected to the control end of the positive current source (1) and the negative current source (2) through the DA conversion and low-pass filtering module (5). The input end of the control processing module (4) is connected to the output end of the current amplifier (3) through the low-pass filtering and AD conversion module (6). The control processing module (4) is used to control the positive current source (1) and the negative current source (2) to generate a multi-frequency sinusoidal reference signal, and to process the impedance response signal output by the current amplifier (3) to obtain the amplitude and phase at K reference frequencies.

8. The multi-frequency digital lock-in amplifier device according to claim 7, characterized in that: The control processing module (4) includes an FPGA module and an ARM processor interconnected by a bus, the FPGA module includes a clock and reset management module (41), an AD conversion drive module (42), a reference frequency generation module (43), a synchronous digital phase-locked unit (44), a coordinate rotation digital calculation module (45), a FIFO storage queue (46), a FIFO read-write controller (47), a multi-frequency sinusoidal reference signal generator (48) and a DA conversion drive module (49), the clock and reset management module (41) is respectively an AD conversion drive module (42), a reference frequency generation module (43), a coordinate rotation digital calculation module (45), a FIFO storage queue (46), a FIFO read-write controller (47), a multi-frequency sinusoidal reference signal generator (48) and a DA conversion drive module (49). The block (45), the FIFO storage queue (46), the FIFO read-write controller (47), the multi-frequency sinusoidal reference signal generator (48) and the DA conversion drive module (49) provide clock and reset signals, the AD conversion drive module (42) is connected to the drive signal end of the low-pass filter and AD conversion module (6), the number of the synchronous digital phase-locked units (44) is K and the input ends are all connected to the output end of the low-pass filter and AD conversion module (6), the synchronous digital phase-locked unit (44), the coordinate rotation digital calculation module (45) and the FIFO storage queue (46) are connected in sequence, and the synchronous digital phase-locked unit (44) is used to convert the discrete resistor The anti-response signal sequence is multiplied with the two orthogonal reference sequences of the sine reference sequence and the cosine reference sequence at the corresponding reference frequency output by the reference frequency generation module (43) to obtain the in-phase component and the orthogonal component. The coordinate rotation digital calculation module (45) is used to calculate the amplitude and phase at the corresponding reference frequency according to the in-phase component and the orthogonal component. The coordinate rotation digital calculation module (45) is connected to the FIFO read-write controller (47) to write the amplitude and phase at each reference frequency into the FIFO storage queue (46). The ARM processor is connected to the FIFO storage queue (46) and the FIFO read-write controller (47) through a bus. The invention is used to read the amplitude and phase of each reference frequency stored in the FIFO storage queue (46) and perform moving average filtering, format conversion, and data packet encapsulation in sequence and then output through its data communication interface. The reference frequency generation module (43) includes an address accumulator AA and a ROM memory for storing K reference frequencies. The address accumulator AA repeatedly counts from 0 to K-1 according to the clock signal generated by the clock and reset management module (41), and repeatedly addresses the K reference frequencies stored in the ROM memory from 0 to K-1 based on the count value, and finds the kth reference frequency f stored in the ROM memory by addressing when any count value is k. k , outputting K reference frequencies to a multi-frequency sinusoidal reference signal generator (48), and respectively calculating two orthogonal reference sequences of a sinusoidal reference sequence and a cosine reference sequence at the kth reference frequency and outputting them to a synchronous digital phase-locked unit (44) corresponding to the kth reference frequency, wherein the multi-frequency sinusoidal reference signal generator (48) is used to generate sinusoidal signals of K reference frequencies, and summing up the sinusoidal signals of the K reference frequencies to obtain a multi-frequency sinusoidal reference signal and outputting it to a DA conversion and low-pass filtering module (5) through a DA conversion drive module (49).

9. The multi-frequency digital lock-in amplifier device according to claim 8, characterized in that: The synchronous digital phase-locked unit (44) comprises a data extraction module (441), a multiplier (442), an adder (443), a shift module (444) and an FIR filter (445) connected in sequence, wherein the data extraction module (441) is used to extract impedance response signal sampling values ​​from a discrete impedance response signal sequence and send them to the multiplier (442), and the multiplier (442) is used to compare the impedance response signal sampling values ​​with the sampling values ​​of two orthogonal reference sequences, namely, the sine reference sequence and the cosine reference sequence, at the corresponding reference frequency output by the reference frequency generation module (43). The in-phase component and the quadrature component are multiplied to obtain the in-phase component and the quadrature component. The adder (443) is used to accumulate the in-phase component and the quadrature component within a sampling period to obtain the in-phase component and the quadrature component of the entire discrete impedance response signal sequence. The shift module (444) is used to perform a shift operation on the in-phase component and the quadrature component to replace the divider in the mean filter so that the calculation result and the true value are in a fixed multiple relationship. The FIR filter (445) is used to perform FIR low-pass filtering with a sampling frequency of 5 kHz and a cutoff frequency of 100 Hz on the in-phase component and the quadrature component to obtain the final in-phase component and the quadrature component.

Images