A pseudo-synchronous sampling method for asynchronous ADC based on DFT sampling point offset

Abstract

The present invention provides a pseudo-synchronous sampling method for asynchronous ADCs based on DFT sampling point offset, which is implemented based on a discrete Fourier algorithm and includes the following steps: step (1): offsetting the DFT sampling point of the phase difference caused by the time delay of channel switching and conversion of the asynchronous ADC, and obtaining the DFT coefficients of any channel in the same ADC after the DFT sampling point offset; step (2): offsetting the DFT sampling point of the phase difference caused by asynchronous sampling between different ADC chips; superimposing the sampling point offsets caused by the phase difference between AD channels and between different ADCs, and obtaining the DFT coefficients of any AD channel of a relay protection device after the DFT sampling point offset. The present invention compensates for the sampling point offset of the asynchronous sampling signal by utilizing the spectrum characteristics of DFT, thereby realizing pseudo-synchronous sampling and improving the signal reconstruction accuracy and spectrum analysis accuracy.

Description

Technical Field

[0001] The present invention belongs to the field of power protection and control, and relates to a pseudo-synchronous sampling method of an asynchronous analog-to-digital converter (ADC) based on discrete Fourier transform (DFT) sampling point offset, which is suitable for signal reconstruction and spectrum analysis in an asynchronous sampling system. Background Art

[0002] In power system relay protection devices, voltage and current phasors are crucial variables for describing system operating status. The phase relationship between voltage and current at each node is a crucial basis for stability assessment and analysis. Phasor measurements include frequency, phase angle, and amplitude, with phase angle and frequency being the primary focus. Measuring the phase difference between different signals is crucial for ensuring power grid security. Analog-to-digital converters (ADCs) with synchronous sampling and independent multi-channel inputs are ideal for these applications. However, to reduce channel count and control costs, non-synchronous sampling, multi-channel input ADCs with internal multiplexers, such as the AD7616, ADS8686S, and BL1088, are often used in real-world applications.

[0003] When a multiplexed input asynchronous sampling ADC cycles through and converts its input channels one by one, a conversion time delay is introduced between channels. This delay depends on the ADC's channel switching and sampling rate. From a system perspective, this time delay creates a system-level phase error between the analog channels. Assume that the same 50Hz sine wave signal is applied to the input of an 8-channel multiplexed ADC (all channels share a common input source), and the ADC samples each channel at a 1MSPS rate. When the final ADC conversion result is read, a discrete Fourier transform (DFT) algorithm is used to calculate the phase angle between the channels. In theory, the phase angle difference between the first and second channels is: .

[0004] To address this issue, the reference designs in patents CN102946251, "A Method for Implementing Multi-Channel Synchronous Sampling in a Multi-Channel Asynchronous Sampling ADC," and CN101764614, "V-Shaped Sampling Method for FPGA-Based AD Converters," introduce a method to compensate for the additional phase delay caused by channel switching on the multiplexer. This method samples the signal twice, around the reference sampling time point, and then averages the two sampled values ​​from the same channel to form the data for the quasi-synchronous sampling point. To ensure that the time difference between the two sampling points and the reference sampling time point is as close as possible, a V-shaped sampling method is proposed, alternating sequential and reverse sampling. This involves additional channel switching operations, and the different time differences between channels have different impacts on the quasi-synchronous sampling values ​​(average values) of each channel, potentially introducing new errors. Summary of the Invention

[0005] To address the shortcomings of existing methods, this paper proposes a pseudo-synchronous sampling method based on DFT sampling point offsets. This method compensates for phase angle differences between asynchronously sampled ADC channels without changing the sampling order or the amount of sampled data, achieving the computational effect of synchronous sampling. This method can also be used to address asynchronous sampling between different ADCs, further expanding the number of AC input channels in the device.

[0006] In order to compensate for the phase angle difference between asynchronous sampling ADC channels, the present invention introduces a sampling point offset method based on the conventional discrete Fourier algorithm, performs DFT calculation on the data of each sampling channel, and then realizes phase difference compensation of each channel and realizes pseudo-synchronous sampling of asynchronous sampling ADC.

[0007] This technical solution is based on the discrete Fourier algorithm and includes the following steps:

[0008] Step (1): Based on the DFT sampling point offset of the phase difference caused by the channel switching and conversion time delay of the asynchronous ADC, the DFT coefficients of any channel in the same ADC after the DFT sampling point offset are obtained, thereby realizing pseudo-synchronous conversion of the sampling data of the asynchronous ADC;

[0009] Step (2): Based on the DFT sampling point offset of the phase difference caused by the asynchronous sampling between different ADC chips, the sampling point offset caused by the phase difference between AD channels and different ADCs is superimposed to obtain the DFT coefficients of any AD channel of the relay protection device after the DFT sampling point offset, thereby realizing the pseudo-synchronous conversion of the sampling data of the asynchronous ADC of the entire device.

[0010] As a preferred embodiment of the present invention, different channels within the same ADC can complete all channel switching and data conversion autonomously and sequentially after receiving a conversion start signal through sampling sequence and burst mode settings.

[0011] As a preferred embodiment of the present invention, the control signal for triggering conversion between different ADCs is a single signal source, and the start-up conversion times between different ADCs are not synchronized.

[0012] Step (1-1): Connect the standard sinusoidal signal to all input channels of the ADC. Assume there are 8 channels and the input signal is:

[0013]

[0014] Where: X: input signal, A: signal amplitude, f: signal frequency, t: time.

[0015] Step (1-2): Design the sampling frequency fs, and the number of sampling points in one cycle with the time interval Ts is N, forming an N-point sequence. After each sampling starts, the 8 or 16 channels of the asynchronous ADC switch channels and convert data in burst mode in sequence. The time delay between each channel is relatively fixed, such as The phase difference between each channel due to time delay is ψ.

[0016] Steps (1-3): The CPU or FPGA reads the ADC conversion data through the data bus, reading the data of all channels of the ADC at one time. After N times of conversion and reading, each channel can form a set of N discrete data. .

[0017]

[0018] i: i-th sampling point; c: c-th channel of the same ADC, usually the maximum value is 8 or 16; X c (i): the i-th sampling value of the c-th channel; T s : sampling time interval; ψ: sampling phase difference between adjacent channels in the same ADC;

[0019] Steps (1-4): Based on the ADC conversion data collected from each channel, using the data from channel 1 as a benchmark, a conventional DFT operation is performed on the first channel to obtain the real and imaginary parts of each harmonic order, and then the phase angle of this channel is calculated. To reduce frequency leakage in the discrete Fourier transform operation, a windowing function is used to optimize the calculation.

[0020]

[0021] X1[k]: kth harmonic of channel 1, N: total N sampling points; X1(i): i-th sampling value of channel 1; ψ k : The phase angle of the kth harmonic; Equation 3-1 is the complex plane representation of DFT; Equation 3-2 is the polar coordinate representation of DFT; Equation 3-3 is the real part calculated according to 3-1; Equation 3-4 is the imaginary part calculated according to 3-1; Equation 3-5 is the phase angle calculated according to 3-3 and 3-4.

[0022] The DFT coefficients at this time are based on the coefficients obtained when Z0=1 in the Z transform. That is, the starting point Z0 is on the positive half axis of the real axis of the complex plane.

[0023] Steps (1-5): Based on the phase difference ψ caused by the time delay between channels, the DFT coefficients of the other channels are recalculated. Based on the DFT coefficients of the current channel, the DFT operation is performed on the sampled data to calculate the AC characteristic. To reduce the amount of calculation, the DFT coefficients of each channel are calculated and stored in memory. The stored DFT coefficients are directly called during the DFT calculation process. Each channel corresponds to a set of DFT coefficients.

[0024]

[0025] Where: X c [k]: Kth harmonic of channel c; N: total N sampling points; X c (i): the i-th sampling value of the c-th channel; ψ: the sampling phase difference between adjacent channels in the same ADC; Equation 4-1 is the complex plane representation of DFT, and Equation 4-2 is the polar coordinate representation of DFT.

[0026] The DFT coefficients at this time are the coefficients obtained by performing an angular rotation shift (c-1)ψ on Z0 in the complex plane according to the sampling lag angle of each channel.

[0027] Step (2): Although different ADCs use the same start signal to trigger ADC conversion, due to factors such as hardware signal delay and individual ADC differences, there will still be a certain phase difference between different ADCs. This phase difference is not fixed. At this time, when performing channel calibration, it is necessary to use the first channel of the first ADC as the reference, calculate the phase of the first channel of each ADC and compare it with the phase value of the reference channel to obtain the phase difference ψ of each ADC. A The phase difference of each ADC is added to the phase offset between the different channels of the corresponding ADC to form the DFT coefficients of each channel. Take an 8-channel ADC as an example:

[0028]

[0029] in: : Kth harmonic of the cth channel of the Ath ADC; ψ: sampling phase difference between adjacent channels in the same ADC; ψ A : The sampling phase difference between the first channel of the Ath ADC and the first channel of the 1st ADC; Equation 5-1 is the complex plane representation of DFT; Equation 5-2 is the polar coordinate representation of DFT.

[0030] Calculating AC signatures after DFT coefficient offset effectively compensates for phase differences caused by asynchronous ADC channel conversion delays. The exponential form of the DFT coefficients indicates that offsetting the DFT sampling point is equivalent to performing a phase shift on the sampled data. This phase shift synchronizes the asynchronously sampled data, allowing for the subsequent DFT calculation.

[0031] Compared with existing technologies, this invention effectively reduces spectrum leakage caused by asynchronous sampling and improves signal reconstruction accuracy through DFT spectrum analysis and sampling point offset compensation. Based entirely on digital signal processing technology, this invention requires no additional hardware clock synchronization circuitry, reducing system cost and complexity. It is widely applicable to various asynchronous sampling systems, such as power system harmonic analysis, communication signal processing, and vibration signal measurement. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 Schematic diagram of AC sampling hardware in this embodiment.

[0033] Figure 2 Schematic diagram of asynchronous ADC burst mode sampling in this embodiment.

[0034] Figure 3 This is a schematic diagram of conventional DFT coefficient calculation in this embodiment.

[0035] Figure 4 FIG. 4 is a schematic diagram of DFT coefficient calculation after the DFT sampling point is shifted in this embodiment. DETAILED DESCRIPTION

[0036] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0037] exist Figure 1 In this process, the connection between the CPU or FPGA and the ADC consists of a data bus and control signals. Different ADCs, under the control of these control signals, trigger ADC conversions simultaneously. Internally, the ADCs switch and convert data across all channels sequentially, using sampling sequences and burst mode settings. The CPU or FPGA reads the conversion results of all channels from the ADC via the data bus, completing a data sampling cycle. Then, when the next sampling time arrives, the ADC conversion is triggered again, repeating the cycle.

[0038] Inside a single ADC, when the ADC receives a trigger signal to start conversion, the conversion is started. At this time, the ADC will complete the switching and conversion of all channels at the fastest speed. Figure 2 As shown in Figure 1, the time delay between each channel is relatively fixed, such as Δt = 1us. The phase difference caused by the time delay between each channel is ψ.

[0039] After reading the conversion results of each ADC, in order to compensate for the phase difference caused by the channel conversion delay of the asynchronous ADC, the DFT sampling point is offset based on the exponential formula of the DFT coefficient. That is, the sampled data is phase-shifted in advance. The asynchronously sampled data is phase-shifted to achieve pseudo-synchronization in phase, and then the DFT operation is performed synchronously. The specific steps include:

[0040] (1) Based on the time delay of channel switching and conversion of asynchronous ADC, the DFT sampling point offset of the phase difference is caused. The DFT coefficients of any channel in the same ADC after the DFT sampling point offset are obtained to achieve pseudo-synchronous conversion of the sampling data of the asynchronous ADC.

[0041] (2) DFT sampling point offset based on phase difference caused by asynchronous sampling between different ADC chips. The sampling point offset caused by phase difference between AD channels and between different ADCs is superimposed to obtain the DFT coefficients of any AD channel of the relay protection device after DFT sampling point offset, thereby realizing pseudo-synchronous conversion of the sampling data of the asynchronous ADC of the entire device.

[0042] Step (1-1): Connect the standard sinusoidal signal to all input channels of the ADC. Assume there are 8 channels and the input signal is:

[0043]

[0044] Where: X: input signal, A: signal amplitude, f: signal frequency, t: time.

[0045] Step (1-2): Design the sampling frequency fs, and the number of sampling points in one cycle with a time interval of Ts is N, forming a sequence of N points. After each sampling starts, the 8 or 16 channels of the asynchronous ADC switch channels and convert data in burst mode in sequence. The time delay between each channel is relatively fixed, such as Δt = 1us. The phase difference caused by the time delay between each channel is ψ, such as Figure 2 shown.

[0046] Steps (1-3): The CPU or FPGA reads the ADC conversion data through the data bus, reading the data of all channels of the ADC at one time. After N times of conversion and reading, each channel can form a set of N discrete data. .

[0047]

[0048] i: i-th sampling point; c: c-th channel of the same ADC, usually the maximum value is 8 or 16; X c (i): the i-th sampling value of the c-th channel; Ts: sampling time interval; ψ: sampling phase difference between adjacent channels in the same ADC;

[0049] Steps (1-4): Based on the ADC conversion data collected from each channel, using the data from channel 1 as a benchmark, a conventional DFT operation is performed on the first channel to obtain the real and imaginary parts of each harmonic order, and then the phase angle of this channel is calculated. To reduce frequency leakage in the discrete Fourier transform operation, a windowing function is used to optimize the calculation.

[0050]

[0051] X1[k]: kth harmonic of channel 1, N: total N sampling points; X1(i): i-th sampling value of channel 1; ψ k : The phase angle of the kth harmonic; Equation 3-1 is the complex plane representation of DFT; Equation 3-2 is the polar coordinate representation of DFT; Equation 3-3 is the real part calculated according to 3-1; Equation 3-4 is the imaginary part calculated according to 3-1; Equation 3-5 is the phase angle calculated according to 3-3 and 3-4.

[0052] The DFT coefficients at this time are based on the coefficients obtained when Z0=1 in the Z transform. That is, the starting point Z0 is on the positive half axis of the real axis of the complex plane, such as Figure 3 .

[0053] Steps (1-5): Based on the phase difference ψ caused by the time delay between channels, the DFT coefficients of the other channels are recalculated. Based on the DFT coefficients of the current channel, the DFT operation is performed on the sampled data to calculate the AC characteristic. To reduce the amount of calculation, the DFT coefficients of each channel are calculated and stored in memory. The stored DFT coefficients are directly called during the DFT calculation process. Each channel corresponds to a set of DFT coefficients.

[0054]

[0055] Where: X c [k]: Kth harmonic of channel c; N: total N sampling points; X c (i): the i-th sampling value of the c-th channel; ψ: the sampling phase difference between adjacent channels in the same ADC; Equation 4-1 is the complex plane representation of DFT, and Equation 4-2 is the polar coordinate representation of DFT.

[0056] The DFT coefficients at this time are the coefficients after the angle rotation offset (c-1)ψ of Z0 in the complex plane according to the sampling lag angle of each channel, as shown in Figure 4 .

[0057] Step (2): Although different ADCs use the same start signal to trigger ADC conversion, due to factors such as hardware signal delay and individual ADC differences, there will still be a certain phase difference between different ADCs. This phase difference is not fixed. At this time, when performing channel calibration, it is necessary to use the first channel of the first ADC as the reference, calculate the phase of the first channel of each ADC and compare it with the phase value of the reference channel to obtain the phase difference ψ of each ADC. A The phase difference of each ADC is added to the phase offset between the different channels of the corresponding ADC to form the DFT coefficients of each channel. Take an 8-channel ADC as an example:

[0058]

[0059] in: : Kth harmonic of the cth channel of the Ath ADC; ψ: sampling phase difference between adjacent channels in the same ADC; ψ A : The sampling phase difference between the first channel of the Ath ADC and the first channel of the 1st ADC; Equation 5-1 is the complex plane representation of DFT; Equation 5-2 is the polar coordinate representation of DFT.

[0060] Calculating AC signatures after DFT coefficient offset effectively compensates for phase differences caused by asynchronous ADC channel conversion delays. The exponential form of the DFT coefficients indicates that offsetting the DFT sampling point is equivalent to performing a phase shift on the sampled data. This phase shift synchronizes the asynchronously sampled data, allowing for the subsequent DFT calculation.

[0061] The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any equivalent structural changes made using the contents of the description and drawings of the present invention should be included in the patent protection scope of the invention.

Claims

1. A pseudo-synchronous sampling method for asynchronous ADC based on DFT sampling point offset, characterized in that: include: Step (1): Based on the DFT sampling point offset of the phase difference caused by the channel switching and conversion time delay of the asynchronous ADC, the DFT coefficients of any channel in the same ADC after the DFT sampling point offset are obtained, thereby realizing pseudo-synchronous conversion of the sampling data of the asynchronous ADC; Step (2): Based on the DFT sampling point offset of the phase difference caused by the asynchronous sampling between different ADC chips, the sampling point offset caused by the phase difference between AD channels and between different ADCs is superimposed to obtain the DFT coefficients of any AD channel of the relay protection device after the DFT sampling point offset, thereby realizing the pseudo-synchronous conversion of the sampling data of the asynchronous ADC of the entire device; The step (1) specifically includes: Step (1-1): Connect the standard sinusoidal signal to all input channels of the ADC. Assume there are 8 channels and the input signal X is: ， Where: A: signal amplitude, f: signal frequency, t: time; Step (1-2): Design the sampling frequency f s , with T s The number of sampling points within one cycle is N, forming a sequence of N points; Steps (1-3): The CPU or FPGA reads the ADC conversion data through the data bus, reading the data of all channels of the ADC at one time. After N times of conversion and reading, each channel can form a set of N discrete data X c (i)=X(T s *i),(i=0,1...,N-1); Where i is the i-th sampling point; c is the c-th channel of the same ADC, with a maximum value of 8 or 16; X c (i) is the i-th sampling value of the c-th channel; T s is the sampling time interval; Steps (1-4): Based on the conversion data collected from the ADC of each channel, the data of the first channel is used as the benchmark; Steps (1-5): Based on the phase difference ψ caused by the time delay between channels, the DFT coefficients of other channels are recalculated, and based on the DFT coefficients of this channel, DFT operation is performed on the sampled data to calculate the AC characteristic quantity; The step (2) is specifically as follows: When channel calibration is required, the first channel of the first ADC is used as a reference. The phase of the first channel of each ADC is calculated and compared with the phase value of the reference channel to obtain the phase difference ψA of each ADC. The phase difference value of each ADC is then added to the phase offset between different channels of the corresponding ADC to form the DFT coefficients of each channel. Taking an 8-channel ADC as an example, the complex plane representation of the DFT is: ， The polar coordinate representation of DFT is: ， Where: X A*8+c [k] is the Kth harmonic of the cth channel of the Ath ADC; ψ is the sampling phase difference between adjacent channels in the same ADC; ψA is the sampling phase difference between the first channel of the Ath ADC and the first channel of the first ADC; The AC characteristic quantity calculation after the DFT coefficient offset compensates for the influence of the phase difference caused by the channel conversion delay of the asynchronous ADC.

2. The asynchronous ADC pseudo-synchronous sampling method based on DFT sampling point offset according to claim 1, characterized in that: Different channels within the same ADC can complete all channel switching and data conversion autonomously and sequentially after receiving a conversion start signal through sampling sequence and burst mode settings.

3. The asynchronous ADC pseudo-synchronous sampling method based on DFT sampling point offset according to claim 1, characterized in that: The control signal for triggering conversion between different ADCs is a signal source, and the start conversion time between different ADCs is not synchronized.

4. The asynchronous ADC pseudo-synchronous sampling method based on DFT sampling point offset according to claim 1, characterized in that: In the steps (1-2), after each sampling starts, the 8 or 16 channels of the asynchronous ADC are sequentially switched and data converted in a burst mode; the time delay between each channel is relatively determined, and the phase difference caused by the time delay between each channel is ψ.

5. The asynchronous ADC pseudo-synchronous sampling method based on DFT sampling point offset according to claim 1, characterized in that: In the steps (1-3): ， Where ψ is the sampling phase difference between adjacent channels in the same ADC.

6. The asynchronous ADC pseudo-synchronous sampling method based on DFT sampling point offset according to claim 1, characterized in that: The steps (1-4) are specifically: First, perform conventional DFT operation on the first channel to obtain the real and imaginary parts of each order harmonic, and then calculate the phase angle of this channel; in order to reduce frequency leakage in discrete Fourier operation, the calculation is optimized by adding window function processing, specifically: The complex plane representation of the DFT is: ， The polar coordinate representation of DFT is: , The real part calculated according to formula (3-1) is: ， The imaginary part calculated according to formula (3-1) is: ， The phase angle calculated according to formula (3-3) and formula (3-4) is: ， Where, X1[k] is the kth harmonic of the first channel; N is the total N sampling points; X1(i) is the i-th sampling value of the first channel; ψ k is the phase angle of the kth harmonic; in formula (3-5), K=(0, 1, N / 2); The DFT coefficients at this time are based on the coefficients obtained when Z0=1 in the Z transform, that is, the starting point Z0 is on the positive half axis of the real axis of the complex plane.

7. The asynchronous ADC pseudo-synchronous sampling method based on DFT sampling point offset according to claim 1, characterized in that: The steps (1-5) are specifically: In order to reduce the amount of calculation, the DFT coefficients of each channel are calculated and saved in the memory. The stored DFT coefficients are directly called during the DFT calculation process. Each channel corresponds to a set of DFT coefficients. The complex plane of DFT is represented as: ， The polar coordinate representation of DFT is: ， Where: X c [k] is the Kth harmonic of the cth channel; N is the total N sampling points; X c (i) is the i-th sampling value of the c-th channel; ψ is the sampling phase difference between adjacent channels in the same ADC; The DFT coefficients at this time are the coefficients obtained by performing an angular rotation shift (c-1)ψ on Z0 in the complex plane according to the sampling lag angle of each channel.

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