Scaling analog-to-digital converter based on SAR-SDM mixed structure

Abstract

The invention discloses a scaling type analog-to-digital converter based on an SAR-SDM mixed structure. The scaling type analog-to-digital converter comprises an SAR ADC module, an SDM modulator module, a scaling factor generation module, a five-bit summator, a five-bit subtracter and a data selector. The SAR ADC module is used for carrying out quantitative conversion processing on an analog input signal and outputting a first digital output signal; the scaling factor generation module is used for generating a five-bit scaling factor; the five-bit summator and the five-bit subtracter are used for performing digital addition and subtraction operation on the first digital output signal and the five-bit scaling factor to obtain a second digital output signal corresponding to the reference voltage; the SDM modulator module is used for outputting a one-bit digital code stream; and the data selector is used for performing data selection scaling operation on the second digital output signal based on the one-bit digital code stream and outputting a final digital output signal. According to the invention, a mixed structure of the SAR ADC and the SDM modulator is adopted, the design difficulty of the analog-to-digital converter is simplified, and the conversion precision is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular, to a scaled analog-to-digital converter based on a SAR-SDM hybrid structure. Background Art

[0002] In a real physical system, the efficient digital conversion of continuous analog signals such as temperature, pressure, acoustic vibration, biometrics, and optical images is a key technical bottleneck for realizing information processing in modern electronic systems. As the core interface device between the analog domain and the digital domain, the performance of an analog-to-digital converter (ADC) directly determines the accuracy and energy efficiency of a data acquisition system. In high-resolution application scenarios such as wearable electronics and industrial inspection, traditional single-architecture ADCs face a trade-off dilemma between accuracy and power consumption: The Sigma-Delta Modulator (SDM) analog-to-digital converter can improve the signal-to-noise ratio through oversampling and noise shaping techniques, but its high-order architecture has a risk of non-linear oscillation; The Successive Approximation Register (SAR) analog-to-digital converter has the advantage of a simple structure, but its quantization accuracy is limited by the matching accuracy of the capacitor array. These two traditional single-architecture analog-to-digital converters have corresponding problems, and the achieved analog-to-digital conversion effect is not good. Summary of the Invention

[0003] The purpose of the present invention is to overcome the deficiencies of the prior art. The present invention provides a scaled analog-to-digital converter based on a SAR-SDM hybrid structure, which adopts a hybrid structure of a SAR ADC and an SDM modulator, simplifies the design difficulty of the analog-to-digital converter, and improves the conversion accuracy.

[0004] The present invention provides a scaled analog-to-digital converter based on a SAR-SDM hybrid structure. The scaled analog-to-digital converter includes a SAR ADC module, an SDM modulator module, a scaling factor generation module, a five-bit adder, a five-bit subtractor, and a data selector;

[0005] The input end of the SAR ADC module is connected to an analog input signal. The output ends of the SAR ADC module and the scaling factor generation module are both connected to the input ends of the five-bit adder and the input ends of the five-bit subtractor. The output ends of the five-bit adder and the five-bit subtractor are both connected to the data signal input ends of the data selector. The output end of the SDM modulator module is connected to the control signal input end of the data selector. The output end of the data selector outputs a final digital output signal;

[0006] The SAR ADC module is used to perform quantization conversion processing on the analog input signal, output a first digital output signal, and transmit the first digital output signal to the first input end of the five-bit adder and the first input end of the five-bit subtractor;

[0007] The scaling factor generation module is used to generate a five-bit scaling factor and transmit the five-bit scaling factor to the second input end of the five-bit adder and the second input end of the five-bit subtractor;

[0008] The five-bit adder and the five-bit subtractor are used to perform digital addition and subtraction operations on the first digital output signal and the five-bit scaling factor, obtain a second digital output signal corresponding to the reference voltage, and transmit the second digital output signal to the data signal input end of the data selector;

[0009] The SDM modulator module is used to output a one-bit digital bit stream and transmit it to the control signal input end of the data selector;

[0010] The data selector is used to perform data selection and scaling operations on the second digital output signal based on the one-bit digital bit stream and output a final digital output signal.

[0011] Further, the SAR ADC module includes a differential capacitor DAC array, a Strong ARM comparator, and a SAR logic unit;

[0012] The input end of the differential capacitor DAC array is connected to the analog input signal, the output end of the differential capacitor DAC array is connected to the input end of the Strong ARM comparator, the output end of the Strong ARM comparator is connected to the input end of the SAR logic unit, and the output end of the SAR logic unit is connected to the differential capacitor DAC array based on a feedback circuit and outputs a first digital output signal.

[0013] Further, the differential capacitor DAC array adopts a binary weighted capacitor array, including a first capacitor array and a second capacitor array. The first capacitor array and the second capacitor array respectively include capacitors C1, C2, C3, C4, C5, C0. The capacitance value ratio of the capacitors C1, C2, C3, C4, C5, C0 is 1:2:4:8:16:1. The upper plate of each capacitor is connected to the input end of the Strong ARM comparator, and the lower plate of each capacitor is connected to a phase switch. The lower plate of each capacitor except C0 is also connected to the analog input signal and the reference voltage.

[0014] Further, the phase switch is a CMOS switch, and the CMOS switch is formed by the parallel connection of an NMOS switch and a PMOS switch.

[0015] Further, the Strong ARM comparator is a dynamic Strong ARM comparator with an RS latch.

[0016] Further, the SAR logic unit includes an upper D flip-flop bank and a lower D flip-flop bank. The SAR logic unit performs shift register processing on the output signal of the Strong ARM. Among them, the upper D flip-flop bank performs shift processing on the comparison result based on the output signal of the Strong ARM comparator, and the lower D flip-flop bank latches the shift processing result and outputs a first digital output signal of a five-digit digital signal.

[0017] Further, the SAR logic unit performs shift register processing on the output signal of the Strong ARM using the DWA algorithm. The SAR logic unit extracts a 32-bit code generated based on the output signal of the Strong ARM and a 5-bit binary pointer generated based on the analog input signal, generates a DWA algorithm output code, and transmits it to the differential capacitor DAC array through a feedback circuit based on the DWA algorithm output code.

[0018] Further, the SDM modulator module includes a first-stage integrator circuit, a second-stage integrator circuit, and a chopper circuit;

[0019] The input end of the chopper circuit is connected to an input voltage, the output end of the chopper circuit is connected to the input end of the first-stage integrator circuit, the output end of the first-stage integrator circuit is connected to the input end of the second-stage integrator circuit, and the output end of the second-stage integrator circuit outputs a digital code stream to the control signal input end of the data selector;

[0020] The first-stage integrator circuit and the second-stage integrator circuit are also provided with feedback circuits.

[0021] Further, the first-stage integrator circuit includes a first operational amplifier, and the second-stage integrator circuit includes a second operational amplifier. The first operational amplifier and the second operational amplifier are CLADD A / AB fully differential two-stage operational amplifiers.

[0022] Further, the chopper circuit includes a third operational amplifier, two operational amplifiers, a sampler, an integrating capacitor, and eight sampling switches. Among them, four sampling switches are connected to the input end of the third operational amplifier, four sampling switches are connected to the output end of the third operational amplifier, and the two operational amplifiers, the sampler, and the integrating capacitor are connected in parallel with the third operational amplifier.

[0023] The present invention provides a scaled analog-to-digital converter based on a SAR-SDM hybrid structure, which adopts a five-bit SAR ADC and a third-order single-loop one-bit quantization structure SDM modulator, integrating the advantages of high conversion accuracy of the SAR ADC and simple structure of the SDM modulator, simplifying the design difficulty of the analog-to-digital converter, and effectively improving the conversion accuracy; a combinational logic circuit composed of a five-bit adder, a five-bit subtractor, and a data selector is used to realize the combination of the SAR ADC and the SDM modulator structure, combining the fast conversion characteristics of the SAR and the high-precision characteristics of the SDM, providing a new technical path for solving the co-optimization of high resolution and low power consumption. Description of the Drawings

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0025] Figure 1 It is the architecture diagram of the scaled analog-to-digital converter based on the SAR-SDM hybrid structure in the embodiment of the present invention;

[0026] Figure 2 It is the architecture diagram of the combinational logic design in the embodiment of the present invention;

[0027] Figure 3 It is the architecture diagram of the SAR ADC module in the embodiment of the present invention;

[0028] Figure 4 It is the architecture diagram of the differential capacitor DAC array in the embodiment of the present invention;

[0029] Figure 5 It is the architecture diagram of the CMOS switch in the embodiment of the present invention;

[0030] Figure 6 It is the architecture diagram of the Strong ARM comparator in the embodiment of the present invention;

[0031] Figure 7 It is the architecture diagram of the SAR logic unit in the embodiment of the present invention;

[0032] Figure 8 It is the architecture diagram of the SDM modulator module in the embodiment of the present invention;

[0033] Figure 9 It is the architecture diagram of the integrator circuit in the embodiment of the present invention;

[0034] Figure 10It is the architecture diagram of the CLADD A / AB fully differential two-stage operational amplifier in the embodiment of the present invention;

[0035] Figure 11 It is the architecture diagram of the switched-capacitor common-mode feedback circuit in the embodiment of the present invention;

[0036] Figure 12 It is the architecture diagram of the bootstrap switch in the embodiment of the present invention;

[0037] Figure 13 It is the architecture diagram of the chopper circuit in the embodiment of the present invention;

[0038] Figure 14 It is the timing diagram of the operation of the chopper circuit in the embodiment of the present invention;

[0039] Figure 15 It is the architecture diagram of the five-bit adder and five-bit subtractor in the embodiment of the present invention;

[0040] Figure 16 It is the architecture diagram of the one-bit full adder in the embodiment of the present invention;

[0041] Figure 17 It is the architecture diagram of the data selector in the first embodiment of the present invention. Detailed implementation manners

[0042] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0043] In the present invention, it should be understood that terms such as "including" or "having" are intended to indicate the existence of features, numbers, steps, actions, components, parts, or combinations thereof disclosed in this specification, and do not intend to exclude the possibility of the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0044] In addition, it should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0045] The embodiment of the present invention provides a scaled analog-to-digital converter based on a SAR-SDM hybrid structure. The scaled analog-to-digital converter includes a SAR ADC module, an SDM modulator module, a scaling factor generation module, a five-bit adder, a five-bit subtractor, and a data selector.

[0046] In an alternative implementation of this embodiment, as Figure 1 shown, Figure 1 FIG. shows the architecture diagram of a scaled analog-to-digital converter based on a SAR-SDM hybrid structure in an embodiment of the present invention. The scaled analog-to-digital converter includes a SAR ADC module, an SDM modulator module, a scaling factor generation module, a five-bit adder, a five-bit subtractor, and a data selector. The input end of the SAR ADC module is connected to an analog input signal. The output ends of the SAR ADC module and the scaling factor generation module are both connected to the input ends of the five-bit adder and the input ends of the five-bit subtractor. The output ends of the five-bit adder and the five-bit subtractor are both connected to the data signal input ends of the data selector. The output end of the SDM modulator module is connected to the control signal input end of the data selector. The output end of the data selector outputs a final digital output signal.

[0047] Specifically, the SAR ADC module is configured to perform quantization conversion processing on the analog input signal, output a first digital output signal, and transmit the first digital output signal to the first input end of the five-bit adder and the first input end of the five-bit subtractor. The scaling factor generation module is configured to generate a five-bit scaling factor and transmit the five-bit scaling factor to the second input end of the five-bit adder and the second input end of the five-bit subtractor. The five-bit adder and the five-bit subtractor are configured to perform digital addition and subtraction operations on the first digital output signal and the five-bit scaling factor to obtain a second digital output signal corresponding to a reference voltage, and transmit the second digital output signal to the data signal input end of the data selector. The SDM modulator module is configured to output a one-bit digital bitstream and transmit it to the control signal input end of the data selector. The data selector is configured to perform data selection and scaling operations on the second digital output signal based on the one-bit digital bitstream and output a final digital output signal.

[0048] In an alternative implementation of this embodiment, the SAR ADC module, the SDM modulator module, the scaling factor generation module, the five-bit adder, the five-bit subtractor, and the data selector are connected by Combine combinational logic design.

[0049] Specifically, as Figure 2 shown, Figure 2The architecture diagram of the combinational logic design in the embodiment of the present invention is shown. The first digital output signal SAR<5:1> with a five-bit structure output by the SARADC module is respectively transmitted to the first input end of the five-bit adder 5bit ADD and the first input end of the five-bit subtractor 5bit MINUS. At the same time, the five-bit scaling factor M<5:1> generated by the scaling factor generation module is transmitted to the second input end of the five-bit adder 5bit ADD and the second input end of the five-bit subtractor 5bit MINUS. After digital addition and subtraction operations by the five-bit adder and the five-bit subtractor, the second digital output signal corresponding to the reference voltage Vref is obtained and respectively transmitted to the data signal input end of the data selector DS. The one-bit digital code stream Select output by the SDM modulator module is transmitted to the control signal input end of the data selector DS. The data selector uses the first digital output signal as the processed data. When the one-bit digital code stream Select is a high-level code stream, it selects the second digital output signal of the five-bit adder. When the one-bit digital code stream Select is a low-level code stream, it selects the second digital output signal of the five-bit subtractor, completing the data scaling operation of the SDMF modulator module for the data within the range of the reference voltage Vref. The data selector outputs the final digital output signal as the final digital output of the scaled analog-to-digital converter in this embodiment.

[0050] In an alternative implementation manner of this embodiment, as Figure 3 shown, Figure 3 The architecture diagram of the SARADC module in the embodiment of the present invention is shown. The SAR ADC module includes a differential capacitor DAC array, a Strong ARM comparator, and a SAR logic unit. The input end of the differential capacitor DAC array is connected to an analog input signal. The output end of the differential capacitor DAC array is connected to the input end of the Strong ARM comparator. The output end of the Strong ARM comparator is connected to the input end of the SAR logic unit. The output end of the SAR logic unit is connected to the differential capacitor DAC array based on a feedback circuit and outputs a first digital output signal.

[0051] In an alternative implementation manner of this embodiment, the differential capacitor DAC array adopts a binary-weighted capacitor array, including a first capacitor array and a second capacitor array. The first capacitor array and the second capacitor array respectively include capacitors C1, C2, C3, C4, C5, C0. The capacitance value ratio of the capacitors C1, C2, C3, C4, C5, C0 is 1:2:4:8:16:1. The upper plate of each capacitor is connected to the input end of the Strong ARM comparator. The lower plate of each capacitor is connected to a phase switch. The lower plate of each capacitor except C0 is also connected to the analog input signal and the reference voltage.

[0052] Specifically, asFigure 4 As shown Figure 4 Figure 4 shows an architecture diagram of a differential capacitor DAC array in an embodiment of the present invention. The differential capacitor DAC array includes a first capacitor array and a second capacitor array that are symmetrically arranged up and down. The first capacitor array, from left to right, includes capacitors C0, C1, C2, C3, C4, and C5. The capacitance value ratio of capacitors C0, C1, C2, C3, C4, and C5 is 1:1:2:4:8:16. Capacitors C1, C2, C3, C4, and C5 are weight capacitors, and capacitor C0 is a redundant capacitor to complement the full weight. The capacitance values of capacitors C0 and C1 are 49 fF, the capacitance value of capacitor C2 is 49*2 fF, the capacitance value of capacitor C3 is 49*4 fF, the capacitance value of capacitor C4 is 49*8 fF, and the capacitance value of capacitor C5 is 49*16 fF. The structure of the second capacitor array is completely symmetric to that of the first capacitor array.

[0053] Furthermore, in the first capacitor array, the upper plates of capacitors C0, C1, C2, C3, C4, and C5 are all connected to the positive input terminal of the StrongARM comparator (CMP). In the second capacitor array, the upper plates of capacitors C0, C1, C2, C3, C4, and C5 are all connected to the negative input terminal of the Strong ARM comparator (CMP). In the first capacitor array and the second capacitor array, the lower plates of capacitors C0, C1, C2, C3, C4, and C5 are connected to the corresponding phase switches PA and PB. The lower plate of the redundant capacitor C0 is also connected to the analog input signal Vin or Vip, and the reference voltage Vrefn. The lower plates of capacitors C1, C2, C3, C4, and C5 except the redundant capacitor C0 are also connected to the analog input signal Vin or Vip, and the reference voltages Vrefn and Vrefp.

[0054] In an alternative implementation of this embodiment, the working principle of the differential capacitor DAC array includes: during the sampling operation, the phase is at the sampling phase, the clock signal controls the phase switch PA to close, and controls the phase switch PB to open. The lower plates of all capacitors are connected to the analog input signal for sampling. After sampling is completed, the comparison operation is performed. The phase is at the comparison phase, the clock signal controls the phase switch PA to open, and controls the phase switch PB to close. The weight capacitors except the redundant capacitor are controlled by the five-bit digital output signal transmitted by the SAR logic unit (SAR Logic) through the feedback circuit to connect to Vrefn or Vrefp respectively, and transfer the charge stored in the capacitor to the input terminal of the comparator CMP, completing the conversion of the analog input signal to a level. The redundant capacitor only participates in the sampling operation and does not participate in the comparison operation.

[0055] In an alternative implementation of this embodiment, the phase switch is a CMOS switch, and the CMOS switch is formed by connecting an NMOS switch and a PMOS switch in parallel.

[0056] Specifically, as Figure 5 shown, Figure 5 The architecture diagram of the CMOS switch in the embodiment of the present invention is shown. The CMOS switch is composed of an NMOS transistor and a PMOS transistor in parallel, that is, sharing the source and drain to form a bidirectional conduction path. The substrate of the PMOS transistor is connected to the power supply, and the substrate of the NMOS transistor is grounded. The gates of both are driven by complementary signals CLK and When CLK is at a high level, is at a low level, and both transistors are turned on to form a low-resistance path, allowing the signal to pass through at this time; when CLK is at a low level, is at a high level, and both transistors are turned off, blocking the signal from passing through at this time.

[0057] By setting the CMOS switch here, the signal transmission range from the power supply to the ground can be obtained, as well as a relatively high linearity of the on-resistance. And since the SAR ADC module has relatively loose requirements for accuracy, the CMOS switch is suitable for use in the SAR ADC module.

[0058] In an alternative implementation of this embodiment, the Strong ARM comparator is a dynamic Strong ARM comparator with an RS latch.

[0059] Specifically, it is considered that the SDM modulator module part of the scaled analog-to-digital converter in this embodiment adopts a 1-bit (i.e., one-bit) quantization structure. Therefore, only one comparator is required. And since the noise of the quantization comparator is introduced only at the end of the ring structure and will undergo third-order shaping, a dynamic comparator is used. The circuit structure is simple, occupies a small chip area, and has no static power consumption. In this embodiment, a dynamic Strong ARM comparator with an RS latch is used.

[0060] In an alternative implementation of this embodiment, as Figure 6 shown, Figure 6 The architecture diagram of the Strong ARM comparator in the embodiment of the present invention is shown, including a differential pair: two parallel AND gates and NOT gates respectively connected in series with the two AND gates. Specifically, it includes NMOS devices M0, M1, M2, M3, M4, and PMOS devices M5, M6. Its working principle is: when the signal ck is at a low level, the comparator is in a reset state, the differential pair is turned off, and all the nodes above the differential pair are pulled to VDD; when the signal ck rises, the current in the differential pair pulls down between the p node and the q node, activating the NMOS devices M3 and M4, pulling down and nodes. The imbalance of the pull-down current from the differential pair is amplified by the positive feedback provided by the PMOS devices M5 and M6 until and The node goes low. At this time, conversely, the RS latch is set to the comparison result, and then the comparison result is output.

[0061] In an alternative implementation of this embodiment, the SAR logic unit includes an upper D flip-flop bank and a lower D flip-flop bank. The SAR logic unit performs shift register processing on the output signal of the Strong ARM. Among them, the upper D flip-flop bank performs shift processing on the comparison result based on the output signal of the Strong ARM comparator, and the lower D flip-flop bank stores the shift processing result and outputs the first digital output signal of the five-digit digital signal.

[0062] Specifically, as Figure 7 shown, Figure 7 The architecture diagram of the SAR logic unit in the embodiment of the present invention is shown. The SAR logic unit includes an upper D flip-flop bank and a lower D flip-flop bank. The D flip-flops with reset and set functions form a five-bit shift register, which performs shift register processing on the digital signal output by the Strong ARM comparator. Among them, the upper D flip-flop bank realizes the shift function, and the lower D flip-flop bank realizes the storage function and outputs the five-digit digital results of D4, D3, D2, D1, and D0.

[0063] Furthermore, its working principle includes: COMP is the output signal of the Strong ARM comparator, pb is the clock signal, SET is the logic set 1 / 0 signal, high level is valid, and the output terminals D4 to D0 are used as the five-digit digital signal output by the SAR ADC module. In the sampling stage of the SAR ADC module, SET is set to 1, the output terminal of the highest bit flip-flop in the upper layer is set to 1, which controls the highest bit output D4 in the lower layer to be set to 1, and the remaining bits remain 0, and the output is 10000. The logic circuit determines the final output of D4 according to the comparison result and stores it during the current comparison period without change. After completing the comparison of the highest bit, the shift function controls the second highest bit to be set to 1, and the output result is 01000; the comparison result is stored in the Dn-1 bit. Similarly, the logic circuit controls the comparison bits to switch from high to low to complete the shift function.

[0064] In an alternative implementation of this embodiment, the SAR logic unit performs shift register processing on the output signal of the Strong ARM using the DWA algorithm. The SAR logic unit extracts a 32-bit code generated based on the output signal of the Strong ARM and a 5-bit binary pointer generated based on the analog input signal, generates a DWA algorithm output code, and transmits it to the differential capacitor DAC array through a feedback circuit based on the DWA algorithm output code.

[0065] Specifically, the SAR logic unit generates a 32-bit code through quantization encoding of the output signal of Strong ARM, and for the analog input signal as the original input data, after passing through an adder modulo 5, a 5-bit binary pointer is generated, and after being stored in a register, a DWA algorithm output code is generated, which is transmitted to the differential capacitor DAC array through a feedback circuit, thereby determining the selection of the corresponding capacitor array element.

[0066] Here, the DWA algorithm is adopted, which has simple implementation, small circuit area, low power consumption, and improves the working efficiency and working accuracy of the SAR ADC.

[0067] In an alternative implementation manner of this embodiment, as Figure 8 shown, Figure 8 shows the architecture diagram of the SDM modulator module in the embodiment of the present invention. The SDM modulator module includes a first-stage integrator circuit, a second-stage integrator circuit, and a chopper circuit; the input end of the chopper circuit is connected to an input voltage, the output end of the chopper circuit is connected to the input end of the first-stage integrator circuit, the output end of the first-stage integrator circuit is connected to the input end of the second-stage integrator circuit, and the output end of the second-stage integrator circuit outputs a one-bit digital code stream to the control signal input end of the data selector; the first-stage integrator circuit and the second-stage integrator circuit are also provided with a feedback circuit.

[0068] Specifically, the SDM modulator module adopts a third-order CIFF structure. The third order includes two-stage integrator circuits and a chopper circuit, and a feedforward path, that is, a feedback circuit, is introduced to optimize the frequency response or suppress quantization noise.

[0069] In an alternative implementation manner of this embodiment, as Figure 9 shown, Figure 9 shows the architecture diagram of the integrator circuit in the embodiment of the present invention. The first-stage integrator circuit and the second-stage integrator circuit have the same structure, both of which are fully differential capacitor integrators. Here, taking the first-stage integrator circuit as an example, it includes switches P1, P 1D , P2, capacitors C1, C2, and an operational amplifier, and their connection relationship is as Figure 9 shown.

[0070] Specifically, its working principle includes: Figure 9 All the switches in it work under two-phase non-overlapping clocks. Assuming that the period of the two-phase non-overlapping clock is T, at the nth cycle, P1 is at a high level, and P 1D is the delayed signal of P1, so the switches controlled by P1 and P 1D are both closed; while P1 and P2 are in an inverted relationship, then P2 must be at a low level, that is, the switch controlled by P2 is open. At this time, the integrator works in the sampling phase, and the sampling capacitor CS The total charge on it is C S V in (nT), and the output voltage is V out (nT) remains unchanged, so the capacitance C I The total charge on it is C I V out (nT). At the moment of (nT + T / 2), P1 and P 1D are at low level, then P2 must be at high level. Therefore, the switches controlled by P1 and P 1D are open, and the switch controlled by P2 is closed. At this time, the integrator works in the integration phase, and the capacitance C S discharges, and the charge on the sampling capacitor is transferred to the integration capacitor. The total charge on C S becomes 0, and the total charge on the integration capacitor C I The total charge on it is C I V out (nT + T / 2). In the (n + 1)-th cycle, the circuit works in the sampling phase, and at this time the output voltage becomes V out (nT), and the total charge on C S The total charge on it is C S V in (nT + T), and the total charge on C I The total charge on it is C I V out (nT + T). In a cycle T, the total charge of the integrator is conserved, and the charge transfer equation of the integrator can be expressed as the following formula:

[0071] C S V in (nT)+C I V out (nT)=C I V out (nT + T / 2)

[0072] C I V out (nT + T)=C I V out (nT + T / 2)

[0073] By solving the equations simultaneously and performing z-domain transformation, we can obtain:

[0074]

[0075] Through the above calculation, the outputs of the first-stage integrator circuit and the second-stage integrator circuit can be obtained.

[0076] In an alternative implementation of this embodiment, the first-stage integrator circuit includes a first operational amplifier, and the second-stage integrator circuit includes a second operational amplifier. The first operational amplifier and the second operational amplifier are CLADD A / AB fully differential two-stage operational amplifiers.

[0077] Specifically, as Figure 10 and Figure 11 shown, Figure 10 shows the architecture diagram of the CLADD A / AB fully differential two-stage operational amplifier in the embodiment of the present invention. Figure 11 shows the architecture diagram of the switched-capacitor common-mode feedback circuit in the embodiment of the present invention. The CLADD A / AB fully differential two-stage operational amplifier includes two-stage operational amplifiers, where the first stage is a class A amplifier, the second stage is a push-pull output stage, and also includes switched-capacitor common-mode feedback circuits (vop, vop1), (von, von1), etc. for implementing the common-mode feedback function.

[0078] Here, a CLADD A / AB fully differential two-stage operational amplifier is adopted to achieve a higher output swing while achieving high gain. The push-pull output stage has a higher transconductance efficiency and saves more power consumption. The switched-capacitor common-mode feedback circuit is set, which has the advantages of not introducing poles and having no static power consumption.

[0079] In an alternative implementation of this embodiment, the sampling switch at the input end of the integrator circuit of the SDM modulator module adopts a gate-bootstrapped switch.

[0080] Specifically, as Figure 12 shown, Figure 12The architecture diagram of the gate voltage bootstrap switch in the embodiment of the present invention is shown, and the working principle includes: when the clock signal clk is low (clkn is high), M1 and M7 are turned on, M2 and M9 are turned off, and both ends of the capacitor C1 are connected to VDD and ground respectively for pre-charging. The gate G of the switch transistor M10 is connected to ground through M3 and M4, and the switch is in the off state. Since the gate voltage of M10 will be higher than VDD (but lower than twice VDD) during the sampling period, the discharge path needs to be composed of two transistors M3 and M4, so that it can be ensured that the drain-source voltages Vds3 and Vds4 of both of them will not exceed VDD during the charge discharge process of the node G, and they are in a safe operating state. When the clock signal clkn is high (clk is low), M1 and M7 are turned off. At this time, the source voltage of M10 is the input signal Vin, and the voltage at the gate G point is the source voltage plus the voltage VDD pre-stored in the capacitor C1, that is, Vin + VDD. Therefore, the gate-source voltage VGS of M10 is the stored voltage VDD of the capacitor C1, which is a constant value. It should be noted that since the voltage on the upper plate of the capacitor C1 will exceed VDD during the sampling period, the substrates of the two PMOS transistors M1 and M2 should be connected to the upper plate of CB instead of VDD to ensure that the circuit is still in a safe operating state.

[0081] Here, a gate voltage bootstrap switch is adopted. The gate voltage bootstrap switch is a common switch structure in high linearity application scenarios. It uses a charge pump boost technology to ensure that the gate-source voltage of the switch is constant, thereby ensuring the linearity of the on-resistance. At the sampling switch at the input end of the SDM modulator module, the accuracy requirement is relatively high, while the accuracy of the CMOS complementary switch does not meet the requirement. Therefore, a gate voltage bootstrap switch with better performance and higher accuracy needs to be adopted to ensure the accuracy of the sampling switch.

[0082] In an alternative implementation manner of this embodiment, the chopping circuit includes a third operational amplifier, two operational amplifiers, a sampler, an integrating capacitor, and eight sampling switches. Among them, four sampling switches are connected to the input end of the third operational amplifier, four sampling switches are connected to the output end of the third operational amplifier, and the two operational amplifiers, the sampler, and the integrating capacitor are connected in parallel with the third operational amplifier.

[0083] Specifically, as Figure 13 shown, Figure 13 The architecture diagram of the chopping circuit in the embodiment of the present invention is shown. The chopping circuit includes a third operational amplifier, sampling switches chopclk1, chopclk1d, chopclk2, chopclk2d, an operational amplifier sampler integrating capacitor C i , and the working principle includes: the chopping switches chopclk1 and chopclk2 shift the input signal V i to the odd harmonics of the chopping frequency, and superimpose the inherent 1 / f noise of the operational amplifier to become Vif , after being amplified by the operational amplifier, and then chopped by switches chopclk1 and chopclk2 at the same sampling frequency at the output end of the operational amplifier, thus shifting the signal V if back to the original frequency, and at the same time chopping the 1 / f noise to the odd frequencies of the chopping frequency. Since the 1 / f noise only goes through one chopping, the 1 / f noise only appears at the odd frequencies of the chopping frequency, and only needs to go through a filter for noise filtering. Therefore, the switch chopping technology can effectively remove low-frequency noise.

[0084] Furthermore, as Figure 14 shown, Figure 14 shows the working timing diagram of the chopping circuit in the embodiment of the present invention, where P1 (P1D) is the timing of the modulator sampling clock, P2 (P2D) is the complementary signal, hopclk is the timing of the corresponding chopping switch, and the working frequency of the chopping switch circuit is set to half of the system sampling frequency.

[0085] Here, considering the actual process, the amplitude of the 1 / f noise brought by the MOS transistor decreases with the increase of the frequency, which is a kind of low-frequency noise. Therefore, in order to eliminate the influence of the 1 / f noise at low frequencies, the switch chopping technology is adopted at the input end of the first-stage integrator of the modulator, effectively realizing the functions of optimizing noise and suppressing offset voltage.

[0086] In an alternative implementation of this embodiment, the scaling factor generation module generates a five-bit scaling factor M and transmits it to the input ends of the five-bit adder and the five-bit subtractor.

[0087] In an alternative implementation of this embodiment, as Figure 15 shown, Figure 15 shows the architecture diagram of the five-bit adder and the five-bit subtractor in the embodiment of the present invention, which is composed of five one-bit full adders A1, A2, A3, A4, A5 and five exclusive-OR gate circuits MB1, MB2, MB3, MB4, MB5. Among them, A and B are two input ends, S is the output end, and M is the control end. Figure 16 shows the architecture diagram of the one-bit full adder in the embodiment of the present invention. When M is at a low level, the overall circuit behaves as a five-bit adder. When M is at a high level, the overall circuit behaves as a five-bit subtractor.

[0088] In an alternative implementation of this embodiment, the data selector is a two-to-one data selector. Figure 17 shows the architecture diagram of the data selector in the first embodiment of the present invention, which is composed of two AND gates, one NOT gate and one NOR gate. A is the output signal of the five-bit adder and the five-bit subtractor, B is the input of the five-bit scaling factor, Select is the output signal of the SDM modulator module, and Y is the final digital output signal, realizing the two-to-one data selection operation of a one-bit multiplexer.

[0089] In summary, the embodiment of the present invention provides a scalable analog-to-digital converter based on a SAR-SDM hybrid structure, which adopts a five-bit SAR ADC and a third-order single-loop one-bit quantization structure SDM modulator, integrating the advantages of high conversion accuracy of the SAR ADC and simple structure of the SDM modulator, simplifying the design difficulty of the analog-to-digital converter, and effectively improving the conversion accuracy; a combinational logic circuit composed of a five-bit adder, a five-bit subtractor, and a data selector is used to realize the combination of the SAR ADC and the SDM modulator structure, combining the fast conversion characteristics of the SAR and the high-precision characteristics of the SDM, providing a new technical path for solving the co-optimization of high resolution and low power consumption.

[0090] The above has introduced in detail a scalable analog-to-digital converter based on a SAR-SDM hybrid structure provided by the present invention. Those of ordinary skill in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing relevant hardware through a program, and the program can be stored in a computer-readable storage medium. The storage medium may include: read-only memory (ROM, Read Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk, etc.

[0091] In addition, the above has introduced the embodiments of the present invention in detail. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A scalable analog-to-digital converter based on a SAR-SDM hybrid structure, characterized in that, The scaling analog-to-digital converter includes a SAR ADC module, an SDM modulator module, a scaling factor generation module, a five-bit adder, a five-bit subtractor, and a data selector; The input end of the SAR ADC module is connected to an analog input signal. The output ends of the SAR ADC module and the scaling factor generation module are both connected to the input ends of the five-bit adder and the five-bit subtractor. The output ends of the five-bit adder and the five-bit subtractor are both connected to the data signal input ends of the data selector. The output end of the SDM modulator module is connected to the control signal input end of the data selector. The output end of the data selector outputs a final digital output signal; The SAR ADC module is used to perform quantization conversion processing on the analog input signal, output a first digital output signal, and transmit the first digital output signal to the first input end of the five-bit adder and the first input end of the five-bit subtractor; The scaling factor generation module is used to generate a five-bit scaling factor and transmit the five-bit scaling factor to the second input end of the five-bit adder and the second input end of the five-bit subtractor; The five-bit adder and the five-bit subtractor are used to perform digital addition and subtraction operations on the first digital output signal and the five-bit scaling factor, obtain a second digital output signal corresponding to the reference voltage, and transmit the second digital output signal to the data signal input end of the data selector; The SDM modulator module is used to output a one-bit digital bitstream and transmit it to the control signal input end of the data selector; The data selector is used to perform data selection and scaling operations on the second digital output signal based on the one-bit digital bitstream and output a final digital output signal.

2. The scaled analog-to-digital converter based on the SAR-SDM hybrid structure according to claim 1, wherein The SAR ADC module includes a differential capacitor DAC array, a Strong ARM comparator, and a SAR logic unit; The input end of the differential capacitor DAC array is connected to an analog input signal. The output end of the differential capacitor DAC array is connected to the input end of the Strong ARM comparator. The output end of the Strong ARM comparator is connected to the input end of the SAR logic unit. The output end of the SAR logic unit is connected to the differential capacitor DAC array based on a feedback circuit and outputs a first digital output signal.

3. The scaled analog-to-digital converter based on the SAR-SDM hybrid structure according to claim 2, wherein The differential capacitor DAC array adopts a binary weighted capacitor array, including a first capacitor array and a second capacitor array. The first capacitor array and the second capacitor array respectively include capacitors C1, C2, C3, C4, C5, C0. The capacitance value ratio of the capacitors C1, C2, C3, C4, C5, C0 is 1:2:4:8:16:

1. The upper plate of each capacitor is connected to the input end of the Strong ARM comparator. The lower plate of each capacitor is connected to a phase switch. The lower plate of each capacitor except C0 is also connected to the analog input signal and the reference voltage.

4. The scalable analog-to-digital converter based on the SAR-SDM hybrid structure according to claim 3, wherein The phase switch is a CMOS switch, and the CMOS switch is formed by connecting an NMOS switch and a PMOS switch in parallel.

5. The scaled analog-to-digital converter based on the SAR-SDM hybrid structure according to claim 2, wherein The Strong ARM comparator is a dynamic Strong ARM comparator with an RS latch.

6. The scalable analog-to-digital converter based on the SAR-SDM hybrid structure according to claim 2, wherein The SAR logic unit includes an upper D flip-flop group and a lower D flip-flop group. The SAR logic unit performs shift register processing on the output signal of the Strong ARM. Among them, the upper D flip-flop group performs shift processing on the comparison result based on the output signal of the Strong ARM comparator, and the lower D flip-flop group stores the shift processing result and outputs a first digital output signal of a five-digit digital signal.

7. The scaled analog-to-digital converter based on the SAR-SDM hybrid structure according to claim 6, characterized in that The SAR logic unit performs shift register processing on the output signal of the Strong ARM using the DWA algorithm. The SAR logic unit extracts a 32-bit code generated based on the output signal of the Strong ARM and a 5-bit binary pointer generated based on the analog input signal, generates a DWA algorithm output code, and transmits it to the differential capacitor DAC array through a feedback circuit based on the DWA algorithm output code.

8. The scaled analog-to-digital converter based on the SAR-SDM hybrid structure according to claim 1, wherein The SDM modulator module includes a first-stage integrator circuit, a second-stage integrator circuit, and a chopper circuit; The input end of the chopper circuit is connected to an input voltage, the output end of the chopper circuit is connected to the input end of the first-stage integrator circuit, the output end of the first-stage integrator circuit is connected to the input end of the second-stage integrator circuit, and the output end of the second-stage integrator circuit outputs a digital code stream to the control signal input end of the data selector; The first-stage integrator circuit and the second-stage integrator circuit are also provided with a feedback circuit.

9. The scaled analog-to-digital converter based on the SAR-SDM hybrid structure according to claim 8, wherein, The first-stage integrator circuit includes a first operational amplifier, and the second-stage integrator circuit includes a second operational amplifier. The first operational amplifier and the second operational amplifier are CLADD A / AB fully differential two-stage operational amplifiers.

10. The scaled analog-to-digital converter based on the SAR-SDM hybrid structure according to claim 8, wherein, The chopper circuit includes a third operational amplifier, two operational amplifiers, a sampler, an integrating capacitor, and eight sampling switches. Among them, four sampling switches are connected to the input end of the third operational amplifier, four sampling switches are connected to the output end of the third operational amplifier, and the two operational amplifiers, the sampler, and the integrating capacitor are connected in parallel with the third operational amplifier.

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