High-speed low-delay real-time signal convolution modulation method and device based on FGPA

Abstract

The invention relates to a high-speed low-delay real-time signal convolution modulation method and device based on FGPA, and belongs to the technical field of digital signal processing, and the method comprises the steps: obtaining a noise convolution kernel signal in an FPGA memory based on a random addressing code generated by a radio frequency signal; performing cyclic shift on the noise convolution kernel signal in a pipeline mode to obtain a noise convolution kernel signal to be convolved, and copying the radio frequency signal to obtain a radio frequency signal to be convolved; and reading signal points in the to-be-convolved noise convolution kernel signal and the to-be-convolved radio frequency signal in parallel through an assembly line mode to perform multiplication calculation, and accumulating multiplication calculation results to obtain a convolution modulation result. According to the FGPA-based high-speed low-delay real-time signal convolution modulation method provided by the invention, the interference effect of the signal is improved, linear convolution is replaced by cyclic convolution, a large amount of calculation time is saved, the problem of long calculation time is solved, and real-time convolution calculation is completed under the condition of low delay.

Description

Technical Field

[0001] The present invention relates to the technical field of digital signal processing, and in particular to a high-speed low-latency real-time signal convolution modulation method and device based on FGPA. Background Art

[0002] The real-time convolution modulation of radio frequency signals with low latency can be widely applied to the field of digital signal processing, including: wireless communication, industrial automation control, radar and electronic countermeasure systems, etc. The radio frequency signal band range usually refers to the frequency between 3 kHz and 300 GHz, and can be divided into multiple sub-bands according to different frequencies. Taking the field of radar electronic countermeasures as an example, the microwave band (3 GHz to 300 GHz) is widely used, and the convolution modulation processing of radio frequency radar signals can achieve effective radar interference effects in electronic countermeasures. When implementing the convolution modulation interference task of radio frequency signals at a high sampling rate on hardware, it is necessary to perform real-time modulation processing on high-speed radio frequency signals through digital signal processing methods. When the convolution modulation device receives a radio frequency signal, it will store the radio frequency signal through a digital radio frequency memory. Next, in the signal modulation processing module, it is necessary to read the stored radio frequency signal and the noise convolution kernel signal into the convolution modulation module respectively within an extremely short time and modulate the signal through convolution. Finally, power control is performed on the convolution modulation processed signal to obtain the final required radio frequency radar convolution modulation interference signal. To achieve this purpose, the main technologies used include signal sampling and signal convolution technologies in digital signal processing. However, the convolution modulation of radio frequency signals at a high sampling rate still has certain defects and problems in the actual application environment.

[0003] The first category is the problem that the noise signal distribution type in the noise signal convolution kernel participating in the convolution modulation is single, making the corresponding interference effect it generates easy to be recognized. Using a single convolution kernel to perform convolution modulation with all radio frequency signals will make the final convolution modulation interference output easy to be recognized. By means of signal analysis, the used noise signal convolution kernel can be recognized, and then the modulation interference effect will be greatly reduced.

[0004] The second category is due to the insufficient computing power of hardware devices. When performing convolution modulation processing of radio frequency signals, a large amount of time and registers are required, which is difficult to meet the real-time requirements at a high sampling rate. For convolution calculation, from its mathematical principle analysis, its calculation process is a process of cyclic shift multiplication and addition. The discrete digital signal linear convolution formula is as follows: . The formula represents a process of shift, multiplication, and accumulation. Each step of the operation processing requires one CLK clock and will also occupy the corresponding register resources at the same time. Summary of the Invention

[0005] In view of this, it is necessary to provide a high-speed and low-latency real-time signal convolution modulation method and device based on FGPA to achieve the purpose of improving the interference effect and reducing the convolution modulation time.

[0006] To achieve the above object, in a first aspect, the present invention provides a high-speed and low-latency real-time signal convolution modulation method based on FGPA, including: Based on the random addressing code generated by the radio frequency signal, obtain the noise convolution kernel signal in the FPGA memory; the FPGA memory is used to store convolution noise signals of various distribution types; For the noise convolution kernel signal, perform cyclic shift in a pipelined manner to obtain the to-be-convolved noise convolution kernel signal, and copy the radio frequency signal to obtain the to-be-convolved radio frequency signal; In a pipelined manner, parallelly read the signal points in the to-be-convolved noise convolution kernel signal and the to-be-convolved radio frequency signal for multiplication calculation, and accumulate the multiplication calculation results to obtain the convolution modulation result.

[0007] In a possible implementation manner, the step of performing cyclic shift in a pipelined manner on the noise convolution kernel signal to obtain the to-be-convolved noise convolution kernel signal, and copying the radio frequency signal to obtain the to-be-convolved radio frequency signal includes: Invert the highest bits of the signal points of the radio frequency signal and the noise convolution kernel signal respectively to obtain a signed target radio frequency signal and a target noise convolution kernel signal; Through parallel processing, cyclically shift the target noise convolution kernel signal and splice it to obtain the to-be-convolved noise convolution kernel signal; Copy the target radio frequency signal and splice it to obtain the to-be-convolved radio frequency signal.

[0008] In a possible implementation manner, the step of parallelly reading the signal points in the to-be-convolved noise convolution kernel signal and the to-be-convolved radio frequency signal in a pipelined manner for multiplication calculation, and accumulating the multiplication calculation results to obtain the convolution modulation result includes: Based on a preset corresponding relationship, parallelly read the signal points in the to-be-convolved noise convolution kernel signal and the to-be-convolved radio frequency signal to obtain associated radio frequency signals and convolution kernel signals; Perform multiplication calculation on the signal points in the associated radio frequency signal and convolution kernel signal to obtain a multiplication calculation result; Accumulate and splice the multiplication calculation results to obtain the convolution modulation result.

[0009] In a possible implementation, after parallelly reading signal points in the to-be-convolved noise convolution kernel signal and the to-be-convolved RF signal in a pipelined manner for multiplication calculation and accumulating the multiplication calculation results to obtain a convolution modulation result, the method further includes: Adjusting the bit width of the convolution modulation result based on the bit width requirement of the output signal.

[0010] In a possible implementation, the adjusting the bit width of the convolution modulation result based on the bit width requirement of the output signal includes: Converting the convolution modulation result from a fixed-point number with a first bit width to a floating-point number with a second bit width; Converting the floating-point number with the second bit width to a fixed-point number meeting the requirement.

[0011] In a possible implementation, before obtaining the noise convolution kernel signal from the FPGA memory based on the random addressing code generated from the RF signal, the method further includes: Determining the random addressing code based on the value of a target signal point in the RF signal.

[0012] In a second aspect, the present invention further provides a high-speed low-latency real-time signal convolution modulation device based on FGPA, including: An acquisition unit, configured to obtain a noise convolution kernel signal from an FPGA memory based on a random addressing code generated from an RF signal; the FPGA memory is used to store convolution noise signals of multiple distribution types; A preprocessing unit, configured to perform circular shifting on the noise convolution kernel signal in a pipelined manner to obtain a to-be-convolved noise convolution kernel signal, and copy the RF signal to obtain a to-be-convolved RF signal; A convolution modulation unit, configured to parallelly read signal points in the to-be-convolved noise convolution kernel signal and the to-be-convolved RF signal in a pipelined manner for multiplication calculation, and accumulate the multiplication calculation results to obtain a convolution modulation result.

[0013] In a third aspect, the present invention further provides an electronic device, including a memory and a processor, where The memory is used to store a program; The processor is coupled to the memory and configured to execute the program stored in the memory to implement the high-speed low-latency real-time signal convolution modulation method based on FGPA in any of the above implementations.

[0014] Fourthly, the present invention also provides a computer-readable storage medium for storing computer-readable programs or instructions, which can implement the steps in the FGPA-based high-speed and low-latency real-time signal convolution modulation method described in any of the above implementation manners when executed by a processor.

[0015] The beneficial effects of the present invention are as follows: The FGPA-based high-speed and low-latency real-time signal convolution modulation method and device provided by the present invention store convolution noise signals of various distribution types in the FPGA memory. When a set of radio frequency signals needs to be convolved, the noise convolution kernel signals are randomly obtained from the FPGA memory according to the random addressing code, which increases the richness and randomness of the noise signals and solves the problem that the noise signal types are single and easy to be recognized, thereby improving the interference effect of the signals. The noise convolution kernel signals are circularly shifted to obtain the to-be-convolved noise convolution kernel signals, and the radio frequency signals are copied to obtain the to-be-convolved radio frequency signals. Using circular convolution instead of linear convolution saves a large amount of calculation time. The signal points in the to-be-convolved noise convolution kernel signals and the to-be-convolved radio frequency signals are read in parallel for multiplication calculation, and the multiplication calculation results are accumulated to obtain the convolution modulation result, which solves the problem of long calculation time and completes real-time convolution calculation under the condition of low latency. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative efforts.

[0017] Figure 1 It is a schematic flowchart of an embodiment of the FGPA-based high-speed and low-latency real-time signal convolution modulation method provided by the present invention; Figure 2 It is a schematic diagram of the generation and storage of multi-type noise signals provided by the present invention; Figure 3 It is a preprocessing pipeline diagram of convolution modulation data provided by the present invention; Figure 4 It is a double-parallel and circular convolution pipeline diagram provided by the present invention; Figure 5 It is a data bit width adjustment pipeline diagram provided by the present invention; Figure 6 It is a low-latency and multi-random real-time convolution implementation framework provided by the present invention; Figure 7 It is a low-latency and multi-random real-time convolution flowchart provided by the present invention; Figure 8Schematic diagram of an embodiment structure of the high-speed and low-latency real-time signal convolution modulation device based on FGPA provided by the present invention; Figure 9 Schematic diagram of an embodiment structure of the electronic device provided by the present invention. Detailed implementation manners

[0018] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts belong to the protection scope of the present invention.

[0019] In the description of the embodiments of the present invention, unless otherwise specified, the meaning of "a plurality" is two or more. "And / or" describes the association relationship of associated objects, indicating that there can be three relationships, for example: A and / or B, which can represent: A exists alone, A and B exist simultaneously, and B exists alone these three situations.

[0020] The descriptions such as "first" and "second" involved in the embodiments of the present invention are only for descriptive purposes, and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Therefore, the technical features defined with "first" and "second" may explicitly or implicitly include at least one of such features.

[0021] Referring to "embodiment" herein means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The phrase appears in various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0022] The present invention provides a high-speed and low-latency real-time signal convolution modulation method and device based on FGPA, which will be described separately below.

[0023] Figure 1 Schematic diagram of an embodiment process of the high-speed and low-latency real-time signal convolution modulation method based on FGPA provided by the present invention, as Figure 1 shown, the high-speed and low-latency real-time signal convolution modulation method based on FGPA includes: S101. Obtain a noise convolution kernel signal in the FPGA memory based on the random addressing code generated by the radio frequency signal; the FPGA memory is used to store convolution noise signals of various distribution types.

[0024] A simulation software can be used to generate noise signals of various different distribution types. For example, it can include Gaussian noise signals, white noise signals, random noise signals, etc. The generated noise signals are converted into binary digital signal forms and stored in the FPGA memory in the form of noise convolution kernels (Noise_Kernels).

[0025] When a set of radio frequency signals needs to be convolved, a random addressing code can be generated according to the radio frequency signals, and then the noise convolution kernel signals can be randomly obtained from the FPGA memory according to the random addressing code, so as to randomly access the noise convolution kernel signals, making the convolution kernels participating in the convolution have randomness, and increasing the difficulty of analyzing the noise signals when detecting and identifying interference signals.

[0026] S102. The noise convolution kernel signals are circularly shifted in a pipeline manner to obtain the noise convolution kernel signals to be convolved, and the radio frequency signals are copied to obtain the radio frequency signals to be convolved.

[0027] The obtained noise convolution kernel signals and radio frequency signals are respectively preprocessed. For example, the sign bits of the noise convolution kernel signals and radio frequency signals can be converted, and the obtained unsigned noise convolution kernel signals and radio frequency signals are converted into signed signals.

[0028] And the noise convolution kernel signals are subjected to the circular convolution shift processing required in the circular convolution in a pipeline manner, and then spliced to obtain the noise convolution kernel signals to be convolved. At the same time, the radio frequency signals are copied and spliced to obtain the radio frequency signals to be convolved.

[0029] S103. In a pipeline manner, the signal points in the noise convolution kernel signals to be convolved and the radio frequency signals to be convolved are read in parallel for multiplication calculation, and the multiplication calculation results are accumulated to obtain the convolution modulation result.

[0030] In a pipeline manner, the signal points in the noise convolution kernel signals to be convolved and the radio frequency signals to be convolved are read in parallel, and the multiplication calculation is simultaneously performed on each group of read signal points, and then the multiplication calculation results are accumulated, that is, the addition calculation is performed, to obtain the convolution modulation result.

[0031] The high-speed low-latency real-time signal convolution modulation method based on FGPA provided by the embodiments of the present invention stores convolution noise signals of various distribution types in the FPGA memory. When a set of radio frequency signals needs to perform convolution calculation, according to the random addressing code, the noise convolution kernel signal is randomly obtained in the FPGA memory, which increases the richness and randomness of the noise signal, solves the problem that the noise signal type is single and easy to be recognized, thereby improving the interference effect of the signal. The noise convolution kernel signal is circularly shifted to obtain the to-be-convolved noise convolution kernel signal, and the radio frequency signal is copied to obtain the to-be-convolved radio frequency signal. Using circular convolution to replace linear convolution saves a large amount of calculation time. By parallelly reading the signal points in the to-be-convolved noise convolution kernel signal and the to-be-convolved radio frequency signal and performing multiplication calculation, and accumulating the multiplication calculation results to obtain the convolution modulation result, the problem of long calculation time is solved, and real-time convolution calculation is completed under the condition of low latency.

[0032] In some embodiments of the present invention, before obtaining the noise convolution kernel signal in the FPGA memory based on the random addressing code generated based on the radio frequency signal, it further includes: Generating noise signals of various distribution types through simulation software; Converting the noise signal into a binary digital signal and storing it in the FPGA memory in the form of a noise convolution kernel.

[0033] The main purpose of generating and storing multi-type noise signals is to achieve the diversification of noise signal types and the storage and subsequent use of noise signals. In the noise signal generation preprocessing stage of the embodiments of the present invention, first, various distribution types of noise signals are generated through mathematical tools, including Gaussian noise signals, white noise signals, random noise signals, etc., and different types of noise signals are further adjusted with different parameters, so that various noise convolution kernel signals with different types and distributions can be obtained.

[0034] Then, the generated noise signal is converted into a binary digital signal form and stored in the memory of the FPGA in the form of a noise convolution kernel (Noise_Kernels), and it can be read from it when used later. Figure 2 For the generation and storage schematic diagram of multi-type noise signals provided by the present invention, as Figure 2 shown is the specific implementation scheme process.

[0035] In some embodiments of the present invention, before obtaining the noise convolution kernel signal in the FPGA memory based on the random addressing code generated based on the radio frequency signal, it further includes: Determining the random addressing code based on the value of the target signal point in the radio frequency signal.

[0036] The generation of the noise convolution kernel signal is a preprocessing process, and the reading of the noise convolution kernel signal is the first step in the convolution adjustment pipeline scheme. The specific implementation scheme is as follows: When a set of radio frequency signals needs to be convolved, the number of points of the radio frequency signals is , and the bit width of each signal point is N (bit), that is, the total length of the radio frequency signal is .

[0037] Obtain a set of random addressing codes Random_Code with a bit width of M through the radio frequency signals. Each bit of the addressing code is the value of the i N bits of the radio frequency signal, that is, Random_Code(i) = N i (where i = 1:M).

[0038] In this way, random access to the noise convolution kernel signal can be realized, making the convolution kernel participating in the convolution random, and increasing the analysis difficulty of the noise signal when detecting and identifying interference signals.

[0039] In some embodiments of the present invention, for the noise convolution kernel signal, circular shifting is performed in a pipeline manner to obtain a noise convolution kernel signal to be convolved, and the radio frequency signal is copied to obtain a radio frequency signal to be convolved, including: Invert the highest bits of the signal points of the radio frequency signal and the noise convolution kernel signal respectively to obtain a signed target radio frequency signal and a target noise convolution kernel signal; Circularly shift the target noise convolution kernel signal through parallel processing and then splice it to obtain the noise convolution kernel signal to be convolved; Copy the target radio frequency signal and then splice it to obtain the radio frequency signal to be convolved.

[0040] The preprocessing part of the convolution modulation data mainly preprocesses the high-speed radio frequency signal to be convolved and the noise convolution kernel to prepare data for the subsequent parallel processing scheme.

[0041] Using the random reading method provided in the above embodiments to obtain the noise convolution kernel, the randomness of the noise signal to be convolved can be further improved by using the random reading method, enhancing the interference effect.

[0042] After obtaining the radio frequency signal Signal and the convolution kernel Noise_Kernels required for convolution, the subsequent processing process begins. The following is a detailed introduction to the pipeline preprocessing process of the high-speed radio frequency signal data Signal(N ) and the noise convolution kernel Noise_Kernels(N ).

[0043] Figure 3 This is the convolution modulation data preprocessing pipeline diagram provided by the present invention. As Figure 3 shown, the bit width of each group of radio frequency signals Signal(N ) to be processed is N, and the number of signal points Point is ones. The signal bit width of the convolution kernel Noise_Kernels(N ) participating in the convolution is also N, and the number of points is .

[0044] Specifically, the preprocessing pipeline includes the following three steps: (1) The first step of the pipeline: At the first CLK clock, convert the radio frequency signal and the convolution kernel signal from unsigned signal points to signed signal points. That is, take the inverse of the highest bit of the signal points of the radio frequency signal and the noise convolution kernel signal respectively to obtain the signed target radio frequency signal and the target noise convolution kernel signal.

[0045] (2) The second step of the pipeline: At the second CLK clock, registers are required for parallel shift storage processing. Within this one CLK clock, cycles of circular shift required for the convolution kernel Noise_Kernels are completed simultaneously, that is, convolution kernel signals after

[0046] cycles are obtained. (3) The third step of the pipeline: At the third CLK clock, splice the noise convolution kernel signals after the previous cycles to obtain the noise convolution kernel signal to be convolved, and use a register to store the spliced convolution kernel signal. The obtained data can be used for subsequent loop parallel processing. Similarly, the radio frequency signal Signal also needs to be copied

[0047] times and then spliced and stored to obtain the radio frequency signal to be convolved.

[0048] At this point, the data preprocessing pipeline for convolution modulation has been completed. In terms of clock consumption, only three CLK clocks are required to complete the data preprocessing of dual-parallel low-latency loop convolution modulation, thus ensuring the real-time processing of high-speed radio frequency signals. In some embodiments of the present invention, the method of parallelly reading the signal points in the noise convolution kernel signal to be convolved and the radio frequency signal to be convolved through the pipeline for multiplication calculation, and accumulating the multiplication calculation results to obtain the convolution modulation result includes: Parallelly reading the signal points in the noise convolution kernel signal to be convolved and the radio frequency signal to be convolved based on a preset correspondence relationship to obtain the associated radio frequency signal and convolution kernel signal; Multiply the signal points in the associated radio frequency signal and convolution kernel signal to obtain a multiplication result; Accumulate and splice the multiplication result to obtain a convolution modulation result.

[0049] In the convolution modulation data preprocessing stage, 3 CLK clocks are consumed to complete the data preparation for subsequent dual-parallel and low-latency cyclic convolution. The convolution modulation data preprocessing stage has been completed before, and at the same time, two sets of Spliced signals to be convolved are obtained, namely the replicated and spliced radio frequency signal Signal and the cycled and spliced convolution kernel signal Noise_Kernels.

[0050] The subsequent convolution calculation will adopt a cyclic parallel method to process these two sets of Signals, and combine the radio frequency signal and convolution kernel in them one by one according to the convolution calculation method for subsequent calculation and processing.

[0051] The completion of the dual-parallel and low-latency cyclic convolution calculation is also achieved by means of a pipeline. Figure 4 This is the dual-parallel and cyclic convolution pipeline diagram provided by the present invention.

[0052] As Figure 4 shown, this stage mainly needs to complete the multiplication and addition calculations in the convolution operation. Two sets of Signals need to be corresponded one by one according to the mathematical model of cyclic convolution, and then the corresponding mathematical calculations are completed. The pipeline steps are divided into the following three steps: (1) The first step of the pipeline: For the two sets of Signals to be convolved obtained in the convolution modulation data preprocessing stage, through the method of cyclic parallel processing, according to the corresponding relationship as Figure 4 shown (i.e., the preset corresponding relationship), read the points with a bit width of N bits in each corresponding set of signals to obtain the associated radio frequency signal and convolution kernel signal, and then load them into the multiply-accumulate module of the convolution calculation. That is, within one CLK clock, the

[0053] Times of data to be convolved required for cyclic convolution are simultaneously loaded into the Multiplication and addition processing modules for subsequent convolution. Here, Register calculation resources of multiply-accumulate processing modules are required.

[0054] (2) The second step of the pipeline: When the signals participating in the convolution are loaded, next, within the time of one CLK clock, complete the Group of multiplications with a bit width of N and Points again in the way of parallel processing.

[0055] Taking the processing of a group of multiplication and addition calculation modules as an example, in the module, there is a corresponding group of radio frequency signals Signal and convolution kernel signals Noise_Kernels. Each signal has signal points with a bit width of N. When performing multiplication calculations, the loop parallel method is adopted again. At the same time, multiplying the corresponding points of the radio frequency signal and the convolution kernel can obtain mult1.1 to mult in total multiplication calculation results.

[0056] (3)The third step of the pipeline: After completing the parallel multiplication calculations, at the next CLK clock, for each group of multiplication calculation results obtained after multiplying each group of corresponding signals in a group, add them up through an accumulator Adder to obtain the multiply-accumulate result Adder Result (3N) of this group of signals. Concatenate the accumulation results with a bit width of 3N to obtain the final convolution calculation result Conv_Result (3N ).

[0057] Thus, the entire calculation process of the cyclic convolution is completed.

[0058] In summary, by combining the convolution modulation data preprocessing and the parallel cyclic convolution calculation, only 6 CLK clocks are required for the overall clock consumption. This solution meets the requirement of low latency and solves the problem of excessive time required for convolution modulation. At the same time, the register has the function of data storage, and real-time processing can also be achieved for radio frequency signals at high sampling rates.

[0059] In some embodiments of the present invention, after multiplying the signal points in the convolution noise convolution kernel signal to be convolved and the radio frequency signal to be convolved in parallel by means of a pipeline and accumulating the multiplication calculation results to obtain the convolution modulation result, it further includes: Adjusting the bit width of the convolution modulation result based on the requirement of the output signal for the bit width.

[0060] For some specific industrial application scenarios, after the convolution modulation is completed, the bit width of the final modulation data needs to be adjusted accordingly to meet the requirement of the output signal for the bit width.

[0061] In some embodiments of the present invention, adjusting the bit width of the convolution modulation result based on the requirement of the output signal for the bit width includes: Converting the convolution modulation result from a fixed-point number with the first bit width to a floating-point number with the second bit width; Convert the floating-point number with the second bit width into a fixed-point number that meets the requirements.

[0062] Using the direct truncation method will result in loss of data precision. Therefore, when adjusting the bit width, it is necessary to ensure the data precision as much as possible. The present invention will adopt the following method to adjust the bit width while maintaining the data precision.

[0063] Figure 5 This is the data bit width adjustment pipeline diagram provided by the present invention. As Figure 5 shown, the specific pipeline steps are as follows: In the first step, a fixed-point to floating-point IP core is used. After 4CLK clocks, the convolution modulation result output by the convolution modulation, which is a fixed-point number with a bit width of 3N (i.e., the first bit width), is converted into a floating-point number with a bit width of M (i.e., the second bit width).

[0064] In the second step, an IP core for converting a floating-point number to a fixed-point number is used. After 5CLK clocks, the floating-point number with a bit width of M is converted into a fixed-point number that meets the output bit width requirements, and the final convolution modulation output result that meets the bit width requirements is obtained: Conv_Result(L ).

[0065] So far, the low-latency convolution modulation of high-speed radio frequency signals is all completed.

[0066] That is, in view of the problem that the first type of noise signal distribution type is easy to be recognized, the present invention proposes a method for storing multi-type digital noise signals based on FPGA. The main principle is to utilize the memory in the FPGA to store digital signals in advance. First, noise signals with different distribution types are generated through mathematical tools, and then the previously obtained noise signals are stored in the memory of the FPGA development board in the form of digital signals. When the noise signals need to be used subsequently, a random code addressing method is adopted to randomly read the stored noise signals, so that the problem of single and easy-to-recognize noise signal types can be better solved.

[0067] In view of the problem that the signal convolution modulation processing time is long and difficult to meet the real-time requirement at high sampling rates for the second type, the present invention proposes a dual-parallel convolution calculation method based on circular convolution. The principle is to complete the calculation process of circular shift and multiplication and addition in the circular convolution by means of parallel processing.

[0068] Here, a comparative analysis is carried out. Taking a group of convolution signals with signal points as an example, the time consumption in the linear convolution process is analyzed in detail: The number of circular shift times is: times.

[0069] The number of multiplication calculations after each shift is: 1 + 2 + … + + +…+2+1 = 。

[0070] The number of addition operations after each shift is: 0 + 1 + 2 + … + + +…+2+1+0 = + 。

[0071] Similarly, taking an array with two sets of point numbers as an example, analyze the time required for each step of the circular convolution under the original scheme: Number of circular shifts: 。

[0072] The number of multiplication operations after each shift is: 。

[0073] The number of addition operations after each shift is: 。

[0074] From the above analysis results, the time and register resources required by the circular convolution method itself are much less than those of the linear convolution. In addition, on the basis of the circular convolution, the idea of double-parallel processing can further reduce a large amount of time.

[0075] The principle is to complete all the circular convolutions required for the convolution within one clock cycle, which requires a large amount of register resources. Then, through a loop calculation method, the multiplication and addition operations of the group of signals completed previously are calculated simultaneously, so the multiplication and addition calculation time of can be saved. At the same time, in the multiplication and addition calculation module, the parallel calculation method is also adopted to perform multiplication operations on each point in each group of signals in the group of signals, then the calculation time of can be saved.

[0076] This algorithm framework mainly consists of the following parts: a noise signal generation and reading preprocessing module, a convolution data preprocessing module, and a double-parallel low-latency circular convolution implementation module.

[0077] Figure 6 This is a low-latency multi-random real-time convolution implementation framework provided by the present invention. As Figure 6 shown, first is the noise signal generation and reading preprocessing stage, where various types of noise signals required are generated by simulation software and then stored in the memory in digital signal form for subsequent modulation needs.

[0078] When performing convolution calculations, taking a group of high-speed radio frequency signals Signal as an example, this group of signals has signal points. When the convolution module receives the radio frequency signal, it will first generate a group of random addressing codes based on this group of signals, and obtain the Gaussian convolution kernel through this code.

[0079] Next is the data preprocessing stage before convolution modulation calculation. The radio frequency signal to be convolved and the noise convolution kernel are preprocessed correspondingly. Finally, it is a double-parallel and low-latency cyclic convolution calculation. The result of the convolution calculation is finally adjusted according to the requirements of the output signal for the bit width, and the final convolution modulation output can be obtained.

[0080] The convolution scheme of the present invention for low-latency and multi-random high-speed radio frequency signals still uses a pipeline form for real-time processing. Figure 7 For the low-latency and multi-random real-time convolution flowchart provided by the present invention, as Figure 7 shown, the specific pipeline steps are as follows: (1) The first step of the pipeline: Complete the reading of the noise convolution kernel data to be convolved.

[0081] (2) The second step of the pipeline: Complete the conversion of the sign bit of the data to be convolved, and convert the unsigned radio frequency signal and the previously read noise convolution kernel signal into signed signals.

[0082] (3) The third step of the pipeline: Preprocess the two groups of signals to be convolved, complete the cyclic convolution shift required by the noise convolution kernel in the cyclic convolution, and then splice them to form the data required for the subsequent parallel convolution calculation.

[0083] (4) The fourth step of the pipeline: Adopt a double-parallel processing method. On the basis of parallel processing of multiple groups of data, the multiplication and addition calculations of each single group of signals are also processed in parallel.

[0084] (5) The fifth step of the pipeline: Complete the adjustment of the data bit width on the basis of retaining the data accuracy.

[0085] The high-speed low-latency real-time signal convolution modulation method and device based on FGPA provided by the present invention have the following advantages: A dual-parallel method is adopted to achieve fast convolution calculation of RF signals at high sampling rates. First, aiming at the problem that the noise signal type is single and easy to be recognized, a scheme of mixing multiple types of noise signals is adopted. Multiple different types of noise signals are stored in a mixed manner in the form of digital signals. When performing convolution calculation, a random reading method is used to obtain the noise signals for the final calculation, increasing the richness and randomness of the noise signals, and making the final signal interference effect better. At the same time, aiming at the problems of too long convolution calculation time of RF signals at high sampling rates and non-real-time data processing, a dual-parallel processing method is proposed. Using circular convolution to replace linear convolution saves a large amount of calculation time, solves the problem of long calculation time, and completes real-time convolution calculation under the condition of low latency.

[0086] From the perspective of performance, adopting the processing scheme of the present invention and taking the convolution data preprocessing stage into consideration at the same time, the total number of clock cycles required is: six CLK clock cycles, which is much less than the time of linear convolution: + + 。

[0087] From the perspective of cost, in terms of time cost, the method of parallel computing adopted in this scheme consumes less time than the traditional method of linear one-by-one computing.

[0088] In terms of the cost of register resource consumption, the circular convolution scheme is adopted in this scheme. In terms of register consumption: the number of digits consumed by the circular shift register is: ,the number of multipliers consumed is: , the adder consumption is: ,compared with the number of registers of linear convolution: + + is significantly reduced, and the calculation cost is lower. However, this scheme has a certain requirement for parallel computing ability and requires a corresponding chip to be able to process a large amount of data simultaneously.

[0089] From the perspective of security and reliability, this scheme completely adopts the mathematical principle of circular convolution and transforms it into a specific implementation algorithm on the mathematical model of circular convolution. Its calculation results can be verified through simulation results, and the results are exactly the same as the actual calculation results.

[0090] That is, in order to achieve the purpose of fast calculation of convolution modulation of RF signals at high sampling rates, the present invention combines digital signal processing technology, adopts the method of circular fast convolution, and designs a real-time convolution implementation scheme with multiple noise types and low latency.

[0091] This solution consists of three main parts: noise signal generation and storage preprocessing module, convolution modulation data preprocessing module, and dual parallel low-latency convolution implementation module. The specific implementation process of the entire solution is as follows: (1) The first step is to generate and store noise signals. Use mathematical tools to generate noise signals of various distribution types. Then store them in the memory in the form of digital signals. When the noise signal is needed for convolution calculation later, the corresponding noise signal can be randomly read from the memory through a set of random addressing codes.

[0092] (2) The next step is the convolution modulation data preprocessing stage. The number of points in a group of signals is the number of cycles required for the circular convolution. Here, a large number of registers are required to complete all the cycles of the noise signal simultaneously within one CLK clock. point as an example, using registers, and then use a The register concatenates all the noise signals after the loop. At the same time, the RF signal also needs to be copied to the same length, so that the data preprocessing result before convolution modulation can be obtained.

[0093] (3) Finally, the low-latency convolution calculation implementation process under the dual parallel mode first needs to adopt the parallel processing method to splice the previous Each group of registers The RF signal and the corresponding noise signal are loaded into the multiplication and addition calculation module, and a total of groups, and in the multiplication and addition calculation modules of the RF signal and the noise signal of each group, each corresponding point in each group of signals is calculated in parallel. The multiplication results are added together to obtain the multiplication and addition results of the RF signal and the noise signal. The result is the final output of the convolution modulation. According to this scheme, the circular convolution calculation can be completed within six CLK clocks, thereby meeting the low latency requirement of the convolution modulation of the RF signal at a high sampling rate.

[0094] In summary, in view of the problem that noise signals are of a single type and easy to identify in signal interference modulation in the current industrial environment, the present invention proposes a solution of using multiple types of noise signals for mixed storage and random reading, making the noise signal more difficult to identify and enhancing the signal interference effect.

[0095] Regarding the problem of long calculation time and poor real-time performance of radio frequency signal convolution modulation at high sampling rates in FPGAs, the present invention proposes a double-parallel and low-latency convolution modulation calculation scheme. By using circular convolution to replace linear convolution, a significant reduction in register resource utilization is achieved. Before performing convolution calculation, all circular results of the noise signal in the circular convolution are completed within the same clock, and then in a parallel manner, the multiplication and addition calculations of the signals after all circular shifts are completed simultaneously. Moreover, when performing the multiplication and addition calculations of the circularly shifted signals in each group, a parallel manner is also adopted, and the multiplication calculations are performed simultaneously for all points in each group of signals, and the calculation results are then added simultaneously to obtain the calculation result of this group of signals. The calculations of other groups of signals will also be completed within the same time. Finally, a low-latency real-time convolution modulation interference signal can be obtained.

[0096] To better implement the high-speed, low-latency, real-time signal convolution modulation method based on FGPA in the embodiments of the present invention, correspondingly, on the basis of the high-speed, low-latency, real-time signal convolution modulation method based on FGPA, as Figure 8 shown, the embodiments of the present invention also provide a high-speed, low-latency, real-time signal convolution modulation device based on FGPA. The high-speed, low-latency, real-time signal convolution modulation device 800 based on FGPA includes: An acquisition unit 801, configured to obtain a noise convolution kernel signal in the FPGA memory based on a random addressing code generated from a radio frequency signal; the FPGA memory is used to store convolution noise signals of various distribution types; A preprocessing unit 802, configured to perform circular shift on the noise convolution kernel signal in a pipelined manner to obtain a to-be-convolved noise convolution kernel signal, and copy the radio frequency signal to obtain a to-be-convolved radio frequency signal; A convolution modulation unit 803, configured to read signal points in the to-be-convolved noise convolution kernel signal and the to-be-convolved radio frequency signal in parallel in a pipelined manner for multiplication calculation, and accumulate the multiplication calculation results to obtain a convolution modulation result.

[0097] The above-mentioned high-speed, low-latency, real-time signal convolution modulation device 800 based on FGPA provided in the above embodiments can implement the technical solutions described in the embodiments of the above-mentioned high-speed, low-latency, real-time signal convolution modulation method based on FGPA. The specific implementation principles of the above-mentioned modules or units can be referred to the corresponding content in the embodiments of the above-mentioned high-speed, low-latency, real-time signal convolution modulation method based on FGPA, and will not be elaborated here.

[0098] As Figure 9 shown, the present invention also correspondingly provides an electronic device 900. The electronic device 900 includes a processor 901, a memory 902, and a display 903. Figure 9Only some components of the electronic device 900 are shown, but it should be understood that it is not required to implement all the shown components, and more or fewer components can be alternatively implemented.

[0099] In some embodiments, the processor 901 may be a central processing unit (CPU), a microprocessor, or other data processing chips, and is used to run the program code stored in the memory 902 or process data, such as the FGPA-based high-speed low-latency real-time signal convolution modulation method in the present invention.

[0100] In some embodiments, the processor 901 may be a single server or a server group. The server group may be centralized or distributed. In some embodiments, the processor 901 may be local or remote. In some embodiments, the processor 901 may be implemented on a cloud platform. In some embodiments, the cloud platform may include a private cloud, a public cloud, a hybrid cloud, a community cloud, a distributed cloud, an internal cloud, a multi-cloud, etc., or any combination of the above.

[0101] In some embodiments, the memory 902 may be an internal storage unit of the electronic device 900, such as the hard disk or memory of the electronic device 900. In some other embodiments, the memory 902 may also be an external storage device of the electronic device 900, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the electronic device 900.

[0102] Furthermore, the memory 902 may also include both the internal storage unit and the external storage device of the electronic device 900. The memory 902 is used to store the application software installed in the electronic device 900 and various types of data.

[0103] In some embodiments, the display 903 may be an LED display, a liquid crystal display, a touch liquid crystal display, an organic light-emitting diode (OLED) toucher, etc. The display 903 is used to display the information in the electronic device 900 and to display a visual user interface. The components 901-903 of the electronic device 900 communicate with each other through a system bus.

[0104] In one embodiment, when the processor 901 executes the FGPA-based high-speed low-latency real-time signal convolution modulation program in the memory 902, the following steps may be implemented: Obtain a noise convolution kernel signal in the FPGA memory based on the random addressing code generated by the radio frequency signal; the FPGA memory is used to store convolution noise signals of various distribution types; For the noise convolution kernel signal, perform cyclic shift in a pipelined manner to obtain the noise convolution kernel signal to be convolved, and copy the radio frequency signal to obtain the radio frequency signal to be convolved; In a pipelined manner, parallelly read signal points in the noise convolution kernel signal to be convolved and the radio frequency signal to be convolved for multiplication calculation, and accumulate the multiplication calculation results to obtain the convolution modulation result.

[0105] It should be understood that when the processor 901 executes the FGPA-based high-speed and low-latency real-time signal convolution modulation program in the memory 902, in addition to the above functions, other functions can also be implemented. For specific details, refer to the description of the corresponding method embodiments above.

[0106] Furthermore, the embodiments of the present invention do not specifically limit the type of the mentioned electronic device 900. The electronic device 900 can be a mobile phone, a tablet computer, a personal digital assistant (PDA), a wearable device, a laptop computer, or other portable electronic devices. Exemplary embodiments of the portable electronic device include, but are not limited to, portable electronic devices equipped with IOS, android, microsoft, or other operating systems. The above portable electronic devices can also be other portable electronic devices, such as a laptop computer with a touch-sensitive surface (such as a touch panel). It should also be understood that in some other embodiments of the present invention, the electronic device 900 may not be a portable electronic device, but a desktop computer with a touch-sensitive surface (such as a touch panel).

[0107] Correspondingly, the embodiments of the present invention also provide a computer-readable storage medium. The computer-readable storage medium is used to store computer-readable programs or instructions. When the programs or instructions are executed by a processor, the steps or functions in the FGPA-based high-speed and low-latency real-time signal convolution modulation method provided by the above method embodiments can be implemented.

[0108] Those skilled in the art can understand that all or part of the processes of implementing the methods in the above embodiments can be completed by instructing relevant hardware (such as a processor, a controller, etc.) through a computer program. The computer program can be stored in a computer-readable storage medium. Among them, the computer-readable storage medium is a disk, an optical disk, a read-only memory, or a random access memory, etc.

[0109] The above has introduced in detail the high-speed low-latency real-time signal convolution modulation method and device based on FGPA provided by the present invention. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A high-speed and low-latency real-time signal convolution modulation method based on FGPA, characterized in that Including: A random addressing code generated based on a radio frequency signal, and obtaining a noise convolution kernel signal in an FPGA memory; The FPGA memory is used to store convolution noise signals of various distribution types; For the noise convolution kernel signal, performing circular shift in a pipeline manner to obtain a to-be-convolved noise convolution kernel signal, and copying the radio frequency signal to obtain a to-be-convolved radio frequency signal; In a pipeline manner, parallelly reading signal points in the to-be-convolved noise convolution kernel signal and the to-be-convolved radio frequency signal for multiplication calculation, and accumulating the multiplication calculation results to obtain a convolution modulation result.

2. The method for high-speed and low-latency real-time signal convolutional modulation based on FGPA according to claim 1, wherein The step of, for the noise convolution kernel signal, performing circular shift in a pipeline manner to obtain a to-be-convolved noise convolution kernel signal, and copying the radio frequency signal to obtain a to-be-convolved radio frequency signal, includes: Taking the inverse of the most significant bits of the signal points of the radio frequency signal and the noise convolution kernel signal respectively to obtain a signed target radio frequency signal and a target noise convolution kernel signal; Performing circular shift on the target noise convolution kernel signal through parallel processing and then splicing to obtain the to-be-convolved noise convolution kernel signal; Copying the target radio frequency signal and then splicing to obtain the to-be-convolved radio frequency signal.

3. The high-speed low-latency real-time signal convolutional modulation method based on FGPA according to claim 1, wherein The step of, in a pipeline manner, parallelly reading signal points in the to-be-convolved noise convolution kernel signal and the to-be-convolved radio frequency signal for multiplication calculation, and accumulating the multiplication calculation results to obtain a convolution modulation result, includes: Parallelly reading signal points in the to-be-convolved noise convolution kernel signal and the to-be-convolved radio frequency signal based on a preset corresponding relationship to obtain associated radio frequency signals and convolution kernel signals; Performing multiplication calculation on the signal points in the associated radio frequency signals and convolution kernel signals to obtain a multiplication calculation result; Accumulating and splicing the multiplication calculation results to obtain a convolution modulation result.

4. The high-speed low-latency real-time signal convolution modulation method based on FGPA according to claim 1, wherein After the step of, in a pipeline manner, parallelly reading signal points in the to-be-convolved noise convolution kernel signal and the to-be-convolved radio frequency signal for multiplication calculation, and accumulating the multiplication calculation results to obtain a convolution modulation result, further includes: Adjusting the bit width of the convolution modulation result based on the requirement of the output signal for the bit width.

5. The high-speed and low-latency real-time signal convolution modulation method based on FGPA according to claim 4, wherein The step of adjusting the bit width of the convolution modulation result based on the requirement of the output signal for the bit width, includes: Converting the convolution modulation result from a fixed-point number of the first bit width to a floating-point number of the second bit width; Converting the floating-point number of the second bit width to a fixed-point number meeting the requirement.

6. The high-speed and low-latency real-time signal convolution modulation method based on FGPA according to claim 1, wherein Before obtaining the noise convolution kernel signal in the FPGA memory based on the random addressing code generated based on the radio frequency signal, further includes: Determining the random addressing code based on the value of the target signal point in the radio frequency signal.

7. The method for high-speed low-latency real-time signal convolutional modulation based on FGPA according to claim 1, wherein Before obtaining the noise convolution kernel signal in the FPGA memory based on the random addressing code generated based on the radio frequency signal, further includes: Generating noise signals of various distribution types through simulation software; Converting the noise signals into binary digital signals and storing them in the FPGA memory in the form of noise convolution kernels.

8. A high-speed and low-latency real-time signal convolutional modulation device based on FGPA, characterized in that, Including: An obtaining unit, configured to obtain a noise convolution kernel signal in an FPGA memory based on a random addressing code generated based on a radio frequency signal; The FPGA memory is used to store convolution noise signals of various distribution types; The preprocessing unit is configured to cyclically shift the noise convolution kernel signal in a pipelined manner to obtain a convolution noise convolution kernel signal to be convolved, and copy the radio frequency signal to obtain a radio frequency signal to be convolved; The convolution modulation unit is configured to, in a pipelined manner, parallelly read signal points in the convolution noise convolution kernel signal to be convolved and the radio frequency signal to be convolved for multiplication calculation, and accumulate the multiplication calculation results to obtain a convolution modulation result.

9. An electronic device, characterized in that, It includes a memory and a processor, wherein, The memory is used to store programs; The processor is coupled to the memory and is configured to execute the program stored in the memory to implement the steps in the FGPA-based high-speed low-latency real-time signal convolution modulation method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, It is used to store computer-readable programs or instructions, and when the programs or instructions are executed by a processor, the steps in the FGPA-based high-speed low-latency real-time signal convolution modulation method according to any one of claims 1 to 7 can be implemented.

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