Multi-interface software and hardware dual-definition precision fault injection device based on electrical layer signals

Abstract

The invention discloses a multi-interface software and hardware dual-definition precise fault injection device based on electrical layer signals. The device comprises an MCU / CPU system, a hardware coprocessor module, a high-speed ASIC FIFO sending module, a high-speed DAC module, a burr injection module, an external interrupt high-speed ASIC hardware trigger module, a power-down burr driving module and a peripheral communication module. The MCU / CPU module is electrically connected with the hardware coprocessor module, the high-speed ASIC FIFO sending module, the external interrupt ASIC hardware triggering module, the burr injection module, the power-down burr driving module and the peripheral communication module. The hardware coprocessor module is electrically connected with the high-speed ASIC FIFO sending module and the high-speed DAC module, the high-speed DAC module is electrically connected with the burr injection module, and the high-speed ASIC FIFO sending module is electrically connected with the external interrupt high-speed ASIC hardware trigger module. The technical problems that an existing fault injection hardware device is complex in structure and cannot adapt to diversified application scenes are solved.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a precise fault injection device based on electrical layer signal multi-interface software and hardware dual definition. Background Art

[0002] The destructive power of fault injection technology on the cracking and penetration of core components / equipment such as hardware devices, computing processing chips, interface communication devices, and security detection and evaluation cannot be underestimated. Different from the traditional network security concept, this technology goes deep into the bottom layer of the network and directly reaches the hardware circuits and internal structures of chips / components of the tested objects. It sends highly adjustable, controllable and configurable diversified fault injection signals at a specific time and location, including single-mode / differential-mode / common-mode voltage glitches, clock glitches, power-off glitches, communication interface protocol glitches, etc. This fault injection technology can not only be used in application fields such as penetration testing, security detection and evaluation of hardware security, chip security, and firmware security, but is also very practical and effective in testing and evaluating the reliability, availability, conventional technical indicators, communication vulnerability, and error correction of traditional hardware / chips / key components.

[0003] At present, traditional fault injection technology is single and has weak performance. Fault injection signals cannot achieve comprehensive balance in terms of diversity, automation, high quality, high precision, high performance, multiple trigger sources, ultra-high speed, and high user customization. In particular, they cannot adapt to the application scenarios of diversified hardware / chip interface devices, high-speed communication protocols, and hardware circuit security penetration / traditional testing. This greatly limits the breadth and depth of its application scenarios in the fields of hardware / chip security and conventional testing, and also greatly weakens the destructive power, lethality, and influence of fault injection, an advanced penetration technology. Therefore, it is urgent to propose a precision fault injection device based on electrical layer signal multi-interface software and hardware dual definition to solve the technical problems of the complex structure of existing fault injection hardware devices and their inability to adapt to diversified application scenarios. Summary of the invention

[0004] The main purpose of the present invention is to propose a precise fault injection device based on electrical layer signal multi-interface software and hardware dual definition, aiming to solve the technical problems of the existing fault injection hardware device with complex structure and inability to adapt to diverse application scenarios.

[0005] To achieve the above object, the present invention provides a precise fault injection device based on dual software and hardware definition of multi-interface electrical layer signals. Among them, the precise fault injection device based on dual software and hardware definition of multi-interface electrical layer signals includes: an MCU / CPU system, a hardware coprocessor module, a high-speed ASIC FIFO transmission module, a high-speed DAC module, a glitch injection module, an external interrupt high-speed ASIC hardware trigger module, a power-down glitch drive module, and a peripheral communication module; the MCU / CPU module is electrically connected to the hardware coprocessor module, the high-speed ASIC FIFO transmission module, the external interrupt ASIC hardware trigger module, the glitch injection module, the power-down glitch drive module, and the peripheral communication module respectively; the hardware coprocessor module is electrically connected to the high-speed ASIC FIFO transmission module and the high-speed DAC module respectively, the high-speed DAC module is electrically connected to the glitch injection module, and the high-speed ASIC FIFO transmission module is electrically connected to the external interrupt high-speed ASIC hardware trigger module.

[0006] One of the preferred solutions, the glitch injection module includes a CH1&CH2 single-mode / common-mode / differential-mode synchronous high-voltage glitch injection module, a CLKFI clock glitch injection module, a DCFI differential glitch injection module, and an HDCFI high-voltage glitch injection module; the CH1&CH2 single-mode / common-mode / differential-mode synchronous high-voltage glitch injection module is electrically connected to the high-speed DAC module, and the CLKFI clock glitch injection module, the DCFI differential glitch injection module, and the HDCFI high-voltage glitch injection module are all electrically connected to the MCU / CPU system.

[0007] One of the preferred solutions, the CH1&CH2 single-mode / common-mode / differential-mode synchronous high-voltage glitch injection module includes a CH1 single-mode / common-mode / differential-mode synchronous high-voltage glitch injection circuit and a CH2 single-mode / common-mode / differential-mode synchronous high-voltage glitch injection circuit;

[0008] The CH1 single-mode / common-mode / differential-mode synchronous high-voltage glitch injection circuit includes a CH1 impedance conversion circuit, a first differential high-speed amplifier circuit, a first impedance matching circuit, a first high-speed high-voltage amplifier circuit, and a second impedance matching circuit connected in sequence; the CH1 impedance conversion circuit is connected to the high-speed DAC module;

[0009] The CH2 single-mode / common-mode / differential-mode synchronous high-voltage glitch injection circuit includes a CH2 impedance conversion circuit, a second differential high-speed amplifier circuit, a third impedance matching circuit, a second high-speed high-voltage amplifier circuit, and a fourth impedance matching circuit connected in sequence; the CH2 impedance conversion circuit is connected to the high-speed DAC module.

[0010] One of the preferred solutions, the HDCFI high-voltage glitch injection module includes an HDCFI differential glitch conditioning module, a third differential amplifier circuit, a fifth impedance matching circuit, a third high-speed high-voltage amplifier circuit, and a sixth impedance matching circuit connected in sequence. The HDCFI differential glitch conditioning module is connected to the MCU / CPU system.

[0011] One of the preferred solutions, the CLKFI clock glitch injection module includes a CLKFI clock channel control module and a CLKFI clock glitch aggregation and conditioning module connected in sequence; the MCU / CPU system is respectively connected to the CLKFI clock channel control module and the CLKFI clock glitch aggregation and conditioning module.

[0012] One of the preferred solutions, the external interrupt high-speed ASIC hardware trigger module includes an asynchronous control D flip-flop, a pulse counter & comparator ASIC hardware module, and a rising / falling edge trigger control module connected in sequence; the MCU / CPU system is respectively connected to the asynchronous control D flip-flop, the pulse counter & comparator ASIC hardware module, and the rising / falling edge trigger control module. The asynchronous control D flip-flop is connected to the high-speed ASIC FIFO transmission module.

[0013] One of the preferred solutions, the peripheral communication module includes an RS232 interface circuit, an RS485 interface circuit, a CAN / CANFD interface circuit, a LIN interface circuit, an RJ45 Ethernet circuit, a 1553B interface driver circuit, an I2C interface circuit, an SPI2 interface circuit, and a UART interface circuit.

[0014] One of the preferred solutions, the power-down glitch drive module includes a resistor RC1, a resistor RC2, a diode D1, a diode D2, a MOS transistor Q1, and a resistor RC3; one end of the resistor RC1 is respectively connected to the MCU / CPU system and the resistor RC2. The other end of the resistor RC2 is respectively connected to the anode of the diode D1, the cathode of the diode D2, and the gate of the MOS transistor Q1. The drain of the MOS transistor Q is connected to the resistor RC3. The other end of the resistor RC3 is connected to the socket and the external device. The other end of the resistor RC1, the anode of the diode D2, and the source of the MOS transistor Q1 are grounded. The cathode of the diode D1 is connected to the power supply terminal.

[0015] One of the preferred solutions, the multi-interface software and hardware dual-defined precision fault injection device based on electrical layer signals further includes a DAC1 amplification drive module and a DAC2 amplification drive module; both the DAC1 amplification drive module and the DAC2 amplification drive module are respectively connected to the hardware coprocessor module and the glitch injection module.

[0016] One of the preferred solutions is that the hardware coprocessor module includes a first hardware clock generator, a second hardware clock generator, a DAC1 module, a DAC2 module, and a DAC3 module; the first hardware clock generator is respectively connected to the high-speed DAC module and the high-speed ASIC FIFO transmission module, the second hardware clock generator and the glitch injection module, the DAC1 module is connected to the DAC1 amplification and drive module, and the DAC2 module is connected to the DAC2 amplification and drive module.

[0017] In the above technical solution of the present invention, the precision fault injection device with dual software and hardware definitions for multi-interfaces of electrical layer signals includes: an MCU / CPU system, a hardware coprocessor module, a high-speed ASIC FIFO transmission module, a high-speed DAC module, a glitch injection module, an external interrupt high-speed ASIC hardware trigger module, a power-down glitch drive module, and a peripheral communication module; the MCU / CPU module is electrically connected to the hardware coprocessor module, the high-speed ASIC FIFO transmission module, the external interrupt ASIC hardware trigger module, the glitch injection module, the power-down glitch drive module, and the peripheral communication module respectively; the hardware coprocessor module is electrically connected to the high-speed ASIC FIFO transmission module and the high-speed DAC module respectively, the high-speed DAC module is electrically connected to the glitch injection module, and the high-speed ASIC FIFO transmission module is electrically connected to the external interrupt high-speed ASIC hardware trigger module. The present invention solves the technical problems of the complex structure of the existing fault injection hardware device and the inability to adapt to diverse application scenarios.

[0018] In the present invention, through the CH1&CH2 single-mode / common-mode / differential-mode synchronous high-voltage glitch injection module, the CLKFI clock glitch injection module, the DCFI differential glitch injection module, and the HDCFI high-voltage glitch injection module, it is possible to meet the extremely narrow glitch fault injection as low as 3 ns, realize the precision fault injection of different glitch voltages and glitch widths, support different trigger source types such as ultra-high-speed external interrupt trigger, manual trigger, hysteresis trigger, and diverse protocol command word trigger, and achieve the precision fault injection of specific trigger conditions in different scenarios.

[0019] In the present invention, through the peripheral communication module, it is possible to realize the communication of external interface protocols such as 1553B bus, CAN / CANFD bus, LIN bus, RS485 bus, RS422 bus, RS232, UART, I2C, SPI, and Ethernet bus, support the matrix routing gateway forwarding, transparently forward data between different interface protocols, realize the capture and analysis of data protocols, and at the same time realize the precision fault injection triggered by command words of different interface protocols.

[0020] In the present invention, the power-down glitch driving module can perform low-voltage power-down injection with an extremely low falling edge on the hardware electronic device, chip or other device to be measured. The pulse width of the power-down injection glitch can be precisely configured by instructions sent remotely. Relying on the MCU / CPU system, it can meet the power-down glitch fault injection as low as the ns level, support different trigger source types such as ultra-high-speed external interrupt trigger, manual trigger, hysteresis trigger, and diverse protocol command word triggers, and achieve precise fault injection of specific trigger conditions in different scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following-described drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on the structures shown in these drawings.

[0022] Figure 1 Schematic diagram of the precise fault injection device based on the dual definition of software and hardware for multi-interface electrical layer signals in the embodiment of the present invention;

[0023] Figure 2 Schematic diagram of the DAC1 amplification driving module and the DAC2 amplification driving module in the embodiment of the present invention;

[0024] Figure 3 Schematic diagram of the DAC buffer driving module in the embodiment of the present invention;

[0025] Figure 4 Schematic diagram of the external interrupt high-speed ASIC hardware trigger module in the embodiment of the present invention;

[0026] Figure 5 Schematic diagram of the CLKFI clock glitch injection module in the embodiment of the present invention;

[0027] Figure 6 Schematic diagram of the DCFI differential glitch injection module in the embodiment of the present invention;

[0028] Figure 7 Schematic diagram of the HDCFI high-voltage glitch injection module in the embodiment of the present invention;

[0029] Figure 8 Schematic diagram of the CH1 single-mode / common-mode / differential-mode synchronous high-voltage glitch injection circuit in the embodiment of the present invention;

[0030] Figure 9 Schematic diagram of the CH2 single-mode / common-mode / differential-mode synchronous high-voltage glitch injection circuit in the embodiment of the present invention;

[0031] Figure 10Schematic diagram of the power-down glitch driving module according to an embodiment of the present invention;

[0032] Figure 11 Schematic diagram of the system power management module according to an embodiment of the present invention.

[0033] The implementation, functional features and advantages of the present invention will be further described in conjunction with the embodiments and with reference to the accompanying drawings. Specific embodiments

[0034] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0035] Moreover, the technical solutions between the various embodiments of the present invention can be combined with each other, but it must be based on the fact that those of ordinary skill in the art can implement them. When the combination of technical solutions appears to be contradictory or unable to be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope required by the present invention.

[0036] See Figures 1 - 10 , according to one aspect of the present invention, the present invention provides a precision fault injection device based on dual software and hardware definitions of multiple interfaces of electrical layer signals. Among them, the precision fault injection device based on dual software and hardware definitions of multiple interfaces of electrical layer signals includes: an MCU / CPU system, a hardware coprocessor module, a high-speed ASIC FIFO sending module, a high-speed DAC module, a glitch injection module, an external interrupt high-speed ASIC hardware trigger module, a power-down glitch driving module, and a peripheral communication module; the MCU / CPU module is electrically connected to the hardware coprocessor module, the high-speed ASIC FIFO sending module, the external interrupt ASIC hardware trigger module, the glitch injection module, the power-down glitch driving module, and the peripheral communication module respectively; the hardware coprocessor module is electrically connected to the high-speed ASIC FIFO sending module and the high-speed DAC module respectively, the high-speed DAC module is electrically connected to the glitch injection module, and the high-speed ASIC FIFO sending module is electrically connected to the external interrupt high-speed ASIC hardware trigger module.

[0037] Specifically, in this embodiment, the MCU / CPU system is responsible for communicating with the host computer software, receiving and processing relevant command messages, and sending relevant data and other information; it is responsible for communicating with the hardware coprocessor module, using the SPI interface for communication, and controlling the 5 sub-modules inside the first hardware clock generator, the second hardware clock generator, the DAC1 module, the DAC2 module, and the DAC3 module; it is responsible for driving the high-speed ASIC FIFO sending module and synchronously monitoring the status feedback information of this module, and providing diversified communication protocols, glitch amplitudes, glitch pulse widths, glitch phases, adjustable frequencies, and configurable two independent or linked fault injection signals to the CH1&CH2 single-mode / common-mode / differential-mode synchronous high-voltage glitch injection module; it is responsible for driving the high-speed DAC module and providing diversified communication protocols, glitch amplitudes, glitch pulse widths, glitch phases, adjustable frequencies, and configurable two independent or linked fault injection signals to the CH1&CH2 single-mode / common-mode / differential-mode synchronous high-voltage glitch injection module; it is responsible for controlling the external interrupt high-speed ASIC hardware trigger module and synchronously and real-time detecting the external trigger interrupt signal. Combined with the host computer software control, it can achieve 32-bit pulse counting and comparison triggering based on the ASIC pure hardware circuit, accurately count and compare the edges of the external trigger signal, and automatically output a valid trigger signal in hardware when a specific count value is reached, meeting the application scenarios of precise external interrupt trigger fault injection. At the same time, it can respectively implement the trigger configuration for the external interrupt rising edge or the external interrupt falling edge. Based on the design of the automated high-speed hardware external interrupt trigger system, it realizes the automated high-speed hardware synchronization drive of the high-speed ASIC FIFO sending module and the high-speed DAC module, meets the ultra-high-speed ns-level external interrupt response, and executes various algorithms of specific software-defined precision fault injection with high speed and accuracy. It synchronously drives the CH1&CH2 single-mode / common-mode / differential-mode synchronous high-voltage glitch injection module to provide diversified communication protocols, glitch amplitudes, glitch pulse widths, glitch phases, adjustable frequencies, and configurable two independent or linked fault injection signals; it is responsible for driving and controlling the CLKFI clock glitch injection module, which is mainly used for clock glitch injection or DC-coupled voltage glitch injection (external blocking capacitors can be used to achieve AC-coupled voltage glitch injection), and can synchronously enable the output of a specific clock frequency (the clock frequency output can be individually prohibited / activated). It is one of the core modules for extremely narrow glitch fault injection. Relying on the MCU / CPU, an efficient task scheduling software mechanism, and underlying instruction optimization design, it can meet the extremely narrow glitch fault injection as low as 3 ns. By linking the control of the DAC1 module, it can achieve precise fault injection with different glitch voltages and glitch widths, support different trigger source types such as ultra-high-speed external interrupt trigger, manual trigger, hysteresis trigger, and diversified protocol command word trigger, and realize precise fault injection under specific trigger conditions in different scenarios;Responsible for driving and controlling the DCFI differential glitch injection module, which is mainly used for DC-coupled differential / single-ended glitch injection (external DC-blocking capacitors can be used to achieve AC-coupled differential / single-ended glitch injection) or voltage glitch injection. It is one of the core modules for ultra-narrow glitch fault injection. Relying on the MCU / CPU, an efficient task scheduling software mechanism, and underlying instruction optimization design, it can meet ultra-narrow glitch fault injection as low as 3 ns. Linking with the control of the DAC1 module, it can achieve precise fault injection with different glitch voltages and glitch widths, support different trigger source types such as ultra-high-speed external interrupt trigger, manual trigger, hysteresis trigger, and diverse protocol command word trigger, and realize precise fault injection under specific trigger conditions in different scenarios; responsible for driving and controlling the HDCFI high-voltage glitch injection module, which is mainly used for DC single-ended high-voltage glitch injection (external DC-blocking capacitors can be used to achieve AC differential / single-ended glitch injection). It is one of the core modules for ultra-narrow high-voltage glitch fault injection. Relying on the MCU / CPU, an efficient task scheduling software mechanism, and underlying instruction optimization design, it can meet glitch fault injection as low as the ns level. Linking with the control of the DAC2 module, it can achieve precise fault injection with different glitch voltages and glitch widths, support different trigger source types such as ultra-high-speed external interrupt trigger, manual trigger, hysteresis trigger, and diverse protocol command word trigger, and realize precise fault injection under specific trigger conditions in different scenarios; responsible for controlling the power-down glitch drive module, which can achieve low-voltage power-down injection with an extremely low falling edge for the hardware electronic devices, chips, or other devices under test. The pulse width of the power-down injection glitch can be precisely configured through instructions sent remotely. Relying on the MCU / CPU, an efficient task scheduling software mechanism, and underlying instruction optimization design, it can meet power-down glitch fault injection as low as the ns level, support different trigger source types such as ultra-high-speed external interrupt trigger, manual trigger, hysteresis trigger, and diverse protocol command word trigger, and realize precise fault injection under specific trigger conditions in different scenarios; responsible for driving the peripheral communication module to achieve external interface protocol communication such as 1553B bus, CAN / CANFD bus, LIN bus, RS485 bus, RS422 bus, RS232, UART, I2C, SPI, and Ethernet bus, support matrix routing gateway forwarding, can transparently forward data between different interface protocols, realize the capture and analysis of data protocols, and at the same time can achieve precise fault injection triggered by command words based on different interface protocols.;

[0038] Specifically, in this embodiment, the hardware coprocessor module includes a first hardware clock generator, a second hardware clock generator, a DAC1 module, a DAC2 module, and a DAC3 module; the first hardware clock generator is respectively connected to the high-speed DAC module and the high-speed ASIC FIFO transmission module, the second hardware clock generator and the glitch injection module, the DAC1 module is connected to the DAC1 amplification driving module, and the DAC2 module is connected to the DAC2 amplification driving module; the first hardware clock generator outputs a clock CLKOUT_DAC signal with a specific frequency according to the configuration instructions of the MCU / CPU system, and this signal drives both the high-speed DAC module and the high-speed ASIC FIFO transmission module at the same time; the second hardware clock generation module outputs a clock CLKOUT_HS signal with a specific frequency according to the configuration instructions of the MCU / CPU system, and this signal drives the CLKFI clock glitch injection module of the glitch injection module; the DAC1 module outputs a specific DAC voltage signal VDAC1 according to the configuration instructions of the MCU / CPU system, and this signal is output to the DAC1 amplification driving module to ensure the subsequent load working voltage and driving ability; the DAC2 module outputs a specific DAC voltage signal VDAC2 according to the configuration instructions of the MCU / CPU system, and this signal is output to the DAC2 amplification driving module to ensure the subsequent load working voltage and driving ability; the DAC3 module outputs a specific DAC voltage signal VDAC3 according to the configuration instructions of the MCU / CPU system, and this signal is output to the DAC buffer driving module, and the external auxiliary DAC signal EXTDAC is output through the DAC buffer driving module.

[0039] Specifically, in this embodiment, the precision fault injection device with dual software and hardware definitions for multi-interface based on electrical layer signals further includes a DAC1 amplification and driving module and a DAC2 amplification and driving module; both the DAC1 amplification and driving module and the DAC2 amplification and driving module are respectively connected to the hardware coprocessor module and the glitch injection module; the DAC1 amplification and driving module and the DAC2 amplification and driving module are used to amplify the two-way DAC signals VDAC1 and VDAC2 output by the hardware coprocessor module to meet the specific working voltage requirements of related sub-modules; the DAC1 amplification and driving module includes an amplifier U1, a resistor RD1, and a resistor RD2. The negative input terminal of the amplifier U1 is respectively connected to the resistor RD1 and the resistor RD2. The positive input terminal of the amplifier U1 is connected to the DAC1 module. The output terminal of the amplifier U1 is respectively connected to the glitch injection module and the other end of the resistor RD2. The other end of the resistor RD1 is grounded; the DAC2 amplification and driving module includes an amplifier U2, a resistor RD3, and a resistor RD4. The negative input terminal of the amplifier U2 is respectively connected to the resistor RD3 and the resistor RD4. The positive input terminal of the amplifier U2 is connected to the DAC2 module. The output terminal of the amplifier U2 is respectively connected to the other end of the resistor RD4 and the glitch injection module. The other end of the resistor RD3 is grounded.

[0040] Specifically, in this embodiment, the precision fault injection device with dual software and hardware definitions for multi-interface based on electrical layer signals further includes a DAC buffer driving module; the DAC buffer driving module is connected to the DAC3 module of the hardware coprocessor module. The DAC buffer driving module uses an amplifier U3. The DAC buffer driving module is used to buffer and isolate the VDAC3 voltage signal output by the DAC3 module inside the hardware coprocessor module to output an external auxiliary DAC signal EXTDAC for external auxiliary use, mainly realizing signal isolation and buffering, effectively protecting the working environments of the front and rear stage sub-modules, and reducing interference and noise.

[0041] Specifically, in this embodiment, the high-speed ASIC FIFO transmission module is designed based on a high-speed dedicated ASIC integrated chip. The high-speed ASIC FIFO transmission module mainly loads a specific precise fault injection algorithm into the module for processing and execution by the MCU / CPU system, providing a diversified communication protocol, glitch amplitude, glitch pulse width, glitch phase, adjustable frequency, and configurable two-way independent or linked fault injection signals for the CH1&CH2 single-mode / common-mode / differential-mode synchronous high-voltage glitch injection module; WRST, WEN, and WCLK are the write data control signals of the high-speed ASIC FIFO transmission module, driven by the MCU / CPU system. The WRST signal is the write reset control signal, WEN is the write enable control signal, and WCLK is the write clock control signal. DataIn[0:13] is the write data signal, driven by the MCU / CPU system. DataIn[0:11] is the write data signal driven by the high-speed DAC module, and DataIn

[12] and DataIn

[13] are the control and status flag indication signals respectively. The REN signal is driven by the MCU / CPU system and is the read enable signal of the high-speed ASIC FIFO transmission module. The RRST signal is driven by the external interrupt high-speed ASIC hardware trigger module and is the read reset control signal of the high-speed ASIC FIFO transmission module. The CLKOUT_DAC signal is the read clock signal of the high-speed ASIC FIFO transmission module, driven by the first hardware clock generator sub-module of the hardware coprocessor module. DataOut[0:12] is a 12-bit read data signal used to drive the high-speed DAC module, and DataOut

[13] is the read status flag indication signal, synchronously output to the MCU / CPU system for detection.

[0042] Specifically, in this embodiment, the high-speed DAC module is designed based on a dual-channel 12-bit high-speed DAC synchronous chip architecture, which can also be extended to 14 bits. The high-speed DAC module is jointly controlled by four parts: the MCU / CPU system, the hardware coprocessor module, the high-speed ASIC FIFO transmission module, and the external interrupt high-speed ASIC hardware trigger module. DataOut[0:12] is the DAC data input signal of this module, jointly driven by the high-speed ASIC FIFO transmission module. CLKOUT_DAC is the clock drive signal of the high-speed DAC module, driven by the first hardware clock generator sub-module of the hardware coprocessor module. IA1 / IA2 and IB1 / IB2 are two groups of current differential signals output synchronously by the DAC of the high-speed DAC module, corresponding to the CH1 and CH2 channel glitch injection signals of the CH1&CH2 single-mode / common-mode / differential-mode synchronous high-voltage glitch injection module, and are respectively output to the CH1 impedance conversion circuit and the CH2 impedance conversion circuit sub-module of the CH1&CH2 single-mode / common-mode / differential-mode synchronous high-voltage glitch injection module.

[0043] Specifically, in this embodiment, the external interrupt high-speed ASIC hardware trigger module is designed based on a high-speed dedicated hardware architecture. It is the core key module for ultra-high-speed ns-level external interrupt single-trigger response and external interrupt count trigger. It can implement 32-bit pulse counting and comparison triggering based on ASIC pure hardware circuits, accurately count and compare the edges of external trigger signals, and automatically output a valid trigger signal in hardware when a specific count value is reached, meeting the application scenarios of precise external interrupt trigger fault injection. At the same time, it can separately implement the trigger configuration for the rising edge or falling edge of the external interrupt. Based on the design of an automated high-speed hardware external interrupt trigger system, it realizes the automated high-speed hardware synchronization drive for the high-speed ASIC FIFO transmission module and the high-speed DAC module, meets the ultra-high-speed ns-level external interrupt response, and executes various algorithms of specific software-defined precision fault injection with high speed and precision. It synchronously drives the CH1&CH2 single-mode / common-mode / differential-mode synchronous high-voltage glitch injection module to provide two independent or linked fault injection signals with diverse communication protocols, glitch amplitudes, glitch pulse widths, glitch phases, adjustable frequencies, and configurable parameters, which can not only meet diverse external interrupt trigger application scenarios but also ensure the underlying core technical conditions for ultra-high-speed precision fault injection. The external interrupt high-speed ASIC hardware trigger module includes an asynchronous control D flip-flop, a pulse counter & comparator ASIC hardware module, and a rising / falling edge trigger control module connected in sequence. The MCU / CPU system is respectively connected to the asynchronous control D flip-flop, the pulse counter & comparator ASIC hardware module, and the rising / falling edge trigger control module. The asynchronous control D flip-flop is connected to the high-speed ASIC FIFO transmission module. The pulse counter & comparator ASIC hardware module is a 32-bit ultra-high-speed pulse counter & comparator ASIC hardware module.The external trigger signal of ExtTrgIn is triggered and controlled by the rising / falling edge of the external signal input to the external interrupt high-speed ASIC hardware trigger module. The rising / falling edge trigger control module is internally composed of two channels of ultra-high-speed analog switches and one ultra-high-speed logic inverter. The TgrIn trigger signal output by this sub-module is output to the pulse counter & comparator ASIC hardware module for counting and comparison, realizing the counting and comparison of the number of specific external trigger signals, meeting the precise trigger fault injection of external interrupt counting. The interrupt trigger counting comparison value is set by the MCU / CPU system according to the host computer software through the UART serial port for the pulse counter & comparator ASIC hardware module. The setting range of the external interrupt trigger signal counting & comparison value is from 1 to 232 - 1 and can be set arbitrarily, meeting the large-capacity count value trigger, and can adapt to different external interrupt counting trigger precise fault injection scenarios. The TrgIN2 signal output by the pulse counter & comparator ASIC hardware module is given to the asynchronous control D flip-flop, which is the final effective external interrupt trigger signal for this module. At the same time, it will also be output to the MCU / CPU system for synchronous detection. The RRST signal output by the asynchronous control D flip-flop is output to the high-speed ASIC FIFO sending module as the read reset control signal for the high-speed ASIC FIFO sending module. / RD and / SD are controlled by the MCU / CPU system and are used to asynchronously control the state output of the RRST signal to achieve cooperative control.;

[0044] Specifically, in this embodiment, the glitch injection module includes a CH1&CH2 single-mode / common-mode / differential-mode synchronous high-voltage glitch injection module, a CLKFI clock glitch injection module, a DCFI differential glitch injection module, and an HDCFI high-voltage glitch injection module; the CH1&CH2 single-mode / common-mode / differential-mode synchronous high-voltage glitch injection module is electrically connected to the high-speed DAC module, and the CLKFI clock glitch injection module, the DCFI differential glitch injection module, and the HDCFI high-voltage glitch injection module are all electrically connected to the MCU / CPU system.

[0045] Specifically, in this embodiment, the CH1&CH2 single-mode / common-mode / differential-mode synchronous high-voltage glitch injection module includes a CH1 single-mode / common-mode / differential-mode synchronous high-voltage glitch injection circuit and a CH2 single-mode / common-mode / differential-mode synchronous high-voltage glitch injection circuit; the CH1 single-mode / common-mode / differential-mode synchronous high-voltage glitch injection circuit includes a CH1 impedance conversion circuit, a first differential high-speed amplifier circuit, a first impedance matching circuit, a first high-speed high-voltage amplifier circuit, and a second impedance matching circuit connected in sequence; the CH1 impedance conversion circuit is connected to the high-speed DAC module; the CH2 single-mode / common-mode / differential-mode synchronous high-voltage glitch injection circuit includes a CH2 impedance conversion circuit, a second differential high-speed amplifier circuit, a third impedance matching circuit, a second high-speed high-voltage amplifier circuit, and a fourth impedance matching circuit connected in sequence; the CH2 impedance conversion circuit is connected to the high-speed DAC module; the CH1&CH2 single-mode / common-mode / differential-mode synchronous high-voltage glitch injection module is the most direct execution module for single-mode / common-mode / differential-mode synchronous high-voltage glitch injection, and is the key part of extremely narrow high-voltage glitches and high synchronization performance. It can meet single-mode / common-mode / differential-mode synchronous high-voltage glitch fault injection as low as the ns level, and can achieve precise fault injection with different glitch voltages and glitch widths. It supports different trigger source types such as ultra-high-speed external interrupt trigger, manual trigger, hysteresis trigger, and diverse protocol command word trigger, and realizes precise fault injection under specific trigger conditions in different scenarios. The two groups of current differential signals IA1 / IA2 and IB1 / IB2 are the input of the primary differential current signals for the two channels CH1 and CH2. By setting the output characteristics, precise glitch fault injection for dynamic protocol transmission can be synchronously achieved. The two groups of current differential signal sources are respectively converted into two groups of corresponding differential voltage signals VA1 / VA2 and VB1 / VB2 after passing through the CH1 impedance conversion circuit and the CH2 impedance conversion circuit. Each group of differential voltage signals is processed by two independent differential high-speed amplifier circuits to differentially amplify the glitch voltage amplitude, and are respectively output as two signals VAS and VBS. After being processed by two independent impedance matching circuits, they are synchronously output to two independent high-speed high-voltage amplifier circuits, and the signals VH1 and VH2 are respectively output. After passing through two independent impedance matching circuits, the two specific glitches corresponding to the CH1 and CH2 channels are finally output, simultaneously meeting the characteristics of diverse fault injection scenarios, precise high-speed fault injection, ultra-high speed, high performance, high quality, high flexibility, and large load drive.

[0046] The CH1 single-mode / common-mode / differential-mode synchronous high-voltage glitch injection circuit includes a CH1 impedance conversion circuit, a first differential high-speed amplifier circuit, a first impedance matching circuit, a first high-speed high-voltage amplifier circuit, and a second impedance matching circuit connected in sequence;

[0047] Specifically, in this embodiment, the CH1 impedance conversion circuit includes resistor RA1 and resistor RA2. One end of resistor RA1 and resistor RA2 is respectively connected to the high-speed DAC module and the first differential high-speed amplifier circuit, and the other end of resistor RA1 and resistor RA2 is grounded. The first differential high-speed amplifier circuit includes amplifier U7, amplifier U8, resistor RA3, resistor RA7, resistor RA4, and resistor RA6. The negative input terminal of amplifier U7 is respectively connected to resistor RA3, resistor RA7, and resistor RA4. The other end of resistor RA3 is connected to the CH1 impedance conversion circuit. The other end of resistor RA7 is respectively connected to the output terminal of amplifier U7 and the first impedance matching circuit. The other end of resistor RA4 is respectively connected to RA5, the output terminal of amplifier U8, and the CH1 impedance conversion circuit. The other end of resistor RA5 is respectively connected to resistor RA6 and the negative input terminal of amplifier U8. The other end of resistor RA6 is connected to the output terminal of amplifier U8. The first impedance matching circuit includes resistor RA8. One end of resistor RA8 is respectively connected to the first differential high-speed amplifier circuit and the first high-speed high-voltage amplifier circuit, and the other end of resistor RA8 is grounded. The high-speed high-voltage amplifier circuit includes amplifier U9, resistor RA9, and resistor RA10. The positive input terminal of amplifier U9 is connected to the first impedance matching circuit. The negative input terminal of amplifier U9 is respectively connected to resistor RA9 and resistor RA10. The other end of resistor RA9 is grounded. The other end of resistor RA10 is respectively connected to the output terminal of amplifier U9 and the second impedance matching circuit. The second impedance matching circuit includes resistor RA11 and resistor RA12. The other end of resistor RA11 is grounded. The other end of RA12 is connected to an external device. The structure of the CH2 impedance conversion circuit is the same as that of the CH1 impedance conversion circuit, and will not be elaborated in this invention.

[0048] Specifically, in the present embodiment, the HDCFI high-voltage glitch injection module comprises a HDCFI differential glitch conditioning module, a third differential amplifier circuit, a fifth impedance matching circuit, a third high-speed high-voltage amplifier circuit and a sixth impedance matching circuit connected in sequence, and the HDCFI differential glitch conditioning module is connected to the MCU / CPU system; the HDCFI high-voltage glitch injection module is used for DC single-ended high-voltage glitch injection (an external DC blocking capacitor can realize AC differential / single-ended glitch injection), which is an extremely narrow high-voltage glitch fault injection core module, which can meet the requirements of high-voltage glitch fault injection as low as ns level, and the linkage control of the DAC2 module can realize precise fault injection of different glitch voltages and glitch widths, and supports ultra-high-voltage glitch injection. Different trigger source types such as high-speed external interrupt trigger, manual trigger, hysteresis trigger, and diversified protocol command word trigger can realize precise fault injection under specific trigger conditions in different scenarios. HDCFI+_IN and HDCFI-_IN are the primary output signals of HDCFI differential glitch of MCU / CPU system, which are input to the HDCFI differential glitch conditioning module inside the HDCFI high-voltage glitch injection module for conditioning. Its internal structure consists of two-channel independent ultra-high-speed logic or gate circuits. VD2 is the power supply voltage of the HDCFI differential glitch conditioning module. The signal is driven by the DAC2 amplification drive module to realize customized control of the HDCFI high-voltage glitch voltage amplitude to meet different glitch depths. According to the application scenario requirements of fault injection, after internal conditioning and drive amplification, the output HDCFI+_OUT and HDCFI-_OUT are output as differential input signal sources to the third differential amplifier circuit to amplify the differential signal and then output the VCS signal to the third high-speed high-voltage amplifier circuit module for further amplification, and output the VH3 signal, and output the final HDCFI high-voltage burr through the fifth impedance matching circuit module; the third differential amplifier circuit includes an amplifier U4, an amplifier U5, a resistor R1, a resistor R2, a resistor R3, a resistor R4, and a resistor R5; the negative input terminal of the amplifier U4 is respectively connected to the resistor R1, the resistor R2 and the resistor R3, and the other end of the resistor R1 is connected to the HDCF I differential burr conditioning module, the other end of the resistor R2 is respectively connected to the output end of the amplifier U4 and the fifth impedance matching circuit, the other end of the resistor R3 is respectively connected to the HDCFI differential burr conditioning module, the resistor R4 and the output end of the amplifier U5, the other end of the resistor R4 is respectively connected to the resistor R5 and the negative input end of the amplifier U5, the other end of the resistor R5 is connected to the output end of the amplifier U5, the positive input end of the amplifier U4 and the positive input end of the amplifier U5 are grounded; the fifth impedance matching circuit includes a resistor R6, one end of the resistor R6 is respectively connected to the third differential amplifier circuit and the third high-speed high-voltage amplifier circuit, and the other end of the resistor R6 is grounded;The third high-speed high-voltage amplification circuit includes an amplifier U6, a resistor R7, and a resistor R8. The negative input terminal of the amplifier U6 is connected to the resistor R7 and the resistor R8 respectively. The other end of the resistor R7 is connected to the output terminal of the amplifier U6 and the sixth impedance matching circuit respectively. The positive input terminal of the amplifier U6 is connected to the fifth impedance matching circuit. The other end of the resistor R8 is grounded. The sixth impedance matching circuit includes a resistor R10 and a resistor R9. One end of the resistor R10 is connected to the resistor R9 and the third high-speed high-voltage amplification circuit respectively. The other end of the resistor R9 is grounded. The other end of the resistor R10 is connected to an external device.

[0049] Specifically, in this embodiment, the CLKFI clock glitch injection module includes a CLKFI clock channel control module and a CLKFI clock glitch aggregation conditioning module connected in sequence; the MCU / CPU system is connected to the CLKFI clock channel control module and the CLKFI clock glitch aggregation conditioning module respectively; the CLKFI clock glitch injection module is mainly used for clock glitch injection and DC coupling voltage glitch injection. An external DC blocking capacitor can realize AC coupling voltage glitch injection, and can synchronously enable a specific clock frequency output. The clock frequency output can be disabled / enabled separately. It is an extremely narrow glitch fault injection core module that can meet an extremely narrow range as low as 3ns. Glitch fault injection, linkage to the drive control of the DAC1 module, can realize precise fault injection of different glitch voltages and glitch widths, support different trigger source types such as ultra-high-speed external interrupt trigger, manual trigger, hysteresis trigger, and diversified protocol command word trigger, to realize precise fault injection of specific trigger conditions in different scenarios. CLKOUT_LS is the low-frequency clock output signal of the MCU / CPU system, and CLKOUT_HS is the high-frequency clock output signal, which is driven by the second hardware clock generator of the hardware coprocessor module. CLKOUT_LS and CLKOUT_HS are synchronously input to the CLKFI of the CLKFI clock glitch injection module. The clock channel control module selects the clock signal channel by the Ctr_CLKCH control signal. The module is composed of 2-channel high-speed analog switches. The Ctr_CLKCH control signal is provided by the MCU / CPU system driver. The CLKOUT signal is the clock signal output by the CLKFI clock channel control module in the CLKFI clock glitch injection module. The CLKOUT signal is controlled to be the CLKOUT_LS clock signal or the CLKOUT_HS clock signal according to the Ctr_CLKCH signal. The CLKOUT signal is output to the CLKFI clock glitch aggregation conditioning module in the CLKFI clock glitch injection module. The FI_IN signal is a clock glitch injection signal, which is driven and controlled by the MCU / CPU system. The CLKFI_IN and CLKOUT signals are synchronously output to the CLKFI clock glitch aggregation conditioning module. The module is composed of ultra-high-speed logic OR gate circuits. The two signals are logically ORed and aggregated and output to further improve its load driving capability as the final CLKFI clock glitch injection channel output. VD1 is the power supply voltage of the CLKFI clock glitch aggregation conditioning module. This signal is driven by the DAC1 amplification drive module to achieve customized control of the CLK clock glitch voltage amplitude to meet the application scenario requirements of fault injection with different glitch depths.

[0050] Specifically, in this embodiment, the DCFI differential glitch injection module is used for DC coupling differential / single-ended glitch injection (external DC blocking capacitors can realize AC coupling differential / single-ended glitch injection) or voltage glitch injection. It is an extremely narrow glitch fault injection core module that can meet the extremely narrow glitch fault injection as low as 3ns. The linkage control of the DAC1 module can realize precise fault injection of different glitch voltages and glitch widths, support ultra-high-speed external interrupt triggering, manual triggering, hysteresis triggering, diversified protocol command word triggering and other different trigger source types, and realize precise fault injection of specific trigger conditions in different scenarios. DCFI+_IN and DCFI-_IN are differential glitch initialization of the MCU / CPU system. The output signal of the first level is input to the internal conditioning of the DCFI differential glitch injection module. The DCFI differential glitch injection module includes a DCFI differential glitch conditioning module. The DCFI differential glitch conditioning module is composed of two-channel independent ultra-high-speed logic OR gate circuits. After internal conditioning and drive amplification, the output DCFI+ and DCFI- are the final DCFI differential voltage glitch injection signals, which can also be used as two independent single-ended voltage glitch injection signals. VD1 is the power supply voltage of the DCFI differential glitch conditioning module. The signal is driven by the DAC1 amplification drive module to achieve customized control of the DC-coupled differential / single-ended glitch voltage amplitude to meet the application scenario requirements of fault injection with different glitch depths.

[0051] Specifically, in this embodiment, the power-off glitch driving module includes a resistor RC1, a resistor RC2, a diode D1, a diode D2, a MOS tube Q1 and a resistor RC3; one end of the resistor RC1 is respectively connected to the MCU / CPU system and the resistor RC2, the other end of the resistor RC2 is respectively connected to the anode of the diode D1, the cathode of the diode D2 and the gate of the MOS tube Q1, the drain of the MOS tube Q is connected to the resistor RC3, the other end of the resistor RC3 is connected to the socket and the external device, the other end of the resistor RC1, the anode of the diode D2 and the source of the MOS tube Q1 are grounded, and the cathode of the diode D1 is connected to the power supply end; the power-off glitch driving module defaults to the drain The extremely open-drain output and low internal node capacitance value can meet the requirements of ns-level power-off glitch fault injection. At the same time, it can also be connected to the external hardware electronic equipment, chip or other devices under test without interference. The extremely low on-resistance can ensure that power-off injection can be effectively achieved even when working with large current and high voltage. This part of the circuit is driven in real time by the MCU / CPU system. The power-off glitch width can be flexibly configured. The drive circuit has positive and negative overvoltage protection circuits. At the same time, the drive side and the power-off fault injection output side can be targeted to choose whether to achieve isolation control through a high-speed optoelectronic isolation circuit or add an overcurrent protection circuit module. CTR_VDROP is the power-off glitch control signal, which is controlled by the MCU / CPU system, and VDROP_OUT is the power-off glitch fault injection signal.

[0052] Specifically, in this embodiment, the peripheral communication module includes an RS232 interface circuit, an RS485 interface circuit, a CAN / CANFD interface circuit, a LIN interface circuit, an RJ45 Ethernet circuit, a 1553B interface driver circuit, an I2C interface circuit, an SPI2 interface circuit, and a UART interface circuit; the peripheral communication module is the external communication core module of this device, mainly realizing external interface protocol communications such as 1553B bus, CAN / CANFD bus, LIN bus, RS485 bus, RS422 bus, RS232, UART, I2C, SPI, and Ethernet bus, supporting matrix routing gateway forwarding, enabling transparent data forwarding between different interface protocols, realizing the capture and analysis of data protocols, and at the same time enabling precise fault injection triggered by command words based on different interface protocols.

[0053] Specifically, in this embodiment, the 1553B interface driver circuit is an external interface led out from the MCU / CPU system, supporting BC controller and RT remote terminal identity communication, with adjustable communication rate, capable of implementing digital trigger fault injection and protocol analysis based on the 1553B communication protocol, and the trigger mode supports flexible configuration of the 1553B communication protocol; the I2C interface circuit is an external interface led out from the MCU / CPU system, supporting master-slave communication mode, with high and adjustable communication rate and configurable slave address, capable of implementing digital trigger fault injection and protocol analysis based on the I2C communication protocol, and the trigger mode supports flexible configuration of the I2C communication protocol; the SPI2 interface circuit is an external interface led out from the MCU / CPU system, supporting master-slave communication mode, with high and adjustable communication rate, capable of implementing digital trigger fault injection and protocol analysis based on the SPI communication protocol, and the trigger mode supports flexible configuration of the SPI communication protocol; the UART interface circuit is an external interface led out from the MCU / CPU system, with high and adjustable communication rate, capable of implementing digital trigger fault injection and protocol analysis based on the UART communication protocol, and the trigger mode supports flexible configuration of the UART communication protocol; the RS232 interface circuit is driven by the MCU / CPU system, with high and adjustable communication rate, capable of implementing digital trigger fault injection and protocol analysis based on the RS232 communication protocol, and the trigger mode supports flexible configuration of the RS232 communication protocol; the RS485 interface circuit is driven by the MCU / CPU system, supporting master-slave communication mode, with high and adjustable communication rate and configurable slave address, capable of implementing digital trigger fault injection and protocol analysis based on the RS485 communication protocol, and the trigger mode supports flexible configuration of the RS485 communication protocol; the CAN / CANFD interface circuit is driven by the MCU / CPU system, supporting CAN and CANFD protocols, with high and adjustable communication rate and configurable communication messages, mainly applied to the Internet of Vehicles, capable of implementing digital trigger fault injection and protocol analysis based on the CAN / CANFD bus communication protocol, and the trigger mode supports flexible configuration of the CAN / CANFD bus communication protocol; the LIN interface circuit is driven by the MCU / CPU system, supporting master-slave communication mode, with adjustable communication rate and configurable address, mainly applied to the Internet of Vehicles, capable of implementing digital trigger fault injection and protocol analysis based on the LIN bus communication protocol, and the trigger mode supports flexible configuration of the LIN bus communication protocol, and the CTR_SM control signal is the LIN interface master-slave control signal to realize the identity control of the master device and the slave device; the RJ45 Ethernet circuit is driven by the MCU / CPU system based on the RMII interface, capable of implementing digital trigger fault injection and protocol analysis based on the RJ45 Ethernet communication protocol, and the trigger mode supports flexible configuration of the RJ45 Ethernet communication protocol;

[0054] Specifically, in this embodiment, the multi-interface software and hardware dual-defined precision fault injection device based on electrical layer signals further includes a system power management module. The system power management module is provided by an external +12V / DC DC power input. After being converted and filtered by the first DC / DC power module, it outputs two DC voltages of positive and negative 15V. After being converted and filtered by the second DC / DC power module, it outputs a +5V DC voltage. The second DC / DC power module outputs five voltages of +3.3V, +3.3V, +2.85V, +2.5V, and -5V respectively by the first power conversion module, the second power conversion module, the third power conversion module, the fourth power conversion module, and the fifth power conversion module. The positive and negative 15V DC voltages mainly supply power to the high-speed high-voltage amplification circuit, and the +12V DC voltage mainly supplies power to the LIN interface circuit of the peripheral communication module; the +5V DC voltage mainly supplies power to the MCU / CPU system, the peripheral communication module, the DAC1 amplification and drive module, the DAC2 amplification and drive module, the CLKFI clock glitch injection module, the DCFI differential glitch injection module, the HDCFI high-voltage glitch injection module, the DAC buffer drive module, the external interrupt high-speed ASIC hardware trigger module, and the CH1&CH2 single-mode / common-mode / differential-mode synchronous high-voltage glitch injection module; the +3.3V DC voltage mainly supplies power to the high-speed DAC module; the +3.3V DC voltage mainly supplies power to the high-speed DAC module and the external interrupt high-speed ASIC hardware trigger module; the +2.85V DC voltage mainly supplies power to the hardware coprocessor module; the -5V DC voltage mainly supplies power to the HDCFI high-voltage glitch injection module and the CH1&CH2 single-mode / common-mode / differential-mode synchronous high-voltage glitch injection module; the system power management module provides a stable and continuous load power supply to each sub-module, and at the same time ensures that each module meets the working requirements of the power-on timing.

[0055] Specifically, in this embodiment, the present invention is different from the traditional network security digital protocol penetration concept. This device relies on the flexible advantages of software-defined fault injection and the underlying architecture of high-performance hardware collaboration, greatly simplifying the complexity and redundancy of the overall hardware design and layout, efficiently integrating the software-defined fault injection algorithm with high-speed and high-performance professional hardware. The fault injection algorithm can be secondarily loaded to run at high speed without relying on the CPU's own environment, greatly improving the ultra-high-speed and ultra-precision fault injection ability, and designing a precision fault injection mechanism of 32-bit ultra-high-speed external interrupt automatic counting comparison trigger based on the ASIC dedicated hardware circuit (the setting range of the counting comparison value: 1 to 2 32-1), The fault injection algorithm can be pre-loaded twice and run at high speed without relying on the CPU's own environment. The whole process does not require the intervention of CPU operation processing instructions, fundamentally eliminating the inherent time consumption of CPU pipeline architecture instructions and the inherent dead time of CPU context protection instructions. From the technical underlying architecture design, it effectively ensures the precise fault injection ability of ultra-high-speed external interrupt automatic counting and comparison triggering. This technology is an effective guarantee for realizing precise trigger fault injection, ultra-high-speed fault injection response, and enhancing the lethality, destructiveness, and success rate of fault injection; for the physical and electrical layer signals of the device under test (including but not limited to hardware / card / circuit / chip / components, etc.), its communication interfaces / protocols include but not limited to 1553B bus, CAN / CANFD bus, LIN bus, RS232, RS485, RS422, UART, I2C, SPI, AD / DA, isolated IO and other communication interfaces. Under the precondition of ensuring dynamic real-time communication (zero-interference fault injection), it restores the real operating environment of the device under test and emits diversified ultra-high-speed fault injection signals (including but not limited to single-mode / differential-mode / common-mode voltage glitches, clock glitches, power-off glitches, communication interface protocol glitches, etc.) that are highly adjustable, controllable, and configurable (software-defined) at specific times and specific positions; The present invention effectively makes up for the defects and deficiencies of the existing structure, adopts a new design concept, a unique software and hardware technology architecture, and a rich hardware trigger mechanism, and proposes a new design concept of S&HDFI software and hardware dual-defined fault injection. The fault injection algorithm can be pre-loaded twice and run at high speed without relying on the CPU's own environment. The whole process does not require the intervention of CPU operation processing instructions, fundamentally eliminating the inherent time consumption of CPU pipeline architecture instructions and the inherent dead time of CPU context protection instructions, greatly improving the ultra-high-speed and ultra-precise fault injection ability. At the same time, the proposed ASIC dedicated ultra-high-speed hardware external interrupt trigger response and the integrated high-speed execution mechanism of the fault injection algorithm after trigger response, combined with the precise fault injection technology, designs a 32-bit ultra-high-speed external interrupt automatic counting comparison trigger precise fault injection mechanism based on ASIC dedicated hardware circuit (counting comparison value setting range: 1~2 32-1), it completely avoids the dead time of CPU instruction jump execution / response from the technical mechanism, and effectively ensures the precise fault injection ability of ultra-high-speed external interrupt automatic counting and comparison triggering from the technical underlying design architecture. This technology is an effective guarantee for truly realizing precise trigger fault injection, ultra-high-speed fault injection response, and enhancing the lethality, destructiveness, and success rate of fault injection. The present invention greatly simplifies the complexity and redundancy of the overall hardware design and layout, efficiently integrates the software-defined fault injection algorithm with a high-speed and high-performance ASIC dedicated hardware circuit. For multi-interface physical electrical layer signals, it can precisely implement highly user-defined specific glitch fault injection (zero-interference fault injection) under the condition of meeting the dynamic real-time communication of different interface protocols. Relying on the flexible advantages of the software-defined fault injection algorithm and the underlying architecture of high-performance hardware collaboration, the present invention can support precise glitch fault injection (non-traditional digital protocol penetration) for the physical electrical layer signals of communication interfaces such as 1553B bus, CAN / CANFD bus, LIN bus, RS232, RS485, RS422, UART, I2C, SPI, etc. In particular, it has the advanced fault injection ability to precisely implement highly user-defined fault injection during the dynamic communication with the object under test. During fault injection, it dynamically restores the real operating environment of the object under test. At the same time, this patent also supports fault injection for other non-digital communication interface application scenarios such as AD / DA and isolated IO.

[0056] The above are only the preferred embodiments of the present invention, and do not limit the patent scope of the present invention accordingly. Any equivalent structural transformation made by using the content of the specification and drawings of the present invention under the inventive concept of the present invention, or direct / indirect application in other related technical fields is included in the patent protection scope of the present invention.

Claims

1. A precise fault injection device based on dual software and hardware definition of multiple interfaces for electrical layer signals, characterized in that, Including: MCU / CPU system, hardware coprocessor module, high-speed ASIC FIFO transmission module, high-speed DAC module, glitch injection module, external interrupt high-speed ASIC hardware trigger module, power-down glitch driving module, and peripheral communication module; the MCU / CPU module is electrically connected to the hardware coprocessor module, high-speed ASIC FIFO transmission module, external interrupt ASIC hardware trigger module, glitch injection module, power-down glitch driving module, and peripheral communication module respectively; the hardware coprocessor module is electrically connected to the high-speed ASIC FIFO transmission module and high-speed DAC module respectively, the high-speed DAC module is electrically connected to the glitch injection module, and the high-speed ASIC FIFO transmission module is electrically connected to the external interrupt high-speed ASIC hardware trigger module.

2. The precision fault injection device based on dual definition of software and hardware for multiple interfaces of electrical layer signals according to claim 1, characterized in that, The glitch injection module includes CH1&CH2 single-mode / common-mode / differential-mode synchronous high-voltage glitch injection module, CLKFI clock glitch injection module, DCFI differential glitch injection module, and HDCFI high-voltage glitch injection module; the CH1&CH2 single-mode / common-mode / differential-mode synchronous high-voltage glitch injection module is electrically connected to the high-speed DAC module, and the CLKFI clock glitch injection module, DCFI differential glitch injection module, and HDCFI high-voltage glitch injection module are all electrically connected to the MCU / CPU system.

3. The precision fault injection device based on the dual definition of software and hardware with multiple interfaces for electrical layer signals according to claim 2, characterized in that, The CH1&CH2 single-mode / common-mode / differential-mode synchronous high-voltage glitch injection module includes CH1 single-mode / common-mode / differential-mode synchronous high-voltage glitch injection circuit and CH2 single-mode / common-mode / differential-mode synchronous high-voltage glitch injection circuit; The CH1 single-mode / common-mode / differential-mode synchronous high-voltage glitch injection circuit includes a CH1 impedance conversion circuit, a first differential high-speed amplifier circuit, a first impedance matching circuit, a first high-speed high-voltage amplifier circuit, and a second impedance matching circuit connected in sequence; the CH1 impedance conversion circuit is connected to the high-speed DAC module; The CH2 single-mode / common-mode / differential-mode synchronous high-voltage glitch injection circuit includes a CH2 impedance conversion circuit, a second differential high-speed amplifier circuit, a third impedance matching circuit, a second high-speed high-voltage amplifier circuit, and a fourth impedance matching circuit connected in sequence; the CH2 impedance conversion circuit is connected to the high-speed DAC module.

4. The precision fault injection device based on dual definition of software and hardware for multi-interface of electrical layer signals according to claim 2, characterized in that, The HDCFI high-voltage glitch injection module includes an HDCFI differential glitch conditioning module, a third differential amplifier circuit, a fifth impedance matching circuit, a third high-speed high-voltage amplifier circuit, and a sixth impedance matching circuit connected in sequence, and the HDCFI differential glitch conditioning module is connected to the MCU / CPU system.

5. The precision fault injection device based on dual definition of software and hardware for multiple interfaces of electrical layer signals according to claim 2, wherein The CLKFI clock glitch injection module includes a CLKFI clock channel control module and a CLKFI clock glitch aggregation conditioning module connected in sequence; the MCU / CPU system is connected to the CLKFI clock channel control module and the CLKFI clock glitch aggregation conditioning module respectively.

6. The precision fault injection device based on dual definition of software and hardware for multiple interfaces of electrical layer signals according to any one of claims 1-5, characterized in that The external interrupt high-speed ASIC hardware trigger module includes an asynchronous control D flip-flop, a pulse counter & comparator ASIC hardware module, and a rising / falling edge trigger control module connected in sequence; the MCU / CPU system is respectively connected to the asynchronous control D flip-flop, the pulse counter & comparator ASIC hardware module, and the rising / falling edge trigger control module, and the asynchronous control D flip-flop is connected to the high-speed ASIC FIFO transmission module.

7. The precision fault injection device based on the dual definition of software and hardware with multiple interfaces for electrical layer signals according to any one of claims 1-5, characterized in that The peripheral communication module includes an RS232 interface circuit, an RS485 interface circuit, a CAN / CANFD interface circuit, a LIN interface circuit, an RJ45 Ethernet circuit, a 1553B interface driver circuit, an I2C interface circuit, an SPI2 interface circuit, and a UART interface circuit.

8. The precision fault injection device based on dual definition of software and hardware with multiple interfaces for electrical layer signals according to any one of claims 1-5, characterized in that, The power-down glitch drive module includes a resistor RC1, a resistor RC2, a diode D1, a diode D2, a MOS transistor Q1, and a resistor RC3; one end of the resistor RC1 is respectively connected to the MCU / CPU system and the resistor RC2, the other end of the resistor RC2 is respectively connected to the anode of the diode D1, the cathode of the diode D2, and the gate of the MOS transistor Q1, the drain of the MOS transistor Q is connected to the resistor RC3, the other end of the resistor RC3 is connected to the socket and the external device, the other end of the resistor RC1, the anode of the diode D2, and the source of the MOS transistor Q1 are grounded, and the cathode of the diode D1 is connected to the power supply terminal.

9. The precision fault injection device based on dual definition of software and hardware with multiple interfaces for electrical layer signals according to any one of claims 1-5, characterized in that, The multi-interface software and hardware dual-defined precision fault injection device based on the electrical layer signal further includes a DAC1 amplification drive module and a DAC2 amplification drive module; both the DAC1 amplification drive module and the DAC2 amplification drive module are respectively connected to the hardware coprocessor module and the glitch injection module.

10. The precision fault injection device based on the dual definition of software and hardware with multiple interfaces for electrical layer signals according to claim 9, characterized in that, The hardware coprocessor module includes a first hardware clock generator, a second hardware clock generator, a DAC1 module, a DAC2 module, and a DAC3 module; the first hardware clock generator is respectively connected to the high-speed DAC module and the high-speed ASIC FIFO transmission module, the second hardware clock generator and the glitch injection module, the DAC1 module is connected to the DAC1 amplification drive module, and the DAC2 module is connected to the DAC2 amplification drive module.

Images