IC carrier plate and preparation method thereof
Through ionic vapor deposition technology, an electroplating lead layer is formed on the solder resist layer of the IC carrier plate and the exposed circuit layer, and a protective layer is formed thereon, which solves the problems of poor adhesion and poor conductivity caused by the sputtering copper process, and achieves cost reduction and yield improvement.
Patent Information
- Application Number
- CN202410083054.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-19
- Publication Date
- 2025-07-22
AI Technical Summary
In the production of existing IC carrier plates, the copper layer formed by the sputtering copper process is insufficient on the surface of the solder resist layer, resulting in poor adhesion and poor conductivity, increasing processing costs and reducing yield.
An ionic vapor deposition technology is used to form an electroplating lead layer on the solder resist layer and the exposed circuit layer, and a protective layer is formed on it through an image transfer process. Finally, gold is plating on the exposed circuit layer, removing the excess layers to form a uniform gold-plating layer.
The adhesion between the electroplating lead layer and the solder resist layer is improved, the conductivity is ensured, the cost is reduced and the yield of the IC carrier plate is improved.
Smart Images
Figure CN120358678A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of IC substrates, and particularly to an IC substrate and a method for manufacturing the same. Background Art
[0002] In the manufacturing process of IC substrates, the industry often uses a leadless gold plating process to plate gold on the circuits to be plated on the circuit board. Among them, the process of first applying solder mask and then gold plating is a commonly used process for leadless gold plating. In this process, a copper layer formed by sputtering copper is often used as a conduction layer during the gold plating process. However, the copper layer formed on the surface of the solder mask by the sputtering copper process needs to have a certain thickness to ensure adhesion, and thus ensure the conductivity of the copper layer during the gold plating process, resulting in high processing costs. In addition, the copper layer formed on the surface of the solder mask by the sputtering copper process has poor copper plating ability on the sidewalls of the solder mask (corresponding to the areas to be plated with gold) and at the positions where the solder mask undergoes side etching, resulting in poor conductivity at these positions, and then resulting in a thin gold plating layer formed during the gold plating process, and finally a low yield of the manufactured IC substrate. Summary of the Invention
[0003] In view of this, this application provides a method for manufacturing an IC substrate that can reduce costs and improve the yield of the IC substrate.
[0004] This application also provides an IC substrate manufactured by using the above method for manufacturing an IC substrate.
[0005] To solve the above problems, the technical solutions provided by this application are as follows:
[0006] In a first aspect, this application provides a method for manufacturing an IC substrate, including: providing a circuit board, the circuit board including a substrate, a first circuit layer, a second circuit layer, a first solder mask layer, and a second solder mask layer, the first circuit layer and the second circuit layer being formed on opposite surfaces of the substrate, the first solder mask layer being formed on the first circuit layer, and the second solder mask layer being formed on the second circuit layer; the first solder mask layer including a first opening, and part of the first circuit layer being exposed from the first opening, the second solder mask layer including a second opening, and part of the second circuit layer being exposed from the second opening; forming a first electroplating lead layer on the circuit board by ion vapor deposition technology, the first electroplating lead layer covering the first solder mask layer and part of the first circuit layer exposed from the first opening; forming a first protective layer covering the first electroplating lead layer on the first electroplating lead layer; forming a first gold plating layer on the second circuit layer exposed from the second opening of the second solder mask layer; and removing the first protective layer and removing the first electroplating lead layer.
[0007] In some embodiments, after the step of removing the first electroplated lead layer and the first protective layer, the method further includes: forming a second electroplated lead layer on the circuit board by ion vapor deposition technology, the second electroplated lead layer covering the second solder mask layer and the first gold plating layer; forming a second protective layer covering the second electroplated lead layer on the second electroplated lead layer and forming a second gold plating layer on the first circuit layer exposed within the first opening of the first solder mask layer; and removing the second protective layer and removing the second electroplated lead layer to obtain an IC carrier board.
[0008] In some embodiments, the step of forming a first protective layer covering the first electroplated lead layer on the first electroplated lead layer includes: forming a first initial protective layer covering the first electroplated lead layer and the second solder mask layer on the first electroplated lead layer and the second solder mask layer; locally exposing the first initial protective layer according to a preset pattern; and removing the first initial protective layer located on the second solder mask layer through a developing process; wherein, the first initial protective layer located on the first electroplated lead layer is the first protective layer.
[0009] In some embodiments, the step of forming a second protective layer covering the second electroplated lead layer on the second electroplated lead layer includes: forming a second initial protective layer covering the second electroplated lead layer and the first solder mask layer on the second electroplated lead layer and the first solder mask layer; locally exposing the second initial protective layer according to a preset pattern; and removing the second initial protective layer located on the first solder mask layer; wherein, the second initial protective layer located on the second electroplated lead layer is the second protective layer.
[0010] In some embodiments, the first circuit layer and the substrate are stacked in a first direction; wherein, the thickness of the first electroplated lead layer and / or the second electroplated lead layer in the first direction is less than 0.8 μm.
[0011] In some embodiments, the thickness of the first electroplated lead layer and / or the second electroplated lead layer in the first direction is greater than or equal to 0.05 μm and less than or equal to 0.15 μm.
[0012] In some embodiments, the first electroplated lead layer and the second electroplated lead layer are removed by a flash etching process.
[0013] In some embodiments, the first gold plating layer and the second gold plating layer are nickel-gold plating layers.
[0014] In some embodiments, the thickness of each part of the first electroplated lead layer and the second electroplated lead layer is uniform.
[0015] In some embodiments, the first electroplated lead layer includes a first main body portion and a first branch portion extending from the first main body portion. A plurality of the first branch portions are arranged at intervals. The first main body portion is formed on the first solder mask layer, and the first branch portion is embedded in the first solder mask layer; the second electroplated lead layer includes a second main body portion and a second branch portion extending from the second main body portion. A plurality of the second branch portions are arranged at intervals. The second main body portion is formed on the second solder mask layer, and the second branch portion is embedded in the second solder mask layer and the first gold plating layer.
[0016] In a second aspect, the present application provides an IC substrate, and the IC substrate is prepared by using the preparation method of the IC substrate described above.
[0017] In some embodiments, the first gold plating layer of the IC substrate has a plurality of micro-holes.
[0018] For the IC substrate and its preparation method of the present application, through the ion vapor deposition (IVD) technology, a first electroplated lead layer is formed on the first solder mask layer of the circuit board and the first circuit layer exposed from the first opening of the first solder mask layer, and a first protective layer covering the first electroplated lead layer is formed on the first electroplated lead layer through an image transfer process. Then, a first gold plating layer is formed on the second circuit layer exposed from the second opening of the second solder mask layer of the circuit board, and finally, the first protective layer and the first electroplated lead layer are removed. The first electroplated lead layer formed in this way has a high adhesion to the surface of the first solder mask layer. When the thickness of the first electroplated lead layer is relatively thin, the electrical conductivity of the first electroplated lead layer during the gold plating process can be ensured, and the cost can be reduced. In addition, the first electroplated lead layer formed in this way has a relatively uniform thickness at various positions of the first solder mask layer, so that the copper plating ability of the side wall of the first solder mask layer (corresponding to the area to be gold plated) and the position where the first solder mask layer undergoes side etching is better, and the thickness of the formed gold plating layer is uniform. In this way, the defect rate of the IC substrate can be reduced. Description of the Drawings
[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative efforts.
[0020] Figure 1 It is a flowchart of a preparation method of an IC substrate provided by some embodiments of the present application.
[0021] Figure 2 It is a cross-sectional view of a circuit board provided by some embodiments of the present application.
[0022] Figure 3 A cross-sectional view after forming a first electroplated lead layer on the first solder mask layer of the circuit board shown in Figure 2
[0023] Figure 4 For Figure 3 A partial enlarged view of the circuit board with the first electroplated lead layer shown in
[0024] Figure 5 A cross-sectional view after forming an initial first protective layer on the circuit board with the first electroplated lead layer shown in Figure 3
[0025] Figure 6 For Figure 5 A cross-sectional view of exposing the initial first protective layer shown in
[0026] Figure 7 A cross-sectional view after removing the initial first protective layer on the second solder mask layer shown in Figure 6
[0027] Figure 8 A cross-sectional view after forming a first gold plating layer on the exposed second circuit layer shown in Figure 7
[0028] Figure 9 A cross-sectional view after removing the first protective layer shown in Figure 8
[0029] Figure 10 A cross-sectional view after removing the first electroplated lead layer in Figure 9
[0030] Figure 11 A cross-sectional view after forming a second electroplated lead layer on the second solder mask layer and the first gold plating layer shown in Figure 10
[0031] Figure 12 A cross-sectional view after forming a second protective layer on the second electroplated lead layer and the first solder mask layer shown in Figure 11
[0032] Figure 13 For Figure 11 A cross-sectional view of exposing the second protective layer shown in
[0033] Figure 14 A cross-sectional view after removing the second protective layer located on the first solder mask layer shown in Figure 13
[0034] Figure 15 A cross-sectional view after forming on Figure 14 Cross-sectional view after forming a second gold plating layer on the exposed first circuit layer.
[0035] Figure 16 To remove Figure 15 Cross-sectional view after removing the second protective layer shown.
[0036] Figure 17 To remove Figure 16 Cross-sectional view of the IC carrier after forming by removing the second electroplated lead layer in Detailed implementation manners
[0037] Next, the technical solutions in the embodiments of the present application will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of the present application.
[0038] In the description of the present application, it should be understood that the orientation or positional relationship indicated by terms such as "upper", "lower", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation to the present application. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more, unless otherwise specifically defined.
[0039] The present application may repeat reference numerals and / or reference letters in different embodiments. This repetition is for the purpose of simplification and clarity, and does not in itself indicate the relationship between the various embodiments and / or arrangements discussed.
[0040] In a first aspect, the present application provides a method for manufacturing an IC substrate, including: providing a circuit board, the circuit board including a substrate, a first circuit layer, a second circuit layer, a first solder mask layer, and a second solder mask layer, the first circuit layer and the second circuit layer being formed on opposite surfaces of the substrate, the first solder mask layer being formed on the first circuit layer, and the second solder mask layer being formed on the second circuit layer; the first solder mask layer including a first opening, a part of the first circuit layer being exposed from the first opening, the second solder mask layer including a second opening, a part of the second circuit layer being exposed from the second opening; forming a first electroplating lead layer on the circuit board by ion vapor deposition technology, the first electroplating lead layer covering the first solder mask layer and the part of the first circuit layer exposed from the first opening; forming a first protective layer covering the first electroplating lead layer on the first electroplating lead layer; forming a first gold plating layer on the second circuit layer exposed from the second opening; removing the first protective layer; and removing the first electroplating lead layer.
[0041] In a second aspect, the present application further provides an IC substrate, the IC substrate being manufactured by using the method for manufacturing an IC substrate as described above.
[0042] A first electroplating lead layer is formed on the first solder mask layer of the circuit board and the first circuit layer exposed from the first opening of the first solder mask layer by ion vapor deposition (IVD) technology, and a first protective layer covering the first electroplating lead layer is formed on the first electroplating lead layer through an image transfer process. Then, a first gold plating layer is formed on the second circuit layer exposed from the second opening of the second solder mask layer of the circuit board. Finally, the first protective layer and the first electroplating lead layer are removed. In this way, the first electroplating lead layer has a high adhesion to the surface of the first solder mask layer. When the thickness of the first electroplating lead layer is relatively thin, the electrical conductivity of the first electroplating lead layer during the gold plating process can be ensured, and the cost can be reduced. In addition, the first electroplating lead layer formed in this way has a relatively uniform thickness at various positions of the first solder mask layer, so that the copper plating ability of the side wall of the first solder mask layer (corresponding to the area to be gold plated) and the position where the first solder mask layer undergoes side etching is better, and the thickness of the formed gold plating layer is uniform. In this way, the defect rate of the IC substrate can be reduced.
[0043] The following will combine specific embodiments and appendices Figure 1-17 to describe in detail the IC substrate and its manufacturing method provided by the present application.
[0044] The manufacturing method of the IC substrate 100 provided by the present application includes:
[0045] Step S1, please refer to Figure 1 and Figure 2, providing a circuit board 110, the circuit board 110 includes a substrate 10, a first circuit layer 20, a second circuit layer 30, a first solder resist layer 40 and a second solder resist layer 50, the first circuit layer 20 and the second circuit layer 30 are formed on opposite surfaces of the substrate 10, the first solder resist layer 40 is formed on the first circuit layer 20, and the second solder resist layer 50 is formed on the second circuit layer 30; the first solder resist layer 40 includes a first opening 41, and a portion of the first circuit layer 20 is exposed from the first opening 41, and the second solder resist layer 50 includes a second opening 51, and a portion of the second circuit layer 30 is exposed from the second opening 51.
[0046] The first solder resist layer 40 , the first circuit layer 20 , the substrate 10 , the second circuit layer 30 , and the second solder resist layer 50 are stacked in a first direction Z.
[0047] In some embodiments, the substrate 10 is also provided with a through hole 11 that penetrates the substrate 10 in the first direction Z. The circuit board 110 also includes a connecting line 111 and a third solder resist layer 112. The connecting line 111 is located on the inner wall of the through hole 11 and connects the first circuit layer 20 and the second circuit layer 30. The third solder resist layer 112 is located in the through hole 11 and on the side of the connecting line 111 away from the inner wall of the through hole 11.
[0048] In some embodiments, the number of the first opening 41 and the number of the second opening 51 can be plural.
[0049] In some embodiments, a portion of the second solder resist layer 50 also penetrates the second circuit layer 30 and is connected to the substrate 10 .
[0050] Step S2, see Figure 1 , Figure 3 and Figure 4 A first electroplated lead layer 61 is formed on the circuit board 110 by ion vapor deposition (IVD) technology, and the first electroplated lead layer 61 covers the first solder resist layer 40 and a portion of the first circuit layer 20 exposed from the first opening 41 .
[0051] In some embodiments, the thickness of the first electroplated lead layer 61 in the first direction Z is less than 0.8 μm. In some embodiments, the thickness of the first electroplated lead layer 61 in the first direction Z is greater than or equal to 0.05 μm and less than or equal to 0.15 μm. In some embodiments, the thickness of the first electroplated lead layer 61 in the first direction Z is greater than or equal to 0.1 μm.
[0052] In some embodiments, the thickness of the first electroplated lead layer 61 is uniform everywhere on the first solder mask layer 40. Specifically, the first solder mask layer 40 includes a solder mask surface 42 and side walls 43. The solder mask surface 42 faces away from the first circuit layer 20, and the side walls 43 are connected to the solder mask surface 42 and are the inner walls of the first opening 41. The thickness of the first electroplated lead layer 61 is uniform on the solder mask surface 42 and the side walls 43.
[0053] Due to process reasons, side etching will occur at the position where the side wall 43 contacts the first circuit layer 20. The thickness of the copper layer formed by the sputtering copper process is relatively thin at the side wall 43 of the first solder mask layer 40 and at the position where side etching occurs, resulting in poor conductivity at this position, and thus resulting in a relatively thin thickness of the gold plating layer formed during the subsequent gold plating process, ultimately leading to a low yield of the prepared IC substrate. However, in the present application, the first electroplated lead layer 61 (i.e., the copper layer) formed on the first solder mask layer 40 by the IVD technology has a uniform thickness on the solder mask surface 42 and the side walls 43 of the first solder mask layer 40, and there will be no situation where the copper layer thickness is relatively thin at the side wall 43 of the first solder mask layer 40 and at the position where side etching occurs. In this way, the first electroplated lead layer 61 (i.e., the copper layer) formed on the first solder mask layer 40 by the IVD technology has good conductivity and can reduce the defect rate of the IC substrate.
[0054] Please refer to Figure 4 , in some embodiments, the first electroplated lead layer 61 includes a first main body portion 611 and first branch portions 612 extending from the first main body portion 611. The plurality of first branch portions 612 are arranged at intervals; the first main body portion 611 of the first electroplated lead layer 61 is formed on the first solder mask layer 40, and the first branch portions 612 of the first electroplated lead layer 61 are embedded in the first solder mask layer 40.
[0055] Among them, the first main body portion 611 of the first electroplated lead layer 61 is in contact adhesion with the first solder mask layer 40, and the first branch portions 612 can penetrate into the interior of the first solder mask layer 40 and adhere to the first solder mask layer 40. The first branch portions 612 further enhance the adhesion between the first electroplated lead layer 61 and the first solder mask layer 40, thereby further enhancing the conductivity of the first electroplated lead layer 61 during the gold plating process.
[0056] Step S3, please refer to Figure 1 and Figures 5 to 7 , form a first protective layer 71 covering the first electroplated lead layer 61 on the first electroplated lead layer 61.
[0057] In some embodiments, a first protective layer 71 covering the first electroplated lead layer 61 may be formed on the first electroplated lead layer 61 through an image transfer process.
[0058] In some embodiments, step S3 includes: First, please refer to Figure 1 and Figure 5 , and a first initial protective layer 70 covering the first electroplated lead layer 61 and the second solder mask layer 50 is formed on the first electroplated lead layer 61 and the second solder mask layer 50; Second, partial exposure is performed on the first initial protective layer 70 according to a preset pattern; Third, through a developing process, a part of the first initial protective layer 70 located on the second solder mask layer 50 is removed, and the first initial protective layer 70 located on the first electroplated lead layer 61 is the first protective layer 71.
[0059] In some embodiments, the material of the first initial protective layer 70 is a dry film (DF), and the dry film is a photosensitive polymer material. After being irradiated by ultraviolet light, the dry film can generate a polymerization reaction to form a stable substance attached to the board surface, so as to achieve the functions of blocking electroplating and etching.
[0060] In some embodiments, the first initial protective layer 70 is a negative photoresist or a positive photoresist. In this embodiment, the first initial protective layer 70 is a negative photoresist.
[0061] Step S4, please refer to Figure 1 and Figure 8 , and a first gold plating layer 81 is formed on the second circuit layer 30 exposed in the second opening 51 of the second solder mask layer 50.
[0062] In some embodiments, the first gold plating layer 81 is a nickel-gold plating layer.
[0063] Step S5, please refer to Figure 1 , Figure 9 and Figure 10 , the first protective layer 71 is removed and the first electroplated lead layer 61 is removed.
[0064] In some embodiments, the first electroplated lead layer 61 is removed through a flash etching process or the like. The first protective layer 71 is removed through a wet etching process or the like.
[0065] Step S6, please refer to Figure 1 and Figure 11 , a second electroplated lead layer 62 is formed on the circuit board 110 through an ion vapor deposition (IVD) technique, and the second electroplated lead layer 62 covers the second solder mask layer 50 and the first gold plating layer 81.
[0066] The second electroplated lead layer 62 includes a second main body portion 621 and second branch portions 622 extending from the second main body portion 621, and a plurality of the second branch portions 622 are arranged at intervals; the second main body portion 621 is formed on the second solder resist layer 50 and the first gold plating layer 81, and the second branch portions 622 are embedded in the second solder resist layer 50 and the first gold plating layer 81. The adhesion between the second electroplated lead layer 62 and the second solder resist layer 50 and the first gold plating layer 81 is relatively strong, so that the conductivity of the second electroplated lead layer 62 during the gold plating process can be further enhanced.
[0067] Step S7, please refer to Figure 1 and Figures 12 to 15 , a second protective layer 91 covering the second electroplated lead layer 62 is formed on the second electroplated lead layer 62, and a second gold plating layer 82 is formed on the first circuit layer 20 exposed in the first opening 41 of the first solder resist layer 40.
[0068] In some embodiments, the second gold plating layer 82 is a nickel-gold plating layer.
[0069] In some embodiments, step S7 includes: First, please refer to Figure 1 and Figure 12 , a second initial protective layer 90 covering the second electroplated lead layer 62 and the first solder resist layer 40 is formed on the second electroplated lead layer 62 and the first solder resist layer 40; Second, please refer to Figure 1 and Figure 13 , local exposure is performed on the second initial protective layer 90 according to a preset pattern; Third, please refer to Figure 1 and Figure 14 , part of the second initial protective layer 90 located on the first solder resist layer 40 is removed through a developing process, and the second initial protective layer 90 located on the second electroplated lead layer 62 is the second protective layer 91; Finally, please refer to Figure 15 , a second gold plating layer 82 is formed on the first circuit layer 20 exposed in the first opening 41 of the first solder resist layer 40 through an electroplating process.
[0070] In some embodiments, the material of the second initial protective layer 90 is a dry film, the dry film is a photosensitive polymer material, and the dry film can generate a polymerization reaction after being irradiated by ultraviolet light to form a stable substance attached to the board surface, so as to achieve the functions of blocking electroplating and etching.
[0071] In some embodiments, the second initial protective layer 90 is a negative photoresist or a positive photoresist. In this embodiment, the second initial protective layer 90 is a negative photoresist.
[0072] Step S8, please refer to Figure 1 and Figures 16 to 17 , remove the second protective layer 91 and remove the second electroplated lead layer 62 to obtain the IC substrate 100.
[0073] In some embodiments, the second electroplated lead layer 62 is removed by an etch-back process or the like. The second protective layer 91 is removed by a wet etching process or the like.
[0074] Please refer to Figure 10 , the present application also provides an IC substrate 100, and the IC substrate 100 is prepared by using the preparation method of the IC substrate 100 as described above. The first gold plating layer 81 of the IC substrate 100 has micropores.
[0075] For the IC substrate and its preparation method of the present application, a first electroplated lead layer is formed on the first solder mask layer of the circuit board and the first circuit layer exposed from the first opening of the first solder mask layer by ion vapor deposition (IVD) technology, and a first protective layer covering the first electroplated lead layer is formed on the first electroplated lead layer by an image transfer process. Then, a first gold plating layer is formed on the second circuit layer exposed from the second opening of the second solder mask layer of the circuit board. Finally, the first protective layer and the first electroplated lead layer are removed; then, a second electroplated lead layer covering the second solder mask layer and the first gold plating layer is formed, and a second gold plating layer is formed by performing a second gold plating on the first circuit layer exposed from the first opening of the first solder mask layer. In this way, the first electroplated lead layer and the surface of the first solder mask layer and the second electroplated lead layer and the surface of the second solder mask layer have high adhesion. When the thickness of the first electroplated lead layer and / or the second electroplated lead layer is relatively thin, the electrical conductivity of the first electroplated lead layer and / or the second electroplated lead layer during the gold plating process can be ensured, and the cost is reduced. In addition, the thickness of the first electroplated lead layer and / or the second electroplated lead layer formed in this way is relatively uniform at each part of the first solder mask layer and / or the second solder mask layer, so that the copper plating ability of the side wall (corresponding to the area to be gold plated) of the first solder mask layer and / or the second solder mask layer and the position where the first solder mask layer and / or the second solder mask layer undergoes side etching is good, and the thickness of the formed gold plating layer is uniform. In this way, the defect rate of the IC substrate can be reduced.
[0076] In summary, although the present application has been disclosed above with preferred embodiments, the above preferred embodiments are not intended to limit the present application. Those of ordinary skill in the art can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application is subject to the scope defined by the claims.
Claims
1. A method for preparing an IC carrier board, characterized in that, Comprising: Providing a circuit board, the circuit board including a substrate, a first circuit layer, a second circuit layer, a first solder mask layer, and a second solder mask layer. The first circuit layer and the second circuit layer are formed on opposite two surfaces of the substrate. The first solder mask layer is formed on the first circuit layer, and the second solder mask layer is formed on the second circuit layer. The first solder mask layer includes a first opening, and a part of the first circuit layer is exposed from the first opening. The second solder mask layer includes a second opening, and a part of the second circuit layer is exposed from the second opening. Forming a first electroplating lead layer on the circuit board by ion vapor deposition technology, the first electroplating lead layer covering the first solder mask layer and the part of the first circuit layer exposed from the first opening. Forming a first protective layer covering the first electroplating lead layer on the first electroplating lead layer. Forming a first gold plating layer on the second circuit layer exposed from the second opening of the second solder mask layer; and Removing the first protective layer and removing the first electroplating lead layer.
2. The manufacturing method of the IC substrate according to claim 1, wherein After the step of removing the first electroplating lead layer and the first protective layer, it further includes: Forming a second electroplating lead layer on the circuit board by ion vapor deposition technology, the second electroplating lead layer covering the second solder mask layer and the first gold plating layer. Forming a second protective layer covering the second electroplating lead layer on the second electroplating lead layer and forming a second gold plating layer on the first circuit layer exposed from the first opening of the first solder mask layer; and Removing the second protective layer and removing the second electroplating lead layer to obtain an IC carrier board.
3. The manufacturing method of the IC substrate according to claim 1, wherein The step of forming a first protective layer covering the first electroplating lead layer on the first electroplating lead layer includes: Forming a first initial protective layer covering the first electroplating lead layer and the second solder mask layer on the first electroplating lead layer and the second solder mask layer. Performing local exposure on the first initial protective layer according to a preset pattern; and Removing the first initial protective layer located on the second solder mask layer through a developing process. Wherein, the first initial protective layer located on the first electroplating lead layer is the first protective layer.
4. The manufacturing method of the IC substrate according to claim 2, wherein, The step of forming a second protective layer covering the second electroplating lead layer on the second electroplating lead layer includes: Forming a second initial protective layer covering the second electroplating lead layer and the first solder mask layer on the second electroplating lead layer and the first solder mask layer. Performing local exposure on the second initial protective layer according to a preset pattern; and Removing the second initial protective layer located on the first solder mask layer. Wherein, the second initial protective layer located on the second electroplating lead layer is the second protective layer.
5. The manufacturing method of the IC carrier as described in claim 2, characterized in that, The first circuit layer and the substrate are stacked in a first direction; Wherein, the thickness of the first electroplating lead layer and / or the second electroplating lead layer in the first direction is less than 0.8 μm.
6. The method for manufacturing an IC substrate according to claim 5, wherein The thickness of the first electroplating lead layer and / or the second electroplating lead layer in the first direction is greater than or equal to 0.05 μm and less than or equal to 0.15 μm.
7. The manufacturing method of the IC substrate according to claim 2, wherein, Removing the first electroplating lead layer and the second electroplating lead layer by flash etching process.
8. The manufacturing method of the IC carrier board according to claim 2, characterized in that, The first gold plating layer and the second gold plating layer are nickel-gold plating layers.
9. The manufacturing method of the IC carrier as claimed in claim 2, wherein The thicknesses of all parts of the first electroplated lead layer and the second electroplated lead layer are uniform.
10. The manufacturing method of the IC carrier as described in claim 2, wherein, The first electroplated lead layer includes a first main body portion and first branch portions extending from the first main body portion. The plurality of first branch portions are arranged at intervals. The first main body portion is formed on the first solder mask layer, and the first branch portions are embedded in the first solder mask layer; The second electroplated lead layer includes a second main body portion and second branch portions extending from the second main body portion. The plurality of second branch portions are arranged at intervals. The second main body portion is formed on the second solder mask layer, and the second branch portions are embedded in the second solder mask layer and the first gold plating layer.
11. An IC carrier board, characterized in that, The IC carrier is prepared by using the preparation method of the IC carrier according to any one of claims 1-10.
12. The IC substrate according to claim 11, wherein, The first gold plating layer of the IC carrier has a plurality of micro-holes.